opcodes/ChangeLog

   1 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/23655
   4         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
   5         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
   6         * i386-dis.c (EXxEVexR64): New.
   7         (evex_rounding_64_mode): Likewise.
   8         (OP_Rounding): Handle evex_rounding_64_mode.
   9
  10 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         PR binutils/23655
  13         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
  14         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
  15         * i386-dis.c (Edqa): New.
  16         (dqa_mode): Likewise.
  17         (intel_operand_size): Handle dqa_mode as m_mode.
  18         (OP_E_register): Handle dqa_mode as dq_mode.
  19         (OP_E_memory): Set shift for dqa_mode based on address_mode.
  20
  21 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         * i386-dis.c (OP_E_memory): Reformat.
  24
  25 2018-09-14  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl (crc32): Fold byte and word forms.
  28         * i386-tbl.h: Re-generate.
  29
  30 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
  31
  32         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
  33         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
  34         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
  35         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
  36         * i386-tbl.h: Regenerated.
  37
  38 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  39
  40         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
  41         meaningless.
  42         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
  43         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
  44         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
  45         * i386-tbl.h: Re-generate.
  46
  47 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
  50         AVX512_4VNNIW insns.
  51         * i386-tbl.h: Re-generate.
  52
  53 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  54
  55         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
  56         meaningless.
  57         * i386-tbl.h: Re-generate.
  58
  59 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
  62         meaningless.
  63         * i386-tbl.h: Re-generate.
  64
  65 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  66
  67         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
  68         meaningless.
  69         * i386-tbl.h: Re-generate.
  70
  71 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
  74         meaningless.
  75         * i386-tbl.h: Re-generate.
  76
  77 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
  80         meaningless.
  81         * i386-tbl.h: Re-generate.
  82
  83 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  84
  85         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
  86         * i386-tbl.h: Re-generate.
  87
  88 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  89
  90         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
  91         * i386-tbl.h: Re-generate.
  92
  93 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  94
  95         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
  96         meaningless.
  97         * i386-tbl.h: Re-generate.
  98
  99 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 100
 101         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 102         meaningless.
 103         * i386-tbl.h: Re-generate.
 104
 105 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 108         * i386-tbl.h: Re-generate.
 109
 110 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 111
 112         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 113         * i386-tbl.h: Re-generate.
 114
 115 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 118         * i386-tbl.h: Re-generate.
 119
 120 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 123         meaningless.
 124         * i386-tbl.h: Re-generate.
 125
 126 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 127
 128         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 129         meaningless.
 130         * i386-tbl.h: Re-generate.
 131
 132 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 133
 134         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 135         meaningless.
 136         * i386-tbl.h: Re-generate.
 137
 138 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 141         * i386-tbl.h: Re-generate.
 142
 143 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 146         * i386-tbl.h: Re-generate.
 147
 148 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 151         * i386-tbl.h: Re-generate.
 152
 153 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 156         (vpbroadcastw, rdpid): Drop NoRex64.
 157         * i386-tbl.h: Re-generate.
 158
 159 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 162         store templates, adding D.
 163         * i386-tbl.h: Re-generate.
 164
 165 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 166
 167         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 168         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 169         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 170         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 171         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 172         Fold load and store templates where possible, adding D. Drop
 173         IgnoreSize where it was pointlessly present. Drop redundant
 174         *word.
 175         * i386-tbl.h: Re-generate.
 176
 177 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 180         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 181         (intel_operand_size): Handle v_bndmk_mode.
 182         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 183
 184 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 185
 186         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 187
 188 2018-08-31  Kito Cheng  <kito@andestech.com>
 189
 190         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 191         compressed floating point instructions.
 192
 193 2018-08-30  Kito Cheng  <kito@andestech.com>
 194
 195         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 196         riscv_opcode.xlen_requirement.
 197         * riscv-opc.c (riscv_opcodes): Update for struct change.
 198
 199 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 200
 201         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 202         psr (PWRPSR) instruction.
 203
 204 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 205
 206         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 207
 208 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 209
 210         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 211
 212 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 213
 214         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 215         loongson3a as an alias of gs464 for compatibility.
 216         * mips-opc.c (mips_opcodes): Change Comments.
 217
 218 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 219
 220         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 221         option.
 222         (print_mips_disassembler_options): Document -M loongson-ext.
 223         * mips-opc.c (LEXT2): New macro.
 224         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 225
 226 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 227
 228          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 229          descriptors.
 230          (parse_mips_ase_option): Handle -M loongson-ext option.
 231          (print_mips_disassembler_options): Document -M loongson-ext.
 232          * mips-opc.c (IL3A): Delete.
 233          * mips-opc.c (LEXT): New macro.
 234          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 235          instructions.
 236
 237 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 238
 239         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 240         descriptors.
 241         (parse_mips_ase_option): Handle -M loongson-cam option.
 242         (print_mips_disassembler_options): Document -M loongson-cam.
 243         * mips-opc.c (LCAM): New macro.
 244         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 245         instructions.
 246
 247 2018-08-21  Alan Modra  <amodra@gmail.com>
 248
 249         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 250         (skip_optional_operands): Count optional operands, and update
 251         ppc_optional_operand_value call.
 252         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 253         (extract_vlensi): Likewise.
 254         (extract_fxm): Return default value for missing optional operand.
 255         (extract_ls, extract_raq, extract_tbr): Likewise.
 256         (insert_sxl, extract_sxl): New functions.
 257         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 258         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 259         flag and extra entry.
 260         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 261         extract_sxl.
 262
 263 2018-08-20  Alan Modra  <amodra@gmail.com>
 264
 265         * sh-opc.h (MASK): Simplify.
 266
 267 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 268
 269         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 270         BM_RESERVED0 or BM_RESERVED1
 271         (bm_rel_decode, bm_n_bytes): Ditto.
 272
 273 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 274
 275         * s12z.h: Delete.
 276
 277 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 280         address with the addr32 prefix and without base nor index
 281         registers.
 282
 283 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 284
 285         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 286         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 287         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 288         (cpu_flags): Add CpuCMOV and CpuFXSR.
 289         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 290         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 291         * i386-init.h: Regenerated.
 292         * i386-tbl.h: Likewise.
 293
 294 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 295
 296         * arc-regs.h: Update auxiliary registers.
 297
 298 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 301         (RegIP, RegIZ): Define.
 302         * i386-reg.tbl: Adjust comments.
 303         (rip): Use Qword instead of BaseIndex. Use RegIP.
 304         (eip): Use Dword instead of BaseIndex. Use RegIP.
 305         (riz): Add Qword. Use RegIZ.
 306         (eiz): Add Dword. Use RegIZ.
 307         * i386-tbl.h: Re-generate.
 308
 309 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 312         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 313         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 314         * i386-tbl.h: Re-generate.
 315
 316 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-gen.c (operand_types): Remove Mem field.
 319         * i386-opc.h (union i386_operand_type): Remove mem field.
 320         * i386-init.h, i386-tbl.h: Re-generate.
 321
 322 2018-08-01  Alan Modra  <amodra@gmail.com>
 323
 324         * po/POTFILES.in: Regenerate.
 325
 326 2018-07-31  Nick Clifton  <nickc@redhat.com>
 327
 328         * po/sv.po: Updated Swedish translation.
 329
 330 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 333         * i386-init.h, i386-tbl.h: Re-generate.
 334
 335 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 336
 337         * i386-opc.h (ZEROING_MASKING) Rename to ...
 338         (DYNAMIC_MASKING): ... this. Adjust comment.
 339         * i386-opc.tbl (MaskingMorZ): Define.
 340         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 341         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 342         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 343         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 344         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 345         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 346         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 347         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 348         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 349
 350 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 351
 352         * i386-opc.tbl: Use element rather than vector size for AVX512*
 353         scatter/gather insns.
 354         * i386-tbl.h: Re-generate.
 355
 356 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 357
 358         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 359         (cpu_flags): Drop CpuVREX.
 360         * i386-opc.h (CpuVREX): Delete.
 361         (union i386_cpu_flags): Remove cpuvrex.
 362         * i386-init.h, i386-tbl.h: Re-generate.
 363
 364 2018-07-30  Jim Wilson  <jimw@sifive.com>
 365
 366         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 367         fields.
 368         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 369
 370 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 371
 372         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 373         * Makefile.in: Regenerated.
 374         * configure.ac: Add C-SKY.
 375         * configure: Regenerated.
 376         * csky-dis.c: New file.
 377         * csky-opc.h: New file.
 378         * disassemble.c (ARCH_csky): Define.
 379         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 380         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 381
 382 2018-07-27  Alan Modra  <amodra@gmail.com>
 383
 384         * ppc-opc.c (insert_sprbat): Correct function parameter and
 385         return type.
 386         (extract_sprbat): Likewise, variable too.
 387
 388 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 389             Alan Modra  <amodra@gmail.com>
 390
 391         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 392         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 393         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 394         support disjointed BAT.
 395         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 396         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 397         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 398
 399 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 400             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 401
 402         * i386-gen.c (adjust_broadcast_modifier): New function.
 403         (process_i386_opcode_modifier): Add an argument for operands.
 404         Adjust the Broadcast value based on operands.
 405         (output_i386_opcode): Pass operand_types to
 406         process_i386_opcode_modifier.
 407         (process_i386_opcodes): Pass NULL as operands to
 408         process_i386_opcode_modifier.
 409         * i386-opc.h (BYTE_BROADCAST): New.
 410         (WORD_BROADCAST): Likewise.
 411         (DWORD_BROADCAST): Likewise.
 412         (QWORD_BROADCAST): Likewise.
 413         (i386_opcode_modifier): Expand broadcast to 3 bits.
 414         * i386-tbl.h: Regenerated.
 415
 416 2018-07-24  Alan Modra  <amodra@gmail.com>
 417
 418         PR 23430
 419         * or1k-desc.h: Regenerate.
 420
 421 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 422
 423         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 424         vcvtusi2ss, and vcvtusi2sd.
 425         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 426         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 427         * i386-tbl.h: Re-generate.
 428
 429 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 430
 431         * arc-opc.c (extract_w6): Fix extending the sign.
 432
 433 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 434
 435         * arc-tbl.h (vewt): Allow it for ARC EM family.
 436
 437 2018-07-23  Alan Modra  <amodra@gmail.com>
 438
 439         PR 23419
 440         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 441         opcode variants for mtspr/mfspr encodings.
 442
 443 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 444             Maciej W. Rozycki  <macro@mips.com>
 445
 446         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 447         loongson3a descriptors.
 448         (parse_mips_ase_option): Handle -M loongson-mmi option.
 449         (print_mips_disassembler_options): Document -M loongson-mmi.
 450         * mips-opc.c (LMMI): New macro.
 451         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 452         instructions.
 453
 454 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 455
 456         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 457         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 458         IgnoreSize and [XYZ]MMword where applicable.
 459         * i386-tbl.h: Re-generate.
 460
 461 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 462
 463         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 464         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 465         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 466         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 467         * i386-tbl.h: Re-generate.
 468
 469 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 470
 471         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 472         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 473         VPCLMULQDQ templates into their respective AVX512VL counterparts
 474         where possible, using Disp8ShiftVL and CheckRegSize instead of
 475         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 476         * i386-tbl.h: Re-generate.
 477
 478 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 479
 480         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 481         AVX512VL counterparts where possible, using Disp8ShiftVL and
 482         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 483         IgnoreSize) as appropriate.
 484         * i386-tbl.h: Re-generate.
 485
 486 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-opc.tbl: Fold AVX512BW templates into their respective
 489         AVX512VL counterparts where possible, using Disp8ShiftVL and
 490         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 491         IgnoreSize) as appropriate.
 492         * i386-tbl.h: Re-generate.
 493
 494 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 495
 496         * i386-opc.tbl: Fold AVX512CD templates into their respective
 497         AVX512VL counterparts where possible, using Disp8ShiftVL and
 498         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 499         IgnoreSize) as appropriate.
 500         * i386-tbl.h: Re-generate.
 501
 502 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 503
 504         * i386-opc.h (DISP8_SHIFT_VL): New.
 505         * i386-opc.tbl (Disp8ShiftVL):  Define.
 506         (various): Fold AVX512VL templates into their respective
 507         AVX512F counterparts where possible, using Disp8ShiftVL and
 508         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 509         IgnoreSize) as appropriate.
 510         * i386-tbl.h: Re-generate.
 511
 512 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 513
 514         * Makefile.am: Change dependencies and rule for
 515         $(srcdir)/i386-init.h.
 516         * Makefile.in: Re-generate.
 517         * i386-gen.c (process_i386_opcodes): New local variable
 518         "marker". Drop opening of input file. Recognize marker and line
 519         number directives.
 520         * i386-opc.tbl (OPCODE_I386_H): Define.
 521         (i386-opc.h): Include it.
 522         (None): Undefine.
 523
 524 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 525
 526         PR gas/23418
 527         * i386-opc.h (Byte): Update comments.
 528         (Word): Likewise.
 529         (Dword): Likewise.
 530         (Fword): Likewise.
 531         (Qword): Likewise.
 532         (Tbyte): Likewise.
 533         (Xmmword): Likewise.
 534         (Ymmword): Likewise.
 535         (Zmmword): Likewise.
 536         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 537         vcvttps2uqq.
 538         * i386-tbl.h: Regenerated.
 539
 540 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 541
 542         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 543         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 544         * aarch64-asm-2.c: Regenerate.
 545         * aarch64-dis-2.c: Regenerate.
 546         * aarch64-opc-2.c: Regenerate.
 547
 548 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 549
 550         PR binutils/23192
 551         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 552         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 553         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 554         sqdmulh, sqrdmulh): Use Em16.
 555
 556 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 557
 558         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 559         csdb together with them.
 560         (thumb32_opcodes): Likewise.
 561
 562 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 563
 564         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 565         requiring 32-bit registers as operands 2 and 3. Improve
 566         comments.
 567         (mwait, mwaitx): Fold templates. Improve comments.
 568         OPERAND_TYPE_INOUTPORTREG.
 569         * i386-tbl.h: Re-generate.
 570
 571 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-gen.c (operand_type_init): Remove
 574         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 575         OPERAND_TYPE_INOUTPORTREG.
 576         * i386-init.h: Re-generate.
 577
 578 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 581         (wrssq, wrussq): Add Qword.
 582         * i386-tbl.h: Re-generate.
 583
 584 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-opc.h: Rename OTMax to OTNum.
 587         (OTNumOfUints): Adjust calculation.
 588         (OTUnused): Directly alias to OTNum.
 589
 590 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 591
 592         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 593         `reg_xys'.
 594         (lea_reg_xys): Likewise.
 595         (print_insn_loop_primitive): Rename `reg' local variable to
 596         `reg_dxy'.
 597
 598 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 599
 600         PR binutils/23242
 601         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 602
 603 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 604
 605         PR binutils/23369
 606         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 607         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 608
 609 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 610
 611         PR tdep/8282
 612         * mips-dis.c (mips_option_arg_t): New enumeration.
 613         (mips_options): New variable.
 614         (disassembler_options_mips): New function.
 615         (print_mips_disassembler_options): Reimplement in terms of
 616         `disassembler_options_mips'.
 617         * arm-dis.c (disassembler_options_arm): Adapt to using the
 618         `disasm_options_and_args_t' structure.
 619         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 620         * s390-dis.c (disassembler_options_s390): Likewise.
 621
 622 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 623
 624         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 625         expected result.
 626         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 627         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 628         * testsuite/ld-arm/tls-longplt.d: Likewise.
 629
 630 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 631
 632         PR binutils/23192
 633         * aarch64-asm-2.c: Regenerate.
 634         * aarch64-dis-2.c: Likewise.
 635         * aarch64-opc-2.c: Likewise.
 636         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 637         * aarch64-opc.c (operand_general_constraint_met_p,
 638         aarch64_print_operand): Likewise.
 639         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 640         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 641         fmlal2, fmlsl2.
 642         (AARCH64_OPERANDS): Add Em2.
 643
 644 2018-06-26  Nick Clifton  <nickc@redhat.com>
 645
 646         * po/uk.po: Updated Ukranian translation.
 647         * po/de.po: Updated German translation.
 648         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 649
 650 2018-06-26  Nick Clifton  <nickc@redhat.com>
 651
 652         * nfp-dis.c: Fix spelling mistake.
 653
 654 2018-06-24  Nick Clifton  <nickc@redhat.com>
 655
 656         * configure: Regenerate.
 657         * po/opcodes.pot: Regenerate.
 658
 659 2018-06-24  Nick Clifton  <nickc@redhat.com>
 660
 661         2.31 branch created.
 662
 663 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 664
 665         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 666         * aarch64-asm-2.c: Regenerate.
 667         * aarch64-dis-2.c: Likewise.
 668
 669 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 670
 671         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 672         `-M ginv' option description.
 673
 674 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 675
 676         PR gas/23305
 677         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 678         la and lla.
 679
 680 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 681
 682         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 683         * configure.ac: Remove AC_PREREQ.
 684         * Makefile.in: Re-generate.
 685         * aclocal.m4: Re-generate.
 686         * configure: Re-generate.
 687
 688 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 689
 690         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 691         mips64r6 descriptors.
 692         (parse_mips_ase_option): Handle -Mginv option.
 693         (print_mips_disassembler_options): Document -Mginv.
 694         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 695         (GINV): New macro.
 696         (mips_opcodes): Define ginvi and ginvt.
 697
 698 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 699             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 700
 701         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 702         * mips-opc.c (CRC, CRC64): New macros.
 703         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 704         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 705         crc32cd for CRC64.
 706
 707 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 708
 709         PR 20319
 710         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 711         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 712
 713 2018-06-06  Alan Modra  <amodra@gmail.com>
 714
 715         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 716         setjmp.  Move init for some other vars later too.
 717
 718 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 719
 720         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 721         (dis_private): Add new fields for property section tracking.
 722         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 723         (xtensa_instruction_fits): New functions.
 724         (fetch_data): Bump minimal fetch size to 4.
 725         (print_insn_xtensa): Make struct dis_private static.
 726         Load and prepare property table on section change.
 727         Don't disassemble literals. Don't disassemble instructions that
 728         cross property table boundaries.
 729
 730 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 731
 732         * configure: Regenerated.
 733
 734 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 735
 736         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 737         * i386-tbl.h: Re-generate.
 738
 739 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-opc.tbl (sldt, str): Add NoRex64.
 742         * i386-tbl.h: Re-generate.
 743
 744 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 745
 746         * i386-opc.tbl (invpcid): Add Oword.
 747         * i386-tbl.h: Re-generate.
 748
 749 2018-06-01  Alan Modra  <amodra@gmail.com>
 750
 751         * sysdep.h (_bfd_error_handler): Don't declare.
 752         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 753         * rl78-decode.opc: Likewise.
 754         * msp430-decode.c: Regenerate.
 755         * rl78-decode.c: Regenerate.
 756
 757 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 758
 759         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 760         * i386-init.h : Regenerated.
 761
 762 2018-05-25  Alan Modra  <amodra@gmail.com>
 763
 764         * Makefile.in: Regenerate.
 765         * po/POTFILES.in: Regenerate.
 766
 767 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 768
 769         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 770         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 771         (insert_bab, extract_bab, insert_btab, extract_btab,
 772         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 773         (BAT, BBA VBA RBS XB6S): Delete macros.
 774         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 775         (BB, BD, RBX, XC6): Update for new macros.
 776         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 777         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 778         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 779         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 780
 781 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 782
 783         * Makefile.am: Add support for s12z architecture.
 784         * configure.ac: Likewise.
 785         * disassemble.c: Likewise.
 786         * disassemble.h: Likewise.
 787         * Makefile.in: Regenerate.
 788         * configure: Regenerate.
 789         * s12z-dis.c: New file.
 790         * s12z.h: New file.
 791
 792 2018-05-18  Alan Modra  <amodra@gmail.com>
 793
 794         * nfp-dis.c: Don't #include libbfd.h.
 795         (init_nfp3200_priv): Use bfd_get_section_contents.
 796         (nit_nfp6000_mecsr_sec): Likewise.
 797
 798 2018-05-17  Nick Clifton  <nickc@redhat.com>
 799
 800         * po/zh_CN.po: Updated simplified Chinese translation.
 801
 802 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 803
 804         PR binutils/23109
 805         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 806         * aarch64-dis-2.c: Regenerate.
 807
 808 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 809
 810         PR binutils/21446
 811         * aarch64-asm.c (opintl.h): Include.
 812         (aarch64_ins_sysreg): Enforce read/write constraints.
 813         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 814         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 815         (F_REG_READ, F_REG_WRITE): New.
 816         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 817         AARCH64_OPND_SYSREG.
 818         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 819         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 820         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 821         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 822         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 823         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 824         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 825         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 826         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 827         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 828         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 829         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 830         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 831         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 832         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 833         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 834         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 835
 836 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 837
 838         PR binutils/21446
 839         * aarch64-dis.c (no_notes: New.
 840         (parse_aarch64_dis_option): Support notes.
 841         (aarch64_decode_insn, print_operands): Likewise.
 842         (print_aarch64_disassembler_options): Document notes.
 843         * aarch64-opc.c (aarch64_print_operand): Support notes.
 844
 845 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 846
 847         PR binutils/21446
 848         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 849         and take error struct.
 850         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 851         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 852         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 853         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 854         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 855         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 856         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 857         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 858         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 859         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 860         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 861         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 862         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 863         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 864         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 865         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 866         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 867         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 868         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 869         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 870         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 871         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 872         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 873         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 874         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 875         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 876         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 877         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 878         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 879         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 880         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 881         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 882         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 883         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 884         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 885         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 886         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 887         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 888         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 889         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 890         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 891         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 892         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 893         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 894         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 895         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 896         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 897         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 898         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 899         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 900         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 901         (determine_disassembling_preference, aarch64_decode_insn,
 902         print_insn_aarch64_word, print_insn_data): Take errors struct.
 903         (print_insn_aarch64): Use errors.
 904         * aarch64-asm-2.c: Regenerate.
 905         * aarch64-dis-2.c: Regenerate.
 906         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 907         boolean in aarch64_insert_operan.
 908         (print_operand_extractor): Likewise.
 909         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 910
 911 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 912
 913         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 914
 915 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 916
 917         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 918
 919 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 920
 921         * cr16-opc.c (cr16_instruction): Comment typo fix.
 922         * hppa-dis.c (print_insn_hppa): Likewise.
 923
 924 2018-05-08  Jim Wilson  <jimw@sifive.com>
 925
 926         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 927         (match_c_slli64, match_srxi_as_c_srxi): New.
 928         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 929         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 930         <c.slli, c.srli, c.srai>: Use match_s_slli.
 931         <c.slli64, c.srli64, c.srai64>: New.
 932
 933 2018-05-08  Alan Modra  <amodra@gmail.com>
 934
 935         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 936         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 937         partition opcode space for index lookup.
 938
 939 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 940
 941         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 942         <insn_length>: ...with this.  Update usage.
 943         Remove duplicate call to *info->memory_error_func.
 944
 945 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 946             H.J. Lu  <hongjiu.lu@intel.com>
 947
 948         * i386-dis.c (Gva): New.
 949         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 950         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 951         (prefix_table): New instructions (see prefix above).
 952         (mod_table): New instructions (see prefix above).
 953         (OP_G): Handle va_mode.
 954         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 955         CPU_MOVDIR64B_FLAGS.
 956         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 957         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 958         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 959         * i386-opc.tbl: Add movidir{i,64b}.
 960         * i386-init.h: Regenerated.
 961         * i386-tbl.h: Likewise.
 962
 963 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 964
 965         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 966         AddrPrefixOpReg.
 967         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 968         (AddrPrefixOpReg): This.
 969         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 970         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 971
 972 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 973
 974         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 975         (vle_num_opcodes): Likewise.
 976         (spe2_num_opcodes): Likewise.
 977         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 978         initialization loop.
 979         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 980         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 981         only once.
 982
 983 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 984
 985         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 986
 987 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 988
 989         Makefile.am: Added nfp-dis.c.
 990         configure.ac: Added bfd_nfp_arch.
 991         disassemble.h: Added print_insn_nfp prototype.
 992         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 993         nfp-dis.c: New, for NFP support.
 994         po/POTFILES.in: Added nfp-dis.c to the list.
 995         Makefile.in: Regenerate.
 996         configure: Regenerate.
 997
 998 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 999
1000         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1001         templates into their base ones.
1002         * i386-tlb.h: Re-generate.
1003
1004 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1005
1006         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1007         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1008         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1009         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1010         * i386-init.h: Re-generate.
1011
1012 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1013
1014         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1015         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1016         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1017         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1018         comment.
1019         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1020         and CpuRegMask.
1021         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1022         CpuRegMask: Delete.
1023         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1024         cpuregzmm, and cpuregmask.
1025         * i386-init.h: Re-generate.
1026         * i386-tbl.h: Re-generate.
1027
1028 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1029
1030         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1031         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1032         * i386-init.h: Re-generate.
1033
1034 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1035
1036         * i386-gen.c (VexImmExt): Delete.
1037         * i386-opc.h (VexImmExt, veximmext): Delete.
1038         * i386-opc.tbl: Drop all VexImmExt uses.
1039         * i386-tlb.h: Re-generate.
1040
1041 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1044         register-only forms.
1045         * i386-tlb.h: Re-generate.
1046
1047 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1048
1049         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1050
1051 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1052
1053         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1054         PREFIX_0F1C.
1055         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1056         (cpu_flags): Add CpuCLDEMOTE.
1057         * i386-init.h: Regenerate.
1058         * i386-opc.h (enum): Add CpuCLDEMOTE,
1059         (i386_cpu_flags): Add cpucldemote.
1060         * i386-opc.tbl: Add cldemote.
1061         * i386-tbl.h: Regenerate.
1062
1063 2018-04-16  Alan Modra  <amodra@gmail.com>
1064
1065         * Makefile.am: Remove sh5 and sh64 support.
1066         * configure.ac: Likewise.
1067         * disassemble.c: Likewise.
1068         * disassemble.h: Likewise.
1069         * sh-dis.c: Likewise.
1070         * sh64-dis.c: Delete.
1071         * sh64-opc.c: Delete.
1072         * sh64-opc.h: Delete.
1073         * Makefile.in: Regenerate.
1074         * configure: Regenerate.
1075         * po/POTFILES.in: Regenerate.
1076
1077 2018-04-16  Alan Modra  <amodra@gmail.com>
1078
1079         * Makefile.am: Remove w65 support.
1080         * configure.ac: Likewise.
1081         * disassemble.c: Likewise.
1082         * disassemble.h: Likewise.
1083         * w65-dis.c: Delete.
1084         * w65-opc.h: Delete.
1085         * Makefile.in: Regenerate.
1086         * configure: Regenerate.
1087         * po/POTFILES.in: Regenerate.
1088
1089 2018-04-16  Alan Modra  <amodra@gmail.com>
1090
1091         * configure.ac: Remove we32k support.
1092         * configure: Regenerate.
1093
1094 2018-04-16  Alan Modra  <amodra@gmail.com>
1095
1096         * Makefile.am: Remove m88k support.
1097         * configure.ac: Likewise.
1098         * disassemble.c: Likewise.
1099         * disassemble.h: Likewise.
1100         * m88k-dis.c: Delete.
1101         * Makefile.in: Regenerate.
1102         * configure: Regenerate.
1103         * po/POTFILES.in: Regenerate.
1104
1105 2018-04-16  Alan Modra  <amodra@gmail.com>
1106
1107         * Makefile.am: Remove i370 support.
1108         * configure.ac: Likewise.
1109         * disassemble.c: Likewise.
1110         * disassemble.h: Likewise.
1111         * i370-dis.c: Delete.
1112         * i370-opc.c: Delete.
1113         * Makefile.in: Regenerate.
1114         * configure: Regenerate.
1115         * po/POTFILES.in: Regenerate.
1116
1117 2018-04-16  Alan Modra  <amodra@gmail.com>
1118
1119         * Makefile.am: Remove h8500 support.
1120         * configure.ac: Likewise.
1121         * disassemble.c: Likewise.
1122         * disassemble.h: Likewise.
1123         * h8500-dis.c: Delete.
1124         * h8500-opc.h: Delete.
1125         * Makefile.in: Regenerate.
1126         * configure: Regenerate.
1127         * po/POTFILES.in: Regenerate.
1128
1129 2018-04-16  Alan Modra  <amodra@gmail.com>
1130
1131         * configure.ac: Remove tahoe support.
1132         * configure: Regenerate.
1133
1134 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1135
1136         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1137         umwait.
1138         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1139         64-bit mode.
1140         * i386-tbl.h: Regenerated.
1141
1142 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1143
1144         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1145         PREFIX_MOD_1_0FAE_REG_6.
1146         (va_mode): New.
1147         (OP_E_register): Use va_mode.
1148         * i386-dis-evex.h (prefix_table):
1149         New instructions (see prefixes above).
1150         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1151         (cpu_flags): Likewise.
1152         * i386-opc.h (enum): Likewise.
1153         (i386_cpu_flags): Likewise.
1154         * i386-opc.tbl: Add umonitor, umwait, tpause.
1155         * i386-init.h: Regenerate.
1156         * i386-tbl.h: Likewise.
1157
1158 2018-04-11  Alan Modra  <amodra@gmail.com>
1159
1160         * opcodes/i860-dis.c: Delete.
1161         * opcodes/i960-dis.c: Delete.
1162         * Makefile.am: Remove i860 and i960 support.
1163         * configure.ac: Likewise.
1164         * disassemble.c: Likewise.
1165         * disassemble.h: Likewise.
1166         * Makefile.in: Regenerate.
1167         * configure: Regenerate.
1168         * po/POTFILES.in: Regenerate.
1169
1170 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1171
1172         PR binutils/23025
1173         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1174         to 0.
1175         (print_insn): Clear vex instead of vex.evex.
1176
1177 2018-04-04  Nick Clifton  <nickc@redhat.com>
1178
1179         * po/es.po: Updated Spanish translation.
1180
1181 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1182
1183         * i386-gen.c (opcode_modifiers): Delete VecESize.
1184         * i386-opc.h (VecESize): Delete.
1185         (struct i386_opcode_modifier): Delete vecesize.
1186         * i386-opc.tbl: Drop VecESize.
1187         * i386-tlb.h: Re-generate.
1188
1189 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1190
1191         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1192         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1193         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1194         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1195         * i386-tlb.h: Re-generate.
1196
1197 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1198
1199         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1200         Fold AVX512 forms
1201         * i386-tlb.h: Re-generate.
1202
1203 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1204
1205         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1206         (vex_len_table): Drop Y for vcvt*2si.
1207         (putop): Replace plain 'Y' handling by abort().
1208
1209 2018-03-28  Nick Clifton  <nickc@redhat.com>
1210
1211         PR 22988
1212         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1213         instructions with only a base address register.
1214         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1215         handle AARHC64_OPND_SVE_ADDR_R.
1216         (aarch64_print_operand): Likewise.
1217         * aarch64-asm-2.c: Regenerate.
1218         * aarch64_dis-2.c: Regenerate.
1219         * aarch64-opc-2.c: Regenerate.
1220
1221 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1222
1223         * i386-opc.tbl: Drop VecESize from register only insn forms and
1224         memory forms not allowing broadcast.
1225         * i386-tlb.h: Re-generate.
1226
1227 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1228
1229         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1230         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1231         sha256*): Drop Disp<N>.
1232
1233 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1234
1235         * i386-dis.c (EbndS, bnd_swap_mode): New.
1236         (prefix_table): Use EbndS.
1237         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1238         * i386-opc.tbl (bndmov): Move misplaced Load.
1239         * i386-tlb.h: Re-generate.
1240
1241 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1242
1243         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1244         templates allowing memory operands and folded ones for register
1245         only flavors.
1246         * i386-tlb.h: Re-generate.
1247
1248 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1249
1250         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1251         256-bit templates. Drop redundant leftover Disp<N>.
1252         * i386-tlb.h: Re-generate.
1253
1254 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1255
1256         * riscv-opc.c (riscv_insn_types): New.
1257
1258 2018-03-13  Nick Clifton  <nickc@redhat.com>
1259
1260         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1261
1262 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1263
1264         * i386-opc.tbl: Add Optimize to clr.
1265         * i386-tbl.h: Regenerated.
1266
1267 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1268
1269         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1270         * i386-opc.h (OldGcc): Removed.
1271         (i386_opcode_modifier): Remove oldgcc.
1272         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1273         instructions for old (<= 2.8.1) versions of gcc.
1274         * i386-tbl.h: Regenerated.
1275
1276 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1277
1278         * i386-opc.h (EVEXDYN): New.
1279         * i386-opc.tbl: Fold various AVX512VL templates.
1280         * i386-tlb.h: Re-generate.
1281
1282 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1283
1284         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1285         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1286         vpexpandd, vpexpandq): Fold AFX512VF templates.
1287         * i386-tlb.h: Re-generate.
1288
1289 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1290
1291         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1292         Fold 128- and 256-bit VEX-encoded templates.
1293         * i386-tlb.h: Re-generate.
1294
1295 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1296
1297         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1298         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1299         vpexpandd, vpexpandq): Fold AVX512F templates.
1300         * i386-tlb.h: Re-generate.
1301
1302 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1303
1304         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1305         64-bit templates. Drop Disp<N>.
1306         * i386-tlb.h: Re-generate.
1307
1308 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1309
1310         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1311         and 256-bit templates.
1312         * i386-tlb.h: Re-generate.
1313
1314 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1315
1316         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1317         * i386-tlb.h: Re-generate.
1318
1319 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1320
1321         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1322         Drop NoAVX.
1323         * i386-tlb.h: Re-generate.
1324
1325 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1326
1327         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1328         * i386-tlb.h: Re-generate.
1329
1330 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1331
1332         * i386-gen.c (opcode_modifiers): Delete FloatD.
1333         * i386-opc.h (FloatD): Delete.
1334         (struct i386_opcode_modifier): Delete floatd.
1335         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1336         FloatD by D.
1337         * i386-tlb.h: Re-generate.
1338
1339 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1340
1341         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1342
1343 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1344
1345         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1346         * i386-tlb.h: Re-generate.
1347
1348 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1349
1350         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1351         forms.
1352         * i386-tlb.h: Re-generate.
1353
1354 2018-03-07  Alan Modra  <amodra@gmail.com>
1355
1356         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1357         bfd_arch_rs6000.
1358         * disassemble.h (print_insn_rs6000): Delete.
1359         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1360         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1361         (print_insn_rs6000): Delete.
1362
1363 2018-03-03  Alan Modra  <amodra@gmail.com>
1364
1365         * sysdep.h (opcodes_error_handler): Define.
1366         (_bfd_error_handler): Declare.
1367         * Makefile.am: Remove stray #.
1368         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1369         EDIT" comment.
1370         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1371         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1372         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1373         opcodes_error_handler to print errors.  Standardize error messages.
1374         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1375         and include opintl.h.
1376         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1377         * i386-gen.c: Standardize error messages.
1378         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1379         * Makefile.in: Regenerate.
1380         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1381         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1382         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1383         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1384         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1385         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1386         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1387         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1388         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1389         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1390         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1391         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1392         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1393
1394 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1395
1396         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1397         vpsub[bwdq] instructions.
1398         * i386-tbl.h: Regenerated.
1399
1400 2018-03-01  Alan Modra  <amodra@gmail.com>
1401
1402         * configure.ac (ALL_LINGUAS): Sort.
1403         * configure: Regenerate.
1404
1405 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1406
1407         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1408         macro by assignements.
1409
1410 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1411
1412         PR gas/22871
1413         * i386-gen.c (opcode_modifiers): Add Optimize.
1414         * i386-opc.h (Optimize): New enum.
1415         (i386_opcode_modifier): Add optimize.
1416         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1417         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1418         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1419         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1420         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1421         vpxord and vpxorq.
1422         * i386-tbl.h: Regenerated.
1423
1424 2018-02-26  Alan Modra  <amodra@gmail.com>
1425
1426         * crx-dis.c (getregliststring): Allocate a large enough buffer
1427         to silence false positive gcc8 warning.
1428
1429 2018-02-22  Shea Levy <shea@shealevy.com>
1430
1431         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1432
1433 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1434
1435         * i386-opc.tbl: Add {rex},
1436         * i386-tbl.h: Regenerated.
1437
1438 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1439
1440         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1441         (mips16_opcodes): Replace `M' with `m' for "restore".
1442
1443 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1444
1445         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1446
1447 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1448
1449         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1450         variable to `function_index'.
1451
1452 2018-02-13  Nick Clifton  <nickc@redhat.com>
1453
1454         PR 22823
1455         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1456         about truncation of printing.
1457
1458 2018-02-12  Henry Wong <henry@stuffedcow.net>
1459
1460         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1461
1462 2018-02-05  Nick Clifton  <nickc@redhat.com>
1463
1464         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1465
1466 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1467
1468         * i386-dis.c (enum): Add pconfig.
1469         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1470         (cpu_flags): Add CpuPCONFIG.
1471         * i386-opc.h (enum): Add CpuPCONFIG.
1472         (i386_cpu_flags): Add cpupconfig.
1473         * i386-opc.tbl: Add PCONFIG instruction.
1474         * i386-init.h: Regenerate.
1475         * i386-tbl.h: Likewise.
1476
1477 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1478
1479         * i386-dis.c (enum): Add PREFIX_0F09.
1480         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1481         (cpu_flags): Add CpuWBNOINVD.
1482         * i386-opc.h (enum): Add CpuWBNOINVD.
1483         (i386_cpu_flags): Add cpuwbnoinvd.
1484         * i386-opc.tbl: Add WBNOINVD instruction.
1485         * i386-init.h: Regenerate.
1486         * i386-tbl.h: Likewise.
1487
1488 2018-01-17  Jim Wilson  <jimw@sifive.com>
1489
1490         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1491
1492 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1493
1494         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1495         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1496         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1497         (cpu_flags): Add CpuIBT, CpuSHSTK.
1498         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1499         (i386_cpu_flags): Add cpuibt, cpushstk.
1500         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1501         * i386-init.h: Regenerate.
1502         * i386-tbl.h: Likewise.
1503
1504 2018-01-16  Nick Clifton  <nickc@redhat.com>
1505
1506         * po/pt_BR.po: Updated Brazilian Portugese translation.
1507         * po/de.po: Updated German translation.
1508
1509 2018-01-15  Jim Wilson  <jimw@sifive.com>
1510
1511         * riscv-opc.c (match_c_nop): New.
1512         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1513
1514 2018-01-15  Nick Clifton  <nickc@redhat.com>
1515
1516         * po/uk.po: Updated Ukranian translation.
1517
1518 2018-01-13  Nick Clifton  <nickc@redhat.com>
1519
1520         * po/opcodes.pot: Regenerated.
1521
1522 2018-01-13  Nick Clifton  <nickc@redhat.com>
1523
1524         * configure: Regenerate.
1525
1526 2018-01-13  Nick Clifton  <nickc@redhat.com>
1527
1528         2.30 branch created.
1529
1530 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1531
1532         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1533         * i386-tbl.h: Regenerate.
1534
1535 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1536
1537         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1538         * i386-tbl.h: Re-generate.
1539
1540 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1541
1542         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1543         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1544         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1545         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1546         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1547         Disp8MemShift of AVX512VL forms.
1548         * i386-tbl.h: Re-generate.
1549
1550 2018-01-09  Jim Wilson  <jimw@sifive.com>
1551
1552         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1553         then the hi_addr value is zero.
1554
1555 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1556
1557         * arm-dis.c (arm_opcodes): Add csdb.
1558         (thumb32_opcodes): Add csdb.
1559
1560 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1561
1562         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1563         * aarch64-asm-2.c: Regenerate.
1564         * aarch64-dis-2.c: Regenerate.
1565         * aarch64-opc-2.c: Regenerate.
1566
1567 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1568
1569         PR gas/22681
1570         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1571         Remove AVX512 vmovd with 64-bit operands.
1572         * i386-tbl.h: Regenerated.
1573
1574 2018-01-05  Jim Wilson  <jimw@sifive.com>
1575
1576         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1577         jalr.
1578
1579 2018-01-03  Alan Modra  <amodra@gmail.com>
1580
1581         Update year range in copyright notice of all files.
1582
1583 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1584
1585         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1586         and OPERAND_TYPE_REGZMM entries.
1587
1588 For older changes see ChangeLog-2017
1589 \f
1590 Copyright (C) 2018 Free Software Foundation, Inc.
1591
1592 Copying and distribution of this file, with or without modification,
1593 are permitted in any medium without royalty provided the copyright
1594 notice and this notice are preserved.
1595
1596 Local Variables:
1597 mode: change-log
1598 left-margin: 8
1599 fill-column: 74
1600 version-control: never
1601 End: