opcodes/ChangeLog

   1 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
   4         TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
   5         RGSR_EL1 and GCR_EL1.
   6         (aarch64_sys_reg_supported_p): New check for above.
   7         (aarch64_pstatefields): New entry for TCO.
   8         (aarch64_pstatefield_supported_p): New check for above.
   9
  10 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  11
  12         * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
  13         * aarch64-asm.h (ins_addr_simple_2): Declare the above.
  14         * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
  15         * aarch64-dis.h (ext_addr_simple_2): Declare the above.
  16         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
  17         AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
  18         (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
  19         * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
  20         (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
  21         * aarch64-asm-2.c: Regenerated.
  22         * aarch64-dis-2.c: Regenerated.
  23         * aarch64-opc-2.c: Regenerated.
  24
  25 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  26
  27         * aarch64-tbl.h (QL_LDG): New.
  28         (aarch64_opcode_table): Add ldg.
  29         * aarch64-asm-2.c: Regenerated.
  30         * aarch64-dis-2.c: Regenerated.
  31         * aarch64-opc-2.c: Regenerated.
  32
  33 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  34
  35         * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
  36         for AARCH64_OPND_QLF_imm_tag.
  37         (operand_general_constraint_met_p): Add case for
  38         AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
  39         (aarch64_print_operand): Likewise.
  40         * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
  41         (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
  42         for both offset and pre/post indexed versions.
  43         (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
  44         * aarch64-asm-2.c: Regenerated.
  45         * aarch64-dis-2.c: Regenerated.
  46         * aarch64-opc-2.c: Regenerated.
  47
  48 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  49
  50         * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
  51         * aarch64-asm-2.c: Regenerated.
  52         * aarch64-dis-2.c: Regenerated.
  53         * aarch64-opc-2.c: Regenerated.
  54
  55 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  56
  57         * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
  58         (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
  59         * aarch64-opc.c (fields): Add entry for imm4_3.
  60         (operand_general_constraint_met_p): Add cases for
  61         AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
  62         (aarch64_print_operand): Likewise.
  63         * aarch64-tbl.h (QL_ADDG): New.
  64         (aarch64_opcode_table): Add addg, subg, irg and gmi.
  65         (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
  66         * aarch64-asm.c (aarch64_ins_imm): Add case for
  67         operand_need_shift_by_four.
  68         * aarch64-asm-2.c: Regenerated.
  69         * aarch64-dis-2.c: Regenerated.
  70         * aarch64-opc-2.c: Regenerated.
  71
  72 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  73
  74         * aarch64-tbl.h (aarch64_feature_memtag): New.
  75         (MEMTAG, MEMTAG_INSN): New.
  76
  77 2018-11-06  Sudakshina Das  <sudi.das@arm.com>
  78
  79         * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
  80         with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
  81
  82 2018-11-06  Alan Modra  <amodra@gmail.com>
  83
  84         * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
  85         (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
  86         (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
  87         (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
  88         Don't return zero on error, insert mask bits instead.
  89         (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
  90         (insert_sh6, extract_sh6): Delete dead code.
  91         (insert_sprbat, insert_sprg): Use unsigned comparisions.
  92         (powerpc_operands <OIMM>): Set shift count rather than using
  93         PPC_OPSHIFT_INV.
  94         <SE_SDH, SE_SDW>: Likewise.  Don't use insert/extract functions.
  95
  96 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
  99         vpbroadcast{d,q} with GPR operand.
 100
 101 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
 104         * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
 105         cases up one level in the hierarchy.
 106
 107 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
 110         MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
 111         (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
 112         into MOD_VEX_0F93_P_3_LEN_0.
 113         (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
 114         operand cases up one level in the hierarchy.
 115
 116 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 117
 118         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
 119         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
 120         EVEX_W_0F3A22_P_2): Delete.
 121         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
 122         entries up one level in the hierarchy.
 123         (OP_E_memory): Handle dq_mode when determining Disp8 shift
 124         value.
 125         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
 126         entries up one level in the hierarchy.
 127         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
 128         VexWIG for AVX flavors.
 129         * i386-tbl.h: Re-generate.
 130
 131 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 132
 133         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
 134         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
 135         vcvtusi2ss, kmovd): Drop VexW=1.
 136         * i386-tbl.h: Re-generate.
 137
 138 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
 141         EVex512, EVexLIG, EVexDYN): New.
 142         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
 143         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
 144         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
 145         of EVex=4 (aka EVexLIG).
 146         * i386-tbl.h: Re-generate.
 147
 148 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
 151         (vpmaxub): Re-order attributes on AVX512BW flavor.
 152         * i386-tbl.h: Re-generate.
 153
 154 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
 157         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
 158         Vex=1 on AVX / AVX2 flavors.
 159         (vpmaxub): Re-order attributes on AVX512BW flavor.
 160         * i386-tbl.h: Re-generate.
 161
 162 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-opc.tbl (VexW0, VexW1): New.
 165         (vphadd*, vphsub*): Use VexW0 on XOP variants.
 166         * i386-tbl.h: Re-generate.
 167
 168 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
 169
 170         * s12z-dis.c (decode_possible_symbol): Add fallback case.
 171         (rel_15_7): Likewise.
 172
 173 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
 174
 175         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
 176         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
 177         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
 178
 179 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
 180
 181         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
 182         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
 183
 184 2018-10-10  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
 187         Size64. Add Size.
 188         * i386-opc.h (Size16, Size32, Size64): Delete.
 189         (Size): New.
 190         (SIZE16, SIZE32, SIZE64): Define.
 191         (struct i386_opcode_modifier): Drop size16, size32, and size64.
 192         Add size.
 193         * i386-opc.tbl (Size16, Size32, Size64): Define.
 194         * i386-tbl.h: Re-generate.
 195
 196 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 197
 198         * aarch64-opc.c (operand_general_constraint_met_p): Add
 199         SSBS in the check for one-bit immediate.
 200         (aarch64_sys_regs): New entry for SSBS.
 201         (aarch64_sys_reg_supported_p): New check for above.
 202         (aarch64_pstatefields): New entry for SSBS.
 203         (aarch64_pstatefield_supported_p): New check for above.
 204
 205 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 206
 207         * aarch64-opc.c (aarch64_sys_regs): New entries for
 208         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
 209         (aarch64_sys_reg_supported_p): New checks for above.
 210
 211 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 212
 213         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
 214         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 215         with the hint immediate.
 216         * aarch64-opc.c (aarch64_hint_options): New entries for
 217         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 218         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 219         while checking for HINT_OPD_F_NOPRINT flag.
 220         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 221         extract value.
 222         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 223         (aarch64_opcode_table): Add entry for BTI.
 224         (AARCH64_OPERANDS): Add new description for BTI targets.
 225         * aarch64-asm-2.c: Regenerate.
 226         * aarch64-dis-2.c: Regenerate.
 227         * aarch64-opc-2.c: Regenerate.
 228
 229 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 230
 231         * aarch64-opc.c (aarch64_sys_regs): New entries for
 232         rndr and rndrrs.
 233         (aarch64_sys_reg_supported_p): New check for above.
 234
 235 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 236
 237         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 238         (aarch64_sys_ins_reg_supported_p): New check for above.
 239
 240 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 241
 242         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 243         AARCH64_OPND_SYSREG_SR.
 244         * aarch64-opc.c (aarch64_print_operand): Likewise.
 245         (aarch64_sys_regs_sr): Define table.
 246         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 247         AARCH64_FEATURE_PREDRES.
 248         * aarch64-tbl.h (aarch64_feature_predres): New.
 249         (PREDRES, PREDRES_INSN): New.
 250         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 251         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 252         * aarch64-asm-2.c: Regenerate.
 253         * aarch64-dis-2.c: Regenerate.
 254         * aarch64-opc-2.c: Regenerate.
 255
 256 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 257
 258         * aarch64-tbl.h (aarch64_feature_sb): New.
 259         (SB, SB_INSN): New.
 260         (aarch64_opcode_table): Add entry for sb.
 261         * aarch64-asm-2.c: Regenerate.
 262         * aarch64-dis-2.c: Regenerate.
 263         * aarch64-opc-2.c: Regenerate.
 264
 265 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 266
 267         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 268         (aarch64_feature_frintts): New.
 269         (FLAGMANIP, FRINTTS): New.
 270         (aarch64_opcode_table): Add entries for xaflag, axflag
 271         and frint[32,64][x,z] instructions.
 272         * aarch64-asm-2.c: Regenerate.
 273         * aarch64-dis-2.c: Regenerate.
 274         * aarch64-opc-2.c: Regenerate.
 275
 276 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 277
 278         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 279         (ARMV8_5, V8_5_INSN): New.
 280
 281 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 282
 283         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 284
 285 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 286
 287         * i386-dis.c (rm_table): Add enclv.
 288         * i386-opc.tbl: Add enclv.
 289         * i386-tbl.h: Regenerated.
 290
 291 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 292
 293         * arm-dis.c (arm_opcodes): Add sb.
 294         (thumb32_opcodes): Likewise.
 295
 296 2018-10-05  Richard Henderson  <rth@twiddle.net>
 297             Stafford Horne  <shorne@gmail.com>
 298
 299         * or1k-desc.c: Regenerate.
 300         * or1k-desc.h: Regenerate.
 301         * or1k-opc.c: Regenerate.
 302         * or1k-opc.h: Regenerate.
 303         * or1k-opinst.c: Regenerate.
 304
 305 2018-10-05  Richard Henderson  <rth@twiddle.net>
 306
 307         * or1k-asm.c: Regenerated.
 308         * or1k-desc.c: Regenerated.
 309         * or1k-desc.h: Regenerated.
 310         * or1k-dis.c: Regenerated.
 311         * or1k-ibld.c: Regenerated.
 312         * or1k-opc.c: Regenerated.
 313         * or1k-opc.h: Regenerated.
 314         * or1k-opinst.c: Regenerated.
 315
 316 2018-10-05  Richard Henderson  <rth@twiddle.net>
 317
 318         * or1k-asm.c: Regenerate.
 319
 320 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 321
 322         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 323         * aarch64-dis.c (print_operands): Refactor to take notes.
 324         (print_verifier_notes): New.
 325         (print_aarch64_insn): Apply constraint verifier.
 326         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 327         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 328
 329 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 330
 331         * aarch64-opc.c (init_insn_block): New.
 332         (verify_constraints, aarch64_is_destructive_by_operands): New.
 333         * aarch64-opc.h (verify_constraints): New.
 334
 335 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 336
 337         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 338         * aarch64-opc.c (verify_ldpsw): Update arguments.
 339
 340 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 341
 342         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 343         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 344
 345 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 346
 347         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 348         * aarch64-dis.c (insn_sequence): New.
 349
 350 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 351
 352         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 353         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 354         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 355         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 356         constraints.
 357         (_SVE_INSNC): New.
 358         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 359         constraints.
 360         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 361         F_SCAN flags.
 362         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 363         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 364         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 365         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 366         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 367         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 368         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 369
 370 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 371
 372         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 373
 374 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 375
 376         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 377         are used when extracting signed fields and converting them to
 378         potentially 64-bit types.
 379
 380 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 381
 382         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 383         * Makefile.in: Re-generate.
 384         * aclocal.m4: Re-generate.
 385         * configure: Re-generate.
 386         * configure.ac: Remove check for -Wno-missing-field-initializers.
 387         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 388         (csky_v2_opcodes): Likewise.
 389
 390 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 391
 392         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 393
 394 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 395
 396         * nds32-asm.c (operand_fields): Remove the unused fields.
 397         (nds32_opcodes): Remove the unused instructions.
 398         * nds32-dis.c (nds32_ex9_info): Removed.
 399         (nds32_parse_opcode): Updated.
 400         (print_insn_nds32): Likewise.
 401         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 402         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 403         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 404         build_opcode_hash_table): New functions.
 405         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 406         nds32_opcode_table): New.
 407         (hw_ktabs): Declare it to a pointer rather than an array.
 408         (build_hash_table): Removed.
 409         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 410         SYN_ROPT and upadte HW_GPR and HW_INT.
 411         * nds32-dis.c (keywords): Remove const.
 412         (match_field): New function.
 413         (nds32_parse_opcode): Updated.
 414         * disassemble.c (disassemble_init_for_target):
 415         Add disassemble_init_nds32.
 416         * nds32-dis.c (eum map_type): New.
 417         (nds32_private_data): Likewise.
 418         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 419         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 420         (print_insn_nds32): Updated.
 421         * nds32-asm.c (parse_aext_reg): Add new parameter.
 422         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 423         are allowed to use.
 424         All callers changed.
 425         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 426         (operand_fields): Add new fields.
 427         (nds32_opcodes): Add new instructions.
 428         (keyword_aridxi_mx): New keyword.
 429         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 430         and NASM_ATTR_ZOL.
 431         (ALU2_1, ALU2_2, ALU2_3): New macros.
 432         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 433
 434 2018-09-17  Kito Cheng  <kito@andestech.com>
 435
 436         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 437
 438 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 439
 440         PR gas/23670
 441         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 442         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 443         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 444         (EVEX_LEN_0F7E_P_1): Likewise.
 445         (EVEX_LEN_0F7E_P_2): Likewise.
 446         (EVEX_LEN_0FD6_P_2): Likewise.
 447         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 448         (EVEX_LEN_TABLE): Likewise.
 449         (EVEX_LEN_0F6E_P_2): New enum.
 450         (EVEX_LEN_0F7E_P_1): Likewise.
 451         (EVEX_LEN_0F7E_P_2): Likewise.
 452         (EVEX_LEN_0FD6_P_2): Likewise.
 453         (evex_len_table): New.
 454         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 455         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 456         * i386-tbl.h: Regenerated.
 457
 458 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         PR gas/23665
 461         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 462         VEX_LEN_0F7E_P_2 entries.
 463         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 464         * i386-tbl.h: Regenerated.
 465
 466 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 467
 468         * i386-dis.c (VZERO_Fixup): Removed.
 469         (VZERO): Likewise.
 470         (VEX_LEN_0F10_P_1): Likewise.
 471         (VEX_LEN_0F10_P_3): Likewise.
 472         (VEX_LEN_0F11_P_1): Likewise.
 473         (VEX_LEN_0F11_P_3): Likewise.
 474         (VEX_LEN_0F2E_P_0): Likewise.
 475         (VEX_LEN_0F2E_P_2): Likewise.
 476         (VEX_LEN_0F2F_P_0): Likewise.
 477         (VEX_LEN_0F2F_P_2): Likewise.
 478         (VEX_LEN_0F51_P_1): Likewise.
 479         (VEX_LEN_0F51_P_3): Likewise.
 480         (VEX_LEN_0F52_P_1): Likewise.
 481         (VEX_LEN_0F53_P_1): Likewise.
 482         (VEX_LEN_0F58_P_1): Likewise.
 483         (VEX_LEN_0F58_P_3): Likewise.
 484         (VEX_LEN_0F59_P_1): Likewise.
 485         (VEX_LEN_0F59_P_3): Likewise.
 486         (VEX_LEN_0F5A_P_1): Likewise.
 487         (VEX_LEN_0F5A_P_3): Likewise.
 488         (VEX_LEN_0F5C_P_1): Likewise.
 489         (VEX_LEN_0F5C_P_3): Likewise.
 490         (VEX_LEN_0F5D_P_1): Likewise.
 491         (VEX_LEN_0F5D_P_3): Likewise.
 492         (VEX_LEN_0F5E_P_1): Likewise.
 493         (VEX_LEN_0F5E_P_3): Likewise.
 494         (VEX_LEN_0F5F_P_1): Likewise.
 495         (VEX_LEN_0F5F_P_3): Likewise.
 496         (VEX_LEN_0FC2_P_1): Likewise.
 497         (VEX_LEN_0FC2_P_3): Likewise.
 498         (VEX_LEN_0F3A0A_P_2): Likewise.
 499         (VEX_LEN_0F3A0B_P_2): Likewise.
 500         (VEX_W_0F10_P_0): Likewise.
 501         (VEX_W_0F10_P_1): Likewise.
 502         (VEX_W_0F10_P_2): Likewise.
 503         (VEX_W_0F10_P_3): Likewise.
 504         (VEX_W_0F11_P_0): Likewise.
 505         (VEX_W_0F11_P_1): Likewise.
 506         (VEX_W_0F11_P_2): Likewise.
 507         (VEX_W_0F11_P_3): Likewise.
 508         (VEX_W_0F12_P_0_M_0): Likewise.
 509         (VEX_W_0F12_P_0_M_1): Likewise.
 510         (VEX_W_0F12_P_1): Likewise.
 511         (VEX_W_0F12_P_2): Likewise.
 512         (VEX_W_0F12_P_3): Likewise.
 513         (VEX_W_0F13_M_0): Likewise.
 514         (VEX_W_0F14): Likewise.
 515         (VEX_W_0F15): Likewise.
 516         (VEX_W_0F16_P_0_M_0): Likewise.
 517         (VEX_W_0F16_P_0_M_1): Likewise.
 518         (VEX_W_0F16_P_1): Likewise.
 519         (VEX_W_0F16_P_2): Likewise.
 520         (VEX_W_0F17_M_0): Likewise.
 521         (VEX_W_0F28): Likewise.
 522         (VEX_W_0F29): Likewise.
 523         (VEX_W_0F2B_M_0): Likewise.
 524         (VEX_W_0F2E_P_0): Likewise.
 525         (VEX_W_0F2E_P_2): Likewise.
 526         (VEX_W_0F2F_P_0): Likewise.
 527         (VEX_W_0F2F_P_2): Likewise.
 528         (VEX_W_0F50_M_0): Likewise.
 529         (VEX_W_0F51_P_0): Likewise.
 530         (VEX_W_0F51_P_1): Likewise.
 531         (VEX_W_0F51_P_2): Likewise.
 532         (VEX_W_0F51_P_3): Likewise.
 533         (VEX_W_0F52_P_0): Likewise.
 534         (VEX_W_0F52_P_1): Likewise.
 535         (VEX_W_0F53_P_0): Likewise.
 536         (VEX_W_0F53_P_1): Likewise.
 537         (VEX_W_0F58_P_0): Likewise.
 538         (VEX_W_0F58_P_1): Likewise.
 539         (VEX_W_0F58_P_2): Likewise.
 540         (VEX_W_0F58_P_3): Likewise.
 541         (VEX_W_0F59_P_0): Likewise.
 542         (VEX_W_0F59_P_1): Likewise.
 543         (VEX_W_0F59_P_2): Likewise.
 544         (VEX_W_0F59_P_3): Likewise.
 545         (VEX_W_0F5A_P_0): Likewise.
 546         (VEX_W_0F5A_P_1): Likewise.
 547         (VEX_W_0F5A_P_3): Likewise.
 548         (VEX_W_0F5B_P_0): Likewise.
 549         (VEX_W_0F5B_P_1): Likewise.
 550         (VEX_W_0F5B_P_2): Likewise.
 551         (VEX_W_0F5C_P_0): Likewise.
 552         (VEX_W_0F5C_P_1): Likewise.
 553         (VEX_W_0F5C_P_2): Likewise.
 554         (VEX_W_0F5C_P_3): Likewise.
 555         (VEX_W_0F5D_P_0): Likewise.
 556         (VEX_W_0F5D_P_1): Likewise.
 557         (VEX_W_0F5D_P_2): Likewise.
 558         (VEX_W_0F5D_P_3): Likewise.
 559         (VEX_W_0F5E_P_0): Likewise.
 560         (VEX_W_0F5E_P_1): Likewise.
 561         (VEX_W_0F5E_P_2): Likewise.
 562         (VEX_W_0F5E_P_3): Likewise.
 563         (VEX_W_0F5F_P_0): Likewise.
 564         (VEX_W_0F5F_P_1): Likewise.
 565         (VEX_W_0F5F_P_2): Likewise.
 566         (VEX_W_0F5F_P_3): Likewise.
 567         (VEX_W_0F60_P_2): Likewise.
 568         (VEX_W_0F61_P_2): Likewise.
 569         (VEX_W_0F62_P_2): Likewise.
 570         (VEX_W_0F63_P_2): Likewise.
 571         (VEX_W_0F64_P_2): Likewise.
 572         (VEX_W_0F65_P_2): Likewise.
 573         (VEX_W_0F66_P_2): Likewise.
 574         (VEX_W_0F67_P_2): Likewise.
 575         (VEX_W_0F68_P_2): Likewise.
 576         (VEX_W_0F69_P_2): Likewise.
 577         (VEX_W_0F6A_P_2): Likewise.
 578         (VEX_W_0F6B_P_2): Likewise.
 579         (VEX_W_0F6C_P_2): Likewise.
 580         (VEX_W_0F6D_P_2): Likewise.
 581         (VEX_W_0F6F_P_1): Likewise.
 582         (VEX_W_0F6F_P_2): Likewise.
 583         (VEX_W_0F70_P_1): Likewise.
 584         (VEX_W_0F70_P_2): Likewise.
 585         (VEX_W_0F70_P_3): Likewise.
 586         (VEX_W_0F71_R_2_P_2): Likewise.
 587         (VEX_W_0F71_R_4_P_2): Likewise.
 588         (VEX_W_0F71_R_6_P_2): Likewise.
 589         (VEX_W_0F72_R_2_P_2): Likewise.
 590         (VEX_W_0F72_R_4_P_2): Likewise.
 591         (VEX_W_0F72_R_6_P_2): Likewise.
 592         (VEX_W_0F73_R_2_P_2): Likewise.
 593         (VEX_W_0F73_R_3_P_2): Likewise.
 594         (VEX_W_0F73_R_6_P_2): Likewise.
 595         (VEX_W_0F73_R_7_P_2): Likewise.
 596         (VEX_W_0F74_P_2): Likewise.
 597         (VEX_W_0F75_P_2): Likewise.
 598         (VEX_W_0F76_P_2): Likewise.
 599         (VEX_W_0F77_P_0): Likewise.
 600         (VEX_W_0F7C_P_2): Likewise.
 601         (VEX_W_0F7C_P_3): Likewise.
 602         (VEX_W_0F7D_P_2): Likewise.
 603         (VEX_W_0F7D_P_3): Likewise.
 604         (VEX_W_0F7E_P_1): Likewise.
 605         (VEX_W_0F7F_P_1): Likewise.
 606         (VEX_W_0F7F_P_2): Likewise.
 607         (VEX_W_0FAE_R_2_M_0): Likewise.
 608         (VEX_W_0FAE_R_3_M_0): Likewise.
 609         (VEX_W_0FC2_P_0): Likewise.
 610         (VEX_W_0FC2_P_1): Likewise.
 611         (VEX_W_0FC2_P_2): Likewise.
 612         (VEX_W_0FC2_P_3): Likewise.
 613         (VEX_W_0FD0_P_2): Likewise.
 614         (VEX_W_0FD0_P_3): Likewise.
 615         (VEX_W_0FD1_P_2): Likewise.
 616         (VEX_W_0FD2_P_2): Likewise.
 617         (VEX_W_0FD3_P_2): Likewise.
 618         (VEX_W_0FD4_P_2): Likewise.
 619         (VEX_W_0FD5_P_2): Likewise.
 620         (VEX_W_0FD6_P_2): Likewise.
 621         (VEX_W_0FD7_P_2_M_1): Likewise.
 622         (VEX_W_0FD8_P_2): Likewise.
 623         (VEX_W_0FD9_P_2): Likewise.
 624         (VEX_W_0FDA_P_2): Likewise.
 625         (VEX_W_0FDB_P_2): Likewise.
 626         (VEX_W_0FDC_P_2): Likewise.
 627         (VEX_W_0FDD_P_2): Likewise.
 628         (VEX_W_0FDE_P_2): Likewise.
 629         (VEX_W_0FDF_P_2): Likewise.
 630         (VEX_W_0FE0_P_2): Likewise.
 631         (VEX_W_0FE1_P_2): Likewise.
 632         (VEX_W_0FE2_P_2): Likewise.
 633         (VEX_W_0FE3_P_2): Likewise.
 634         (VEX_W_0FE4_P_2): Likewise.
 635         (VEX_W_0FE5_P_2): Likewise.
 636         (VEX_W_0FE6_P_1): Likewise.
 637         (VEX_W_0FE6_P_2): Likewise.
 638         (VEX_W_0FE6_P_3): Likewise.
 639         (VEX_W_0FE7_P_2_M_0): Likewise.
 640         (VEX_W_0FE8_P_2): Likewise.
 641         (VEX_W_0FE9_P_2): Likewise.
 642         (VEX_W_0FEA_P_2): Likewise.
 643         (VEX_W_0FEB_P_2): Likewise.
 644         (VEX_W_0FEC_P_2): Likewise.
 645         (VEX_W_0FED_P_2): Likewise.
 646         (VEX_W_0FEE_P_2): Likewise.
 647         (VEX_W_0FEF_P_2): Likewise.
 648         (VEX_W_0FF0_P_3_M_0): Likewise.
 649         (VEX_W_0FF1_P_2): Likewise.
 650         (VEX_W_0FF2_P_2): Likewise.
 651         (VEX_W_0FF3_P_2): Likewise.
 652         (VEX_W_0FF4_P_2): Likewise.
 653         (VEX_W_0FF5_P_2): Likewise.
 654         (VEX_W_0FF6_P_2): Likewise.
 655         (VEX_W_0FF7_P_2): Likewise.
 656         (VEX_W_0FF8_P_2): Likewise.
 657         (VEX_W_0FF9_P_2): Likewise.
 658         (VEX_W_0FFA_P_2): Likewise.
 659         (VEX_W_0FFB_P_2): Likewise.
 660         (VEX_W_0FFC_P_2): Likewise.
 661         (VEX_W_0FFD_P_2): Likewise.
 662         (VEX_W_0FFE_P_2): Likewise.
 663         (VEX_W_0F3800_P_2): Likewise.
 664         (VEX_W_0F3801_P_2): Likewise.
 665         (VEX_W_0F3802_P_2): Likewise.
 666         (VEX_W_0F3803_P_2): Likewise.
 667         (VEX_W_0F3804_P_2): Likewise.
 668         (VEX_W_0F3805_P_2): Likewise.
 669         (VEX_W_0F3806_P_2): Likewise.
 670         (VEX_W_0F3807_P_2): Likewise.
 671         (VEX_W_0F3808_P_2): Likewise.
 672         (VEX_W_0F3809_P_2): Likewise.
 673         (VEX_W_0F380A_P_2): Likewise.
 674         (VEX_W_0F380B_P_2): Likewise.
 675         (VEX_W_0F3817_P_2): Likewise.
 676         (VEX_W_0F381C_P_2): Likewise.
 677         (VEX_W_0F381D_P_2): Likewise.
 678         (VEX_W_0F381E_P_2): Likewise.
 679         (VEX_W_0F3820_P_2): Likewise.
 680         (VEX_W_0F3821_P_2): Likewise.
 681         (VEX_W_0F3822_P_2): Likewise.
 682         (VEX_W_0F3823_P_2): Likewise.
 683         (VEX_W_0F3824_P_2): Likewise.
 684         (VEX_W_0F3825_P_2): Likewise.
 685         (VEX_W_0F3828_P_2): Likewise.
 686         (VEX_W_0F3829_P_2): Likewise.
 687         (VEX_W_0F382A_P_2_M_0): Likewise.
 688         (VEX_W_0F382B_P_2): Likewise.
 689         (VEX_W_0F3830_P_2): Likewise.
 690         (VEX_W_0F3831_P_2): Likewise.
 691         (VEX_W_0F3832_P_2): Likewise.
 692         (VEX_W_0F3833_P_2): Likewise.
 693         (VEX_W_0F3834_P_2): Likewise.
 694         (VEX_W_0F3835_P_2): Likewise.
 695         (VEX_W_0F3837_P_2): Likewise.
 696         (VEX_W_0F3838_P_2): Likewise.
 697         (VEX_W_0F3839_P_2): Likewise.
 698         (VEX_W_0F383A_P_2): Likewise.
 699         (VEX_W_0F383B_P_2): Likewise.
 700         (VEX_W_0F383C_P_2): Likewise.
 701         (VEX_W_0F383D_P_2): Likewise.
 702         (VEX_W_0F383E_P_2): Likewise.
 703         (VEX_W_0F383F_P_2): Likewise.
 704         (VEX_W_0F3840_P_2): Likewise.
 705         (VEX_W_0F3841_P_2): Likewise.
 706         (VEX_W_0F38DB_P_2): Likewise.
 707         (VEX_W_0F3A08_P_2): Likewise.
 708         (VEX_W_0F3A09_P_2): Likewise.
 709         (VEX_W_0F3A0A_P_2): Likewise.
 710         (VEX_W_0F3A0B_P_2): Likewise.
 711         (VEX_W_0F3A0C_P_2): Likewise.
 712         (VEX_W_0F3A0D_P_2): Likewise.
 713         (VEX_W_0F3A0E_P_2): Likewise.
 714         (VEX_W_0F3A0F_P_2): Likewise.
 715         (VEX_W_0F3A21_P_2): Likewise.
 716         (VEX_W_0F3A40_P_2): Likewise.
 717         (VEX_W_0F3A41_P_2): Likewise.
 718         (VEX_W_0F3A42_P_2): Likewise.
 719         (VEX_W_0F3A62_P_2): Likewise.
 720         (VEX_W_0F3A63_P_2): Likewise.
 721         (VEX_W_0F3ADF_P_2): Likewise.
 722         (VEX_LEN_0F77_P_0): New.
 723         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 724         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 725         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 726         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 727         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 728         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 729         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 730         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 731         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 732         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 733         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 734         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 735         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 736         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 737         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 738         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 739         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 740         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 741         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 742         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 743         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 744         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 745         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 746         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 747         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 748         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 749         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 750         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 751         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 752         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 753         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 754         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 755         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 756         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 757         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 758         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 759         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 760         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 761         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 762         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 763         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 764         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 765         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 766         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 767         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 768         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 769         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 770         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 771         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 772         (vex_table): Update VEX 0F28 and 0F29 entries.
 773         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 774         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 775         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 776         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 777         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 778         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 779         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 780         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 781         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 782         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 783         VEX_LEN_0F3A0B_P_2 entries.
 784         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 785         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 786         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 787         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 788         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 789         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 790         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 791         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 792         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 793         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 794         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 795         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 796         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 797         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 798         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 799         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 800         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 801         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 802         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 803         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 804         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 805         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 806         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 807         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 808         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 809         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 810         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 811         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 812         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 813         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 814         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 815         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 816         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 817         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 818         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 819         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 820         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 821         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 822         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 823         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 824         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 825         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 826         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 827         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 828         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 829         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 830         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 831         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 832         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 833         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 834         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 835         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 836         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 837         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 838         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 839         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 840         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 841         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 842         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 843         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 844         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 845         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 846         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 847         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 848         VEX_W_0F3ADF_P_2 entries.
 849         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 850         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 851         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 852
 853 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 854
 855         * i386-opc.tbl (VexWIG): New.
 856         Replace VexW=3 with VexWIG.
 857
 858 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 859
 860         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 861         * i386-tbl.h: Regenerated.
 862
 863 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         PR gas/23665
 866         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 867         VEX_LEN_0FD6_P_2 entries.
 868         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 869         * i386-tbl.h: Regenerated.
 870
 871 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 872
 873         PR gas/23642
 874         * i386-opc.h (VEXWIG): New.
 875         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 876         * i386-tbl.h: Regenerated.
 877
 878 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 879
 880         PR binutils/23655
 881         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 882         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 883         * i386-dis.c (EXxEVexR64): New.
 884         (evex_rounding_64_mode): Likewise.
 885         (OP_Rounding): Handle evex_rounding_64_mode.
 886
 887 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 888
 889         PR binutils/23655
 890         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 891         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 892         * i386-dis.c (Edqa): New.
 893         (dqa_mode): Likewise.
 894         (intel_operand_size): Handle dqa_mode as m_mode.
 895         (OP_E_register): Handle dqa_mode as dq_mode.
 896         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 897
 898 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         * i386-dis.c (OP_E_memory): Reformat.
 901
 902 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 903
 904         * i386-opc.tbl (crc32): Fold byte and word forms.
 905         * i386-tbl.h: Re-generate.
 906
 907 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 908
 909         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 910         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 911         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 912         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 913         * i386-tbl.h: Regenerated.
 914
 915 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 916
 917         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 918         meaningless.
 919         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 920         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 921         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 922         * i386-tbl.h: Re-generate.
 923
 924 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 925
 926         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 927         AVX512_4VNNIW insns.
 928         * i386-tbl.h: Re-generate.
 929
 930 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 931
 932         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 933         meaningless.
 934         * i386-tbl.h: Re-generate.
 935
 936 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 937
 938         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 939         meaningless.
 940         * i386-tbl.h: Re-generate.
 941
 942 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 943
 944         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 945         meaningless.
 946         * i386-tbl.h: Re-generate.
 947
 948 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 949
 950         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 951         meaningless.
 952         * i386-tbl.h: Re-generate.
 953
 954 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 957         meaningless.
 958         * i386-tbl.h: Re-generate.
 959
 960 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 963         * i386-tbl.h: Re-generate.
 964
 965 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 968         * i386-tbl.h: Re-generate.
 969
 970 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 973         meaningless.
 974         * i386-tbl.h: Re-generate.
 975
 976 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 979         meaningless.
 980         * i386-tbl.h: Re-generate.
 981
 982 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 985         * i386-tbl.h: Re-generate.
 986
 987 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 990         * i386-tbl.h: Re-generate.
 991
 992 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 993
 994         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 995         * i386-tbl.h: Re-generate.
 996
 997 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 998
 999         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1000         meaningless.
1001         * i386-tbl.h: Re-generate.
1002
1003 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1004
1005         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1006         meaningless.
1007         * i386-tbl.h: Re-generate.
1008
1009 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1012         meaningless.
1013         * i386-tbl.h: Re-generate.
1014
1015 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1016
1017         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1018         * i386-tbl.h: Re-generate.
1019
1020 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1021
1022         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1023         * i386-tbl.h: Re-generate.
1024
1025 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1026
1027         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1028         * i386-tbl.h: Re-generate.
1029
1030 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1033         (vpbroadcastw, rdpid): Drop NoRex64.
1034         * i386-tbl.h: Re-generate.
1035
1036 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1039         store templates, adding D.
1040         * i386-tbl.h: Re-generate.
1041
1042 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1045         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1046         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1047         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1048         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1049         Fold load and store templates where possible, adding D. Drop
1050         IgnoreSize where it was pointlessly present. Drop redundant
1051         *word.
1052         * i386-tbl.h: Re-generate.
1053
1054 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1057         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1058         (intel_operand_size): Handle v_bndmk_mode.
1059         (OP_E_memory): Likewise. Produce (bad) when also riprel.
1060
1061 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
1062
1063         * disassemble.c (ARCH_s12z): Define if ARCH_all.
1064
1065 2018-08-31  Kito Cheng  <kito@andestech.com>
1066
1067         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1068         compressed floating point instructions.
1069
1070 2018-08-30  Kito Cheng  <kito@andestech.com>
1071
1072         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1073         riscv_opcode.xlen_requirement.
1074         * riscv-opc.c (riscv_opcodes): Update for struct change.
1075
1076 2018-08-29  Martin Aberg  <maberg@gaisler.com>
1077
1078         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1079         psr (PWRPSR) instruction.
1080
1081 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1082
1083         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1084
1085 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1086
1087         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1088
1089 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1090
1091         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1092         loongson3a as an alias of gs464 for compatibility.
1093         * mips-opc.c (mips_opcodes): Change Comments.
1094
1095 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1096
1097         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1098         option.
1099         (print_mips_disassembler_options): Document -M loongson-ext.
1100         * mips-opc.c (LEXT2): New macro.
1101         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1102
1103 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1104
1105          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1106          descriptors.
1107          (parse_mips_ase_option): Handle -M loongson-ext option.
1108          (print_mips_disassembler_options): Document -M loongson-ext.
1109          * mips-opc.c (IL3A): Delete.
1110          * mips-opc.c (LEXT): New macro.
1111          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1112          instructions.
1113
1114 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1115
1116         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1117         descriptors.
1118         (parse_mips_ase_option): Handle -M loongson-cam option.
1119         (print_mips_disassembler_options): Document -M loongson-cam.
1120         * mips-opc.c (LCAM): New macro.
1121         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1122         instructions.
1123
1124 2018-08-21  Alan Modra  <amodra@gmail.com>
1125
1126         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1127         (skip_optional_operands): Count optional operands, and update
1128         ppc_optional_operand_value call.
1129         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1130         (extract_vlensi): Likewise.
1131         (extract_fxm): Return default value for missing optional operand.
1132         (extract_ls, extract_raq, extract_tbr): Likewise.
1133         (insert_sxl, extract_sxl): New functions.
1134         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1135         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1136         flag and extra entry.
1137         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1138         extract_sxl.
1139
1140 2018-08-20  Alan Modra  <amodra@gmail.com>
1141
1142         * sh-opc.h (MASK): Simplify.
1143
1144 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1145
1146         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1147         BM_RESERVED0 or BM_RESERVED1
1148         (bm_rel_decode, bm_n_bytes): Ditto.
1149
1150 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1151
1152         * s12z.h: Delete.
1153
1154 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1155
1156         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1157         address with the addr32 prefix and without base nor index
1158         registers.
1159
1160 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1161
1162         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1163         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1164         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1165         (cpu_flags): Add CpuCMOV and CpuFXSR.
1166         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1167         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1168         * i386-init.h: Regenerated.
1169         * i386-tbl.h: Likewise.
1170
1171 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1172
1173         * arc-regs.h: Update auxiliary registers.
1174
1175 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1176
1177         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1178         (RegIP, RegIZ): Define.
1179         * i386-reg.tbl: Adjust comments.
1180         (rip): Use Qword instead of BaseIndex. Use RegIP.
1181         (eip): Use Dword instead of BaseIndex. Use RegIP.
1182         (riz): Add Qword. Use RegIZ.
1183         (eiz): Add Dword. Use RegIZ.
1184         * i386-tbl.h: Re-generate.
1185
1186 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1187
1188         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1189         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1190         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1191         * i386-tbl.h: Re-generate.
1192
1193 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1194
1195         * i386-gen.c (operand_types): Remove Mem field.
1196         * i386-opc.h (union i386_operand_type): Remove mem field.
1197         * i386-init.h, i386-tbl.h: Re-generate.
1198
1199 2018-08-01  Alan Modra  <amodra@gmail.com>
1200
1201         * po/POTFILES.in: Regenerate.
1202
1203 2018-07-31  Nick Clifton  <nickc@redhat.com>
1204
1205         * po/sv.po: Updated Swedish translation.
1206
1207 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1208
1209         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1210         * i386-init.h, i386-tbl.h: Re-generate.
1211
1212 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1213
1214         * i386-opc.h (ZEROING_MASKING) Rename to ...
1215         (DYNAMIC_MASKING): ... this. Adjust comment.
1216         * i386-opc.tbl (MaskingMorZ): Define.
1217         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1218         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1219         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1220         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1221         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1222         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1223         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1224         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1225         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1226
1227 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1228
1229         * i386-opc.tbl: Use element rather than vector size for AVX512*
1230         scatter/gather insns.
1231         * i386-tbl.h: Re-generate.
1232
1233 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1234
1235         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1236         (cpu_flags): Drop CpuVREX.
1237         * i386-opc.h (CpuVREX): Delete.
1238         (union i386_cpu_flags): Remove cpuvrex.
1239         * i386-init.h, i386-tbl.h: Re-generate.
1240
1241 2018-07-30  Jim Wilson  <jimw@sifive.com>
1242
1243         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1244         fields.
1245         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1246
1247 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1248
1249         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1250         * Makefile.in: Regenerated.
1251         * configure.ac: Add C-SKY.
1252         * configure: Regenerated.
1253         * csky-dis.c: New file.
1254         * csky-opc.h: New file.
1255         * disassemble.c (ARCH_csky): Define.
1256         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1257         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1258
1259 2018-07-27  Alan Modra  <amodra@gmail.com>
1260
1261         * ppc-opc.c (insert_sprbat): Correct function parameter and
1262         return type.
1263         (extract_sprbat): Likewise, variable too.
1264
1265 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1266             Alan Modra  <amodra@gmail.com>
1267
1268         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1269         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1270         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1271         support disjointed BAT.
1272         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1273         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1274         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1275
1276 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1277             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1278
1279         * i386-gen.c (adjust_broadcast_modifier): New function.
1280         (process_i386_opcode_modifier): Add an argument for operands.
1281         Adjust the Broadcast value based on operands.
1282         (output_i386_opcode): Pass operand_types to
1283         process_i386_opcode_modifier.
1284         (process_i386_opcodes): Pass NULL as operands to
1285         process_i386_opcode_modifier.
1286         * i386-opc.h (BYTE_BROADCAST): New.
1287         (WORD_BROADCAST): Likewise.
1288         (DWORD_BROADCAST): Likewise.
1289         (QWORD_BROADCAST): Likewise.
1290         (i386_opcode_modifier): Expand broadcast to 3 bits.
1291         * i386-tbl.h: Regenerated.
1292
1293 2018-07-24  Alan Modra  <amodra@gmail.com>
1294
1295         PR 23430
1296         * or1k-desc.h: Regenerate.
1297
1298 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1299
1300         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1301         vcvtusi2ss, and vcvtusi2sd.
1302         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1303         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1304         * i386-tbl.h: Re-generate.
1305
1306 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1307
1308         * arc-opc.c (extract_w6): Fix extending the sign.
1309
1310 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1311
1312         * arc-tbl.h (vewt): Allow it for ARC EM family.
1313
1314 2018-07-23  Alan Modra  <amodra@gmail.com>
1315
1316         PR 23419
1317         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1318         opcode variants for mtspr/mfspr encodings.
1319
1320 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1321             Maciej W. Rozycki  <macro@mips.com>
1322
1323         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1324         loongson3a descriptors.
1325         (parse_mips_ase_option): Handle -M loongson-mmi option.
1326         (print_mips_disassembler_options): Document -M loongson-mmi.
1327         * mips-opc.c (LMMI): New macro.
1328         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1329         instructions.
1330
1331 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1332
1333         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1334         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1335         IgnoreSize and [XYZ]MMword where applicable.
1336         * i386-tbl.h: Re-generate.
1337
1338 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1339
1340         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1341         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1342         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1343         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1344         * i386-tbl.h: Re-generate.
1345
1346 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1347
1348         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1349         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1350         VPCLMULQDQ templates into their respective AVX512VL counterparts
1351         where possible, using Disp8ShiftVL and CheckRegSize instead of
1352         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1353         * i386-tbl.h: Re-generate.
1354
1355 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1356
1357         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1358         AVX512VL counterparts where possible, using Disp8ShiftVL and
1359         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1360         IgnoreSize) as appropriate.
1361         * i386-tbl.h: Re-generate.
1362
1363 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1364
1365         * i386-opc.tbl: Fold AVX512BW templates into their respective
1366         AVX512VL counterparts where possible, using Disp8ShiftVL and
1367         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1368         IgnoreSize) as appropriate.
1369         * i386-tbl.h: Re-generate.
1370
1371 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1372
1373         * i386-opc.tbl: Fold AVX512CD templates into their respective
1374         AVX512VL counterparts where possible, using Disp8ShiftVL and
1375         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1376         IgnoreSize) as appropriate.
1377         * i386-tbl.h: Re-generate.
1378
1379 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1380
1381         * i386-opc.h (DISP8_SHIFT_VL): New.
1382         * i386-opc.tbl (Disp8ShiftVL):  Define.
1383         (various): Fold AVX512VL templates into their respective
1384         AVX512F counterparts where possible, using Disp8ShiftVL and
1385         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1386         IgnoreSize) as appropriate.
1387         * i386-tbl.h: Re-generate.
1388
1389 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1390
1391         * Makefile.am: Change dependencies and rule for
1392         $(srcdir)/i386-init.h.
1393         * Makefile.in: Re-generate.
1394         * i386-gen.c (process_i386_opcodes): New local variable
1395         "marker". Drop opening of input file. Recognize marker and line
1396         number directives.
1397         * i386-opc.tbl (OPCODE_I386_H): Define.
1398         (i386-opc.h): Include it.
1399         (None): Undefine.
1400
1401 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1402
1403         PR gas/23418
1404         * i386-opc.h (Byte): Update comments.
1405         (Word): Likewise.
1406         (Dword): Likewise.
1407         (Fword): Likewise.
1408         (Qword): Likewise.
1409         (Tbyte): Likewise.
1410         (Xmmword): Likewise.
1411         (Ymmword): Likewise.
1412         (Zmmword): Likewise.
1413         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1414         vcvttps2uqq.
1415         * i386-tbl.h: Regenerated.
1416
1417 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1418
1419         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1420         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1421         * aarch64-asm-2.c: Regenerate.
1422         * aarch64-dis-2.c: Regenerate.
1423         * aarch64-opc-2.c: Regenerate.
1424
1425 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1426
1427         PR binutils/23192
1428         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1429         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1430         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1431         sqdmulh, sqrdmulh): Use Em16.
1432
1433 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1434
1435         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1436         csdb together with them.
1437         (thumb32_opcodes): Likewise.
1438
1439 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1440
1441         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1442         requiring 32-bit registers as operands 2 and 3. Improve
1443         comments.
1444         (mwait, mwaitx): Fold templates. Improve comments.
1445         OPERAND_TYPE_INOUTPORTREG.
1446         * i386-tbl.h: Re-generate.
1447
1448 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1449
1450         * i386-gen.c (operand_type_init): Remove
1451         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1452         OPERAND_TYPE_INOUTPORTREG.
1453         * i386-init.h: Re-generate.
1454
1455 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1456
1457         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1458         (wrssq, wrussq): Add Qword.
1459         * i386-tbl.h: Re-generate.
1460
1461 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1462
1463         * i386-opc.h: Rename OTMax to OTNum.
1464         (OTNumOfUints): Adjust calculation.
1465         (OTUnused): Directly alias to OTNum.
1466
1467 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1468
1469         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1470         `reg_xys'.
1471         (lea_reg_xys): Likewise.
1472         (print_insn_loop_primitive): Rename `reg' local variable to
1473         `reg_dxy'.
1474
1475 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1476
1477         PR binutils/23242
1478         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1479
1480 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1481
1482         PR binutils/23369
1483         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1484         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1485
1486 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1487
1488         PR tdep/8282
1489         * mips-dis.c (mips_option_arg_t): New enumeration.
1490         (mips_options): New variable.
1491         (disassembler_options_mips): New function.
1492         (print_mips_disassembler_options): Reimplement in terms of
1493         `disassembler_options_mips'.
1494         * arm-dis.c (disassembler_options_arm): Adapt to using the
1495         `disasm_options_and_args_t' structure.
1496         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1497         * s390-dis.c (disassembler_options_s390): Likewise.
1498
1499 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1500
1501         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1502         expected result.
1503         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1504         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1505         * testsuite/ld-arm/tls-longplt.d: Likewise.
1506
1507 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1508
1509         PR binutils/23192
1510         * aarch64-asm-2.c: Regenerate.
1511         * aarch64-dis-2.c: Likewise.
1512         * aarch64-opc-2.c: Likewise.
1513         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1514         * aarch64-opc.c (operand_general_constraint_met_p,
1515         aarch64_print_operand): Likewise.
1516         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1517         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1518         fmlal2, fmlsl2.
1519         (AARCH64_OPERANDS): Add Em2.
1520
1521 2018-06-26  Nick Clifton  <nickc@redhat.com>
1522
1523         * po/uk.po: Updated Ukranian translation.
1524         * po/de.po: Updated German translation.
1525         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1526
1527 2018-06-26  Nick Clifton  <nickc@redhat.com>
1528
1529         * nfp-dis.c: Fix spelling mistake.
1530
1531 2018-06-24  Nick Clifton  <nickc@redhat.com>
1532
1533         * configure: Regenerate.
1534         * po/opcodes.pot: Regenerate.
1535
1536 2018-06-24  Nick Clifton  <nickc@redhat.com>
1537
1538         2.31 branch created.
1539
1540 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1541
1542         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1543         * aarch64-asm-2.c: Regenerate.
1544         * aarch64-dis-2.c: Likewise.
1545
1546 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1547
1548         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1549         `-M ginv' option description.
1550
1551 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1552
1553         PR gas/23305
1554         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1555         la and lla.
1556
1557 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1558
1559         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1560         * configure.ac: Remove AC_PREREQ.
1561         * Makefile.in: Re-generate.
1562         * aclocal.m4: Re-generate.
1563         * configure: Re-generate.
1564
1565 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1566
1567         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1568         mips64r6 descriptors.
1569         (parse_mips_ase_option): Handle -Mginv option.
1570         (print_mips_disassembler_options): Document -Mginv.
1571         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1572         (GINV): New macro.
1573         (mips_opcodes): Define ginvi and ginvt.
1574
1575 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1576             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1577
1578         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1579         * mips-opc.c (CRC, CRC64): New macros.
1580         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1581         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1582         crc32cd for CRC64.
1583
1584 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1585
1586         PR 20319
1587         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1588         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1589
1590 2018-06-06  Alan Modra  <amodra@gmail.com>
1591
1592         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1593         setjmp.  Move init for some other vars later too.
1594
1595 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1596
1597         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1598         (dis_private): Add new fields for property section tracking.
1599         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1600         (xtensa_instruction_fits): New functions.
1601         (fetch_data): Bump minimal fetch size to 4.
1602         (print_insn_xtensa): Make struct dis_private static.
1603         Load and prepare property table on section change.
1604         Don't disassemble literals. Don't disassemble instructions that
1605         cross property table boundaries.
1606
1607 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1608
1609         * configure: Regenerated.
1610
1611 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1612
1613         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1614         * i386-tbl.h: Re-generate.
1615
1616 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1617
1618         * i386-opc.tbl (sldt, str): Add NoRex64.
1619         * i386-tbl.h: Re-generate.
1620
1621 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1622
1623         * i386-opc.tbl (invpcid): Add Oword.
1624         * i386-tbl.h: Re-generate.
1625
1626 2018-06-01  Alan Modra  <amodra@gmail.com>
1627
1628         * sysdep.h (_bfd_error_handler): Don't declare.
1629         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1630         * rl78-decode.opc: Likewise.
1631         * msp430-decode.c: Regenerate.
1632         * rl78-decode.c: Regenerate.
1633
1634 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1635
1636         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1637         * i386-init.h : Regenerated.
1638
1639 2018-05-25  Alan Modra  <amodra@gmail.com>
1640
1641         * Makefile.in: Regenerate.
1642         * po/POTFILES.in: Regenerate.
1643
1644 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1645
1646         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1647         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1648         (insert_bab, extract_bab, insert_btab, extract_btab,
1649         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1650         (BAT, BBA VBA RBS XB6S): Delete macros.
1651         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1652         (BB, BD, RBX, XC6): Update for new macros.
1653         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1654         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1655         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1656         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1657
1658 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1659
1660         * Makefile.am: Add support for s12z architecture.
1661         * configure.ac: Likewise.
1662         * disassemble.c: Likewise.
1663         * disassemble.h: Likewise.
1664         * Makefile.in: Regenerate.
1665         * configure: Regenerate.
1666         * s12z-dis.c: New file.
1667         * s12z.h: New file.
1668
1669 2018-05-18  Alan Modra  <amodra@gmail.com>
1670
1671         * nfp-dis.c: Don't #include libbfd.h.
1672         (init_nfp3200_priv): Use bfd_get_section_contents.
1673         (nit_nfp6000_mecsr_sec): Likewise.
1674
1675 2018-05-17  Nick Clifton  <nickc@redhat.com>
1676
1677         * po/zh_CN.po: Updated simplified Chinese translation.
1678
1679 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1680
1681         PR binutils/23109
1682         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1683         * aarch64-dis-2.c: Regenerate.
1684
1685 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1686
1687         PR binutils/21446
1688         * aarch64-asm.c (opintl.h): Include.
1689         (aarch64_ins_sysreg): Enforce read/write constraints.
1690         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1691         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1692         (F_REG_READ, F_REG_WRITE): New.
1693         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1694         AARCH64_OPND_SYSREG.
1695         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1696         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1697         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1698         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1699         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1700         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1701         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1702         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1703         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1704         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1705         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1706         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1707         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1708         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1709         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1710         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1711         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1712
1713 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1714
1715         PR binutils/21446
1716         * aarch64-dis.c (no_notes: New.
1717         (parse_aarch64_dis_option): Support notes.
1718         (aarch64_decode_insn, print_operands): Likewise.
1719         (print_aarch64_disassembler_options): Document notes.
1720         * aarch64-opc.c (aarch64_print_operand): Support notes.
1721
1722 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1723
1724         PR binutils/21446
1725         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1726         and take error struct.
1727         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1728         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1729         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1730         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1731         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1732         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1733         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1734         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1735         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1736         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1737         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1738         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1739         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1740         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1741         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1742         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1743         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1744         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1745         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1746         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1747         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1748         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1749         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1750         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1751         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1752         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1753         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1754         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1755         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1756         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1757         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1758         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1759         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1760         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1761         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1762         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1763         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1764         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1765         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1766         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1767         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1768         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1769         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1770         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1771         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1772         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1773         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1774         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1775         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1776         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1777         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1778         (determine_disassembling_preference, aarch64_decode_insn,
1779         print_insn_aarch64_word, print_insn_data): Take errors struct.
1780         (print_insn_aarch64): Use errors.
1781         * aarch64-asm-2.c: Regenerate.
1782         * aarch64-dis-2.c: Regenerate.
1783         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1784         boolean in aarch64_insert_operan.
1785         (print_operand_extractor): Likewise.
1786         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1787
1788 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1789
1790         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1791
1792 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1793
1794         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1795
1796 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1797
1798         * cr16-opc.c (cr16_instruction): Comment typo fix.
1799         * hppa-dis.c (print_insn_hppa): Likewise.
1800
1801 2018-05-08  Jim Wilson  <jimw@sifive.com>
1802
1803         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1804         (match_c_slli64, match_srxi_as_c_srxi): New.
1805         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1806         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1807         <c.slli, c.srli, c.srai>: Use match_s_slli.
1808         <c.slli64, c.srli64, c.srai64>: New.
1809
1810 2018-05-08  Alan Modra  <amodra@gmail.com>
1811
1812         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1813         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1814         partition opcode space for index lookup.
1815
1816 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1817
1818         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1819         <insn_length>: ...with this.  Update usage.
1820         Remove duplicate call to *info->memory_error_func.
1821
1822 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1823             H.J. Lu  <hongjiu.lu@intel.com>
1824
1825         * i386-dis.c (Gva): New.
1826         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1827         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1828         (prefix_table): New instructions (see prefix above).
1829         (mod_table): New instructions (see prefix above).
1830         (OP_G): Handle va_mode.
1831         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1832         CPU_MOVDIR64B_FLAGS.
1833         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1834         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1835         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1836         * i386-opc.tbl: Add movidir{i,64b}.
1837         * i386-init.h: Regenerated.
1838         * i386-tbl.h: Likewise.
1839
1840 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1841
1842         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1843         AddrPrefixOpReg.
1844         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1845         (AddrPrefixOpReg): This.
1846         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1847         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1848
1849 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1850
1851         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1852         (vle_num_opcodes): Likewise.
1853         (spe2_num_opcodes): Likewise.
1854         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1855         initialization loop.
1856         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1857         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1858         only once.
1859
1860 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1861
1862         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1863
1864 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1865
1866         Makefile.am: Added nfp-dis.c.
1867         configure.ac: Added bfd_nfp_arch.
1868         disassemble.h: Added print_insn_nfp prototype.
1869         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1870         nfp-dis.c: New, for NFP support.
1871         po/POTFILES.in: Added nfp-dis.c to the list.
1872         Makefile.in: Regenerate.
1873         configure: Regenerate.
1874
1875 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1876
1877         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1878         templates into their base ones.
1879         * i386-tlb.h: Re-generate.
1880
1881 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1882
1883         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1884         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1885         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1886         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1887         * i386-init.h: Re-generate.
1888
1889 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1890
1891         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1892         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1893         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1894         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1895         comment.
1896         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1897         and CpuRegMask.
1898         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1899         CpuRegMask: Delete.
1900         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1901         cpuregzmm, and cpuregmask.
1902         * i386-init.h: Re-generate.
1903         * i386-tbl.h: Re-generate.
1904
1905 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1906
1907         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1908         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1909         * i386-init.h: Re-generate.
1910
1911 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1912
1913         * i386-gen.c (VexImmExt): Delete.
1914         * i386-opc.h (VexImmExt, veximmext): Delete.
1915         * i386-opc.tbl: Drop all VexImmExt uses.
1916         * i386-tlb.h: Re-generate.
1917
1918 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1919
1920         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1921         register-only forms.
1922         * i386-tlb.h: Re-generate.
1923
1924 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1925
1926         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1927
1928 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1929
1930         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1931         PREFIX_0F1C.
1932         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1933         (cpu_flags): Add CpuCLDEMOTE.
1934         * i386-init.h: Regenerate.
1935         * i386-opc.h (enum): Add CpuCLDEMOTE,
1936         (i386_cpu_flags): Add cpucldemote.
1937         * i386-opc.tbl: Add cldemote.
1938         * i386-tbl.h: Regenerate.
1939
1940 2018-04-16  Alan Modra  <amodra@gmail.com>
1941
1942         * Makefile.am: Remove sh5 and sh64 support.
1943         * configure.ac: Likewise.
1944         * disassemble.c: Likewise.
1945         * disassemble.h: Likewise.
1946         * sh-dis.c: Likewise.
1947         * sh64-dis.c: Delete.
1948         * sh64-opc.c: Delete.
1949         * sh64-opc.h: Delete.
1950         * Makefile.in: Regenerate.
1951         * configure: Regenerate.
1952         * po/POTFILES.in: Regenerate.
1953
1954 2018-04-16  Alan Modra  <amodra@gmail.com>
1955
1956         * Makefile.am: Remove w65 support.
1957         * configure.ac: Likewise.
1958         * disassemble.c: Likewise.
1959         * disassemble.h: Likewise.
1960         * w65-dis.c: Delete.
1961         * w65-opc.h: Delete.
1962         * Makefile.in: Regenerate.
1963         * configure: Regenerate.
1964         * po/POTFILES.in: Regenerate.
1965
1966 2018-04-16  Alan Modra  <amodra@gmail.com>
1967
1968         * configure.ac: Remove we32k support.
1969         * configure: Regenerate.
1970
1971 2018-04-16  Alan Modra  <amodra@gmail.com>
1972
1973         * Makefile.am: Remove m88k support.
1974         * configure.ac: Likewise.
1975         * disassemble.c: Likewise.
1976         * disassemble.h: Likewise.
1977         * m88k-dis.c: Delete.
1978         * Makefile.in: Regenerate.
1979         * configure: Regenerate.
1980         * po/POTFILES.in: Regenerate.
1981
1982 2018-04-16  Alan Modra  <amodra@gmail.com>
1983
1984         * Makefile.am: Remove i370 support.
1985         * configure.ac: Likewise.
1986         * disassemble.c: Likewise.
1987         * disassemble.h: Likewise.
1988         * i370-dis.c: Delete.
1989         * i370-opc.c: Delete.
1990         * Makefile.in: Regenerate.
1991         * configure: Regenerate.
1992         * po/POTFILES.in: Regenerate.
1993
1994 2018-04-16  Alan Modra  <amodra@gmail.com>
1995
1996         * Makefile.am: Remove h8500 support.
1997         * configure.ac: Likewise.
1998         * disassemble.c: Likewise.
1999         * disassemble.h: Likewise.
2000         * h8500-dis.c: Delete.
2001         * h8500-opc.h: Delete.
2002         * Makefile.in: Regenerate.
2003         * configure: Regenerate.
2004         * po/POTFILES.in: Regenerate.
2005
2006 2018-04-16  Alan Modra  <amodra@gmail.com>
2007
2008         * configure.ac: Remove tahoe support.
2009         * configure: Regenerate.
2010
2011 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
2012
2013         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2014         umwait.
2015         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2016         64-bit mode.
2017         * i386-tbl.h: Regenerated.
2018
2019 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2020
2021         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2022         PREFIX_MOD_1_0FAE_REG_6.
2023         (va_mode): New.
2024         (OP_E_register): Use va_mode.
2025         * i386-dis-evex.h (prefix_table):
2026         New instructions (see prefixes above).
2027         * i386-gen.c (cpu_flag_init): Add WAITPKG.
2028         (cpu_flags): Likewise.
2029         * i386-opc.h (enum): Likewise.
2030         (i386_cpu_flags): Likewise.
2031         * i386-opc.tbl: Add umonitor, umwait, tpause.
2032         * i386-init.h: Regenerate.
2033         * i386-tbl.h: Likewise.
2034
2035 2018-04-11  Alan Modra  <amodra@gmail.com>
2036
2037         * opcodes/i860-dis.c: Delete.
2038         * opcodes/i960-dis.c: Delete.
2039         * Makefile.am: Remove i860 and i960 support.
2040         * configure.ac: Likewise.
2041         * disassemble.c: Likewise.
2042         * disassemble.h: Likewise.
2043         * Makefile.in: Regenerate.
2044         * configure: Regenerate.
2045         * po/POTFILES.in: Regenerate.
2046
2047 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
2048
2049         PR binutils/23025
2050         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2051         to 0.
2052         (print_insn): Clear vex instead of vex.evex.
2053
2054 2018-04-04  Nick Clifton  <nickc@redhat.com>
2055
2056         * po/es.po: Updated Spanish translation.
2057
2058 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2059
2060         * i386-gen.c (opcode_modifiers): Delete VecESize.
2061         * i386-opc.h (VecESize): Delete.
2062         (struct i386_opcode_modifier): Delete vecesize.
2063         * i386-opc.tbl: Drop VecESize.
2064         * i386-tlb.h: Re-generate.
2065
2066 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2067
2068         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2069         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2070         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2071         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2072         * i386-tlb.h: Re-generate.
2073
2074 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2075
2076         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2077         Fold AVX512 forms
2078         * i386-tlb.h: Re-generate.
2079
2080 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2081
2082         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2083         (vex_len_table): Drop Y for vcvt*2si.
2084         (putop): Replace plain 'Y' handling by abort().
2085
2086 2018-03-28  Nick Clifton  <nickc@redhat.com>
2087
2088         PR 22988
2089         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2090         instructions with only a base address register.
2091         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2092         handle AARHC64_OPND_SVE_ADDR_R.
2093         (aarch64_print_operand): Likewise.
2094         * aarch64-asm-2.c: Regenerate.
2095         * aarch64_dis-2.c: Regenerate.
2096         * aarch64-opc-2.c: Regenerate.
2097
2098 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2099
2100         * i386-opc.tbl: Drop VecESize from register only insn forms and
2101         memory forms not allowing broadcast.
2102         * i386-tlb.h: Re-generate.
2103
2104 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2105
2106         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2107         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2108         sha256*): Drop Disp<N>.
2109
2110 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2111
2112         * i386-dis.c (EbndS, bnd_swap_mode): New.
2113         (prefix_table): Use EbndS.
2114         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2115         * i386-opc.tbl (bndmov): Move misplaced Load.
2116         * i386-tlb.h: Re-generate.
2117
2118 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2119
2120         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2121         templates allowing memory operands and folded ones for register
2122         only flavors.
2123         * i386-tlb.h: Re-generate.
2124
2125 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2126
2127         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2128         256-bit templates. Drop redundant leftover Disp<N>.
2129         * i386-tlb.h: Re-generate.
2130
2131 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2132
2133         * riscv-opc.c (riscv_insn_types): New.
2134
2135 2018-03-13  Nick Clifton  <nickc@redhat.com>
2136
2137         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2138
2139 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2140
2141         * i386-opc.tbl: Add Optimize to clr.
2142         * i386-tbl.h: Regenerated.
2143
2144 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2145
2146         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2147         * i386-opc.h (OldGcc): Removed.
2148         (i386_opcode_modifier): Remove oldgcc.
2149         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2150         instructions for old (<= 2.8.1) versions of gcc.
2151         * i386-tbl.h: Regenerated.
2152
2153 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2154
2155         * i386-opc.h (EVEXDYN): New.
2156         * i386-opc.tbl: Fold various AVX512VL templates.
2157         * i386-tlb.h: Re-generate.
2158
2159 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2160
2161         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2162         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2163         vpexpandd, vpexpandq): Fold AFX512VF templates.
2164         * i386-tlb.h: Re-generate.
2165
2166 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2167
2168         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2169         Fold 128- and 256-bit VEX-encoded templates.
2170         * i386-tlb.h: Re-generate.
2171
2172 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2173
2174         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2175         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2176         vpexpandd, vpexpandq): Fold AVX512F templates.
2177         * i386-tlb.h: Re-generate.
2178
2179 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2180
2181         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2182         64-bit templates. Drop Disp<N>.
2183         * i386-tlb.h: Re-generate.
2184
2185 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2186
2187         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2188         and 256-bit templates.
2189         * i386-tlb.h: Re-generate.
2190
2191 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2192
2193         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2194         * i386-tlb.h: Re-generate.
2195
2196 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2197
2198         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2199         Drop NoAVX.
2200         * i386-tlb.h: Re-generate.
2201
2202 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2203
2204         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2205         * i386-tlb.h: Re-generate.
2206
2207 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2208
2209         * i386-gen.c (opcode_modifiers): Delete FloatD.
2210         * i386-opc.h (FloatD): Delete.
2211         (struct i386_opcode_modifier): Delete floatd.
2212         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2213         FloatD by D.
2214         * i386-tlb.h: Re-generate.
2215
2216 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2217
2218         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2219
2220 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2221
2222         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2223         * i386-tlb.h: Re-generate.
2224
2225 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2226
2227         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2228         forms.
2229         * i386-tlb.h: Re-generate.
2230
2231 2018-03-07  Alan Modra  <amodra@gmail.com>
2232
2233         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2234         bfd_arch_rs6000.
2235         * disassemble.h (print_insn_rs6000): Delete.
2236         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2237         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2238         (print_insn_rs6000): Delete.
2239
2240 2018-03-03  Alan Modra  <amodra@gmail.com>
2241
2242         * sysdep.h (opcodes_error_handler): Define.
2243         (_bfd_error_handler): Declare.
2244         * Makefile.am: Remove stray #.
2245         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2246         EDIT" comment.
2247         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2248         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2249         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2250         opcodes_error_handler to print errors.  Standardize error messages.
2251         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2252         and include opintl.h.
2253         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2254         * i386-gen.c: Standardize error messages.
2255         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2256         * Makefile.in: Regenerate.
2257         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2258         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2259         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2260         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2261         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2262         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2263         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2264         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2265         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2266         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2267         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2268         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2269         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2270
2271 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2272
2273         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2274         vpsub[bwdq] instructions.
2275         * i386-tbl.h: Regenerated.
2276
2277 2018-03-01  Alan Modra  <amodra@gmail.com>
2278
2279         * configure.ac (ALL_LINGUAS): Sort.
2280         * configure: Regenerate.
2281
2282 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2283
2284         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2285         macro by assignements.
2286
2287 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2288
2289         PR gas/22871
2290         * i386-gen.c (opcode_modifiers): Add Optimize.
2291         * i386-opc.h (Optimize): New enum.
2292         (i386_opcode_modifier): Add optimize.
2293         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2294         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2295         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2296         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2297         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2298         vpxord and vpxorq.
2299         * i386-tbl.h: Regenerated.
2300
2301 2018-02-26  Alan Modra  <amodra@gmail.com>
2302
2303         * crx-dis.c (getregliststring): Allocate a large enough buffer
2304         to silence false positive gcc8 warning.
2305
2306 2018-02-22  Shea Levy <shea@shealevy.com>
2307
2308         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2309
2310 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2311
2312         * i386-opc.tbl: Add {rex},
2313         * i386-tbl.h: Regenerated.
2314
2315 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2316
2317         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2318         (mips16_opcodes): Replace `M' with `m' for "restore".
2319
2320 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2321
2322         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2323
2324 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2325
2326         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2327         variable to `function_index'.
2328
2329 2018-02-13  Nick Clifton  <nickc@redhat.com>
2330
2331         PR 22823
2332         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2333         about truncation of printing.
2334
2335 2018-02-12  Henry Wong <henry@stuffedcow.net>
2336
2337         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2338
2339 2018-02-05  Nick Clifton  <nickc@redhat.com>
2340
2341         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2342
2343 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2344
2345         * i386-dis.c (enum): Add pconfig.
2346         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2347         (cpu_flags): Add CpuPCONFIG.
2348         * i386-opc.h (enum): Add CpuPCONFIG.
2349         (i386_cpu_flags): Add cpupconfig.
2350         * i386-opc.tbl: Add PCONFIG instruction.
2351         * i386-init.h: Regenerate.
2352         * i386-tbl.h: Likewise.
2353
2354 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2355
2356         * i386-dis.c (enum): Add PREFIX_0F09.
2357         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2358         (cpu_flags): Add CpuWBNOINVD.
2359         * i386-opc.h (enum): Add CpuWBNOINVD.
2360         (i386_cpu_flags): Add cpuwbnoinvd.
2361         * i386-opc.tbl: Add WBNOINVD instruction.
2362         * i386-init.h: Regenerate.
2363         * i386-tbl.h: Likewise.
2364
2365 2018-01-17  Jim Wilson  <jimw@sifive.com>
2366
2367         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2368
2369 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2370
2371         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2372         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2373         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2374         (cpu_flags): Add CpuIBT, CpuSHSTK.
2375         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2376         (i386_cpu_flags): Add cpuibt, cpushstk.
2377         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2378         * i386-init.h: Regenerate.
2379         * i386-tbl.h: Likewise.
2380
2381 2018-01-16  Nick Clifton  <nickc@redhat.com>
2382
2383         * po/pt_BR.po: Updated Brazilian Portugese translation.
2384         * po/de.po: Updated German translation.
2385
2386 2018-01-15  Jim Wilson  <jimw@sifive.com>
2387
2388         * riscv-opc.c (match_c_nop): New.
2389         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2390
2391 2018-01-15  Nick Clifton  <nickc@redhat.com>
2392
2393         * po/uk.po: Updated Ukranian translation.
2394
2395 2018-01-13  Nick Clifton  <nickc@redhat.com>
2396
2397         * po/opcodes.pot: Regenerated.
2398
2399 2018-01-13  Nick Clifton  <nickc@redhat.com>
2400
2401         * configure: Regenerate.
2402
2403 2018-01-13  Nick Clifton  <nickc@redhat.com>
2404
2405         2.30 branch created.
2406
2407 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2408
2409         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2410         * i386-tbl.h: Regenerate.
2411
2412 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2413
2414         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2415         * i386-tbl.h: Re-generate.
2416
2417 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2418
2419         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2420         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2421         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2422         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2423         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2424         Disp8MemShift of AVX512VL forms.
2425         * i386-tbl.h: Re-generate.
2426
2427 2018-01-09  Jim Wilson  <jimw@sifive.com>
2428
2429         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2430         then the hi_addr value is zero.
2431
2432 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2433
2434         * arm-dis.c (arm_opcodes): Add csdb.
2435         (thumb32_opcodes): Add csdb.
2436
2437 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2438
2439         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2440         * aarch64-asm-2.c: Regenerate.
2441         * aarch64-dis-2.c: Regenerate.
2442         * aarch64-opc-2.c: Regenerate.
2443
2444 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2445
2446         PR gas/22681
2447         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2448         Remove AVX512 vmovd with 64-bit operands.
2449         * i386-tbl.h: Regenerated.
2450
2451 2018-01-05  Jim Wilson  <jimw@sifive.com>
2452
2453         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2454         jalr.
2455
2456 2018-01-03  Alan Modra  <amodra@gmail.com>
2457
2458         Update year range in copyright notice of all files.
2459
2460 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2461
2462         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2463         and OPERAND_TYPE_REGZMM entries.
2464
2465 For older changes see ChangeLog-2017
2466 \f
2467 Copyright (C) 2018 Free Software Foundation, Inc.
2468
2469 Copying and distribution of this file, with or without modification,
2470 are permitted in any medium without royalty provided the copyright
2471 notice and this notice are preserved.
2472
2473 Local Variables:
2474 mode: change-log
2475 left-margin: 8
2476 fill-column: 74
2477 version-control: never
2478 End: