opcodes/ChangeLog

   1 2020-06-09  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (rex_ignored): Delete.
   4         (ckprefix): Drop rex_ignored initialization.
   5         (get_valid_dis386): Drop setting of rex_ignored.
   6         (print_insn): Drop checking of rex_ignored. Don't record data
   7         size prefix as used with VEX-and-alike encodings.
   8
   9 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
  12         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
  13         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
  14         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
  15         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
  16         VEX_0F12, and VEX_0F16.
  17         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
  18         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
  19         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
  20         from movlps and movhlps. New MOD_0F12_PREFIX_2,
  21         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
  22         MOD_VEX_0F16_PREFIX_2 entries.
  23
  24 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  25
  26         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
  27         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
  28         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  29         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
  30         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
  31         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
  32         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
  33         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
  34         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
  35         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
  36         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
  37         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
  38         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
  39         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
  40         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
  41         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
  42         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
  43         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
  44         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
  45         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
  46         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
  47         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
  48         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
  49         EVEX_W_0FC6_P_2): Delete.
  50         (print_insn): Add EVEX.W vs embedded prefix consistency check
  51         to prefix validation.
  52         * i386-dis-evex.h (evex_table): Don't further descend for
  53         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
  54         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
  55         and 0F2B.
  56         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
  57         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
  58         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
  59         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
  60         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
  61         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  62         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
  63         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
  64         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
  65         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
  66         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
  67         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
  68         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
  69         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
  70         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
  71         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
  72         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
  73         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
  74         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
  75         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
  76         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
  77         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
  78         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
  79         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
  80         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
  81         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
  82         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
  83
  84 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
  87         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
  88         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
  89         vmovmskpX.
  90         (print_insn): Drop pointless check against bad_opcode. Split
  91         prefix validation into legacy and VEX-and-alike parts.
  92         (putop): Re-work 'X' macro handling.
  93
  94 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  95
  96         * i386-dis.c (MOD_0F51): Rename to ...
  97         (MOD_0F50): ... this.
  98
  99 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 100
 101         * arm-dis.c (arm_opcodes): Add dfb.
 102         (thumb32_opcodes): Add dfb.
 103
 104 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 105
 106         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 107
 108 2020-06-06  Alan Modra  <amodra@gmail.com>
 109
 110         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 111
 112 2020-06-05  Alan Modra  <amodra@gmail.com>
 113
 114         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 115         size is large enough.
 116
 117 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 118
 119         * disassemble.c (disassemble_init_for_target): Set endian_code for
 120         bpf targets.
 121         * bpf-desc.c: Regenerate.
 122         * bpf-opc.c: Likewise.
 123         * bpf-dis.c: Likewise.
 124
 125 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 126
 127         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 128         (cgen_put_insn_value): Likewise.
 129         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 130         * cgen-dis.in (print_insn): Likewise.
 131         * cgen-ibld.in (insert_1): Likewise.
 132         (insert_1): Likewise.
 133         (insert_insn_normal): Likewise.
 134         (extract_1): Likewise.
 135         * bpf-dis.c: Regenerate.
 136         * bpf-ibld.c: Likewise.
 137         * bpf-ibld.c: Likewise.
 138         * cgen-dis.in: Likewise.
 139         * cgen-ibld.in: Likewise.
 140         * cgen-opc.c: Likewise.
 141         * epiphany-dis.c: Likewise.
 142         * epiphany-ibld.c: Likewise.
 143         * fr30-dis.c: Likewise.
 144         * fr30-ibld.c: Likewise.
 145         * frv-dis.c: Likewise.
 146         * frv-ibld.c: Likewise.
 147         * ip2k-dis.c: Likewise.
 148         * ip2k-ibld.c: Likewise.
 149         * iq2000-dis.c: Likewise.
 150         * iq2000-ibld.c: Likewise.
 151         * lm32-dis.c: Likewise.
 152         * lm32-ibld.c: Likewise.
 153         * m32c-dis.c: Likewise.
 154         * m32c-ibld.c: Likewise.
 155         * m32r-dis.c: Likewise.
 156         * m32r-ibld.c: Likewise.
 157         * mep-dis.c: Likewise.
 158         * mep-ibld.c: Likewise.
 159         * mt-dis.c: Likewise.
 160         * mt-ibld.c: Likewise.
 161         * or1k-dis.c: Likewise.
 162         * or1k-ibld.c: Likewise.
 163         * xc16x-dis.c: Likewise.
 164         * xc16x-ibld.c: Likewise.
 165         * xstormy16-dis.c: Likewise.
 166         * xstormy16-ibld.c: Likewise.
 167
 168 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 169
 170         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 171         (print_insn_): Handle instruction endian.
 172         * bpf-dis.c: Regenerate.
 173         * bpf-desc.c: Regenerate.
 174         * epiphany-dis.c: Likewise.
 175         * epiphany-desc.c: Likewise.
 176         * fr30-dis.c: Likewise.
 177         * fr30-desc.c: Likewise.
 178         * frv-dis.c: Likewise.
 179         * frv-desc.c: Likewise.
 180         * ip2k-dis.c: Likewise.
 181         * ip2k-desc.c: Likewise.
 182         * iq2000-dis.c: Likewise.
 183         * iq2000-desc.c: Likewise.
 184         * lm32-dis.c: Likewise.
 185         * lm32-desc.c: Likewise.
 186         * m32c-dis.c: Likewise.
 187         * m32c-desc.c: Likewise.
 188         * m32r-dis.c: Likewise.
 189         * m32r-desc.c: Likewise.
 190         * mep-dis.c: Likewise.
 191         * mep-desc.c: Likewise.
 192         * mt-dis.c: Likewise.
 193         * mt-desc.c: Likewise.
 194         * or1k-dis.c: Likewise.
 195         * or1k-desc.c: Likewise.
 196         * xc16x-dis.c: Likewise.
 197         * xc16x-desc.c: Likewise.
 198         * xstormy16-dis.c: Likewise.
 199         * xstormy16-desc.c: Likewise.
 200
 201 2020-06-03  Nick Clifton  <nickc@redhat.com>
 202
 203         * po/sr.po: Updated Serbian translation.
 204
 205 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 206
 207         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 208         (riscv_get_priv_spec_class): Likewise.
 209
 210 2020-06-01  Alan Modra  <amodra@gmail.com>
 211
 212         * bpf-desc.c: Regenerate.
 213
 214 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 215             David Faust <david.faust@oracle.com>
 216
 217         * bpf-desc.c: Regenerate.
 218         * bpf-opc.h: Likewise.
 219         * bpf-opc.c: Likewise.
 220         * bpf-dis.c: Likewise.
 221
 222 2020-05-28  Alan Modra  <amodra@gmail.com>
 223
 224         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 225         values.
 226
 227 2020-05-28  Alan Modra  <amodra@gmail.com>
 228
 229         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 230         immediates.
 231         (print_insn_ns32k): Revert last change.
 232
 233 2020-05-28  Nick Clifton  <nickc@redhat.com>
 234
 235         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 236         static.
 237
 238 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 239
 240         Fix extraction of signed constants in nios2 disassembler (again).
 241
 242         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 243         extractions of signed fields.
 244
 245 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 246
 247         * s390-opc.txt: Relocate vector load/store instructions with
 248         additional alignment parameter and change architecture level
 249         constraint from z14 to z13.
 250
 251 2020-05-21  Alan Modra  <amodra@gmail.com>
 252
 253         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 254         * sparc-dis.c: Likewise.
 255         * tic4x-dis.c: Likewise.
 256         * xtensa-dis.c: Likewise.
 257         * bpf-desc.c: Regenerate.
 258         * epiphany-desc.c: Regenerate.
 259         * fr30-desc.c: Regenerate.
 260         * frv-desc.c: Regenerate.
 261         * ip2k-desc.c: Regenerate.
 262         * iq2000-desc.c: Regenerate.
 263         * lm32-desc.c: Regenerate.
 264         * m32c-desc.c: Regenerate.
 265         * m32r-desc.c: Regenerate.
 266         * mep-asm.c: Regenerate.
 267         * mep-desc.c: Regenerate.
 268         * mt-desc.c: Regenerate.
 269         * or1k-desc.c: Regenerate.
 270         * xc16x-desc.c: Regenerate.
 271         * xstormy16-desc.c: Regenerate.
 272
 273 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 274
 275         * riscv-opc.c (riscv_ext_version_table): The table used to store
 276         all information about the supported spec and the corresponding ISA
 277         versions.  Currently, only Zicsr is supported to verify the
 278         correctness of Z sub extension settings.  Others will be supported
 279         in the future patches.
 280         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 281         classes and the corresponding strings.
 282         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 283         spec class by giving a ISA spec string.
 284         * riscv-opc.c (struct priv_spec_t): New structure.
 285         (struct priv_spec_t priv_specs): List for all supported privilege spec
 286         classes and the corresponding strings.
 287         (riscv_get_priv_spec_class): New function.  Get the corresponding
 288         privilege spec class by giving a spec string.
 289         (riscv_get_priv_spec_name): New function.  Get the corresponding
 290         privilege spec string by giving a CSR version class.
 291         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 292         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 293         according to the chosen version.  Build a hash table riscv_csr_hash to
 294         store the valid CSR for the chosen pirv verison.  Dump the direct
 295         CSR address rather than it's name if it is invalid.
 296         (parse_riscv_dis_option_without_args): New function.  Parse the options
 297         without arguments.
 298         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 299         parse the options without arguments first, and then handle the options
 300         with arguments.  Add the new option -Mpriv-spec, which has argument.
 301         * riscv-dis.c (print_riscv_disassembler_options): Add description
 302         about the new OBJDUMP option.
 303
 304 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 305
 306         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 307         WC values on POWER10 sync, dcbf  and wait instructions.
 308         (insert_pl, extract_pl): New functions.
 309         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 310         (LS3): New , 3-bit L for sync.
 311         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 312         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 313         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 314         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 315         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 316         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 317         <wait>: Enable PL operand on POWER10.
 318         <dcbf>: Enable L3OPT operand on POWER10.
 319         <sync>: Enable SC2 operand on POWER10.
 320
 321 2020-05-19  Stafford Horne  <shorne@gmail.com>
 322
 323         PR 25184
 324         * or1k-asm.c: Regenerate.
 325         * or1k-desc.c: Regenerate.
 326         * or1k-desc.h: Regenerate.
 327         * or1k-dis.c: Regenerate.
 328         * or1k-ibld.c: Regenerate.
 329         * or1k-opc.c: Regenerate.
 330         * or1k-opc.h: Regenerate.
 331         * or1k-opinst.c: Regenerate.
 332
 333 2020-05-11  Alan Modra  <amodra@gmail.com>
 334
 335         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 336         xsmaxcqp, xsmincqp.
 337
 338 2020-05-11  Alan Modra  <amodra@gmail.com>
 339
 340         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 341         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 342
 343 2020-05-11  Alan Modra  <amodra@gmail.com>
 344
 345         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 346
 347 2020-05-11  Alan Modra  <amodra@gmail.com>
 348
 349         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 350         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 351
 352 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 353
 354         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 355         mnemonics.
 356
 357 2020-05-11  Alan Modra  <amodra@gmail.com>
 358
 359         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 360         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 361         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 362         (prefix_opcodes): Add xxeval.
 363
 364 2020-05-11  Alan Modra  <amodra@gmail.com>
 365
 366         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 367         xxgenpcvwm, xxgenpcvdm.
 368
 369 2020-05-11  Alan Modra  <amodra@gmail.com>
 370
 371         * ppc-opc.c (MP, VXVAM_MASK): Define.
 372         (VXVAPS_MASK): Use VXVA_MASK.
 373         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 374         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 375         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 376         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 377
 378 2020-05-11  Alan Modra  <amodra@gmail.com>
 379             Peter Bergner  <bergner@linux.ibm.com>
 380
 381         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 382         New functions.
 383         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 384         YMSK2, XA6a, XA6ap, XB6a entries.
 385         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 386         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 387         (PPCVSX4): Define.
 388         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 389         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 390         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 391         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 392         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 393         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 394         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 395         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 396         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 397         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 398         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 399         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 400         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 401         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 402
 403 2020-05-11  Alan Modra  <amodra@gmail.com>
 404
 405         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 406         (insert_xts, extract_xts): New functions.
 407         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 408         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 409         (VXRC_MASK, VXSH_MASK): Define.
 410         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 411         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 412         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 413         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 414         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 415         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 416         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 417
 418 2020-05-11  Alan Modra  <amodra@gmail.com>
 419
 420         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 421         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 422         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 423         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 424         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 425
 426 2020-05-11  Alan Modra  <amodra@gmail.com>
 427
 428         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 429         (XTP, DQXP, DQXP_MASK): Define.
 430         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 431         (prefix_opcodes): Add plxvp and pstxvp.
 432
 433 2020-05-11  Alan Modra  <amodra@gmail.com>
 434
 435         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 436         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 437         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 438
 439 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 440
 441         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 442
 443 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 444
 445         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 446         (L1OPT): Define.
 447         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 448
 449 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 450
 451         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 452
 453 2020-05-11  Alan Modra  <amodra@gmail.com>
 454
 455         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 456
 457 2020-05-11  Alan Modra  <amodra@gmail.com>
 458
 459         * ppc-dis.c (ppc_opts): Add "power10" entry.
 460         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 461         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 462
 463 2020-05-11  Nick Clifton  <nickc@redhat.com>
 464
 465         * po/fr.po: Updated French translation.
 466
 467 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 468
 469         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 470         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 471         (operand_general_constraint_met_p): validate
 472         AARCH64_OPND_UNDEFINED.
 473         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 474         for FLD_imm16_2.
 475         * aarch64-asm-2.c: Regenerated.
 476         * aarch64-dis-2.c: Regenerated.
 477         * aarch64-opc-2.c: Regenerated.
 478
 479 2020-04-29  Nick Clifton  <nickc@redhat.com>
 480
 481         PR 22699
 482         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 483         and SETRC insns.
 484
 485 2020-04-29  Nick Clifton  <nickc@redhat.com>
 486
 487         * po/sv.po: Updated Swedish translation.
 488
 489 2020-04-29  Nick Clifton  <nickc@redhat.com>
 490
 491         PR 22699
 492         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 493         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 494         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 495         IMM0_8U case.
 496
 497 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 498
 499         PR 25848
 500         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 501         cmpi only on m68020up and cpu32.
 502
 503 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 504
 505         * aarch64-asm.c (aarch64_ins_none): New.
 506         * aarch64-asm.h (ins_none): New declaration.
 507         * aarch64-dis.c (aarch64_ext_none): New.
 508         * aarch64-dis.h (ext_none): New declaration.
 509         * aarch64-opc.c (aarch64_print_operand): Update case for
 510         AARCH64_OPND_BARRIER_PSB.
 511         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 512         (AARCH64_OPERANDS): Update inserter/extracter for
 513         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 514         * aarch64-asm-2.c: Regenerated.
 515         * aarch64-dis-2.c: Regenerated.
 516         * aarch64-opc-2.c: Regenerated.
 517
 518 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 519
 520         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 521         (aarch64_feature_ras, RAS): Likewise.
 522         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 523         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 524         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 525         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 526         * aarch64-asm-2.c: Regenerated.
 527         * aarch64-dis-2.c: Regenerated.
 528         * aarch64-opc-2.c: Regenerated.
 529
 530 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 531
 532         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 533         (print_insn_neon): Support disassembly of conditional
 534         instructions.
 535
 536 2020-02-16  David Faust  <david.faust@oracle.com>
 537
 538         * bpf-desc.c: Regenerate.
 539         * bpf-desc.h: Likewise.
 540         * bpf-opc.c: Regenerate.
 541         * bpf-opc.h: Likewise.
 542
 543 2020-04-07  Lili Cui  <lili.cui@intel.com>
 544
 545         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 546         (prefix_table): New instructions (see prefixes above).
 547         (rm_table): Likewise
 548         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 549         CPU_ANY_TSXLDTRK_FLAGS.
 550         (cpu_flags): Add CpuTSXLDTRK.
 551         * i386-opc.h (enum): Add CpuTSXLDTRK.
 552         (i386_cpu_flags): Add cputsxldtrk.
 553         * i386-opc.tbl: Add XSUSPLDTRK insns.
 554         * i386-init.h: Regenerate.
 555         * i386-tbl.h: Likewise.
 556
 557 2020-04-02  Lili Cui  <lili.cui@intel.com>
 558
 559         * i386-dis.c (prefix_table): New instructions serialize.
 560         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 561         CPU_ANY_SERIALIZE_FLAGS.
 562         (cpu_flags): Add CpuSERIALIZE.
 563         * i386-opc.h (enum): Add CpuSERIALIZE.
 564         (i386_cpu_flags): Add cpuserialize.
 565         * i386-opc.tbl: Add SERIALIZE insns.
 566         * i386-init.h: Regenerate.
 567         * i386-tbl.h: Likewise.
 568
 569 2020-03-26  Alan Modra  <amodra@gmail.com>
 570
 571         * disassemble.h (opcodes_assert): Declare.
 572         (OPCODES_ASSERT): Define.
 573         * disassemble.c: Don't include assert.h.  Include opintl.h.
 574         (opcodes_assert): New function.
 575         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 576         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 577         calculate maxlen.  Omit insn decoding when insn length exceeds
 578         maxlen.  Exit from nibble loop when looking for E, before
 579         accessing next data byte.  Move processing of E outside loop.
 580         Replace tests of maxlen in loop with assertions.
 581
 582 2020-03-26  Alan Modra  <amodra@gmail.com>
 583
 584         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 585
 586 2020-03-25  Alan Modra  <amodra@gmail.com>
 587
 588         * z80-dis.c (suffix): Init mybuf.
 589
 590 2020-03-22  Alan Modra  <amodra@gmail.com>
 591
 592         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 593         successflly read from section.
 594
 595 2020-03-22  Alan Modra  <amodra@gmail.com>
 596
 597         * arc-dis.c (find_format): Use ISO C string concatenation rather
 598         than line continuation within a string.  Don't access needs_limm
 599         before testing opcode != NULL.
 600
 601 2020-03-22  Alan Modra  <amodra@gmail.com>
 602
 603         * ns32k-dis.c (print_insn_arg): Update comment.
 604         (print_insn_ns32k): Reduce size of index_offset array, and
 605         initialize, passing -1 to print_insn_arg for args that are not
 606         an index.  Don't exit arg loop early.  Abort on bad arg number.
 607
 608 2020-03-22  Alan Modra  <amodra@gmail.com>
 609
 610         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 611         * s12z-opc.c: Formatting.
 612         (operands_f): Return an int.
 613         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 614         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 615         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 616         (exg_sex_discrim): Likewise.
 617         (create_immediate_operand, create_bitfield_operand),
 618         (create_register_operand_with_size, create_register_all_operand),
 619         (create_register_all16_operand, create_simple_memory_operand),
 620         (create_memory_operand, create_memory_auto_operand): Don't
 621         segfault on malloc failure.
 622         (z_ext24_decode): Return an int status, negative on fail, zero
 623         on success.
 624         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 625         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 626         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 627         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 628         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 629         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 630         (loop_primitive_decode, shift_decode, psh_pul_decode),
 631         (bit_field_decode): Similarly.
 632         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 633         to return value, update callers.
 634         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 635         Don't segfault on NULL operand.
 636         (decode_operation): Return OP_INVALID on first fail.
 637         (decode_s12z): Check all reads, returning -1 on fail.
 638
 639 2020-03-20  Alan Modra  <amodra@gmail.com>
 640
 641         * metag-dis.c (print_insn_metag): Don't ignore status from
 642         read_memory_func.
 643
 644 2020-03-20  Alan Modra  <amodra@gmail.com>
 645
 646         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 647         Initialize parts of buffer not written when handling a possible
 648         2-byte insn at end of section.  Don't attempt decoding of such
 649         an insn by the 4-byte machinery.
 650
 651 2020-03-20  Alan Modra  <amodra@gmail.com>
 652
 653         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 654         partially filled buffer.  Prevent lookup of 4-byte insns when
 655         only VLE 2-byte insns are possible due to section size.  Print
 656         ".word" rather than ".long" for 2-byte leftovers.
 657
 658 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 659
 660         PR 25641
 661         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 662
 663 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 664
 665         * i386-dis.c (X86_64_0D): Rename to ...
 666         (X86_64_0E): ... this.
 667
 668 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 669
 670         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 671         * Makefile.in: Regenerated.
 672
 673 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 674
 675         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 676         3-operand pseudos.
 677         * i386-tbl.h: Re-generate.
 678
 679 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 680
 681         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 682         vprot*, vpsha*, and vpshl*.
 683         * i386-tbl.h: Re-generate.
 684
 685 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 688         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 689         * i386-tbl.h: Re-generate.
 690
 691 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 692
 693         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 694         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 695         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 696         * i386-tbl.h: Re-generate.
 697
 698 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 699
 700         * i386-gen.c (struct template_arg, struct template_instance,
 701         struct template_param, struct template, templates,
 702         parse_template, expand_templates): New.
 703         (process_i386_opcodes): Various local variables moved to
 704         expand_templates. Call parse_template and expand_templates.
 705         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 706         * i386-tbl.h: Re-generate.
 707
 708 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 709
 710         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 711         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 712         register and memory source templates. Replace VexW= by VexW*
 713         where applicable.
 714         * i386-tbl.h: Re-generate.
 715
 716 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 717
 718         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 719         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 720         * i386-tbl.h: Re-generate.
 721
 722 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 723
 724         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 725         * i386-tbl.h: Re-generate.
 726
 727 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 728
 729         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 730         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 731         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 732         VexW0 on SSE2AVX variants.
 733         (vmovq): Drop NoRex64 from XMM/XMM variants.
 734         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 735         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 736         applicable use VexW0.
 737         * i386-tbl.h: Re-generate.
 738
 739 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 742         * i386-opc.h (Rex64): Delete.
 743         (struct i386_opcode_modifier): Remove rex64 field.
 744         * i386-opc.tbl (crc32): Drop Rex64.
 745         Replace Rex64 with Size64 everywhere else.
 746         * i386-tbl.h: Re-generate.
 747
 748 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-dis.c (OP_E_memory): Exclude recording of used address
 751         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 752         addressed memory operands for MPX insns.
 753
 754 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 757         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 758         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 759         (ptwrite): Split into non-64-bit and 64-bit forms.
 760         * i386-tbl.h: Re-generate.
 761
 762 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 763
 764         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 765         template.
 766         * i386-tbl.h: Re-generate.
 767
 768 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 769
 770         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 771         (prefix_table): Move vmmcall here. Add vmgexit.
 772         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 773         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 774         (cpu_flags): Add CpuSEV_ES entry.
 775         * i386-opc.h (CpuSEV_ES): New.
 776         (union i386_cpu_flags): Add cpusev_es field.
 777         * i386-opc.tbl (vmgexit): New.
 778         * i386-init.h, i386-tbl.h: Re-generate.
 779
 780 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 781
 782         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 783         with MnemonicSize.
 784         * i386-opc.h (IGNORESIZE): New.
 785         (DEFAULTSIZE): Likewise.
 786         (IgnoreSize): Removed.
 787         (DefaultSize): Likewise.
 788         (MnemonicSize): New.
 789         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 790         mnemonicsize.
 791         * i386-opc.tbl (IgnoreSize): New.
 792         (DefaultSize): Likewise.
 793         * i386-tbl.h: Regenerated.
 794
 795 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 796
 797         PR 25627
 798         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 799         instructions.
 800
 801 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 802
 803         PR gas/25622
 804         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 805         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 806         * i386-tbl.h: Regenerated.
 807
 808 2020-02-26  Alan Modra  <amodra@gmail.com>
 809
 810         * aarch64-asm.c: Indent labels correctly.
 811         * aarch64-dis.c: Likewise.
 812         * aarch64-gen.c: Likewise.
 813         * aarch64-opc.c: Likewise.
 814         * alpha-dis.c: Likewise.
 815         * i386-dis.c: Likewise.
 816         * nds32-asm.c: Likewise.
 817         * nfp-dis.c: Likewise.
 818         * visium-dis.c: Likewise.
 819
 820 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 821
 822         * arc-regs.h (int_vector_base): Make it available for all ARC
 823         CPUs.
 824
 825 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 826
 827         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 828         changed.
 829
 830 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 831
 832         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 833         c.mv/c.li if rs1 is zero.
 834
 835 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 836
 837         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 838         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 839         CPU_POPCNT_FLAGS.
 840         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 841         * i386-opc.h (CpuABM): Removed.
 842         (CpuPOPCNT): New.
 843         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 844         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 845         popcnt.  Remove CpuABM from lzcnt.
 846         * i386-init.h: Regenerated.
 847         * i386-tbl.h: Likewise.
 848
 849 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 850
 851         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 852         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 853         VexW1 instead of open-coding them.
 854         * i386-tbl.h: Re-generate.
 855
 856 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 857
 858         * i386-opc.tbl (AddrPrefixOpReg): Define.
 859         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 860         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 861         templates. Drop NoRex64.
 862         * i386-tbl.h: Re-generate.
 863
 864 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 865
 866         PR gas/6518
 867         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 868         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 869         into Intel syntax instance (with Unpsecified) and AT&T one
 870         (without).
 871         (vcvtneps2bf16): Likewise, along with folding the two so far
 872         separate ones.
 873         * i386-tbl.h: Re-generate.
 874
 875 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 876
 877         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 878         CPU_ANY_SSE4A_FLAGS.
 879
 880 2020-02-17  Alan Modra  <amodra@gmail.com>
 881
 882         * i386-gen.c (cpu_flag_init): Correct last change.
 883
 884 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 885
 886         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 887         CPU_ANY_SSE4_FLAGS.
 888
 889 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 890
 891         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 892         (movzx): Likewise.
 893
 894 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 895
 896         PR gas/25438
 897         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 898         destination for Cpu64-only variant.
 899         (movzx): Fold patterns.
 900         * i386-tbl.h: Re-generate.
 901
 902 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 903
 904         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 905         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 906         CPU_ANY_SSE4_FLAGS entry.
 907         * i386-init.h: Re-generate.
 908
 909 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 910
 911         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 912         with Unspecified, making the present one AT&T syntax only.
 913         * i386-tbl.h: Re-generate.
 914
 915 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 916
 917         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 918         * i386-tbl.h: Re-generate.
 919
 920 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 921
 922         PR gas/24546
 923         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 924         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 925         Amd64 and Intel64 templates.
 926         (call, jmp): Likewise for far indirect variants. Dro
 927         Unspecified.
 928         * i386-tbl.h: Re-generate.
 929
 930 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 931
 932         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 933         * i386-opc.h (ShortForm): Delete.
 934         (struct i386_opcode_modifier): Remove shortform field.
 935         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 936         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 937         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 938         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 939         Drop ShortForm.
 940         * i386-tbl.h: Re-generate.
 941
 942 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 943
 944         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 945         fucompi): Drop ShortForm from operand-less templates.
 946         * i386-tbl.h: Re-generate.
 947
 948 2020-02-11  Alan Modra  <amodra@gmail.com>
 949
 950         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 951         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 952         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 953         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 954         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 955
 956 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 957
 958         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 959         (cde_opcodes): Add VCX* instructions.
 960
 961 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 962             Matthew Malcomson  <matthew.malcomson@arm.com>
 963
 964         * arm-dis.c (struct cdeopcode32): New.
 965         (CDE_OPCODE): New macro.
 966         (cde_opcodes): New disassembly table.
 967         (regnames): New option to table.
 968         (cde_coprocs): New global variable.
 969         (print_insn_cde): New
 970         (print_insn_thumb32): Use print_insn_cde.
 971         (parse_arm_disassembler_options): Parse coprocN args.
 972
 973 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 974
 975         PR gas/25516
 976         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 977         with ISA64.
 978         * i386-opc.h (AMD64): Removed.
 979         (Intel64): Likewose.
 980         (AMD64): New.
 981         (INTEL64): Likewise.
 982         (INTEL64ONLY): Likewise.
 983         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 984         * i386-opc.tbl (Amd64): New.
 985         (Intel64): Likewise.
 986         (Intel64Only): Likewise.
 987         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 988         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 989         * i386-tbl.h: Regenerated.
 990
 991 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 992
 993         PR 25469
 994         * z80-dis.c: Add support for GBZ80 opcodes.
 995
 996 2020-02-04  Alan Modra  <amodra@gmail.com>
 997
 998         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 999
1000 2020-02-03  Alan Modra  <amodra@gmail.com>
1001
1002         * m32c-ibld.c: Regenerate.
1003
1004 2020-02-01  Alan Modra  <amodra@gmail.com>
1005
1006         * frv-ibld.c: Regenerate.
1007
1008 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1009
1010         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1011         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1012         (OP_E_memory): Replace xmm_mdq_mode case label by
1013         vex_scalar_w_dq_mode one.
1014         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1015
1016 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1017
1018         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1019         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1020         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1021         (intel_operand_size): Drop vex_w_dq_mode case label.
1022
1023 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1024
1025         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1026         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1027
1028 2020-01-30  Alan Modra  <amodra@gmail.com>
1029
1030         * m32c-ibld.c: Regenerate.
1031
1032 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1033
1034         * bpf-opc.c: Regenerate.
1035
1036 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1039         (dis386): Use them to replace C2/C3 table entries.
1040         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1041         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1042         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1043         * i386-tbl.h: Re-generate.
1044
1045 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1046
1047         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1048         forms.
1049         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1050         DefaultSize.
1051         * i386-tbl.h: Re-generate.
1052
1053 2020-01-30  Alan Modra  <amodra@gmail.com>
1054
1055         * tic4x-dis.c (tic4x_dp): Make unsigned.
1056
1057 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1058             Jan Beulich  <jbeulich@suse.com>
1059
1060         PR binutils/25445
1061         * i386-dis.c (MOVSXD_Fixup): New function.
1062         (movsxd_mode): New enum.
1063         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1064         (intel_operand_size): Handle movsxd_mode.
1065         (OP_E_register): Likewise.
1066         (OP_G): Likewise.
1067         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1068         register on movsxd.  Add movsxd with 16-bit destination register
1069         for AMD64 and Intel64 ISAs.
1070         * i386-tbl.h: Regenerated.
1071
1072 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1073
1074         PR 25403
1075         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1076         * aarch64-asm-2.c: Regenerate
1077         * aarch64-dis-2.c: Likewise.
1078         * aarch64-opc-2.c: Likewise.
1079
1080 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1081
1082         * i386-opc.tbl (sysret): Drop DefaultSize.
1083         * i386-tbl.h: Re-generate.
1084
1085 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1086
1087         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1088         Dword.
1089         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1090         * i386-tbl.h: Re-generate.
1091
1092 2020-01-20  Nick Clifton  <nickc@redhat.com>
1093
1094         * po/de.po: Updated German translation.
1095         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1096         * po/uk.po: Updated Ukranian translation.
1097
1098 2020-01-20  Alan Modra  <amodra@gmail.com>
1099
1100         * hppa-dis.c (fput_const): Remove useless cast.
1101
1102 2020-01-20  Alan Modra  <amodra@gmail.com>
1103
1104         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1105
1106 2020-01-18  Nick Clifton  <nickc@redhat.com>
1107
1108         * configure: Regenerate.
1109         * po/opcodes.pot: Regenerate.
1110
1111 2020-01-18  Nick Clifton  <nickc@redhat.com>
1112
1113         Binutils 2.34 branch created.
1114
1115 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1116
1117         * opintl.h: Fix spelling error (seperate).
1118
1119 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1120
1121         * i386-opc.tbl: Add {vex} pseudo prefix.
1122         * i386-tbl.h: Regenerated.
1123
1124 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1125
1126         PR 25376
1127         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1128         (neon_opcodes): Likewise.
1129         (select_arm_features): Make sure we enable MVE bits when selecting
1130         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1131         any architecture.
1132
1133 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1134
1135         * i386-opc.tbl: Drop stale comment from XOP section.
1136
1137 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1140         (extractps): Add VexWIG to SSE2AVX forms.
1141         * i386-tbl.h: Re-generate.
1142
1143 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1144
1145         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1146         Size64 from and use VexW1 on SSE2AVX forms.
1147         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1148         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1149         * i386-tbl.h: Re-generate.
1150
1151 2020-01-15  Alan Modra  <amodra@gmail.com>
1152
1153         * tic4x-dis.c (tic4x_version): Make unsigned long.
1154         (optab, optab_special, registernames): New file scope vars.
1155         (tic4x_print_register): Set up registernames rather than
1156         malloc'd registertable.
1157         (tic4x_disassemble): Delete optable and optable_special.  Use
1158         optab and optab_special instead.  Throw away old optab,
1159         optab_special and registernames when info->mach changes.
1160
1161 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1162
1163         PR 25377
1164         * z80-dis.c (suffix): Use .db instruction to generate double
1165         prefix.
1166
1167 2020-01-14  Alan Modra  <amodra@gmail.com>
1168
1169         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1170         values to unsigned before shifting.
1171
1172 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1173
1174         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1175         flow instructions.
1176         (print_insn_thumb16, print_insn_thumb32): Likewise.
1177         (print_insn): Initialize the insn info.
1178         * i386-dis.c (print_insn): Initialize the insn info fields, and
1179         detect jumps.
1180
1181 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1182
1183         * arc-opc.c (C_NE): Make it required.
1184
1185 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1186
1187         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1188         reserved register name.
1189
1190 2020-01-13  Alan Modra  <amodra@gmail.com>
1191
1192         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1193         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1194
1195 2020-01-13  Alan Modra  <amodra@gmail.com>
1196
1197         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1198         result of wasm_read_leb128 in a uint64_t and check that bits
1199         are not lost when copying to other locals.  Use uint32_t for
1200         most locals.  Use PRId64 when printing int64_t.
1201
1202 2020-01-13  Alan Modra  <amodra@gmail.com>
1203
1204         * score-dis.c: Formatting.
1205         * score7-dis.c: Formatting.
1206
1207 2020-01-13  Alan Modra  <amodra@gmail.com>
1208
1209         * score-dis.c (print_insn_score48): Use unsigned variables for
1210         unsigned values.  Don't left shift negative values.
1211         (print_insn_score32): Likewise.
1212         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1213
1214 2020-01-13  Alan Modra  <amodra@gmail.com>
1215
1216         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1217
1218 2020-01-13  Alan Modra  <amodra@gmail.com>
1219
1220         * fr30-ibld.c: Regenerate.
1221
1222 2020-01-13  Alan Modra  <amodra@gmail.com>
1223
1224         * xgate-dis.c (print_insn): Don't left shift signed value.
1225         (ripBits): Formatting, use 1u.
1226
1227 2020-01-10  Alan Modra  <amodra@gmail.com>
1228
1229         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1230         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1231
1232 2020-01-10  Alan Modra  <amodra@gmail.com>
1233
1234         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1235         and XRREG value earlier to avoid a shift with negative exponent.
1236         * m10200-dis.c (disassemble): Similarly.
1237
1238 2020-01-09  Nick Clifton  <nickc@redhat.com>
1239
1240         PR 25224
1241         * z80-dis.c (ld_ii_ii): Use correct cast.
1242
1243 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1244
1245         PR 25224
1246         * z80-dis.c (ld_ii_ii): Use character constant when checking
1247         opcode byte value.
1248
1249 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1250
1251         * i386-dis.c (SEP_Fixup): New.
1252         (SEP): Define.
1253         (dis386_twobyte): Use it for sysenter/sysexit.
1254         (enum x86_64_isa): Change amd64 enumerator to value 1.
1255         (OP_J): Compare isa64 against intel64 instead of amd64.
1256         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1257         forms.
1258         * i386-tbl.h: Re-generate.
1259
1260 2020-01-08  Alan Modra  <amodra@gmail.com>
1261
1262         * z8k-dis.c: Include libiberty.h
1263         (instr_data_s): Make max_fetched unsigned.
1264         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1265         Don't exceed byte_info bounds.
1266         (output_instr): Make num_bytes unsigned.
1267         (unpack_instr): Likewise for nibl_count and loop.
1268         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1269         idx unsigned.
1270         * z8k-opc.h: Regenerate.
1271
1272 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1273
1274         * arc-tbl.h (llock): Use 'LLOCK' as class.
1275         (llockd): Likewise.
1276         (scond): Use 'SCOND' as class.
1277         (scondd): Likewise.
1278         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1279         (scondd): Likewise.
1280
1281 2020-01-06  Alan Modra  <amodra@gmail.com>
1282
1283         * m32c-ibld.c: Regenerate.
1284
1285 2020-01-06  Alan Modra  <amodra@gmail.com>
1286
1287         PR 25344
1288         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1289         Peek at next byte to prevent recursion on repeated prefix bytes.
1290         Ensure uninitialised "mybuf" is not accessed.
1291         (print_insn_z80): Don't zero n_fetch and n_used here,..
1292         (print_insn_z80_buf): ..do it here instead.
1293
1294 2020-01-04  Alan Modra  <amodra@gmail.com>
1295
1296         * m32r-ibld.c: Regenerate.
1297
1298 2020-01-04  Alan Modra  <amodra@gmail.com>
1299
1300         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1301
1302 2020-01-04  Alan Modra  <amodra@gmail.com>
1303
1304         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1305
1306 2020-01-04  Alan Modra  <amodra@gmail.com>
1307
1308         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1309
1310 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1311
1312         * aarch64-tbl.h (aarch64_opcode_table): Use
1313         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1314
1315 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1316
1317         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1318         forms of SUDOT and USDOT.
1319
1320 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1321
1322         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1323         uzip{1,2}.
1324         * opcodes/aarch64-dis-2.c: Re-generate.
1325
1326 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1327
1328         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1329         FMMLA encoding.
1330         * opcodes/aarch64-dis-2.c: Re-generate.
1331
1332 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1333
1334         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1335
1336 2020-01-01  Alan Modra  <amodra@gmail.com>
1337
1338         Update year range in copyright notice of all files.
1339
1340 For older changes see ChangeLog-2019
1341 \f
1342 Copyright (C) 2020 Free Software Foundation, Inc.
1343
1344 Copying and distribution of this file, with or without modification,
1345 are permitted in any medium without royalty provided the copyright
1346 notice and this notice are preserved.
1347
1348 Local Variables:
1349 mode: change-log
1350 left-margin: 8
1351 fill-column: 74
1352 version-control: never
1353 End: