opcodes/ChangeLog

   1 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_feature_memtag): New.
   4         (MEMTAG, MEMTAG_INSN): New.
   5
   6 2018-11-06  Sudakshina Das  <sudi.das@arm.com>
   7
   8         * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
   9         with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
  10
  11 2018-11-06  Alan Modra  <amodra@gmail.com>
  12
  13         * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
  14         (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
  15         (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
  16         (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
  17         Don't return zero on error, insert mask bits instead.
  18         (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
  19         (insert_sh6, extract_sh6): Delete dead code.
  20         (insert_sprbat, insert_sprg): Use unsigned comparisions.
  21         (powerpc_operands <OIMM>): Set shift count rather than using
  22         PPC_OPSHIFT_INV.
  23         <SE_SDH, SE_SDW>: Likewise.  Don't use insert/extract functions.
  24
  25 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
  28         vpbroadcast{d,q} with GPR operand.
  29
  30 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
  33         * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
  34         cases up one level in the hierarchy.
  35
  36 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
  39         MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
  40         (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
  41         into MOD_VEX_0F93_P_3_LEN_0.
  42         (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
  43         operand cases up one level in the hierarchy.
  44
  45 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
  48         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
  49         EVEX_W_0F3A22_P_2): Delete.
  50         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
  51         entries up one level in the hierarchy.
  52         (OP_E_memory): Handle dq_mode when determining Disp8 shift
  53         value.
  54         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
  55         entries up one level in the hierarchy.
  56         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
  57         VexWIG for AVX flavors.
  58         * i386-tbl.h: Re-generate.
  59
  60 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
  63         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
  64         vcvtusi2ss, kmovd): Drop VexW=1.
  65         * i386-tbl.h: Re-generate.
  66
  67 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
  70         EVex512, EVexLIG, EVexDYN): New.
  71         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
  72         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
  73         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
  74         of EVex=4 (aka EVexLIG).
  75         * i386-tbl.h: Re-generate.
  76
  77 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
  80         (vpmaxub): Re-order attributes on AVX512BW flavor.
  81         * i386-tbl.h: Re-generate.
  82
  83 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  84
  85         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
  86         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
  87         Vex=1 on AVX / AVX2 flavors.
  88         (vpmaxub): Re-order attributes on AVX512BW flavor.
  89         * i386-tbl.h: Re-generate.
  90
  91 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-opc.tbl (VexW0, VexW1): New.
  94         (vphadd*, vphsub*): Use VexW0 on XOP variants.
  95         * i386-tbl.h: Re-generate.
  96
  97 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
  98
  99         * s12z-dis.c (decode_possible_symbol): Add fallback case.
 100         (rel_15_7): Likewise.
 101
 102 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
 103
 104         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
 105         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
 106         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
 107
 108 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
 109
 110         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
 111         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
 112
 113 2018-10-10  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
 116         Size64. Add Size.
 117         * i386-opc.h (Size16, Size32, Size64): Delete.
 118         (Size): New.
 119         (SIZE16, SIZE32, SIZE64): Define.
 120         (struct i386_opcode_modifier): Drop size16, size32, and size64.
 121         Add size.
 122         * i386-opc.tbl (Size16, Size32, Size64): Define.
 123         * i386-tbl.h: Re-generate.
 124
 125 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 126
 127         * aarch64-opc.c (operand_general_constraint_met_p): Add
 128         SSBS in the check for one-bit immediate.
 129         (aarch64_sys_regs): New entry for SSBS.
 130         (aarch64_sys_reg_supported_p): New check for above.
 131         (aarch64_pstatefields): New entry for SSBS.
 132         (aarch64_pstatefield_supported_p): New check for above.
 133
 134 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 135
 136         * aarch64-opc.c (aarch64_sys_regs): New entries for
 137         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
 138         (aarch64_sys_reg_supported_p): New checks for above.
 139
 140 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 141
 142         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
 143         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 144         with the hint immediate.
 145         * aarch64-opc.c (aarch64_hint_options): New entries for
 146         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 147         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 148         while checking for HINT_OPD_F_NOPRINT flag.
 149         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 150         extract value.
 151         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 152         (aarch64_opcode_table): Add entry for BTI.
 153         (AARCH64_OPERANDS): Add new description for BTI targets.
 154         * aarch64-asm-2.c: Regenerate.
 155         * aarch64-dis-2.c: Regenerate.
 156         * aarch64-opc-2.c: Regenerate.
 157
 158 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 159
 160         * aarch64-opc.c (aarch64_sys_regs): New entries for
 161         rndr and rndrrs.
 162         (aarch64_sys_reg_supported_p): New check for above.
 163
 164 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 165
 166         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 167         (aarch64_sys_ins_reg_supported_p): New check for above.
 168
 169 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 170
 171         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 172         AARCH64_OPND_SYSREG_SR.
 173         * aarch64-opc.c (aarch64_print_operand): Likewise.
 174         (aarch64_sys_regs_sr): Define table.
 175         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 176         AARCH64_FEATURE_PREDRES.
 177         * aarch64-tbl.h (aarch64_feature_predres): New.
 178         (PREDRES, PREDRES_INSN): New.
 179         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 180         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 181         * aarch64-asm-2.c: Regenerate.
 182         * aarch64-dis-2.c: Regenerate.
 183         * aarch64-opc-2.c: Regenerate.
 184
 185 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 186
 187         * aarch64-tbl.h (aarch64_feature_sb): New.
 188         (SB, SB_INSN): New.
 189         (aarch64_opcode_table): Add entry for sb.
 190         * aarch64-asm-2.c: Regenerate.
 191         * aarch64-dis-2.c: Regenerate.
 192         * aarch64-opc-2.c: Regenerate.
 193
 194 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 195
 196         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 197         (aarch64_feature_frintts): New.
 198         (FLAGMANIP, FRINTTS): New.
 199         (aarch64_opcode_table): Add entries for xaflag, axflag
 200         and frint[32,64][x,z] instructions.
 201         * aarch64-asm-2.c: Regenerate.
 202         * aarch64-dis-2.c: Regenerate.
 203         * aarch64-opc-2.c: Regenerate.
 204
 205 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 206
 207         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 208         (ARMV8_5, V8_5_INSN): New.
 209
 210 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 211
 212         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 213
 214 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 215
 216         * i386-dis.c (rm_table): Add enclv.
 217         * i386-opc.tbl: Add enclv.
 218         * i386-tbl.h: Regenerated.
 219
 220 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 221
 222         * arm-dis.c (arm_opcodes): Add sb.
 223         (thumb32_opcodes): Likewise.
 224
 225 2018-10-05  Richard Henderson  <rth@twiddle.net>
 226             Stafford Horne  <shorne@gmail.com>
 227
 228         * or1k-desc.c: Regenerate.
 229         * or1k-desc.h: Regenerate.
 230         * or1k-opc.c: Regenerate.
 231         * or1k-opc.h: Regenerate.
 232         * or1k-opinst.c: Regenerate.
 233
 234 2018-10-05  Richard Henderson  <rth@twiddle.net>
 235
 236         * or1k-asm.c: Regenerated.
 237         * or1k-desc.c: Regenerated.
 238         * or1k-desc.h: Regenerated.
 239         * or1k-dis.c: Regenerated.
 240         * or1k-ibld.c: Regenerated.
 241         * or1k-opc.c: Regenerated.
 242         * or1k-opc.h: Regenerated.
 243         * or1k-opinst.c: Regenerated.
 244
 245 2018-10-05  Richard Henderson  <rth@twiddle.net>
 246
 247         * or1k-asm.c: Regenerate.
 248
 249 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 250
 251         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 252         * aarch64-dis.c (print_operands): Refactor to take notes.
 253         (print_verifier_notes): New.
 254         (print_aarch64_insn): Apply constraint verifier.
 255         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 256         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 257
 258 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 259
 260         * aarch64-opc.c (init_insn_block): New.
 261         (verify_constraints, aarch64_is_destructive_by_operands): New.
 262         * aarch64-opc.h (verify_constraints): New.
 263
 264 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 265
 266         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 267         * aarch64-opc.c (verify_ldpsw): Update arguments.
 268
 269 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 270
 271         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 272         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 273
 274 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 275
 276         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 277         * aarch64-dis.c (insn_sequence): New.
 278
 279 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 280
 281         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 282         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 283         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 284         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 285         constraints.
 286         (_SVE_INSNC): New.
 287         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 288         constraints.
 289         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 290         F_SCAN flags.
 291         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 292         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 293         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 294         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 295         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 296         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 297         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 298
 299 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 300
 301         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 302
 303 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 304
 305         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 306         are used when extracting signed fields and converting them to
 307         potentially 64-bit types.
 308
 309 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 310
 311         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 312         * Makefile.in: Re-generate.
 313         * aclocal.m4: Re-generate.
 314         * configure: Re-generate.
 315         * configure.ac: Remove check for -Wno-missing-field-initializers.
 316         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 317         (csky_v2_opcodes): Likewise.
 318
 319 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 320
 321         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 322
 323 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 324
 325         * nds32-asm.c (operand_fields): Remove the unused fields.
 326         (nds32_opcodes): Remove the unused instructions.
 327         * nds32-dis.c (nds32_ex9_info): Removed.
 328         (nds32_parse_opcode): Updated.
 329         (print_insn_nds32): Likewise.
 330         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 331         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 332         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 333         build_opcode_hash_table): New functions.
 334         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 335         nds32_opcode_table): New.
 336         (hw_ktabs): Declare it to a pointer rather than an array.
 337         (build_hash_table): Removed.
 338         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 339         SYN_ROPT and upadte HW_GPR and HW_INT.
 340         * nds32-dis.c (keywords): Remove const.
 341         (match_field): New function.
 342         (nds32_parse_opcode): Updated.
 343         * disassemble.c (disassemble_init_for_target):
 344         Add disassemble_init_nds32.
 345         * nds32-dis.c (eum map_type): New.
 346         (nds32_private_data): Likewise.
 347         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 348         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 349         (print_insn_nds32): Updated.
 350         * nds32-asm.c (parse_aext_reg): Add new parameter.
 351         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 352         are allowed to use.
 353         All callers changed.
 354         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 355         (operand_fields): Add new fields.
 356         (nds32_opcodes): Add new instructions.
 357         (keyword_aridxi_mx): New keyword.
 358         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 359         and NASM_ATTR_ZOL.
 360         (ALU2_1, ALU2_2, ALU2_3): New macros.
 361         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 362
 363 2018-09-17  Kito Cheng  <kito@andestech.com>
 364
 365         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 366
 367 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 368
 369         PR gas/23670
 370         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 371         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 372         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 373         (EVEX_LEN_0F7E_P_1): Likewise.
 374         (EVEX_LEN_0F7E_P_2): Likewise.
 375         (EVEX_LEN_0FD6_P_2): Likewise.
 376         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 377         (EVEX_LEN_TABLE): Likewise.
 378         (EVEX_LEN_0F6E_P_2): New enum.
 379         (EVEX_LEN_0F7E_P_1): Likewise.
 380         (EVEX_LEN_0F7E_P_2): Likewise.
 381         (EVEX_LEN_0FD6_P_2): Likewise.
 382         (evex_len_table): New.
 383         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 384         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 385         * i386-tbl.h: Regenerated.
 386
 387 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 388
 389         PR gas/23665
 390         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 391         VEX_LEN_0F7E_P_2 entries.
 392         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 393         * i386-tbl.h: Regenerated.
 394
 395 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         * i386-dis.c (VZERO_Fixup): Removed.
 398         (VZERO): Likewise.
 399         (VEX_LEN_0F10_P_1): Likewise.
 400         (VEX_LEN_0F10_P_3): Likewise.
 401         (VEX_LEN_0F11_P_1): Likewise.
 402         (VEX_LEN_0F11_P_3): Likewise.
 403         (VEX_LEN_0F2E_P_0): Likewise.
 404         (VEX_LEN_0F2E_P_2): Likewise.
 405         (VEX_LEN_0F2F_P_0): Likewise.
 406         (VEX_LEN_0F2F_P_2): Likewise.
 407         (VEX_LEN_0F51_P_1): Likewise.
 408         (VEX_LEN_0F51_P_3): Likewise.
 409         (VEX_LEN_0F52_P_1): Likewise.
 410         (VEX_LEN_0F53_P_1): Likewise.
 411         (VEX_LEN_0F58_P_1): Likewise.
 412         (VEX_LEN_0F58_P_3): Likewise.
 413         (VEX_LEN_0F59_P_1): Likewise.
 414         (VEX_LEN_0F59_P_3): Likewise.
 415         (VEX_LEN_0F5A_P_1): Likewise.
 416         (VEX_LEN_0F5A_P_3): Likewise.
 417         (VEX_LEN_0F5C_P_1): Likewise.
 418         (VEX_LEN_0F5C_P_3): Likewise.
 419         (VEX_LEN_0F5D_P_1): Likewise.
 420         (VEX_LEN_0F5D_P_3): Likewise.
 421         (VEX_LEN_0F5E_P_1): Likewise.
 422         (VEX_LEN_0F5E_P_3): Likewise.
 423         (VEX_LEN_0F5F_P_1): Likewise.
 424         (VEX_LEN_0F5F_P_3): Likewise.
 425         (VEX_LEN_0FC2_P_1): Likewise.
 426         (VEX_LEN_0FC2_P_3): Likewise.
 427         (VEX_LEN_0F3A0A_P_2): Likewise.
 428         (VEX_LEN_0F3A0B_P_2): Likewise.
 429         (VEX_W_0F10_P_0): Likewise.
 430         (VEX_W_0F10_P_1): Likewise.
 431         (VEX_W_0F10_P_2): Likewise.
 432         (VEX_W_0F10_P_3): Likewise.
 433         (VEX_W_0F11_P_0): Likewise.
 434         (VEX_W_0F11_P_1): Likewise.
 435         (VEX_W_0F11_P_2): Likewise.
 436         (VEX_W_0F11_P_3): Likewise.
 437         (VEX_W_0F12_P_0_M_0): Likewise.
 438         (VEX_W_0F12_P_0_M_1): Likewise.
 439         (VEX_W_0F12_P_1): Likewise.
 440         (VEX_W_0F12_P_2): Likewise.
 441         (VEX_W_0F12_P_3): Likewise.
 442         (VEX_W_0F13_M_0): Likewise.
 443         (VEX_W_0F14): Likewise.
 444         (VEX_W_0F15): Likewise.
 445         (VEX_W_0F16_P_0_M_0): Likewise.
 446         (VEX_W_0F16_P_0_M_1): Likewise.
 447         (VEX_W_0F16_P_1): Likewise.
 448         (VEX_W_0F16_P_2): Likewise.
 449         (VEX_W_0F17_M_0): Likewise.
 450         (VEX_W_0F28): Likewise.
 451         (VEX_W_0F29): Likewise.
 452         (VEX_W_0F2B_M_0): Likewise.
 453         (VEX_W_0F2E_P_0): Likewise.
 454         (VEX_W_0F2E_P_2): Likewise.
 455         (VEX_W_0F2F_P_0): Likewise.
 456         (VEX_W_0F2F_P_2): Likewise.
 457         (VEX_W_0F50_M_0): Likewise.
 458         (VEX_W_0F51_P_0): Likewise.
 459         (VEX_W_0F51_P_1): Likewise.
 460         (VEX_W_0F51_P_2): Likewise.
 461         (VEX_W_0F51_P_3): Likewise.
 462         (VEX_W_0F52_P_0): Likewise.
 463         (VEX_W_0F52_P_1): Likewise.
 464         (VEX_W_0F53_P_0): Likewise.
 465         (VEX_W_0F53_P_1): Likewise.
 466         (VEX_W_0F58_P_0): Likewise.
 467         (VEX_W_0F58_P_1): Likewise.
 468         (VEX_W_0F58_P_2): Likewise.
 469         (VEX_W_0F58_P_3): Likewise.
 470         (VEX_W_0F59_P_0): Likewise.
 471         (VEX_W_0F59_P_1): Likewise.
 472         (VEX_W_0F59_P_2): Likewise.
 473         (VEX_W_0F59_P_3): Likewise.
 474         (VEX_W_0F5A_P_0): Likewise.
 475         (VEX_W_0F5A_P_1): Likewise.
 476         (VEX_W_0F5A_P_3): Likewise.
 477         (VEX_W_0F5B_P_0): Likewise.
 478         (VEX_W_0F5B_P_1): Likewise.
 479         (VEX_W_0F5B_P_2): Likewise.
 480         (VEX_W_0F5C_P_0): Likewise.
 481         (VEX_W_0F5C_P_1): Likewise.
 482         (VEX_W_0F5C_P_2): Likewise.
 483         (VEX_W_0F5C_P_3): Likewise.
 484         (VEX_W_0F5D_P_0): Likewise.
 485         (VEX_W_0F5D_P_1): Likewise.
 486         (VEX_W_0F5D_P_2): Likewise.
 487         (VEX_W_0F5D_P_3): Likewise.
 488         (VEX_W_0F5E_P_0): Likewise.
 489         (VEX_W_0F5E_P_1): Likewise.
 490         (VEX_W_0F5E_P_2): Likewise.
 491         (VEX_W_0F5E_P_3): Likewise.
 492         (VEX_W_0F5F_P_0): Likewise.
 493         (VEX_W_0F5F_P_1): Likewise.
 494         (VEX_W_0F5F_P_2): Likewise.
 495         (VEX_W_0F5F_P_3): Likewise.
 496         (VEX_W_0F60_P_2): Likewise.
 497         (VEX_W_0F61_P_2): Likewise.
 498         (VEX_W_0F62_P_2): Likewise.
 499         (VEX_W_0F63_P_2): Likewise.
 500         (VEX_W_0F64_P_2): Likewise.
 501         (VEX_W_0F65_P_2): Likewise.
 502         (VEX_W_0F66_P_2): Likewise.
 503         (VEX_W_0F67_P_2): Likewise.
 504         (VEX_W_0F68_P_2): Likewise.
 505         (VEX_W_0F69_P_2): Likewise.
 506         (VEX_W_0F6A_P_2): Likewise.
 507         (VEX_W_0F6B_P_2): Likewise.
 508         (VEX_W_0F6C_P_2): Likewise.
 509         (VEX_W_0F6D_P_2): Likewise.
 510         (VEX_W_0F6F_P_1): Likewise.
 511         (VEX_W_0F6F_P_2): Likewise.
 512         (VEX_W_0F70_P_1): Likewise.
 513         (VEX_W_0F70_P_2): Likewise.
 514         (VEX_W_0F70_P_3): Likewise.
 515         (VEX_W_0F71_R_2_P_2): Likewise.
 516         (VEX_W_0F71_R_4_P_2): Likewise.
 517         (VEX_W_0F71_R_6_P_2): Likewise.
 518         (VEX_W_0F72_R_2_P_2): Likewise.
 519         (VEX_W_0F72_R_4_P_2): Likewise.
 520         (VEX_W_0F72_R_6_P_2): Likewise.
 521         (VEX_W_0F73_R_2_P_2): Likewise.
 522         (VEX_W_0F73_R_3_P_2): Likewise.
 523         (VEX_W_0F73_R_6_P_2): Likewise.
 524         (VEX_W_0F73_R_7_P_2): Likewise.
 525         (VEX_W_0F74_P_2): Likewise.
 526         (VEX_W_0F75_P_2): Likewise.
 527         (VEX_W_0F76_P_2): Likewise.
 528         (VEX_W_0F77_P_0): Likewise.
 529         (VEX_W_0F7C_P_2): Likewise.
 530         (VEX_W_0F7C_P_3): Likewise.
 531         (VEX_W_0F7D_P_2): Likewise.
 532         (VEX_W_0F7D_P_3): Likewise.
 533         (VEX_W_0F7E_P_1): Likewise.
 534         (VEX_W_0F7F_P_1): Likewise.
 535         (VEX_W_0F7F_P_2): Likewise.
 536         (VEX_W_0FAE_R_2_M_0): Likewise.
 537         (VEX_W_0FAE_R_3_M_0): Likewise.
 538         (VEX_W_0FC2_P_0): Likewise.
 539         (VEX_W_0FC2_P_1): Likewise.
 540         (VEX_W_0FC2_P_2): Likewise.
 541         (VEX_W_0FC2_P_3): Likewise.
 542         (VEX_W_0FD0_P_2): Likewise.
 543         (VEX_W_0FD0_P_3): Likewise.
 544         (VEX_W_0FD1_P_2): Likewise.
 545         (VEX_W_0FD2_P_2): Likewise.
 546         (VEX_W_0FD3_P_2): Likewise.
 547         (VEX_W_0FD4_P_2): Likewise.
 548         (VEX_W_0FD5_P_2): Likewise.
 549         (VEX_W_0FD6_P_2): Likewise.
 550         (VEX_W_0FD7_P_2_M_1): Likewise.
 551         (VEX_W_0FD8_P_2): Likewise.
 552         (VEX_W_0FD9_P_2): Likewise.
 553         (VEX_W_0FDA_P_2): Likewise.
 554         (VEX_W_0FDB_P_2): Likewise.
 555         (VEX_W_0FDC_P_2): Likewise.
 556         (VEX_W_0FDD_P_2): Likewise.
 557         (VEX_W_0FDE_P_2): Likewise.
 558         (VEX_W_0FDF_P_2): Likewise.
 559         (VEX_W_0FE0_P_2): Likewise.
 560         (VEX_W_0FE1_P_2): Likewise.
 561         (VEX_W_0FE2_P_2): Likewise.
 562         (VEX_W_0FE3_P_2): Likewise.
 563         (VEX_W_0FE4_P_2): Likewise.
 564         (VEX_W_0FE5_P_2): Likewise.
 565         (VEX_W_0FE6_P_1): Likewise.
 566         (VEX_W_0FE6_P_2): Likewise.
 567         (VEX_W_0FE6_P_3): Likewise.
 568         (VEX_W_0FE7_P_2_M_0): Likewise.
 569         (VEX_W_0FE8_P_2): Likewise.
 570         (VEX_W_0FE9_P_2): Likewise.
 571         (VEX_W_0FEA_P_2): Likewise.
 572         (VEX_W_0FEB_P_2): Likewise.
 573         (VEX_W_0FEC_P_2): Likewise.
 574         (VEX_W_0FED_P_2): Likewise.
 575         (VEX_W_0FEE_P_2): Likewise.
 576         (VEX_W_0FEF_P_2): Likewise.
 577         (VEX_W_0FF0_P_3_M_0): Likewise.
 578         (VEX_W_0FF1_P_2): Likewise.
 579         (VEX_W_0FF2_P_2): Likewise.
 580         (VEX_W_0FF3_P_2): Likewise.
 581         (VEX_W_0FF4_P_2): Likewise.
 582         (VEX_W_0FF5_P_2): Likewise.
 583         (VEX_W_0FF6_P_2): Likewise.
 584         (VEX_W_0FF7_P_2): Likewise.
 585         (VEX_W_0FF8_P_2): Likewise.
 586         (VEX_W_0FF9_P_2): Likewise.
 587         (VEX_W_0FFA_P_2): Likewise.
 588         (VEX_W_0FFB_P_2): Likewise.
 589         (VEX_W_0FFC_P_2): Likewise.
 590         (VEX_W_0FFD_P_2): Likewise.
 591         (VEX_W_0FFE_P_2): Likewise.
 592         (VEX_W_0F3800_P_2): Likewise.
 593         (VEX_W_0F3801_P_2): Likewise.
 594         (VEX_W_0F3802_P_2): Likewise.
 595         (VEX_W_0F3803_P_2): Likewise.
 596         (VEX_W_0F3804_P_2): Likewise.
 597         (VEX_W_0F3805_P_2): Likewise.
 598         (VEX_W_0F3806_P_2): Likewise.
 599         (VEX_W_0F3807_P_2): Likewise.
 600         (VEX_W_0F3808_P_2): Likewise.
 601         (VEX_W_0F3809_P_2): Likewise.
 602         (VEX_W_0F380A_P_2): Likewise.
 603         (VEX_W_0F380B_P_2): Likewise.
 604         (VEX_W_0F3817_P_2): Likewise.
 605         (VEX_W_0F381C_P_2): Likewise.
 606         (VEX_W_0F381D_P_2): Likewise.
 607         (VEX_W_0F381E_P_2): Likewise.
 608         (VEX_W_0F3820_P_2): Likewise.
 609         (VEX_W_0F3821_P_2): Likewise.
 610         (VEX_W_0F3822_P_2): Likewise.
 611         (VEX_W_0F3823_P_2): Likewise.
 612         (VEX_W_0F3824_P_2): Likewise.
 613         (VEX_W_0F3825_P_2): Likewise.
 614         (VEX_W_0F3828_P_2): Likewise.
 615         (VEX_W_0F3829_P_2): Likewise.
 616         (VEX_W_0F382A_P_2_M_0): Likewise.
 617         (VEX_W_0F382B_P_2): Likewise.
 618         (VEX_W_0F3830_P_2): Likewise.
 619         (VEX_W_0F3831_P_2): Likewise.
 620         (VEX_W_0F3832_P_2): Likewise.
 621         (VEX_W_0F3833_P_2): Likewise.
 622         (VEX_W_0F3834_P_2): Likewise.
 623         (VEX_W_0F3835_P_2): Likewise.
 624         (VEX_W_0F3837_P_2): Likewise.
 625         (VEX_W_0F3838_P_2): Likewise.
 626         (VEX_W_0F3839_P_2): Likewise.
 627         (VEX_W_0F383A_P_2): Likewise.
 628         (VEX_W_0F383B_P_2): Likewise.
 629         (VEX_W_0F383C_P_2): Likewise.
 630         (VEX_W_0F383D_P_2): Likewise.
 631         (VEX_W_0F383E_P_2): Likewise.
 632         (VEX_W_0F383F_P_2): Likewise.
 633         (VEX_W_0F3840_P_2): Likewise.
 634         (VEX_W_0F3841_P_2): Likewise.
 635         (VEX_W_0F38DB_P_2): Likewise.
 636         (VEX_W_0F3A08_P_2): Likewise.
 637         (VEX_W_0F3A09_P_2): Likewise.
 638         (VEX_W_0F3A0A_P_2): Likewise.
 639         (VEX_W_0F3A0B_P_2): Likewise.
 640         (VEX_W_0F3A0C_P_2): Likewise.
 641         (VEX_W_0F3A0D_P_2): Likewise.
 642         (VEX_W_0F3A0E_P_2): Likewise.
 643         (VEX_W_0F3A0F_P_2): Likewise.
 644         (VEX_W_0F3A21_P_2): Likewise.
 645         (VEX_W_0F3A40_P_2): Likewise.
 646         (VEX_W_0F3A41_P_2): Likewise.
 647         (VEX_W_0F3A42_P_2): Likewise.
 648         (VEX_W_0F3A62_P_2): Likewise.
 649         (VEX_W_0F3A63_P_2): Likewise.
 650         (VEX_W_0F3ADF_P_2): Likewise.
 651         (VEX_LEN_0F77_P_0): New.
 652         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 653         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 654         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 655         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 656         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 657         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 658         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 659         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 660         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 661         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 662         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 663         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 664         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 665         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 666         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 667         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 668         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 669         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 670         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 671         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 672         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 673         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 674         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 675         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 676         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 677         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 678         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 679         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 680         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 681         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 682         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 683         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 684         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 685         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 686         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 687         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 688         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 689         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 690         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 691         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 692         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 693         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 694         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 695         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 696         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 697         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 698         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 699         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 700         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 701         (vex_table): Update VEX 0F28 and 0F29 entries.
 702         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 703         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 704         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 705         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 706         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 707         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 708         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 709         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 710         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 711         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 712         VEX_LEN_0F3A0B_P_2 entries.
 713         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 714         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 715         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 716         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 717         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 718         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 719         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 720         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 721         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 722         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 723         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 724         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 725         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 726         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 727         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 728         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 729         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 730         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 731         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 732         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 733         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 734         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 735         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 736         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 737         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 738         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 739         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 740         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 741         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 742         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 743         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 744         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 745         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 746         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 747         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 748         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 749         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 750         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 751         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 752         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 753         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 754         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 755         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 756         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 757         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 758         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 759         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 760         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 761         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 762         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 763         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 764         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 765         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 766         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 767         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 768         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 769         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 770         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 771         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 772         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 773         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 774         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 775         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 776         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 777         VEX_W_0F3ADF_P_2 entries.
 778         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 779         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 780         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 781
 782 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         * i386-opc.tbl (VexWIG): New.
 785         Replace VexW=3 with VexWIG.
 786
 787 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 788
 789         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 790         * i386-tbl.h: Regenerated.
 791
 792 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 793
 794         PR gas/23665
 795         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 796         VEX_LEN_0FD6_P_2 entries.
 797         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 798         * i386-tbl.h: Regenerated.
 799
 800 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 801
 802         PR gas/23642
 803         * i386-opc.h (VEXWIG): New.
 804         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 805         * i386-tbl.h: Regenerated.
 806
 807 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 808
 809         PR binutils/23655
 810         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 811         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 812         * i386-dis.c (EXxEVexR64): New.
 813         (evex_rounding_64_mode): Likewise.
 814         (OP_Rounding): Handle evex_rounding_64_mode.
 815
 816 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         PR binutils/23655
 819         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 820         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 821         * i386-dis.c (Edqa): New.
 822         (dqa_mode): Likewise.
 823         (intel_operand_size): Handle dqa_mode as m_mode.
 824         (OP_E_register): Handle dqa_mode as dq_mode.
 825         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 826
 827 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 828
 829         * i386-dis.c (OP_E_memory): Reformat.
 830
 831 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 832
 833         * i386-opc.tbl (crc32): Fold byte and word forms.
 834         * i386-tbl.h: Re-generate.
 835
 836 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 837
 838         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 839         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 840         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 841         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 842         * i386-tbl.h: Regenerated.
 843
 844 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 845
 846         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 847         meaningless.
 848         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 849         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 850         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 851         * i386-tbl.h: Re-generate.
 852
 853 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 854
 855         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 856         AVX512_4VNNIW insns.
 857         * i386-tbl.h: Re-generate.
 858
 859 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 860
 861         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 862         meaningless.
 863         * i386-tbl.h: Re-generate.
 864
 865 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 866
 867         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 868         meaningless.
 869         * i386-tbl.h: Re-generate.
 870
 871 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 872
 873         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 874         meaningless.
 875         * i386-tbl.h: Re-generate.
 876
 877 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 878
 879         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 880         meaningless.
 881         * i386-tbl.h: Re-generate.
 882
 883 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 884
 885         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 886         meaningless.
 887         * i386-tbl.h: Re-generate.
 888
 889 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 890
 891         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 892         * i386-tbl.h: Re-generate.
 893
 894 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 895
 896         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 897         * i386-tbl.h: Re-generate.
 898
 899 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 900
 901         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 902         meaningless.
 903         * i386-tbl.h: Re-generate.
 904
 905 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 906
 907         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 908         meaningless.
 909         * i386-tbl.h: Re-generate.
 910
 911 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 912
 913         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 914         * i386-tbl.h: Re-generate.
 915
 916 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 917
 918         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 919         * i386-tbl.h: Re-generate.
 920
 921 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 924         * i386-tbl.h: Re-generate.
 925
 926 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 927
 928         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 929         meaningless.
 930         * i386-tbl.h: Re-generate.
 931
 932 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 933
 934         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 935         meaningless.
 936         * i386-tbl.h: Re-generate.
 937
 938 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 939
 940         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 941         meaningless.
 942         * i386-tbl.h: Re-generate.
 943
 944 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 945
 946         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 947         * i386-tbl.h: Re-generate.
 948
 949 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 950
 951         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 952         * i386-tbl.h: Re-generate.
 953
 954 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 957         * i386-tbl.h: Re-generate.
 958
 959 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 960
 961         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 962         (vpbroadcastw, rdpid): Drop NoRex64.
 963         * i386-tbl.h: Re-generate.
 964
 965 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 968         store templates, adding D.
 969         * i386-tbl.h: Re-generate.
 970
 971 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 972
 973         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 974         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 975         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 976         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 977         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 978         Fold load and store templates where possible, adding D. Drop
 979         IgnoreSize where it was pointlessly present. Drop redundant
 980         *word.
 981         * i386-tbl.h: Re-generate.
 982
 983 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 986         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 987         (intel_operand_size): Handle v_bndmk_mode.
 988         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 989
 990 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 991
 992         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 993
 994 2018-08-31  Kito Cheng  <kito@andestech.com>
 995
 996         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 997         compressed floating point instructions.
 998
 999 2018-08-30  Kito Cheng  <kito@andestech.com>
1000
1001         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1002         riscv_opcode.xlen_requirement.
1003         * riscv-opc.c (riscv_opcodes): Update for struct change.
1004
1005 2018-08-29  Martin Aberg  <maberg@gaisler.com>
1006
1007         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1008         psr (PWRPSR) instruction.
1009
1010 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1011
1012         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1013
1014 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1015
1016         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1017
1018 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1019
1020         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1021         loongson3a as an alias of gs464 for compatibility.
1022         * mips-opc.c (mips_opcodes): Change Comments.
1023
1024 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1025
1026         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1027         option.
1028         (print_mips_disassembler_options): Document -M loongson-ext.
1029         * mips-opc.c (LEXT2): New macro.
1030         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1031
1032 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1033
1034          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1035          descriptors.
1036          (parse_mips_ase_option): Handle -M loongson-ext option.
1037          (print_mips_disassembler_options): Document -M loongson-ext.
1038          * mips-opc.c (IL3A): Delete.
1039          * mips-opc.c (LEXT): New macro.
1040          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1041          instructions.
1042
1043 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1044
1045         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1046         descriptors.
1047         (parse_mips_ase_option): Handle -M loongson-cam option.
1048         (print_mips_disassembler_options): Document -M loongson-cam.
1049         * mips-opc.c (LCAM): New macro.
1050         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1051         instructions.
1052
1053 2018-08-21  Alan Modra  <amodra@gmail.com>
1054
1055         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1056         (skip_optional_operands): Count optional operands, and update
1057         ppc_optional_operand_value call.
1058         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1059         (extract_vlensi): Likewise.
1060         (extract_fxm): Return default value for missing optional operand.
1061         (extract_ls, extract_raq, extract_tbr): Likewise.
1062         (insert_sxl, extract_sxl): New functions.
1063         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1064         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1065         flag and extra entry.
1066         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1067         extract_sxl.
1068
1069 2018-08-20  Alan Modra  <amodra@gmail.com>
1070
1071         * sh-opc.h (MASK): Simplify.
1072
1073 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1074
1075         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1076         BM_RESERVED0 or BM_RESERVED1
1077         (bm_rel_decode, bm_n_bytes): Ditto.
1078
1079 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1080
1081         * s12z.h: Delete.
1082
1083 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1084
1085         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1086         address with the addr32 prefix and without base nor index
1087         registers.
1088
1089 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1090
1091         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1092         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1093         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1094         (cpu_flags): Add CpuCMOV and CpuFXSR.
1095         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1096         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1097         * i386-init.h: Regenerated.
1098         * i386-tbl.h: Likewise.
1099
1100 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1101
1102         * arc-regs.h: Update auxiliary registers.
1103
1104 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1105
1106         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1107         (RegIP, RegIZ): Define.
1108         * i386-reg.tbl: Adjust comments.
1109         (rip): Use Qword instead of BaseIndex. Use RegIP.
1110         (eip): Use Dword instead of BaseIndex. Use RegIP.
1111         (riz): Add Qword. Use RegIZ.
1112         (eiz): Add Dword. Use RegIZ.
1113         * i386-tbl.h: Re-generate.
1114
1115 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1116
1117         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1118         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1119         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1120         * i386-tbl.h: Re-generate.
1121
1122 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1123
1124         * i386-gen.c (operand_types): Remove Mem field.
1125         * i386-opc.h (union i386_operand_type): Remove mem field.
1126         * i386-init.h, i386-tbl.h: Re-generate.
1127
1128 2018-08-01  Alan Modra  <amodra@gmail.com>
1129
1130         * po/POTFILES.in: Regenerate.
1131
1132 2018-07-31  Nick Clifton  <nickc@redhat.com>
1133
1134         * po/sv.po: Updated Swedish translation.
1135
1136 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1137
1138         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1139         * i386-init.h, i386-tbl.h: Re-generate.
1140
1141 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1142
1143         * i386-opc.h (ZEROING_MASKING) Rename to ...
1144         (DYNAMIC_MASKING): ... this. Adjust comment.
1145         * i386-opc.tbl (MaskingMorZ): Define.
1146         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1147         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1148         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1149         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1150         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1151         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1152         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1153         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1154         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1155
1156 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1157
1158         * i386-opc.tbl: Use element rather than vector size for AVX512*
1159         scatter/gather insns.
1160         * i386-tbl.h: Re-generate.
1161
1162 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1163
1164         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1165         (cpu_flags): Drop CpuVREX.
1166         * i386-opc.h (CpuVREX): Delete.
1167         (union i386_cpu_flags): Remove cpuvrex.
1168         * i386-init.h, i386-tbl.h: Re-generate.
1169
1170 2018-07-30  Jim Wilson  <jimw@sifive.com>
1171
1172         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1173         fields.
1174         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1175
1176 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1177
1178         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1179         * Makefile.in: Regenerated.
1180         * configure.ac: Add C-SKY.
1181         * configure: Regenerated.
1182         * csky-dis.c: New file.
1183         * csky-opc.h: New file.
1184         * disassemble.c (ARCH_csky): Define.
1185         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1186         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1187
1188 2018-07-27  Alan Modra  <amodra@gmail.com>
1189
1190         * ppc-opc.c (insert_sprbat): Correct function parameter and
1191         return type.
1192         (extract_sprbat): Likewise, variable too.
1193
1194 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1195             Alan Modra  <amodra@gmail.com>
1196
1197         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1198         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1199         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1200         support disjointed BAT.
1201         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1202         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1203         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1204
1205 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1206             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1207
1208         * i386-gen.c (adjust_broadcast_modifier): New function.
1209         (process_i386_opcode_modifier): Add an argument for operands.
1210         Adjust the Broadcast value based on operands.
1211         (output_i386_opcode): Pass operand_types to
1212         process_i386_opcode_modifier.
1213         (process_i386_opcodes): Pass NULL as operands to
1214         process_i386_opcode_modifier.
1215         * i386-opc.h (BYTE_BROADCAST): New.
1216         (WORD_BROADCAST): Likewise.
1217         (DWORD_BROADCAST): Likewise.
1218         (QWORD_BROADCAST): Likewise.
1219         (i386_opcode_modifier): Expand broadcast to 3 bits.
1220         * i386-tbl.h: Regenerated.
1221
1222 2018-07-24  Alan Modra  <amodra@gmail.com>
1223
1224         PR 23430
1225         * or1k-desc.h: Regenerate.
1226
1227 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1228
1229         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1230         vcvtusi2ss, and vcvtusi2sd.
1231         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1232         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1233         * i386-tbl.h: Re-generate.
1234
1235 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1236
1237         * arc-opc.c (extract_w6): Fix extending the sign.
1238
1239 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1240
1241         * arc-tbl.h (vewt): Allow it for ARC EM family.
1242
1243 2018-07-23  Alan Modra  <amodra@gmail.com>
1244
1245         PR 23419
1246         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1247         opcode variants for mtspr/mfspr encodings.
1248
1249 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1250             Maciej W. Rozycki  <macro@mips.com>
1251
1252         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1253         loongson3a descriptors.
1254         (parse_mips_ase_option): Handle -M loongson-mmi option.
1255         (print_mips_disassembler_options): Document -M loongson-mmi.
1256         * mips-opc.c (LMMI): New macro.
1257         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1258         instructions.
1259
1260 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1261
1262         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1263         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1264         IgnoreSize and [XYZ]MMword where applicable.
1265         * i386-tbl.h: Re-generate.
1266
1267 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1268
1269         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1270         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1271         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1272         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1273         * i386-tbl.h: Re-generate.
1274
1275 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1276
1277         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1278         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1279         VPCLMULQDQ templates into their respective AVX512VL counterparts
1280         where possible, using Disp8ShiftVL and CheckRegSize instead of
1281         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1282         * i386-tbl.h: Re-generate.
1283
1284 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1285
1286         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1287         AVX512VL counterparts where possible, using Disp8ShiftVL and
1288         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1289         IgnoreSize) as appropriate.
1290         * i386-tbl.h: Re-generate.
1291
1292 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1293
1294         * i386-opc.tbl: Fold AVX512BW templates into their respective
1295         AVX512VL counterparts where possible, using Disp8ShiftVL and
1296         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1297         IgnoreSize) as appropriate.
1298         * i386-tbl.h: Re-generate.
1299
1300 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1301
1302         * i386-opc.tbl: Fold AVX512CD templates into their respective
1303         AVX512VL counterparts where possible, using Disp8ShiftVL and
1304         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1305         IgnoreSize) as appropriate.
1306         * i386-tbl.h: Re-generate.
1307
1308 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1309
1310         * i386-opc.h (DISP8_SHIFT_VL): New.
1311         * i386-opc.tbl (Disp8ShiftVL):  Define.
1312         (various): Fold AVX512VL templates into their respective
1313         AVX512F counterparts where possible, using Disp8ShiftVL and
1314         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1315         IgnoreSize) as appropriate.
1316         * i386-tbl.h: Re-generate.
1317
1318 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1319
1320         * Makefile.am: Change dependencies and rule for
1321         $(srcdir)/i386-init.h.
1322         * Makefile.in: Re-generate.
1323         * i386-gen.c (process_i386_opcodes): New local variable
1324         "marker". Drop opening of input file. Recognize marker and line
1325         number directives.
1326         * i386-opc.tbl (OPCODE_I386_H): Define.
1327         (i386-opc.h): Include it.
1328         (None): Undefine.
1329
1330 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1331
1332         PR gas/23418
1333         * i386-opc.h (Byte): Update comments.
1334         (Word): Likewise.
1335         (Dword): Likewise.
1336         (Fword): Likewise.
1337         (Qword): Likewise.
1338         (Tbyte): Likewise.
1339         (Xmmword): Likewise.
1340         (Ymmword): Likewise.
1341         (Zmmword): Likewise.
1342         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1343         vcvttps2uqq.
1344         * i386-tbl.h: Regenerated.
1345
1346 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1347
1348         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1349         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1350         * aarch64-asm-2.c: Regenerate.
1351         * aarch64-dis-2.c: Regenerate.
1352         * aarch64-opc-2.c: Regenerate.
1353
1354 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1355
1356         PR binutils/23192
1357         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1358         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1359         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1360         sqdmulh, sqrdmulh): Use Em16.
1361
1362 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1363
1364         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1365         csdb together with them.
1366         (thumb32_opcodes): Likewise.
1367
1368 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1369
1370         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1371         requiring 32-bit registers as operands 2 and 3. Improve
1372         comments.
1373         (mwait, mwaitx): Fold templates. Improve comments.
1374         OPERAND_TYPE_INOUTPORTREG.
1375         * i386-tbl.h: Re-generate.
1376
1377 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1378
1379         * i386-gen.c (operand_type_init): Remove
1380         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1381         OPERAND_TYPE_INOUTPORTREG.
1382         * i386-init.h: Re-generate.
1383
1384 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1385
1386         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1387         (wrssq, wrussq): Add Qword.
1388         * i386-tbl.h: Re-generate.
1389
1390 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1391
1392         * i386-opc.h: Rename OTMax to OTNum.
1393         (OTNumOfUints): Adjust calculation.
1394         (OTUnused): Directly alias to OTNum.
1395
1396 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1397
1398         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1399         `reg_xys'.
1400         (lea_reg_xys): Likewise.
1401         (print_insn_loop_primitive): Rename `reg' local variable to
1402         `reg_dxy'.
1403
1404 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1405
1406         PR binutils/23242
1407         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1408
1409 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1410
1411         PR binutils/23369
1412         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1413         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1414
1415 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1416
1417         PR tdep/8282
1418         * mips-dis.c (mips_option_arg_t): New enumeration.
1419         (mips_options): New variable.
1420         (disassembler_options_mips): New function.
1421         (print_mips_disassembler_options): Reimplement in terms of
1422         `disassembler_options_mips'.
1423         * arm-dis.c (disassembler_options_arm): Adapt to using the
1424         `disasm_options_and_args_t' structure.
1425         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1426         * s390-dis.c (disassembler_options_s390): Likewise.
1427
1428 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1429
1430         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1431         expected result.
1432         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1433         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1434         * testsuite/ld-arm/tls-longplt.d: Likewise.
1435
1436 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1437
1438         PR binutils/23192
1439         * aarch64-asm-2.c: Regenerate.
1440         * aarch64-dis-2.c: Likewise.
1441         * aarch64-opc-2.c: Likewise.
1442         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1443         * aarch64-opc.c (operand_general_constraint_met_p,
1444         aarch64_print_operand): Likewise.
1445         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1446         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1447         fmlal2, fmlsl2.
1448         (AARCH64_OPERANDS): Add Em2.
1449
1450 2018-06-26  Nick Clifton  <nickc@redhat.com>
1451
1452         * po/uk.po: Updated Ukranian translation.
1453         * po/de.po: Updated German translation.
1454         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1455
1456 2018-06-26  Nick Clifton  <nickc@redhat.com>
1457
1458         * nfp-dis.c: Fix spelling mistake.
1459
1460 2018-06-24  Nick Clifton  <nickc@redhat.com>
1461
1462         * configure: Regenerate.
1463         * po/opcodes.pot: Regenerate.
1464
1465 2018-06-24  Nick Clifton  <nickc@redhat.com>
1466
1467         2.31 branch created.
1468
1469 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1470
1471         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1472         * aarch64-asm-2.c: Regenerate.
1473         * aarch64-dis-2.c: Likewise.
1474
1475 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1476
1477         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1478         `-M ginv' option description.
1479
1480 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1481
1482         PR gas/23305
1483         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1484         la and lla.
1485
1486 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1487
1488         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1489         * configure.ac: Remove AC_PREREQ.
1490         * Makefile.in: Re-generate.
1491         * aclocal.m4: Re-generate.
1492         * configure: Re-generate.
1493
1494 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1495
1496         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1497         mips64r6 descriptors.
1498         (parse_mips_ase_option): Handle -Mginv option.
1499         (print_mips_disassembler_options): Document -Mginv.
1500         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1501         (GINV): New macro.
1502         (mips_opcodes): Define ginvi and ginvt.
1503
1504 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1505             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1506
1507         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1508         * mips-opc.c (CRC, CRC64): New macros.
1509         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1510         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1511         crc32cd for CRC64.
1512
1513 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1514
1515         PR 20319
1516         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1517         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1518
1519 2018-06-06  Alan Modra  <amodra@gmail.com>
1520
1521         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1522         setjmp.  Move init for some other vars later too.
1523
1524 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1525
1526         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1527         (dis_private): Add new fields for property section tracking.
1528         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1529         (xtensa_instruction_fits): New functions.
1530         (fetch_data): Bump minimal fetch size to 4.
1531         (print_insn_xtensa): Make struct dis_private static.
1532         Load and prepare property table on section change.
1533         Don't disassemble literals. Don't disassemble instructions that
1534         cross property table boundaries.
1535
1536 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1537
1538         * configure: Regenerated.
1539
1540 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1541
1542         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1543         * i386-tbl.h: Re-generate.
1544
1545 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1546
1547         * i386-opc.tbl (sldt, str): Add NoRex64.
1548         * i386-tbl.h: Re-generate.
1549
1550 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1551
1552         * i386-opc.tbl (invpcid): Add Oword.
1553         * i386-tbl.h: Re-generate.
1554
1555 2018-06-01  Alan Modra  <amodra@gmail.com>
1556
1557         * sysdep.h (_bfd_error_handler): Don't declare.
1558         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1559         * rl78-decode.opc: Likewise.
1560         * msp430-decode.c: Regenerate.
1561         * rl78-decode.c: Regenerate.
1562
1563 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1564
1565         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1566         * i386-init.h : Regenerated.
1567
1568 2018-05-25  Alan Modra  <amodra@gmail.com>
1569
1570         * Makefile.in: Regenerate.
1571         * po/POTFILES.in: Regenerate.
1572
1573 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1574
1575         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1576         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1577         (insert_bab, extract_bab, insert_btab, extract_btab,
1578         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1579         (BAT, BBA VBA RBS XB6S): Delete macros.
1580         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1581         (BB, BD, RBX, XC6): Update for new macros.
1582         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1583         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1584         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1585         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1586
1587 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1588
1589         * Makefile.am: Add support for s12z architecture.
1590         * configure.ac: Likewise.
1591         * disassemble.c: Likewise.
1592         * disassemble.h: Likewise.
1593         * Makefile.in: Regenerate.
1594         * configure: Regenerate.
1595         * s12z-dis.c: New file.
1596         * s12z.h: New file.
1597
1598 2018-05-18  Alan Modra  <amodra@gmail.com>
1599
1600         * nfp-dis.c: Don't #include libbfd.h.
1601         (init_nfp3200_priv): Use bfd_get_section_contents.
1602         (nit_nfp6000_mecsr_sec): Likewise.
1603
1604 2018-05-17  Nick Clifton  <nickc@redhat.com>
1605
1606         * po/zh_CN.po: Updated simplified Chinese translation.
1607
1608 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1609
1610         PR binutils/23109
1611         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1612         * aarch64-dis-2.c: Regenerate.
1613
1614 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1615
1616         PR binutils/21446
1617         * aarch64-asm.c (opintl.h): Include.
1618         (aarch64_ins_sysreg): Enforce read/write constraints.
1619         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1620         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1621         (F_REG_READ, F_REG_WRITE): New.
1622         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1623         AARCH64_OPND_SYSREG.
1624         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1625         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1626         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1627         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1628         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1629         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1630         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1631         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1632         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1633         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1634         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1635         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1636         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1637         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1638         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1639         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1640         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1641
1642 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1643
1644         PR binutils/21446
1645         * aarch64-dis.c (no_notes: New.
1646         (parse_aarch64_dis_option): Support notes.
1647         (aarch64_decode_insn, print_operands): Likewise.
1648         (print_aarch64_disassembler_options): Document notes.
1649         * aarch64-opc.c (aarch64_print_operand): Support notes.
1650
1651 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1652
1653         PR binutils/21446
1654         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1655         and take error struct.
1656         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1657         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1658         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1659         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1660         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1661         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1662         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1663         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1664         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1665         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1666         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1667         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1668         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1669         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1670         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1671         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1672         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1673         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1674         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1675         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1676         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1677         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1678         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1679         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1680         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1681         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1682         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1683         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1684         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1685         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1686         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1687         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1688         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1689         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1690         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1691         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1692         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1693         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1694         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1695         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1696         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1697         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1698         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1699         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1700         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1701         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1702         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1703         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1704         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1705         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1706         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1707         (determine_disassembling_preference, aarch64_decode_insn,
1708         print_insn_aarch64_word, print_insn_data): Take errors struct.
1709         (print_insn_aarch64): Use errors.
1710         * aarch64-asm-2.c: Regenerate.
1711         * aarch64-dis-2.c: Regenerate.
1712         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1713         boolean in aarch64_insert_operan.
1714         (print_operand_extractor): Likewise.
1715         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1716
1717 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1718
1719         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1720
1721 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1722
1723         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1724
1725 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1726
1727         * cr16-opc.c (cr16_instruction): Comment typo fix.
1728         * hppa-dis.c (print_insn_hppa): Likewise.
1729
1730 2018-05-08  Jim Wilson  <jimw@sifive.com>
1731
1732         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1733         (match_c_slli64, match_srxi_as_c_srxi): New.
1734         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1735         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1736         <c.slli, c.srli, c.srai>: Use match_s_slli.
1737         <c.slli64, c.srli64, c.srai64>: New.
1738
1739 2018-05-08  Alan Modra  <amodra@gmail.com>
1740
1741         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1742         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1743         partition opcode space for index lookup.
1744
1745 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1746
1747         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1748         <insn_length>: ...with this.  Update usage.
1749         Remove duplicate call to *info->memory_error_func.
1750
1751 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1752             H.J. Lu  <hongjiu.lu@intel.com>
1753
1754         * i386-dis.c (Gva): New.
1755         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1756         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1757         (prefix_table): New instructions (see prefix above).
1758         (mod_table): New instructions (see prefix above).
1759         (OP_G): Handle va_mode.
1760         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1761         CPU_MOVDIR64B_FLAGS.
1762         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1763         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1764         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1765         * i386-opc.tbl: Add movidir{i,64b}.
1766         * i386-init.h: Regenerated.
1767         * i386-tbl.h: Likewise.
1768
1769 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1770
1771         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1772         AddrPrefixOpReg.
1773         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1774         (AddrPrefixOpReg): This.
1775         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1776         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1777
1778 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1779
1780         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1781         (vle_num_opcodes): Likewise.
1782         (spe2_num_opcodes): Likewise.
1783         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1784         initialization loop.
1785         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1786         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1787         only once.
1788
1789 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1790
1791         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1792
1793 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1794
1795         Makefile.am: Added nfp-dis.c.
1796         configure.ac: Added bfd_nfp_arch.
1797         disassemble.h: Added print_insn_nfp prototype.
1798         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1799         nfp-dis.c: New, for NFP support.
1800         po/POTFILES.in: Added nfp-dis.c to the list.
1801         Makefile.in: Regenerate.
1802         configure: Regenerate.
1803
1804 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1805
1806         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1807         templates into their base ones.
1808         * i386-tlb.h: Re-generate.
1809
1810 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1811
1812         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1813         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1814         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1815         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1816         * i386-init.h: Re-generate.
1817
1818 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1819
1820         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1821         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1822         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1823         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1824         comment.
1825         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1826         and CpuRegMask.
1827         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1828         CpuRegMask: Delete.
1829         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1830         cpuregzmm, and cpuregmask.
1831         * i386-init.h: Re-generate.
1832         * i386-tbl.h: Re-generate.
1833
1834 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1835
1836         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1837         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1838         * i386-init.h: Re-generate.
1839
1840 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1841
1842         * i386-gen.c (VexImmExt): Delete.
1843         * i386-opc.h (VexImmExt, veximmext): Delete.
1844         * i386-opc.tbl: Drop all VexImmExt uses.
1845         * i386-tlb.h: Re-generate.
1846
1847 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1848
1849         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1850         register-only forms.
1851         * i386-tlb.h: Re-generate.
1852
1853 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1854
1855         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1856
1857 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1858
1859         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1860         PREFIX_0F1C.
1861         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1862         (cpu_flags): Add CpuCLDEMOTE.
1863         * i386-init.h: Regenerate.
1864         * i386-opc.h (enum): Add CpuCLDEMOTE,
1865         (i386_cpu_flags): Add cpucldemote.
1866         * i386-opc.tbl: Add cldemote.
1867         * i386-tbl.h: Regenerate.
1868
1869 2018-04-16  Alan Modra  <amodra@gmail.com>
1870
1871         * Makefile.am: Remove sh5 and sh64 support.
1872         * configure.ac: Likewise.
1873         * disassemble.c: Likewise.
1874         * disassemble.h: Likewise.
1875         * sh-dis.c: Likewise.
1876         * sh64-dis.c: Delete.
1877         * sh64-opc.c: Delete.
1878         * sh64-opc.h: Delete.
1879         * Makefile.in: Regenerate.
1880         * configure: Regenerate.
1881         * po/POTFILES.in: Regenerate.
1882
1883 2018-04-16  Alan Modra  <amodra@gmail.com>
1884
1885         * Makefile.am: Remove w65 support.
1886         * configure.ac: Likewise.
1887         * disassemble.c: Likewise.
1888         * disassemble.h: Likewise.
1889         * w65-dis.c: Delete.
1890         * w65-opc.h: Delete.
1891         * Makefile.in: Regenerate.
1892         * configure: Regenerate.
1893         * po/POTFILES.in: Regenerate.
1894
1895 2018-04-16  Alan Modra  <amodra@gmail.com>
1896
1897         * configure.ac: Remove we32k support.
1898         * configure: Regenerate.
1899
1900 2018-04-16  Alan Modra  <amodra@gmail.com>
1901
1902         * Makefile.am: Remove m88k support.
1903         * configure.ac: Likewise.
1904         * disassemble.c: Likewise.
1905         * disassemble.h: Likewise.
1906         * m88k-dis.c: Delete.
1907         * Makefile.in: Regenerate.
1908         * configure: Regenerate.
1909         * po/POTFILES.in: Regenerate.
1910
1911 2018-04-16  Alan Modra  <amodra@gmail.com>
1912
1913         * Makefile.am: Remove i370 support.
1914         * configure.ac: Likewise.
1915         * disassemble.c: Likewise.
1916         * disassemble.h: Likewise.
1917         * i370-dis.c: Delete.
1918         * i370-opc.c: Delete.
1919         * Makefile.in: Regenerate.
1920         * configure: Regenerate.
1921         * po/POTFILES.in: Regenerate.
1922
1923 2018-04-16  Alan Modra  <amodra@gmail.com>
1924
1925         * Makefile.am: Remove h8500 support.
1926         * configure.ac: Likewise.
1927         * disassemble.c: Likewise.
1928         * disassemble.h: Likewise.
1929         * h8500-dis.c: Delete.
1930         * h8500-opc.h: Delete.
1931         * Makefile.in: Regenerate.
1932         * configure: Regenerate.
1933         * po/POTFILES.in: Regenerate.
1934
1935 2018-04-16  Alan Modra  <amodra@gmail.com>
1936
1937         * configure.ac: Remove tahoe support.
1938         * configure: Regenerate.
1939
1940 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1941
1942         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1943         umwait.
1944         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1945         64-bit mode.
1946         * i386-tbl.h: Regenerated.
1947
1948 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1949
1950         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1951         PREFIX_MOD_1_0FAE_REG_6.
1952         (va_mode): New.
1953         (OP_E_register): Use va_mode.
1954         * i386-dis-evex.h (prefix_table):
1955         New instructions (see prefixes above).
1956         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1957         (cpu_flags): Likewise.
1958         * i386-opc.h (enum): Likewise.
1959         (i386_cpu_flags): Likewise.
1960         * i386-opc.tbl: Add umonitor, umwait, tpause.
1961         * i386-init.h: Regenerate.
1962         * i386-tbl.h: Likewise.
1963
1964 2018-04-11  Alan Modra  <amodra@gmail.com>
1965
1966         * opcodes/i860-dis.c: Delete.
1967         * opcodes/i960-dis.c: Delete.
1968         * Makefile.am: Remove i860 and i960 support.
1969         * configure.ac: Likewise.
1970         * disassemble.c: Likewise.
1971         * disassemble.h: Likewise.
1972         * Makefile.in: Regenerate.
1973         * configure: Regenerate.
1974         * po/POTFILES.in: Regenerate.
1975
1976 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1977
1978         PR binutils/23025
1979         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1980         to 0.
1981         (print_insn): Clear vex instead of vex.evex.
1982
1983 2018-04-04  Nick Clifton  <nickc@redhat.com>
1984
1985         * po/es.po: Updated Spanish translation.
1986
1987 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1988
1989         * i386-gen.c (opcode_modifiers): Delete VecESize.
1990         * i386-opc.h (VecESize): Delete.
1991         (struct i386_opcode_modifier): Delete vecesize.
1992         * i386-opc.tbl: Drop VecESize.
1993         * i386-tlb.h: Re-generate.
1994
1995 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1996
1997         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1998         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1999         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2000         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2001         * i386-tlb.h: Re-generate.
2002
2003 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2004
2005         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2006         Fold AVX512 forms
2007         * i386-tlb.h: Re-generate.
2008
2009 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2010
2011         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2012         (vex_len_table): Drop Y for vcvt*2si.
2013         (putop): Replace plain 'Y' handling by abort().
2014
2015 2018-03-28  Nick Clifton  <nickc@redhat.com>
2016
2017         PR 22988
2018         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2019         instructions with only a base address register.
2020         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2021         handle AARHC64_OPND_SVE_ADDR_R.
2022         (aarch64_print_operand): Likewise.
2023         * aarch64-asm-2.c: Regenerate.
2024         * aarch64_dis-2.c: Regenerate.
2025         * aarch64-opc-2.c: Regenerate.
2026
2027 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2028
2029         * i386-opc.tbl: Drop VecESize from register only insn forms and
2030         memory forms not allowing broadcast.
2031         * i386-tlb.h: Re-generate.
2032
2033 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2034
2035         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2036         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2037         sha256*): Drop Disp<N>.
2038
2039 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2040
2041         * i386-dis.c (EbndS, bnd_swap_mode): New.
2042         (prefix_table): Use EbndS.
2043         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2044         * i386-opc.tbl (bndmov): Move misplaced Load.
2045         * i386-tlb.h: Re-generate.
2046
2047 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2048
2049         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2050         templates allowing memory operands and folded ones for register
2051         only flavors.
2052         * i386-tlb.h: Re-generate.
2053
2054 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2055
2056         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2057         256-bit templates. Drop redundant leftover Disp<N>.
2058         * i386-tlb.h: Re-generate.
2059
2060 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2061
2062         * riscv-opc.c (riscv_insn_types): New.
2063
2064 2018-03-13  Nick Clifton  <nickc@redhat.com>
2065
2066         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2067
2068 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2069
2070         * i386-opc.tbl: Add Optimize to clr.
2071         * i386-tbl.h: Regenerated.
2072
2073 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2074
2075         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2076         * i386-opc.h (OldGcc): Removed.
2077         (i386_opcode_modifier): Remove oldgcc.
2078         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2079         instructions for old (<= 2.8.1) versions of gcc.
2080         * i386-tbl.h: Regenerated.
2081
2082 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2083
2084         * i386-opc.h (EVEXDYN): New.
2085         * i386-opc.tbl: Fold various AVX512VL templates.
2086         * i386-tlb.h: Re-generate.
2087
2088 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2089
2090         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2091         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2092         vpexpandd, vpexpandq): Fold AFX512VF templates.
2093         * i386-tlb.h: Re-generate.
2094
2095 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2096
2097         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2098         Fold 128- and 256-bit VEX-encoded templates.
2099         * i386-tlb.h: Re-generate.
2100
2101 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2102
2103         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2104         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2105         vpexpandd, vpexpandq): Fold AVX512F templates.
2106         * i386-tlb.h: Re-generate.
2107
2108 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2109
2110         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2111         64-bit templates. Drop Disp<N>.
2112         * i386-tlb.h: Re-generate.
2113
2114 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2115
2116         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2117         and 256-bit templates.
2118         * i386-tlb.h: Re-generate.
2119
2120 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2121
2122         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2123         * i386-tlb.h: Re-generate.
2124
2125 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2126
2127         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2128         Drop NoAVX.
2129         * i386-tlb.h: Re-generate.
2130
2131 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2132
2133         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2134         * i386-tlb.h: Re-generate.
2135
2136 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2137
2138         * i386-gen.c (opcode_modifiers): Delete FloatD.
2139         * i386-opc.h (FloatD): Delete.
2140         (struct i386_opcode_modifier): Delete floatd.
2141         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2142         FloatD by D.
2143         * i386-tlb.h: Re-generate.
2144
2145 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2146
2147         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2148
2149 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2150
2151         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2152         * i386-tlb.h: Re-generate.
2153
2154 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2155
2156         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2157         forms.
2158         * i386-tlb.h: Re-generate.
2159
2160 2018-03-07  Alan Modra  <amodra@gmail.com>
2161
2162         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2163         bfd_arch_rs6000.
2164         * disassemble.h (print_insn_rs6000): Delete.
2165         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2166         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2167         (print_insn_rs6000): Delete.
2168
2169 2018-03-03  Alan Modra  <amodra@gmail.com>
2170
2171         * sysdep.h (opcodes_error_handler): Define.
2172         (_bfd_error_handler): Declare.
2173         * Makefile.am: Remove stray #.
2174         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2175         EDIT" comment.
2176         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2177         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2178         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2179         opcodes_error_handler to print errors.  Standardize error messages.
2180         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2181         and include opintl.h.
2182         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2183         * i386-gen.c: Standardize error messages.
2184         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2185         * Makefile.in: Regenerate.
2186         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2187         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2188         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2189         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2190         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2191         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2192         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2193         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2194         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2195         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2196         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2197         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2198         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2199
2200 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2201
2202         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2203         vpsub[bwdq] instructions.
2204         * i386-tbl.h: Regenerated.
2205
2206 2018-03-01  Alan Modra  <amodra@gmail.com>
2207
2208         * configure.ac (ALL_LINGUAS): Sort.
2209         * configure: Regenerate.
2210
2211 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2212
2213         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2214         macro by assignements.
2215
2216 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2217
2218         PR gas/22871
2219         * i386-gen.c (opcode_modifiers): Add Optimize.
2220         * i386-opc.h (Optimize): New enum.
2221         (i386_opcode_modifier): Add optimize.
2222         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2223         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2224         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2225         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2226         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2227         vpxord and vpxorq.
2228         * i386-tbl.h: Regenerated.
2229
2230 2018-02-26  Alan Modra  <amodra@gmail.com>
2231
2232         * crx-dis.c (getregliststring): Allocate a large enough buffer
2233         to silence false positive gcc8 warning.
2234
2235 2018-02-22  Shea Levy <shea@shealevy.com>
2236
2237         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2238
2239 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2240
2241         * i386-opc.tbl: Add {rex},
2242         * i386-tbl.h: Regenerated.
2243
2244 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2245
2246         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2247         (mips16_opcodes): Replace `M' with `m' for "restore".
2248
2249 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2250
2251         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2252
2253 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2254
2255         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2256         variable to `function_index'.
2257
2258 2018-02-13  Nick Clifton  <nickc@redhat.com>
2259
2260         PR 22823
2261         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2262         about truncation of printing.
2263
2264 2018-02-12  Henry Wong <henry@stuffedcow.net>
2265
2266         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2267
2268 2018-02-05  Nick Clifton  <nickc@redhat.com>
2269
2270         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2271
2272 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2273
2274         * i386-dis.c (enum): Add pconfig.
2275         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2276         (cpu_flags): Add CpuPCONFIG.
2277         * i386-opc.h (enum): Add CpuPCONFIG.
2278         (i386_cpu_flags): Add cpupconfig.
2279         * i386-opc.tbl: Add PCONFIG instruction.
2280         * i386-init.h: Regenerate.
2281         * i386-tbl.h: Likewise.
2282
2283 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2284
2285         * i386-dis.c (enum): Add PREFIX_0F09.
2286         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2287         (cpu_flags): Add CpuWBNOINVD.
2288         * i386-opc.h (enum): Add CpuWBNOINVD.
2289         (i386_cpu_flags): Add cpuwbnoinvd.
2290         * i386-opc.tbl: Add WBNOINVD instruction.
2291         * i386-init.h: Regenerate.
2292         * i386-tbl.h: Likewise.
2293
2294 2018-01-17  Jim Wilson  <jimw@sifive.com>
2295
2296         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2297
2298 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2299
2300         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2301         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2302         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2303         (cpu_flags): Add CpuIBT, CpuSHSTK.
2304         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2305         (i386_cpu_flags): Add cpuibt, cpushstk.
2306         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2307         * i386-init.h: Regenerate.
2308         * i386-tbl.h: Likewise.
2309
2310 2018-01-16  Nick Clifton  <nickc@redhat.com>
2311
2312         * po/pt_BR.po: Updated Brazilian Portugese translation.
2313         * po/de.po: Updated German translation.
2314
2315 2018-01-15  Jim Wilson  <jimw@sifive.com>
2316
2317         * riscv-opc.c (match_c_nop): New.
2318         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2319
2320 2018-01-15  Nick Clifton  <nickc@redhat.com>
2321
2322         * po/uk.po: Updated Ukranian translation.
2323
2324 2018-01-13  Nick Clifton  <nickc@redhat.com>
2325
2326         * po/opcodes.pot: Regenerated.
2327
2328 2018-01-13  Nick Clifton  <nickc@redhat.com>
2329
2330         * configure: Regenerate.
2331
2332 2018-01-13  Nick Clifton  <nickc@redhat.com>
2333
2334         2.30 branch created.
2335
2336 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2337
2338         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2339         * i386-tbl.h: Regenerate.
2340
2341 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2342
2343         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2344         * i386-tbl.h: Re-generate.
2345
2346 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2347
2348         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2349         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2350         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2351         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2352         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2353         Disp8MemShift of AVX512VL forms.
2354         * i386-tbl.h: Re-generate.
2355
2356 2018-01-09  Jim Wilson  <jimw@sifive.com>
2357
2358         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2359         then the hi_addr value is zero.
2360
2361 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2362
2363         * arm-dis.c (arm_opcodes): Add csdb.
2364         (thumb32_opcodes): Add csdb.
2365
2366 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2367
2368         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2369         * aarch64-asm-2.c: Regenerate.
2370         * aarch64-dis-2.c: Regenerate.
2371         * aarch64-opc-2.c: Regenerate.
2372
2373 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2374
2375         PR gas/22681
2376         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2377         Remove AVX512 vmovd with 64-bit operands.
2378         * i386-tbl.h: Regenerated.
2379
2380 2018-01-05  Jim Wilson  <jimw@sifive.com>
2381
2382         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2383         jalr.
2384
2385 2018-01-03  Alan Modra  <amodra@gmail.com>
2386
2387         Update year range in copyright notice of all files.
2388
2389 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2390
2391         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2392         and OPERAND_TYPE_REGZMM entries.
2393
2394 For older changes see ChangeLog-2017
2395 \f
2396 Copyright (C) 2018 Free Software Foundation, Inc.
2397
2398 Copying and distribution of this file, with or without modification,
2399 are permitted in any medium without royalty provided the copyright
2400 notice and this notice are preserved.
2401
2402 Local Variables:
2403 mode: change-log
2404 left-margin: 8
2405 fill-column: 74
2406 version-control: never
2407 End: