opcodes/ChangeLog

   1 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
   2
   3         PR target/20553
   4         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
   5
   6 2016-09-29  Alan Modra  <amodra@gmail.com>
   7
   8         * ppc-opc.c (L): Make compulsory.
   9         (LOPT): New, optional form of L.
  10         (HTM_R): Define as LOPT.
  11         (L0, L1): Delete.
  12         (L32OPT): New, optional for 32-bit L.
  13         (L2OPT): New, 2-bit L for dcbf.
  14         (SVC_LEC): Update.
  15         (L2): Define.
  16         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
  17         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
  18         <dcbf>: Use L2OPT.
  19         <tlbiel, tlbie>: Use LOPT.
  20         <wclr, wclrall>: Use L2.
  21
  22 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
  23
  24         * Makefile.in: Regenerate.
  25         * configure: Likewise.
  26
  27 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
  28
  29         * arc-ext-tbl.h (EXTINSN2OPF): Define.
  30         (EXTINSN2OP): Use EXTINSN2OPF.
  31         (bspeekm, bspop, modapp): New extension instructions.
  32         * arc-opc.c (F_DNZ_ND): Define.
  33         (F_DNZ_D): Likewise.
  34         (F_SIZEB1): Changed.
  35         (C_DNZ_D): Define.
  36         (C_HARD): Changed.
  37         * arc-tbl.h (dbnz): New instruction.
  38         (prealloc): Allow it for ARC EM.
  39         (xbfu): Likewise.
  40
  41 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  42
  43         * aarch64-opc.c (print_immediate_offset_address): Print spaces
  44         after commas in addresses.
  45         (aarch64_print_operand): Likewise.
  46
  47 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  48
  49         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
  50         rather than "should be" or "expected to be" in error messages.
  51
  52 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  53
  54         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
  55         (print_mnemonic_name): ...here.
  56         (print_comment): New function.
  57         (print_aarch64_insn): Call it.
  58         * aarch64-opc.c (aarch64_conds): Add SVE names.
  59         (aarch64_print_operand): Print alternative condition names in
  60         a comment.
  61
  62 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  63
  64         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
  65         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
  66         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
  67         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
  68         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
  69         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
  70         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
  71         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
  72         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
  73         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
  74         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
  75         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
  76         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
  77         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
  78         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
  79         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
  80         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
  81         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
  82         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
  83         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
  84         (OP_SVE_XWU, OP_SVE_XXU): New macros.
  85         (aarch64_feature_sve): New variable.
  86         (SVE): New macro.
  87         (_SVE_INSN): Likewise.
  88         (aarch64_opcode_table): Add SVE instructions.
  89         * aarch64-opc.h (extract_fields): Declare.
  90         * aarch64-opc-2.c: Regenerate.
  91         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
  92         * aarch64-asm-2.c: Regenerate.
  93         * aarch64-dis.c (extract_fields): Make global.
  94         (do_misc_decoding): Handle the new SVE aarch64_ops.
  95         * aarch64-dis-2.c: Regenerate.
  96
  97 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  98
  99         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 100         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 101         aarch64_field_kinds.
 102         * aarch64-opc.c (fields): Add corresponding entries.
 103         * aarch64-asm.c (aarch64_get_variant): New function.
 104         (aarch64_encode_variant_using_iclass): Likewise.
 105         (aarch64_opcode_encode): Call it.
 106         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 107         (aarch64_opcode_decode): Call it.
 108
 109 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 110
 111         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 112         and FP register operands.
 113         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 114         (FLD_SVE_Vn): New aarch64_field_kinds.
 115         * aarch64-opc.c (fields): Add corresponding entries.
 116         (aarch64_print_operand): Handle the new SVE core and FP register
 117         operands.
 118         * aarch64-opc-2.c: Regenerate.
 119         * aarch64-asm-2.c: Likewise.
 120         * aarch64-dis-2.c: Likewise.
 121
 122 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 123
 124         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 125         immediate operands.
 126         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 127         * aarch64-opc.c (fields): Add corresponding entry.
 128         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 129         operands.
 130         (aarch64_print_operand): Likewise.
 131         * aarch64-opc-2.c: Regenerate.
 132         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 133         (ins_sve_float_zero_one): New inserters.
 134         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 135         (aarch64_ins_sve_float_half_two): Likewise.
 136         (aarch64_ins_sve_float_zero_one): Likewise.
 137         * aarch64-asm-2.c: Regenerate.
 138         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 139         (ext_sve_float_zero_one): New extractors.
 140         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 141         (aarch64_ext_sve_float_half_two): Likewise.
 142         (aarch64_ext_sve_float_zero_one): Likewise.
 143         * aarch64-dis-2.c: Regenerate.
 144
 145 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 146
 147         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 148         integer immediate operands.
 149         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 150         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 151         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 152         * aarch64-opc.c (fields): Add corresponding entries.
 153         (operand_general_constraint_met_p): Handle the new SVE integer
 154         immediate operands.
 155         (aarch64_print_operand): Likewise.
 156         (aarch64_sve_dupm_mov_immediate_p): New function.
 157         * aarch64-opc-2.c: Regenerate.
 158         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 159         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 160         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 161         (aarch64_ins_limm): ...here.
 162         (aarch64_ins_inv_limm): New function.
 163         (aarch64_ins_sve_aimm): Likewise.
 164         (aarch64_ins_sve_asimm): Likewise.
 165         (aarch64_ins_sve_limm_mov): Likewise.
 166         (aarch64_ins_sve_shlimm): Likewise.
 167         (aarch64_ins_sve_shrimm): Likewise.
 168         * aarch64-asm-2.c: Regenerate.
 169         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 170         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 171         * aarch64-dis.c (decode_limm): New function, split out from...
 172         (aarch64_ext_limm): ...here.
 173         (aarch64_ext_inv_limm): New function.
 174         (decode_sve_aimm): Likewise.
 175         (aarch64_ext_sve_aimm): Likewise.
 176         (aarch64_ext_sve_asimm): Likewise.
 177         (aarch64_ext_sve_limm_mov): Likewise.
 178         (aarch64_top_bit): Likewise.
 179         (aarch64_ext_sve_shlimm): Likewise.
 180         (aarch64_ext_sve_shrimm): Likewise.
 181         * aarch64-dis-2.c: Regenerate.
 182
 183 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 184
 185         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 186         operands.
 187         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 188         the AARCH64_MOD_MUL_VL entry.
 189         (value_aligned_p): Cope with non-power-of-two alignments.
 190         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 191         (print_immediate_offset_address): Likewise.
 192         (aarch64_print_operand): Likewise.
 193         * aarch64-opc-2.c: Regenerate.
 194         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 195         (ins_sve_addr_ri_s9xvl): New inserters.
 196         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 197         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 198         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 199         * aarch64-asm-2.c: Regenerate.
 200         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 201         (ext_sve_addr_ri_s9xvl): New extractors.
 202         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 203         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 204         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 205         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 206         * aarch64-dis-2.c: Regenerate.
 207
 208 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 209
 210         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 211         address operands.
 212         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 213         (FLD_SVE_xs_22): New aarch64_field_kinds.
 214         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 215         (get_operand_specific_data): New function.
 216         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 217         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 218         (operand_general_constraint_met_p): Handle the new SVE address
 219         operands.
 220         (sve_reg): New array.
 221         (get_addr_sve_reg_name): New function.
 222         (aarch64_print_operand): Handle the new SVE address operands.
 223         * aarch64-opc-2.c: Regenerate.
 224         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 225         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 226         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 227         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 228         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 229         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 230         (aarch64_ins_sve_addr_zi_u5): Likewise.
 231         (aarch64_ins_sve_addr_zz): Likewise.
 232         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 233         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 234         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 235         * aarch64-asm-2.c: Regenerate.
 236         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 237         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 238         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 239         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 240         (aarch64_ext_sve_addr_ri_u6): Likewise.
 241         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 242         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 243         (aarch64_ext_sve_addr_zi_u5): Likewise.
 244         (aarch64_ext_sve_addr_zz): Likewise.
 245         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 246         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 247         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 248         * aarch64-dis-2.c: Regenerate.
 249
 250 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 251
 252         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 253         AARCH64_OPND_SVE_PATTERN_SCALED.
 254         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 255         * aarch64-opc.c (fields): Add a corresponding entry.
 256         (set_multiplier_out_of_range_error): New function.
 257         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 258         (operand_general_constraint_met_p): Handle
 259         AARCH64_OPND_SVE_PATTERN_SCALED.
 260         (print_register_offset_address): Use PRIi64 to print the
 261         shift amount.
 262         (aarch64_print_operand): Likewise.  Handle
 263         AARCH64_OPND_SVE_PATTERN_SCALED.
 264         * aarch64-opc-2.c: Regenerate.
 265         * aarch64-asm.h (ins_sve_scale): New inserter.
 266         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 267         * aarch64-asm-2.c: Regenerate.
 268         * aarch64-dis.h (ext_sve_scale): New inserter.
 269         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 270         * aarch64-dis-2.c: Regenerate.
 271
 272 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 273
 274         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 275         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 276         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 277         (FLD_SVE_prfop): Likewise.
 278         * aarch64-opc.c: Include libiberty.h.
 279         (aarch64_sve_pattern_array): New variable.
 280         (aarch64_sve_prfop_array): Likewise.
 281         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 282         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 283         AARCH64_OPND_SVE_PRFOP.
 284         * aarch64-asm-2.c: Regenerate.
 285         * aarch64-dis-2.c: Likewise.
 286         * aarch64-opc-2.c: Likewise.
 287
 288 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 289
 290         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 291         AARCH64_OPND_QLF_P_[ZM].
 292         (aarch64_print_operand): Print /z and /m where appropriate.
 293
 294 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 295
 296         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 297         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 298         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 299         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 300         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 301         * aarch64-opc.c (fields): Add corresponding entries here.
 302         (operand_general_constraint_met_p): Check that SVE register lists
 303         have the correct length.  Check the ranges of SVE index registers.
 304         Check for cases where p8-p15 are used in 3-bit predicate fields.
 305         (aarch64_print_operand): Handle the new SVE operands.
 306         * aarch64-opc-2.c: Regenerate.
 307         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 308         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 309         (aarch64_ins_sve_reglist): Likewise.
 310         * aarch64-asm-2.c: Regenerate.
 311         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 312         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 313         (aarch64_ext_sve_reglist): Likewise.
 314         * aarch64-dis-2.c: Regenerate.
 315
 316 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 317
 318         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 319         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 320         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 321         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 322         tied operands.
 323
 324 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 325
 326         * aarch64-opc.c (get_offset_int_reg_name): New function.
 327         (print_immediate_offset_address): Likewise.
 328         (print_register_offset_address): Take the base and offset
 329         registers as parameters.
 330         (aarch64_print_operand): Update caller accordingly.  Use
 331         print_immediate_offset_address.
 332
 333 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 334
 335         * aarch64-opc.c (BANK): New macro.
 336         (R32, R64): Take a register number as argument
 337         (int_reg): Use BANK.
 338
 339 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 340
 341         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 342         (aarch64_print_operand): Update accordingly.
 343
 344 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 345
 346         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 347         for FPIMM.
 348         * aarch64-asm.h (ins_fpimm): New inserter.
 349         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 350         * aarch64-asm-2.c: Regenerate.
 351         * aarch64-dis.h (ext_fpimm): New extractor.
 352         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 353         (aarch64_ext_fpimm): New function.
 354         * aarch64-dis-2.c: Regenerate.
 355
 356 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 357
 358         * aarch64-asm.c: Include libiberty.h.
 359         (insert_fields): New function.
 360         (aarch64_ins_imm): Use it.
 361         * aarch64-dis.c (extract_fields): New function.
 362         (aarch64_ext_imm): Use it.
 363
 364 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 365
 366         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 367         with an esize parameter.
 368         (operand_general_constraint_met_p): Update accordingly.
 369         Fix misindented code.
 370         * aarch64-asm.c (aarch64_ins_limm): Update call to
 371         aarch64_logical_immediate_p.
 372
 373 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 374
 375         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 376
 377 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 378
 379         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 380
 381 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 382
 383         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 384
 385 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 386
 387         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 388         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 389         xor3>: Delete mnemonics.
 390         <cp_abort>: Rename mnemonic from ...
 391         <cpabort>: ...to this.
 392         <setb>: Change to a X form instruction.
 393         <sync>: Change to 1 operand form.
 394         <copy>: Delete mnemonic.
 395         <copy_first>: Rename mnemonic from ...
 396         <copy>: ...to this.
 397         <paste, paste.>: Delete mnemonics.
 398         <paste_last>: Rename mnemonic from ...
 399         <paste.>: ...to this.
 400
 401 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 402
 403         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 404
 405 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 406
 407         * s390-mkopc.c (main): Support alternate arch strings.
 408
 409 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 410
 411         * s390-opc.txt: Fix kmctr instruction type.
 412
 413 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 416         * i386-init.h: Regenerated.
 417
 418 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 419
 420         * opcodes/arc-dis.c (print_insn_arc): Changed.
 421
 422 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 423
 424         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 425         camellia_fl.
 426
 427 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 428
 429         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 430         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 431         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 432
 433 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 436         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 437         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 438         PREFIX_MOD_3_0FAE_REG_4.
 439         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 440         PREFIX_MOD_3_0FAE_REG_4.
 441         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 442         (cpu_flags): Add CpuPTWRITE.
 443         * i386-opc.h (CpuPTWRITE): New.
 444         (i386_cpu_flags): Add cpuptwrite.
 445         * i386-opc.tbl: Add ptwrite instruction.
 446         * i386-init.h: Regenerated.
 447         * i386-tbl.h: Likewise.
 448
 449 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 450
 451         * arc-dis.h: Wrap around in extern "C".
 452
 453 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 454
 455         * aarch64-tbl.h (V8_2_INSN): New macro.
 456         (aarch64_opcode_table): Use it.
 457
 458 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 459
 460         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 461         CORE_INSN, __FP_INSN and SIMD_INSN.
 462
 463 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 464
 465         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 466         (aarch64_opcode_table): Update uses accordingly.
 467
 468 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 469         Kwok Cheung Yeung  <kcy@codesourcery.com>
 470
 471         opcodes/
 472         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 473         'e_cmplwi' to 'e_cmpli' instead.
 474         (OPVUPRT, OPVUPRT_MASK): Define.
 475         (powerpc_opcodes): Add E200Z4 insns.
 476         (vle_opcodes): Add context save/restore insns.
 477
 478 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 479
 480         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 481         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 482         "j".
 483
 484 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 485
 486         * arc-nps400-tbl.h: Change block comments to GNU format.
 487         * arc-dis.c: Add new globals addrtypenames,
 488         addrtypenames_max, and addtypeunknown.
 489         (get_addrtype): New function.
 490         (print_insn_arc): Print colons and address types when
 491         required.
 492         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 493         define insert and extract functions for all address types.
 494         (arc_operands): Add operands for colon and all address
 495         types.
 496         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 497         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 498         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 499         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 500         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 501         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 502
 503 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 504
 505         * configure: Regenerated.
 506
 507 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 508
 509         * arc-dis.c (skipclass): New structure.
 510         (decodelist): New variable.
 511         (is_compatible_p): New function.
 512         (new_element): Likewise.
 513         (skip_class_p): Likewise.
 514         (find_format_from_table): Use skip_class_p function.
 515         (find_format): Decode first the extension instructions.
 516         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 517         e_flags.
 518         (parse_option): New function.
 519         (parse_disassembler_options): Likewise.
 520         (print_arc_disassembler_options): Likewise.
 521         (print_insn_arc): Use parse_disassembler_options function.  Proper
 522         select ARCv2 cpu variant.
 523         * disassemble.c (disassembler_usage): Add ARC disassembler
 524         options.
 525
 526 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 527
 528         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 529         annotation from the "nal" entry and reorder it beyond "bltzal".
 530
 531 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 532
 533         * sparc-opc.c (ldtxa): New macro.
 534         (sparc_opcodes): Use the macro defined above to add entries for
 535         the LDTXA instructions.
 536         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 537         instruction.
 538
 539 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 540
 541         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 542         and "jmpc".
 543
 544 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 545
 546         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 547         (movzb): Adjust to cover all permitted suffixes.
 548         (movzw): New.
 549         * i386-tbl.h: Re-generate.
 550
 551 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 552
 553         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 554         (lgdt): Remove Tbyte from non-64-bit variant.
 555         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 556         xsaves64, xsavec64): Remove Disp16.
 557         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 558         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 559         64-bit variants.
 560         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 561         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 562         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 563         64-bit variants.
 564         * i386-tbl.h: Re-generate.
 565
 566 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 569         * i386-tbl.h: Re-generate.
 570
 571 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 572
 573         * arm-dis.c (print_insn): Fix typo in comment.
 574
 575 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 576
 577         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 578         range of ldst_elemlist operands.
 579         (print_register_list): Use PRIi64 to print the index.
 580         (aarch64_print_operand): Likewise.
 581
 582 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 583
 584         * mcore-opc.h: Remove sentinal.
 585         * mcore-dis.c (print_insn_mcore): Adjust.
 586
 587 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 588
 589         * arc-opc.c: Correct description of availability of NPS400
 590         features.
 591
 592 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 593
 594         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 595         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 596         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 597         xor3>: New mnemonics.
 598         <setb>: Change to a VX form instruction.
 599         (insert_sh6): Add support for rldixor.
 600         (extract_sh6): Likewise.
 601
 602 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 603
 604         * arc-ext.h: Wrap in extern C.
 605
 606 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 607
 608         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 609         Use same method for determining instruction length on ARC700 and
 610         NPS-400.
 611         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 612         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 613         with the NPS400 subclass.
 614         * arc-opc.c: Likewise.
 615
 616 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 617
 618         * sparc-opc.c (rdasr): New macro.
 619         (wrasr): Likewise.
 620         (rdpr): Likewise.
 621         (wrpr): Likewise.
 622         (rdhpr): Likewise.
 623         (wrhpr): Likewise.
 624         (sparc_opcodes): Use the macros above to fix and expand the
 625         definition of read/write instructions from/to
 626         asr/privileged/hyperprivileged instructions.
 627         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 628         %hva_mask_nz.  Prefer softint_set and softint_clear over
 629         set_softint and clear_softint.
 630         (print_insn_sparc): Support %ver in Rd.
 631
 632 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 633
 634         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 635         architecture according to the hardware capabilities they require.
 636
 637 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 638
 639         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 640         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 641         bfd_mach_sparc_v9{c,d,e,v,m}.
 642         * sparc-opc.c (MASK_V9C): Define.
 643         (MASK_V9D): Likewise.
 644         (MASK_V9E): Likewise.
 645         (MASK_V9V): Likewise.
 646         (MASK_V9M): Likewise.
 647         (v6): Add MASK_V9{C,D,E,V,M}.
 648         (v6notlet): Likewise.
 649         (v7): Likewise.
 650         (v8): Likewise.
 651         (v9): Likewise.
 652         (v9andleon): Likewise.
 653         (v9a): Likewise.
 654         (v9b): Likewise.
 655         (v9c): Define.
 656         (v9d): Likewise.
 657         (v9e): Likewise.
 658         (v9v): Likewise.
 659         (v9m): Likewise.
 660         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 661
 662 2016-06-15  Nick Clifton  <nickc@redhat.com>
 663
 664         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 665         constants to match expected behaviour.
 666         (nds32_parse_opcode): Likewise.  Also for whitespace.
 667
 668 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 669
 670         * arc-opc.c (extract_rhv1): Extract value from insn.
 671
 672 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 673
 674         * arc-nps400-tbl.h: Add ldbit instruction.
 675         * arc-opc.c: Add flag classes required for ldbit.
 676
 677 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 678
 679         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 680         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 681         support the above instructions.
 682
 683 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 684
 685         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 686         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 687         csma, cbba, zncv, and hofs.
 688         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 689         support the above instructions.
 690
 691 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 692
 693         * arc-nps400-tbl.h: Add andab and orab instructions.
 694
 695 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 696
 697         * arc-nps400-tbl.h: Add addl-like instructions.
 698
 699 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 700
 701         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 702
 703 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 704
 705         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 706         instructions.
 707
 708 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 709
 710         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 711         variable.
 712         (init_disasm): Handle new command line option "insnlength".
 713         (print_s390_disassembler_options): Mention new option in help
 714         output.
 715         (print_insn_s390): Use the encoded insn length when dumping
 716         unknown instructions.
 717
 718 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 719
 720         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 721          to the address and set as symbol address for LDS/ STS immediate operands.
 722
 723 2016-06-07  Alan Modra  <amodra@gmail.com>
 724
 725         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 726         cpu for "vle" to e500.
 727         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 728         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 729         (PPCNONE): Delete, substitute throughout.
 730         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 731         except for major opcode 4 and 31.
 732         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 733
 734 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 735
 736         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 737         ARM_EXT_RAS in relevant entries.
 738
 739 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 740
 741         PR binutils/20196
 742         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 743         opcodes for E6500.
 744
 745 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 746
 747         PR binutis/18386
 748         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 749         (indir_v_mode): New.
 750         Add comments for '&'.
 751         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 752         (putop): Handle '&'.
 753         (intel_operand_size): Handle indir_v_mode.
 754         (OP_E_register): Likewise.
 755         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 756         64-bit indirect call/jmp for AMD64.
 757         * i386-tbl.h: Regenerated
 758
 759 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 760
 761         * arc-dis.c (struct arc_operand_iterator): New structure.
 762         (find_format_from_table): All the old content from find_format,
 763         with some minor adjustments, and parameter renaming.
 764         (find_format_long_instructions): New function.
 765         (find_format): Rewritten.
 766         (arc_insn_length): Add LSB parameter.
 767         (extract_operand_value): New function.
 768         (operand_iterator_next): New function.
 769         (print_insn_arc): Use new functions to find opcode, and iterator
 770         over operands.
 771         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 772         (extract_nps_3bit_dst_short): New function.
 773         (insert_nps_3bit_src2_short): New function.
 774         (extract_nps_3bit_src2_short): New function.
 775         (insert_nps_bitop1_size): New function.
 776         (extract_nps_bitop1_size): New function.
 777         (insert_nps_bitop2_size): New function.
 778         (extract_nps_bitop2_size): New function.
 779         (insert_nps_bitop_mod4_msb): New function.
 780         (extract_nps_bitop_mod4_msb): New function.
 781         (insert_nps_bitop_mod4_lsb): New function.
 782         (extract_nps_bitop_mod4_lsb): New function.
 783         (insert_nps_bitop_dst_pos3_pos4): New function.
 784         (extract_nps_bitop_dst_pos3_pos4): New function.
 785         (insert_nps_bitop_ins_ext): New function.
 786         (extract_nps_bitop_ins_ext): New function.
 787         (arc_operands): Add new operands.
 788         (arc_long_opcodes): New global array.
 789         (arc_num_long_opcodes): New global.
 790         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 791
 792 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 793
 794         * nds32-asm.h: Add extern "C".
 795         * sh-opc.h: Likewise.
 796
 797 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 798
 799         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 800         0,b,limm to the rflt instruction.
 801
 802 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 803
 804         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 805         constant.
 806
 807 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 808
 809         PR gas/20145
 810         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 811         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 812         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 813         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 814         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 815         * i386-init.h: Regenerated.
 816
 817 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 818
 819         PR gas/20145
 820         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 821         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 822         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 823         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 824         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 825         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 826         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 827         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 828         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 829         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 830         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 831         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 832         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 833         CpuRegMask for AVX512.
 834         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 835         and CpuRegMask.
 836         (set_bitfield_from_cpu_flag_init): New function.
 837         (set_bitfield): Remove const on f.  Call
 838         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 839         * i386-opc.h (CpuRegMMX): New.
 840         (CpuRegXMM): Likewise.
 841         (CpuRegYMM): Likewise.
 842         (CpuRegZMM): Likewise.
 843         (CpuRegMask): Likewise.
 844         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 845         and cpuregmask.
 846         * i386-init.h: Regenerated.
 847         * i386-tbl.h: Likewise.
 848
 849 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 850
 851         PR gas/20154
 852         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 853         (opcode_modifiers): Add AMD64 and Intel64.
 854         (main): Properly verify CpuMax.
 855         * i386-opc.h (CpuAMD64): Removed.
 856         (CpuIntel64): Likewise.
 857         (CpuMax): Set to CpuNo64.
 858         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 859         (AMD64): New.
 860         (Intel64): Likewise.
 861         (i386_opcode_modifier): Add amd64 and intel64.
 862         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 863         on call and jmp.
 864         * i386-init.h: Regenerated.
 865         * i386-tbl.h: Likewise.
 866
 867 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 868
 869         PR gas/20154
 870         * i386-gen.c (main): Fail if CpuMax is incorrect.
 871         * i386-opc.h (CpuMax): Set to CpuIntel64.
 872         * i386-tbl.h: Regenerated.
 873
 874 2016-05-27  Nick Clifton  <nickc@redhat.com>
 875
 876         PR target/20150
 877         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 878         (msp430dis_opcode_unsigned): New function.
 879         (msp430dis_opcode_signed): New function.
 880         (msp430_singleoperand): Use the new opcode reading functions.
 881         Only disassenmble bytes if they were successfully read.
 882         (msp430_doubleoperand): Likewise.
 883         (msp430_branchinstr): Likewise.
 884         (msp430x_callx_instr): Likewise.
 885         (print_insn_msp430): Check that it is safe to read bytes before
 886         attempting disassembly.  Use the new opcode reading functions.
 887
 888 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 889
 890         * ppc-opc.c (CY): New define.  Document it.
 891         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 892
 893 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 894
 895         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 896         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 897         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 898         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 899         CPU_ANY_AVX_FLAGS.
 900         * i386-init.h: Regenerated.
 901
 902 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 903
 904         PR gas/20141
 905         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 906         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 907         * i386-init.h: Regenerated.
 908
 909 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 910
 911         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 912         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 913         * i386-init.h: Regenerated.
 914
 915 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 916
 917         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 918         information.
 919         (print_insn_arc): Set insn_type information.
 920         * arc-opc.c (C_CC): Add F_CLASS_COND.
 921         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 922         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 923         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 924         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 925         (brne, brne_s, jeq_s, jne_s): Likewise.
 926
 927 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 928
 929         * arc-tbl.h (neg): New instruction variant.
 930
 931 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 932
 933         * arc-dis.c (find_format, find_format, get_auxreg)
 934         (print_insn_arc): Changed.
 935         * arc-ext.h (INSERT_XOP): Likewise.
 936
 937 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 938
 939         * tic54x-dis.c (sprint_mmr): Adjust.
 940         * tic54x-opc.c: Likewise.
 941
 942 2016-05-19  Alan Modra  <amodra@gmail.com>
 943
 944         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 945
 946 2016-05-19  Alan Modra  <amodra@gmail.com>
 947
 948         * ppc-opc.c: Formatting.
 949         (NSISIGNOPT): Define.
 950         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 951
 952 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 953
 954         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 955         replacing references to `micromips_ase' throughout.
 956         (_print_insn_mips): Don't use file-level microMIPS annotation to
 957         determine the disassembly mode with the symbol table.
 958
 959 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 960
 961         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 962
 963 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 964
 965         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 966         mips64r6.
 967         * mips-opc.c (D34): New macro.
 968         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 969
 970 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 971
 972         * i386-dis.c (prefix_table): Add RDPID instruction.
 973         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 974         (cpu_flags): Add RDPID bitfield.
 975         * i386-opc.h (enum): Add RDPID element.
 976         (i386_cpu_flags): Add RDPID field.
 977         * i386-opc.tbl: Add RDPID instruction.
 978         * i386-init.h: Regenerate.
 979         * i386-tbl.h: Regenerate.
 980
 981 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 982
 983         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 984         branch type of a symbol.
 985         (print_insn): Likewise.
 986
 987 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 988
 989         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 990         Mainline Security Extensions instructions.
 991         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 992         Extensions instructions.
 993         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 994         instructions.
 995         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 996         special registers.
 997
 998 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 999
1000         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1001
1002 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1003
1004         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1005         (arcExtMap_genOpcode): Likewise.
1006         * arc-opc.c (arg_32bit_rc): Define new variable.
1007         (arg_32bit_u6): Likewise.
1008         (arg_32bit_limm): Likewise.
1009
1010 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1011
1012         * aarch64-gen.c (VERIFIER): Define.
1013         * aarch64-opc.c (VERIFIER): Define.
1014         (verify_ldpsw): Use static linkage.
1015         * aarch64-opc.h (verify_ldpsw): Remove.
1016         * aarch64-tbl.h: Use VERIFIER for verifiers.
1017
1018 2016-04-28  Nick Clifton  <nickc@redhat.com>
1019
1020         PR target/19722
1021         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1022         * aarch64-opc.c (verify_ldpsw): New function.
1023         * aarch64-opc.h (verify_ldpsw): New prototype.
1024         * aarch64-tbl.h: Add initialiser for verifier field.
1025         (LDPSW): Set verifier to verify_ldpsw.
1026
1027 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1028
1029         PR binutils/19983
1030         PR binutils/19984
1031         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1032         smaller than address size.
1033
1034 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1035
1036         * alpha-dis.c: Regenerate.
1037         * crx-dis.c: Likewise.
1038         * disassemble.c: Likewise.
1039         * epiphany-opc.c: Likewise.
1040         * fr30-opc.c: Likewise.
1041         * frv-opc.c: Likewise.
1042         * ip2k-opc.c: Likewise.
1043         * iq2000-opc.c: Likewise.
1044         * lm32-opc.c: Likewise.
1045         * lm32-opinst.c: Likewise.
1046         * m32c-opc.c: Likewise.
1047         * m32r-opc.c: Likewise.
1048         * m32r-opinst.c: Likewise.
1049         * mep-opc.c: Likewise.
1050         * mt-opc.c: Likewise.
1051         * or1k-opc.c: Likewise.
1052         * or1k-opinst.c: Likewise.
1053         * tic80-opc.c: Likewise.
1054         * xc16x-opc.c: Likewise.
1055         * xstormy16-opc.c: Likewise.
1056
1057 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1058
1059         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1060         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1061         calcsd, and calcxd instructions.
1062         * arc-opc.c (insert_nps_bitop_size): Delete.
1063         (extract_nps_bitop_size): Delete.
1064         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1065         (extract_nps_qcmp_m3): Define.
1066         (extract_nps_qcmp_m2): Define.
1067         (extract_nps_qcmp_m1): Define.
1068         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1069         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1070         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1071         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1072         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1073         NPS_QCMP_M3.
1074
1075 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1076
1077         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1078
1079 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1080
1081         * Makefile.in: Regenerated with automake 1.11.6.
1082         * aclocal.m4: Likewise.
1083
1084 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1085
1086         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1087         instructions.
1088         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1089         (extract_nps_cmem_uimm16): New function.
1090         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1091
1092 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1093
1094         * arc-dis.c (arc_insn_length): New function.
1095         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1096         (find_format): Change insnLen parameter to unsigned.
1097
1098 2016-04-13  Nick Clifton  <nickc@redhat.com>
1099
1100         PR target/19937
1101         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1102         the LD.B and LD.BU instructions.
1103
1104 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1105
1106         * arc-dis.c (find_format): Check for extension flags.
1107         (print_flags): New function.
1108         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1109         .extAuxRegister.
1110         * arc-ext.c (arcExtMap_coreRegName): Use
1111         LAST_EXTENSION_CORE_REGISTER.
1112         (arcExtMap_coreReadWrite): Likewise.
1113         (dump_ARC_extmap): Update printing.
1114         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1115         (arc_aux_regs): Add cpu field.
1116         * arc-regs.h: Add cpu field, lower case name aux registers.
1117
1118 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1119
1120         * arc-tbl.h: Add rtsc, sleep with no arguments.
1121
1122 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1123
1124         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1125         Initialize.
1126         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1127         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1128         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1129         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1130         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1131         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1132         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1133         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1134         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1135         (arc_opcode arc_opcodes): Null terminate the array.
1136         (arc_num_opcodes): Remove.
1137         * arc-ext.h (INSERT_XOP): Define.
1138         (extInstruction_t): Likewise.
1139         (arcExtMap_instName): Delete.
1140         (arcExtMap_insn): New function.
1141         (arcExtMap_genOpcode): Likewise.
1142         * arc-ext.c (ExtInstruction): Remove.
1143         (create_map): Zero initialize instruction fields.
1144         (arcExtMap_instName): Remove.
1145         (arcExtMap_insn): New function.
1146         (dump_ARC_extmap): More info while debuging.
1147         (arcExtMap_genOpcode): New function.
1148         * arc-dis.c (find_format): New function.
1149         (print_insn_arc): Use find_format.
1150         (arc_get_disassembler): Enable dump_ARC_extmap only when
1151         debugging.
1152
1153 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1154
1155         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1156         instruction bits out.
1157
1158 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1159
1160         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1161         * arc-opc.c (arc_flag_operands): Add new flags.
1162         (arc_flag_classes): Add new classes.
1163
1164 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1165
1166         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1167
1168 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1169
1170         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1171         encode1, rflt, crc16, and crc32 instructions.
1172         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1173         (arc_flag_classes): Add C_NPS_R.
1174         (insert_nps_bitop_size_2b): New function.
1175         (extract_nps_bitop_size_2b): Likewise.
1176         (insert_nps_bitop_uimm8): Likewise.
1177         (extract_nps_bitop_uimm8): Likewise.
1178         (arc_operands): Add new operand entries.
1179
1180 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1181
1182         * arc-regs.h: Add a new subclass field.  Add double assist
1183         accumulator register values.
1184         * arc-tbl.h: Use DPA subclass to mark the double assist
1185         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1186         * arc-opc.c (RSP): Define instead of SP.
1187         (arc_aux_regs): Add the subclass field.
1188
1189 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1190
1191         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1192
1193 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1194
1195         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1196         NPS_R_SRC1.
1197
1198 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1199
1200         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1201         issues.  No functional changes.
1202
1203 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1204
1205         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1206         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1207         (RTT): Remove duplicate.
1208         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1209         (PCT_CONFIG*): Remove.
1210         (D1L, D1H, D2H, D2L): Define.
1211
1212 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1213
1214         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1215
1216 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1217
1218         * arc-tbl.h (invld07): Remove.
1219         * arc-ext-tbl.h: New file.
1220         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1221         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1222
1223 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1224
1225         Fix -Wstack-usage warnings.
1226         * aarch64-dis.c (print_operands): Substitute size.
1227         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1228
1229 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1230
1231         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1232         to get a proper diagnostic when an invalid ASR register is used.
1233
1234 2016-03-22  Nick Clifton  <nickc@redhat.com>
1235
1236         * configure: Regenerate.
1237
1238 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1239
1240         * arc-nps400-tbl.h: New file.
1241         * arc-opc.c: Add top level comment.
1242         (insert_nps_3bit_dst): New function.
1243         (extract_nps_3bit_dst): New function.
1244         (insert_nps_3bit_src2): New function.
1245         (extract_nps_3bit_src2): New function.
1246         (insert_nps_bitop_size): New function.
1247         (extract_nps_bitop_size): New function.
1248         (arc_flag_operands): Add nps400 entries.
1249         (arc_flag_classes): Add nps400 entries.
1250         (arc_operands): Add nps400 entries.
1251         (arc_opcodes): Add nps400 include.
1252
1253 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1254
1255         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1256         the new class enum values.
1257
1258 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1259
1260         * arc-dis.c (print_insn_arc): Handle nps400.
1261
1262 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1263
1264         * arc-opc.c (BASE): Delete.
1265
1266 2016-03-18  Nick Clifton  <nickc@redhat.com>
1267
1268         PR target/19721
1269         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1270         of MOV insn that aliases an ORR insn.
1271
1272 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1273
1274         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1275
1276 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1277
1278         * mcore-opc.h: Add const qualifiers.
1279         * microblaze-opc.h (struct op_code_struct): Likewise.
1280         * sh-opc.h: Likewise.
1281         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1282         (tic4x_print_op): Likewise.
1283
1284 2016-03-02  Alan Modra  <amodra@gmail.com>
1285
1286         * or1k-desc.h: Regenerate.
1287         * fr30-ibld.c: Regenerate.
1288         * rl78-decode.c: Regenerate.
1289
1290 2016-03-01  Nick Clifton  <nickc@redhat.com>
1291
1292         PR target/19747
1293         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1294
1295 2016-02-24  Renlin Li  <renlin.li@arm.com>
1296
1297         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1298         (print_insn_coprocessor): Support fp16 instructions.
1299
1300 2016-02-24  Renlin Li  <renlin.li@arm.com>
1301
1302         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1303         vminnm, vrint(mpna).
1304
1305 2016-02-24  Renlin Li  <renlin.li@arm.com>
1306
1307         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1308         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1309
1310 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1311
1312         * i386-dis.c (print_insn): Parenthesize expression to prevent
1313         truncated addresses.
1314         (OP_J): Likewise.
1315
1316 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1317             Janek van Oirschot  <jvanoirs@synopsys.com>
1318
1319         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1320         variable.
1321
1322 2016-02-04  Nick Clifton  <nickc@redhat.com>
1323
1324         PR target/19561
1325         * msp430-dis.c (print_insn_msp430): Add a special case for
1326         decoding an RRC instruction with the ZC bit set in the extension
1327         word.
1328
1329 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1330
1331         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1332         * epiphany-ibld.c: Regenerate.
1333         * fr30-ibld.c: Regenerate.
1334         * frv-ibld.c: Regenerate.
1335         * ip2k-ibld.c: Regenerate.
1336         * iq2000-ibld.c: Regenerate.
1337         * lm32-ibld.c: Regenerate.
1338         * m32c-ibld.c: Regenerate.
1339         * m32r-ibld.c: Regenerate.
1340         * mep-ibld.c: Regenerate.
1341         * mt-ibld.c: Regenerate.
1342         * or1k-ibld.c: Regenerate.
1343         * xc16x-ibld.c: Regenerate.
1344         * xstormy16-ibld.c: Regenerate.
1345
1346 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1347
1348         * epiphany-dis.c: Regenerated from latest cpu files.
1349
1350 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1351
1352         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1353         test bit.
1354
1355 2016-01-25  Renlin Li  <renlin.li@arm.com>
1356
1357         * arm-dis.c (mapping_symbol_for_insn): New function.
1358         (find_ifthen_state): Call mapping_symbol_for_insn().
1359
1360 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1361
1362         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1363         of MSR UAO immediate operand.
1364
1365 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1366
1367         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1368         instruction support.
1369
1370 2016-01-17  Alan Modra  <amodra@gmail.com>
1371
1372         * configure: Regenerate.
1373
1374 2016-01-14  Nick Clifton  <nickc@redhat.com>
1375
1376         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1377         instructions that can support stack pointer operations.
1378         * rl78-decode.c: Regenerate.
1379         * rl78-dis.c: Fix display of stack pointer in MOVW based
1380         instructions.
1381
1382 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1383
1384         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1385         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1386         erxtatus_el1 and erxaddr_el1.
1387
1388 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1389
1390         * arm-dis.c (arm_opcodes): Add "esb".
1391         (thumb_opcodes): Likewise.
1392
1393 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1394
1395         * ppc-opc.c <xscmpnedp>: Delete.
1396         <xvcmpnedp>: Likewise.
1397         <xvcmpnedp.>: Likewise.
1398         <xvcmpnesp>: Likewise.
1399         <xvcmpnesp.>: Likewise.
1400
1401 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1402
1403         PR gas/13050
1404         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1405         addition to ISA_A.
1406
1407 2016-01-01  Alan Modra  <amodra@gmail.com>
1408
1409         Update year range in copyright notice of all files.
1410
1411 For older changes see ChangeLog-2015
1412 \f
1413 Copyright (C) 2016 Free Software Foundation, Inc.
1414
1415 Copying and distribution of this file, with or without modification,
1416 are permitted in any medium without royalty provided the copyright
1417 notice and this notice are preserved.
1418
1419 Local Variables:
1420 mode: change-log
1421 left-margin: 8
1422 fill-column: 74
1423 version-control: never
1424 End: