opcodes/ChangeLog

   1 2020-05-11  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-dis.c (ppc_opts): Add "power10" entry.
   4         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
   5         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
   6
   7 2020-05-11  Nick Clifton  <nickc@redhat.com>
   8
   9         * po/fr.po: Updated French translation.
  10
  11 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
  12
  13         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
  14         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
  15         (operand_general_constraint_met_p): validate
  16         AARCH64_OPND_UNDEFINED.
  17         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
  18         for FLD_imm16_2.
  19         * aarch64-asm-2.c: Regenerated.
  20         * aarch64-dis-2.c: Regenerated.
  21         * aarch64-opc-2.c: Regenerated.
  22
  23 2020-04-29  Nick Clifton  <nickc@redhat.com>
  24
  25         PR 22699
  26         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
  27         and SETRC insns.
  28
  29 2020-04-29  Nick Clifton  <nickc@redhat.com>
  30
  31         * po/sv.po: Updated Swedish translation.
  32
  33 2020-04-29  Nick Clifton  <nickc@redhat.com>
  34
  35         PR 22699
  36         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
  37         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
  38         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
  39         IMM0_8U case.
  40
  41 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
  42
  43         PR 25848
  44         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
  45         cmpi only on m68020up and cpu32.
  46
  47 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  48
  49         * aarch64-asm.c (aarch64_ins_none): New.
  50         * aarch64-asm.h (ins_none): New declaration.
  51         * aarch64-dis.c (aarch64_ext_none): New.
  52         * aarch64-dis.h (ext_none): New declaration.
  53         * aarch64-opc.c (aarch64_print_operand): Update case for
  54         AARCH64_OPND_BARRIER_PSB.
  55         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  56         (AARCH64_OPERANDS): Update inserter/extracter for
  57         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  58         * aarch64-asm-2.c: Regenerated.
  59         * aarch64-dis-2.c: Regenerated.
  60         * aarch64-opc-2.c: Regenerated.
  61
  62 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  63
  64         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  65         (aarch64_feature_ras, RAS): Likewise.
  66         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  67         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  68         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
  69         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
  70         * aarch64-asm-2.c: Regenerated.
  71         * aarch64-dis-2.c: Regenerated.
  72         * aarch64-opc-2.c: Regenerated.
  73
  74 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  75
  76         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
  77         (print_insn_neon): Support disassembly of conditional
  78         instructions.
  79
  80 2020-02-16  David Faust  <david.faust@oracle.com>
  81
  82         * bpf-desc.c: Regenerate.
  83         * bpf-desc.h: Likewise.
  84         * bpf-opc.c: Regenerate.
  85         * bpf-opc.h: Likewise.
  86
  87 2020-04-07  Lili Cui  <lili.cui@intel.com>
  88
  89         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
  90         (prefix_table): New instructions (see prefixes above).
  91         (rm_table): Likewise
  92         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
  93         CPU_ANY_TSXLDTRK_FLAGS.
  94         (cpu_flags): Add CpuTSXLDTRK.
  95         * i386-opc.h (enum): Add CpuTSXLDTRK.
  96         (i386_cpu_flags): Add cputsxldtrk.
  97         * i386-opc.tbl: Add XSUSPLDTRK insns.
  98         * i386-init.h: Regenerate.
  99         * i386-tbl.h: Likewise.
 100
 101 2020-04-02  Lili Cui  <lili.cui@intel.com>
 102
 103         * i386-dis.c (prefix_table): New instructions serialize.
 104         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 105         CPU_ANY_SERIALIZE_FLAGS.
 106         (cpu_flags): Add CpuSERIALIZE.
 107         * i386-opc.h (enum): Add CpuSERIALIZE.
 108         (i386_cpu_flags): Add cpuserialize.
 109         * i386-opc.tbl: Add SERIALIZE insns.
 110         * i386-init.h: Regenerate.
 111         * i386-tbl.h: Likewise.
 112
 113 2020-03-26  Alan Modra  <amodra@gmail.com>
 114
 115         * disassemble.h (opcodes_assert): Declare.
 116         (OPCODES_ASSERT): Define.
 117         * disassemble.c: Don't include assert.h.  Include opintl.h.
 118         (opcodes_assert): New function.
 119         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 120         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 121         calculate maxlen.  Omit insn decoding when insn length exceeds
 122         maxlen.  Exit from nibble loop when looking for E, before
 123         accessing next data byte.  Move processing of E outside loop.
 124         Replace tests of maxlen in loop with assertions.
 125
 126 2020-03-26  Alan Modra  <amodra@gmail.com>
 127
 128         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 129
 130 2020-03-25  Alan Modra  <amodra@gmail.com>
 131
 132         * z80-dis.c (suffix): Init mybuf.
 133
 134 2020-03-22  Alan Modra  <amodra@gmail.com>
 135
 136         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 137         successflly read from section.
 138
 139 2020-03-22  Alan Modra  <amodra@gmail.com>
 140
 141         * arc-dis.c (find_format): Use ISO C string concatenation rather
 142         than line continuation within a string.  Don't access needs_limm
 143         before testing opcode != NULL.
 144
 145 2020-03-22  Alan Modra  <amodra@gmail.com>
 146
 147         * ns32k-dis.c (print_insn_arg): Update comment.
 148         (print_insn_ns32k): Reduce size of index_offset array, and
 149         initialize, passing -1 to print_insn_arg for args that are not
 150         an index.  Don't exit arg loop early.  Abort on bad arg number.
 151
 152 2020-03-22  Alan Modra  <amodra@gmail.com>
 153
 154         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 155         * s12z-opc.c: Formatting.
 156         (operands_f): Return an int.
 157         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 158         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 159         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 160         (exg_sex_discrim): Likewise.
 161         (create_immediate_operand, create_bitfield_operand),
 162         (create_register_operand_with_size, create_register_all_operand),
 163         (create_register_all16_operand, create_simple_memory_operand),
 164         (create_memory_operand, create_memory_auto_operand): Don't
 165         segfault on malloc failure.
 166         (z_ext24_decode): Return an int status, negative on fail, zero
 167         on success.
 168         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 169         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 170         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 171         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 172         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 173         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 174         (loop_primitive_decode, shift_decode, psh_pul_decode),
 175         (bit_field_decode): Similarly.
 176         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 177         to return value, update callers.
 178         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 179         Don't segfault on NULL operand.
 180         (decode_operation): Return OP_INVALID on first fail.
 181         (decode_s12z): Check all reads, returning -1 on fail.
 182
 183 2020-03-20  Alan Modra  <amodra@gmail.com>
 184
 185         * metag-dis.c (print_insn_metag): Don't ignore status from
 186         read_memory_func.
 187
 188 2020-03-20  Alan Modra  <amodra@gmail.com>
 189
 190         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 191         Initialize parts of buffer not written when handling a possible
 192         2-byte insn at end of section.  Don't attempt decoding of such
 193         an insn by the 4-byte machinery.
 194
 195 2020-03-20  Alan Modra  <amodra@gmail.com>
 196
 197         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 198         partially filled buffer.  Prevent lookup of 4-byte insns when
 199         only VLE 2-byte insns are possible due to section size.  Print
 200         ".word" rather than ".long" for 2-byte leftovers.
 201
 202 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 203
 204         PR 25641
 205         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 206
 207 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-dis.c (X86_64_0D): Rename to ...
 210         (X86_64_0E): ... this.
 211
 212 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 215         * Makefile.in: Regenerated.
 216
 217 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 220         3-operand pseudos.
 221         * i386-tbl.h: Re-generate.
 222
 223 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 226         vprot*, vpsha*, and vpshl*.
 227         * i386-tbl.h: Re-generate.
 228
 229 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 232         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 233         * i386-tbl.h: Re-generate.
 234
 235 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 236
 237         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 238         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 239         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 240         * i386-tbl.h: Re-generate.
 241
 242 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-gen.c (struct template_arg, struct template_instance,
 245         struct template_param, struct template, templates,
 246         parse_template, expand_templates): New.
 247         (process_i386_opcodes): Various local variables moved to
 248         expand_templates. Call parse_template and expand_templates.
 249         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 250         * i386-tbl.h: Re-generate.
 251
 252 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 255         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 256         register and memory source templates. Replace VexW= by VexW*
 257         where applicable.
 258         * i386-tbl.h: Re-generate.
 259
 260 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 263         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 264         * i386-tbl.h: Re-generate.
 265
 266 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 269         * i386-tbl.h: Re-generate.
 270
 271 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 272
 273         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 274         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 275         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 276         VexW0 on SSE2AVX variants.
 277         (vmovq): Drop NoRex64 from XMM/XMM variants.
 278         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 279         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 280         applicable use VexW0.
 281         * i386-tbl.h: Re-generate.
 282
 283 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 284
 285         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 286         * i386-opc.h (Rex64): Delete.
 287         (struct i386_opcode_modifier): Remove rex64 field.
 288         * i386-opc.tbl (crc32): Drop Rex64.
 289         Replace Rex64 with Size64 everywhere else.
 290         * i386-tbl.h: Re-generate.
 291
 292 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-dis.c (OP_E_memory): Exclude recording of used address
 295         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 296         addressed memory operands for MPX insns.
 297
 298 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 301         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 302         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 303         (ptwrite): Split into non-64-bit and 64-bit forms.
 304         * i386-tbl.h: Re-generate.
 305
 306 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 309         template.
 310         * i386-tbl.h: Re-generate.
 311
 312 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 315         (prefix_table): Move vmmcall here. Add vmgexit.
 316         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 317         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 318         (cpu_flags): Add CpuSEV_ES entry.
 319         * i386-opc.h (CpuSEV_ES): New.
 320         (union i386_cpu_flags): Add cpusev_es field.
 321         * i386-opc.tbl (vmgexit): New.
 322         * i386-init.h, i386-tbl.h: Re-generate.
 323
 324 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 325
 326         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 327         with MnemonicSize.
 328         * i386-opc.h (IGNORESIZE): New.
 329         (DEFAULTSIZE): Likewise.
 330         (IgnoreSize): Removed.
 331         (DefaultSize): Likewise.
 332         (MnemonicSize): New.
 333         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 334         mnemonicsize.
 335         * i386-opc.tbl (IgnoreSize): New.
 336         (DefaultSize): Likewise.
 337         * i386-tbl.h: Regenerated.
 338
 339 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 340
 341         PR 25627
 342         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 343         instructions.
 344
 345 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 346
 347         PR gas/25622
 348         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 349         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 350         * i386-tbl.h: Regenerated.
 351
 352 2020-02-26  Alan Modra  <amodra@gmail.com>
 353
 354         * aarch64-asm.c: Indent labels correctly.
 355         * aarch64-dis.c: Likewise.
 356         * aarch64-gen.c: Likewise.
 357         * aarch64-opc.c: Likewise.
 358         * alpha-dis.c: Likewise.
 359         * i386-dis.c: Likewise.
 360         * nds32-asm.c: Likewise.
 361         * nfp-dis.c: Likewise.
 362         * visium-dis.c: Likewise.
 363
 364 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 365
 366         * arc-regs.h (int_vector_base): Make it available for all ARC
 367         CPUs.
 368
 369 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 370
 371         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 372         changed.
 373
 374 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 375
 376         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 377         c.mv/c.li if rs1 is zero.
 378
 379 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 380
 381         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 382         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 383         CPU_POPCNT_FLAGS.
 384         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 385         * i386-opc.h (CpuABM): Removed.
 386         (CpuPOPCNT): New.
 387         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 388         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 389         popcnt.  Remove CpuABM from lzcnt.
 390         * i386-init.h: Regenerated.
 391         * i386-tbl.h: Likewise.
 392
 393 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 394
 395         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 396         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 397         VexW1 instead of open-coding them.
 398         * i386-tbl.h: Re-generate.
 399
 400 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 401
 402         * i386-opc.tbl (AddrPrefixOpReg): Define.
 403         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 404         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 405         templates. Drop NoRex64.
 406         * i386-tbl.h: Re-generate.
 407
 408 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 409
 410         PR gas/6518
 411         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 412         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 413         into Intel syntax instance (with Unpsecified) and AT&T one
 414         (without).
 415         (vcvtneps2bf16): Likewise, along with folding the two so far
 416         separate ones.
 417         * i386-tbl.h: Re-generate.
 418
 419 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 420
 421         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 422         CPU_ANY_SSE4A_FLAGS.
 423
 424 2020-02-17  Alan Modra  <amodra@gmail.com>
 425
 426         * i386-gen.c (cpu_flag_init): Correct last change.
 427
 428 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 429
 430         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 431         CPU_ANY_SSE4_FLAGS.
 432
 433 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 436         (movzx): Likewise.
 437
 438 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 439
 440         PR gas/25438
 441         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 442         destination for Cpu64-only variant.
 443         (movzx): Fold patterns.
 444         * i386-tbl.h: Re-generate.
 445
 446 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 447
 448         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 449         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 450         CPU_ANY_SSE4_FLAGS entry.
 451         * i386-init.h: Re-generate.
 452
 453 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 456         with Unspecified, making the present one AT&T syntax only.
 457         * i386-tbl.h: Re-generate.
 458
 459 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 462         * i386-tbl.h: Re-generate.
 463
 464 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 465
 466         PR gas/24546
 467         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 468         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 469         Amd64 and Intel64 templates.
 470         (call, jmp): Likewise for far indirect variants. Dro
 471         Unspecified.
 472         * i386-tbl.h: Re-generate.
 473
 474 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 477         * i386-opc.h (ShortForm): Delete.
 478         (struct i386_opcode_modifier): Remove shortform field.
 479         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 480         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 481         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 482         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 483         Drop ShortForm.
 484         * i386-tbl.h: Re-generate.
 485
 486 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 489         fucompi): Drop ShortForm from operand-less templates.
 490         * i386-tbl.h: Re-generate.
 491
 492 2020-02-11  Alan Modra  <amodra@gmail.com>
 493
 494         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 495         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 496         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 497         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 498         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 499
 500 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 501
 502         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 503         (cde_opcodes): Add VCX* instructions.
 504
 505 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 506             Matthew Malcomson  <matthew.malcomson@arm.com>
 507
 508         * arm-dis.c (struct cdeopcode32): New.
 509         (CDE_OPCODE): New macro.
 510         (cde_opcodes): New disassembly table.
 511         (regnames): New option to table.
 512         (cde_coprocs): New global variable.
 513         (print_insn_cde): New
 514         (print_insn_thumb32): Use print_insn_cde.
 515         (parse_arm_disassembler_options): Parse coprocN args.
 516
 517 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 518
 519         PR gas/25516
 520         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 521         with ISA64.
 522         * i386-opc.h (AMD64): Removed.
 523         (Intel64): Likewose.
 524         (AMD64): New.
 525         (INTEL64): Likewise.
 526         (INTEL64ONLY): Likewise.
 527         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 528         * i386-opc.tbl (Amd64): New.
 529         (Intel64): Likewise.
 530         (Intel64Only): Likewise.
 531         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 532         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 533         * i386-tbl.h: Regenerated.
 534
 535 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 536
 537         PR 25469
 538         * z80-dis.c: Add support for GBZ80 opcodes.
 539
 540 2020-02-04  Alan Modra  <amodra@gmail.com>
 541
 542         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 543
 544 2020-02-03  Alan Modra  <amodra@gmail.com>
 545
 546         * m32c-ibld.c: Regenerate.
 547
 548 2020-02-01  Alan Modra  <amodra@gmail.com>
 549
 550         * frv-ibld.c: Regenerate.
 551
 552 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 553
 554         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 555         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 556         (OP_E_memory): Replace xmm_mdq_mode case label by
 557         vex_scalar_w_dq_mode one.
 558         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 559
 560 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 561
 562         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 563         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 564         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 565         (intel_operand_size): Drop vex_w_dq_mode case label.
 566
 567 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 568
 569         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 570         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 571
 572 2020-01-30  Alan Modra  <amodra@gmail.com>
 573
 574         * m32c-ibld.c: Regenerate.
 575
 576 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 577
 578         * bpf-opc.c: Regenerate.
 579
 580 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 581
 582         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 583         (dis386): Use them to replace C2/C3 table entries.
 584         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 585         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 586         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 587         * i386-tbl.h: Re-generate.
 588
 589 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 590
 591         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 592         forms.
 593         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 594         DefaultSize.
 595         * i386-tbl.h: Re-generate.
 596
 597 2020-01-30  Alan Modra  <amodra@gmail.com>
 598
 599         * tic4x-dis.c (tic4x_dp): Make unsigned.
 600
 601 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 602             Jan Beulich  <jbeulich@suse.com>
 603
 604         PR binutils/25445
 605         * i386-dis.c (MOVSXD_Fixup): New function.
 606         (movsxd_mode): New enum.
 607         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 608         (intel_operand_size): Handle movsxd_mode.
 609         (OP_E_register): Likewise.
 610         (OP_G): Likewise.
 611         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 612         register on movsxd.  Add movsxd with 16-bit destination register
 613         for AMD64 and Intel64 ISAs.
 614         * i386-tbl.h: Regenerated.
 615
 616 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 617
 618         PR 25403
 619         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 620         * aarch64-asm-2.c: Regenerate
 621         * aarch64-dis-2.c: Likewise.
 622         * aarch64-opc-2.c: Likewise.
 623
 624 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-opc.tbl (sysret): Drop DefaultSize.
 627         * i386-tbl.h: Re-generate.
 628
 629 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 630
 631         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 632         Dword.
 633         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 634         * i386-tbl.h: Re-generate.
 635
 636 2020-01-20  Nick Clifton  <nickc@redhat.com>
 637
 638         * po/de.po: Updated German translation.
 639         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 640         * po/uk.po: Updated Ukranian translation.
 641
 642 2020-01-20  Alan Modra  <amodra@gmail.com>
 643
 644         * hppa-dis.c (fput_const): Remove useless cast.
 645
 646 2020-01-20  Alan Modra  <amodra@gmail.com>
 647
 648         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 649
 650 2020-01-18  Nick Clifton  <nickc@redhat.com>
 651
 652         * configure: Regenerate.
 653         * po/opcodes.pot: Regenerate.
 654
 655 2020-01-18  Nick Clifton  <nickc@redhat.com>
 656
 657         Binutils 2.34 branch created.
 658
 659 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 660
 661         * opintl.h: Fix spelling error (seperate).
 662
 663 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 664
 665         * i386-opc.tbl: Add {vex} pseudo prefix.
 666         * i386-tbl.h: Regenerated.
 667
 668 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 669
 670         PR 25376
 671         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 672         (neon_opcodes): Likewise.
 673         (select_arm_features): Make sure we enable MVE bits when selecting
 674         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 675         any architecture.
 676
 677 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 678
 679         * i386-opc.tbl: Drop stale comment from XOP section.
 680
 681 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 684         (extractps): Add VexWIG to SSE2AVX forms.
 685         * i386-tbl.h: Re-generate.
 686
 687 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 688
 689         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 690         Size64 from and use VexW1 on SSE2AVX forms.
 691         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 692         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 693         * i386-tbl.h: Re-generate.
 694
 695 2020-01-15  Alan Modra  <amodra@gmail.com>
 696
 697         * tic4x-dis.c (tic4x_version): Make unsigned long.
 698         (optab, optab_special, registernames): New file scope vars.
 699         (tic4x_print_register): Set up registernames rather than
 700         malloc'd registertable.
 701         (tic4x_disassemble): Delete optable and optable_special.  Use
 702         optab and optab_special instead.  Throw away old optab,
 703         optab_special and registernames when info->mach changes.
 704
 705 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 706
 707         PR 25377
 708         * z80-dis.c (suffix): Use .db instruction to generate double
 709         prefix.
 710
 711 2020-01-14  Alan Modra  <amodra@gmail.com>
 712
 713         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 714         values to unsigned before shifting.
 715
 716 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 717
 718         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 719         flow instructions.
 720         (print_insn_thumb16, print_insn_thumb32): Likewise.
 721         (print_insn): Initialize the insn info.
 722         * i386-dis.c (print_insn): Initialize the insn info fields, and
 723         detect jumps.
 724
 725 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 726
 727         * arc-opc.c (C_NE): Make it required.
 728
 729 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 730
 731         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 732         reserved register name.
 733
 734 2020-01-13  Alan Modra  <amodra@gmail.com>
 735
 736         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 737         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 738
 739 2020-01-13  Alan Modra  <amodra@gmail.com>
 740
 741         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 742         result of wasm_read_leb128 in a uint64_t and check that bits
 743         are not lost when copying to other locals.  Use uint32_t for
 744         most locals.  Use PRId64 when printing int64_t.
 745
 746 2020-01-13  Alan Modra  <amodra@gmail.com>
 747
 748         * score-dis.c: Formatting.
 749         * score7-dis.c: Formatting.
 750
 751 2020-01-13  Alan Modra  <amodra@gmail.com>
 752
 753         * score-dis.c (print_insn_score48): Use unsigned variables for
 754         unsigned values.  Don't left shift negative values.
 755         (print_insn_score32): Likewise.
 756         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 757
 758 2020-01-13  Alan Modra  <amodra@gmail.com>
 759
 760         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 761
 762 2020-01-13  Alan Modra  <amodra@gmail.com>
 763
 764         * fr30-ibld.c: Regenerate.
 765
 766 2020-01-13  Alan Modra  <amodra@gmail.com>
 767
 768         * xgate-dis.c (print_insn): Don't left shift signed value.
 769         (ripBits): Formatting, use 1u.
 770
 771 2020-01-10  Alan Modra  <amodra@gmail.com>
 772
 773         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 774         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 775
 776 2020-01-10  Alan Modra  <amodra@gmail.com>
 777
 778         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 779         and XRREG value earlier to avoid a shift with negative exponent.
 780         * m10200-dis.c (disassemble): Similarly.
 781
 782 2020-01-09  Nick Clifton  <nickc@redhat.com>
 783
 784         PR 25224
 785         * z80-dis.c (ld_ii_ii): Use correct cast.
 786
 787 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 788
 789         PR 25224
 790         * z80-dis.c (ld_ii_ii): Use character constant when checking
 791         opcode byte value.
 792
 793 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-dis.c (SEP_Fixup): New.
 796         (SEP): Define.
 797         (dis386_twobyte): Use it for sysenter/sysexit.
 798         (enum x86_64_isa): Change amd64 enumerator to value 1.
 799         (OP_J): Compare isa64 against intel64 instead of amd64.
 800         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 801         forms.
 802         * i386-tbl.h: Re-generate.
 803
 804 2020-01-08  Alan Modra  <amodra@gmail.com>
 805
 806         * z8k-dis.c: Include libiberty.h
 807         (instr_data_s): Make max_fetched unsigned.
 808         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 809         Don't exceed byte_info bounds.
 810         (output_instr): Make num_bytes unsigned.
 811         (unpack_instr): Likewise for nibl_count and loop.
 812         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 813         idx unsigned.
 814         * z8k-opc.h: Regenerate.
 815
 816 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 817
 818         * arc-tbl.h (llock): Use 'LLOCK' as class.
 819         (llockd): Likewise.
 820         (scond): Use 'SCOND' as class.
 821         (scondd): Likewise.
 822         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 823         (scondd): Likewise.
 824
 825 2020-01-06  Alan Modra  <amodra@gmail.com>
 826
 827         * m32c-ibld.c: Regenerate.
 828
 829 2020-01-06  Alan Modra  <amodra@gmail.com>
 830
 831         PR 25344
 832         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 833         Peek at next byte to prevent recursion on repeated prefix bytes.
 834         Ensure uninitialised "mybuf" is not accessed.
 835         (print_insn_z80): Don't zero n_fetch and n_used here,..
 836         (print_insn_z80_buf): ..do it here instead.
 837
 838 2020-01-04  Alan Modra  <amodra@gmail.com>
 839
 840         * m32r-ibld.c: Regenerate.
 841
 842 2020-01-04  Alan Modra  <amodra@gmail.com>
 843
 844         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 845
 846 2020-01-04  Alan Modra  <amodra@gmail.com>
 847
 848         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 849
 850 2020-01-04  Alan Modra  <amodra@gmail.com>
 851
 852         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 853
 854 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 855
 856         * aarch64-tbl.h (aarch64_opcode_table): Use
 857         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 858
 859 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 860
 861         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 862         forms of SUDOT and USDOT.
 863
 864 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 865
 866         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 867         uzip{1,2}.
 868         * opcodes/aarch64-dis-2.c: Re-generate.
 869
 870 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 871
 872         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 873         FMMLA encoding.
 874         * opcodes/aarch64-dis-2.c: Re-generate.
 875
 876 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 877
 878         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 879
 880 2020-01-01  Alan Modra  <amodra@gmail.com>
 881
 882         Update year range in copyright notice of all files.
 883
 884 For older changes see ChangeLog-2019
 885 \f
 886 Copyright (C) 2020 Free Software Foundation, Inc.
 887
 888 Copying and distribution of this file, with or without modification,
 889 are permitted in any medium without royalty provided the copyright
 890 notice and this notice are preserved.
 891
 892 Local Variables:
 893 mode: change-log
 894 left-margin: 8
 895 fill-column: 74
 896 version-control: never
 897 End: