opcodes/ChangeLog

   1 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
   2
   3         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
   4         * aarch64-dis.c (insn_sequence): New.
   5
   6 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
   7
   8         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
   9         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
  10         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
  11         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
  12         constraints.
  13         (_SVE_INSNC): New.
  14         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
  15         constraints.
  16         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
  17         F_SCAN flags.
  18         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
  19         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
  20         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
  21         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
  22         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
  23         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
  24         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
  25
  26 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
  27
  28         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
  29
  30 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
  31
  32         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
  33         are used when extracting signed fields and converting them to
  34         potentially 64-bit types.
  35
  36 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
  37
  38         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
  39         * Makefile.in: Re-generate.
  40         * aclocal.m4: Re-generate.
  41         * configure: Re-generate.
  42         * configure.ac: Remove check for -Wno-missing-field-initializers.
  43         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
  44         (csky_v2_opcodes): Likewise.
  45
  46 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
  47
  48         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
  49
  50 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
  51
  52         * nds32-asm.c (operand_fields): Remove the unused fields.
  53         (nds32_opcodes): Remove the unused instructions.
  54         * nds32-dis.c (nds32_ex9_info): Removed.
  55         (nds32_parse_opcode): Updated.
  56         (print_insn_nds32): Likewise.
  57         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
  58         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
  59         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
  60         build_opcode_hash_table): New functions.
  61         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
  62         nds32_opcode_table): New.
  63         (hw_ktabs): Declare it to a pointer rather than an array.
  64         (build_hash_table): Removed.
  65         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
  66         SYN_ROPT and upadte HW_GPR and HW_INT.
  67         * nds32-dis.c (keywords): Remove const.
  68         (match_field): New function.
  69         (nds32_parse_opcode): Updated.
  70         * disassemble.c (disassemble_init_for_target):
  71         Add disassemble_init_nds32.
  72         * nds32-dis.c (eum map_type): New.
  73         (nds32_private_data): Likewise.
  74         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
  75         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
  76         (print_insn_nds32): Updated.
  77         * nds32-asm.c (parse_aext_reg): Add new parameter.
  78         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
  79         are allowed to use.
  80         All callers changed.
  81         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
  82         (operand_fields): Add new fields.
  83         (nds32_opcodes): Add new instructions.
  84         (keyword_aridxi_mx): New keyword.
  85         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
  86         and NASM_ATTR_ZOL.
  87         (ALU2_1, ALU2_2, ALU2_3): New macros.
  88         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
  89
  90 2018-09-17  Kito Cheng  <kito@andestech.com>
  91
  92         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
  93
  94 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  95
  96         PR gas/23670
  97         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
  98         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
  99         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 100         (EVEX_LEN_0F7E_P_1): Likewise.
 101         (EVEX_LEN_0F7E_P_2): Likewise.
 102         (EVEX_LEN_0FD6_P_2): Likewise.
 103         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 104         (EVEX_LEN_TABLE): Likewise.
 105         (EVEX_LEN_0F6E_P_2): New enum.
 106         (EVEX_LEN_0F7E_P_1): Likewise.
 107         (EVEX_LEN_0F7E_P_2): Likewise.
 108         (EVEX_LEN_0FD6_P_2): Likewise.
 109         (evex_len_table): New.
 110         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 111         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 112         * i386-tbl.h: Regenerated.
 113
 114 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 115
 116         PR gas/23665
 117         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 118         VEX_LEN_0F7E_P_2 entries.
 119         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 120         * i386-tbl.h: Regenerated.
 121
 122 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 123
 124         * i386-dis.c (VZERO_Fixup): Removed.
 125         (VZERO): Likewise.
 126         (VEX_LEN_0F10_P_1): Likewise.
 127         (VEX_LEN_0F10_P_3): Likewise.
 128         (VEX_LEN_0F11_P_1): Likewise.
 129         (VEX_LEN_0F11_P_3): Likewise.
 130         (VEX_LEN_0F2E_P_0): Likewise.
 131         (VEX_LEN_0F2E_P_2): Likewise.
 132         (VEX_LEN_0F2F_P_0): Likewise.
 133         (VEX_LEN_0F2F_P_2): Likewise.
 134         (VEX_LEN_0F51_P_1): Likewise.
 135         (VEX_LEN_0F51_P_3): Likewise.
 136         (VEX_LEN_0F52_P_1): Likewise.
 137         (VEX_LEN_0F53_P_1): Likewise.
 138         (VEX_LEN_0F58_P_1): Likewise.
 139         (VEX_LEN_0F58_P_3): Likewise.
 140         (VEX_LEN_0F59_P_1): Likewise.
 141         (VEX_LEN_0F59_P_3): Likewise.
 142         (VEX_LEN_0F5A_P_1): Likewise.
 143         (VEX_LEN_0F5A_P_3): Likewise.
 144         (VEX_LEN_0F5C_P_1): Likewise.
 145         (VEX_LEN_0F5C_P_3): Likewise.
 146         (VEX_LEN_0F5D_P_1): Likewise.
 147         (VEX_LEN_0F5D_P_3): Likewise.
 148         (VEX_LEN_0F5E_P_1): Likewise.
 149         (VEX_LEN_0F5E_P_3): Likewise.
 150         (VEX_LEN_0F5F_P_1): Likewise.
 151         (VEX_LEN_0F5F_P_3): Likewise.
 152         (VEX_LEN_0FC2_P_1): Likewise.
 153         (VEX_LEN_0FC2_P_3): Likewise.
 154         (VEX_LEN_0F3A0A_P_2): Likewise.
 155         (VEX_LEN_0F3A0B_P_2): Likewise.
 156         (VEX_W_0F10_P_0): Likewise.
 157         (VEX_W_0F10_P_1): Likewise.
 158         (VEX_W_0F10_P_2): Likewise.
 159         (VEX_W_0F10_P_3): Likewise.
 160         (VEX_W_0F11_P_0): Likewise.
 161         (VEX_W_0F11_P_1): Likewise.
 162         (VEX_W_0F11_P_2): Likewise.
 163         (VEX_W_0F11_P_3): Likewise.
 164         (VEX_W_0F12_P_0_M_0): Likewise.
 165         (VEX_W_0F12_P_0_M_1): Likewise.
 166         (VEX_W_0F12_P_1): Likewise.
 167         (VEX_W_0F12_P_2): Likewise.
 168         (VEX_W_0F12_P_3): Likewise.
 169         (VEX_W_0F13_M_0): Likewise.
 170         (VEX_W_0F14): Likewise.
 171         (VEX_W_0F15): Likewise.
 172         (VEX_W_0F16_P_0_M_0): Likewise.
 173         (VEX_W_0F16_P_0_M_1): Likewise.
 174         (VEX_W_0F16_P_1): Likewise.
 175         (VEX_W_0F16_P_2): Likewise.
 176         (VEX_W_0F17_M_0): Likewise.
 177         (VEX_W_0F28): Likewise.
 178         (VEX_W_0F29): Likewise.
 179         (VEX_W_0F2B_M_0): Likewise.
 180         (VEX_W_0F2E_P_0): Likewise.
 181         (VEX_W_0F2E_P_2): Likewise.
 182         (VEX_W_0F2F_P_0): Likewise.
 183         (VEX_W_0F2F_P_2): Likewise.
 184         (VEX_W_0F50_M_0): Likewise.
 185         (VEX_W_0F51_P_0): Likewise.
 186         (VEX_W_0F51_P_1): Likewise.
 187         (VEX_W_0F51_P_2): Likewise.
 188         (VEX_W_0F51_P_3): Likewise.
 189         (VEX_W_0F52_P_0): Likewise.
 190         (VEX_W_0F52_P_1): Likewise.
 191         (VEX_W_0F53_P_0): Likewise.
 192         (VEX_W_0F53_P_1): Likewise.
 193         (VEX_W_0F58_P_0): Likewise.
 194         (VEX_W_0F58_P_1): Likewise.
 195         (VEX_W_0F58_P_2): Likewise.
 196         (VEX_W_0F58_P_3): Likewise.
 197         (VEX_W_0F59_P_0): Likewise.
 198         (VEX_W_0F59_P_1): Likewise.
 199         (VEX_W_0F59_P_2): Likewise.
 200         (VEX_W_0F59_P_3): Likewise.
 201         (VEX_W_0F5A_P_0): Likewise.
 202         (VEX_W_0F5A_P_1): Likewise.
 203         (VEX_W_0F5A_P_3): Likewise.
 204         (VEX_W_0F5B_P_0): Likewise.
 205         (VEX_W_0F5B_P_1): Likewise.
 206         (VEX_W_0F5B_P_2): Likewise.
 207         (VEX_W_0F5C_P_0): Likewise.
 208         (VEX_W_0F5C_P_1): Likewise.
 209         (VEX_W_0F5C_P_2): Likewise.
 210         (VEX_W_0F5C_P_3): Likewise.
 211         (VEX_W_0F5D_P_0): Likewise.
 212         (VEX_W_0F5D_P_1): Likewise.
 213         (VEX_W_0F5D_P_2): Likewise.
 214         (VEX_W_0F5D_P_3): Likewise.
 215         (VEX_W_0F5E_P_0): Likewise.
 216         (VEX_W_0F5E_P_1): Likewise.
 217         (VEX_W_0F5E_P_2): Likewise.
 218         (VEX_W_0F5E_P_3): Likewise.
 219         (VEX_W_0F5F_P_0): Likewise.
 220         (VEX_W_0F5F_P_1): Likewise.
 221         (VEX_W_0F5F_P_2): Likewise.
 222         (VEX_W_0F5F_P_3): Likewise.
 223         (VEX_W_0F60_P_2): Likewise.
 224         (VEX_W_0F61_P_2): Likewise.
 225         (VEX_W_0F62_P_2): Likewise.
 226         (VEX_W_0F63_P_2): Likewise.
 227         (VEX_W_0F64_P_2): Likewise.
 228         (VEX_W_0F65_P_2): Likewise.
 229         (VEX_W_0F66_P_2): Likewise.
 230         (VEX_W_0F67_P_2): Likewise.
 231         (VEX_W_0F68_P_2): Likewise.
 232         (VEX_W_0F69_P_2): Likewise.
 233         (VEX_W_0F6A_P_2): Likewise.
 234         (VEX_W_0F6B_P_2): Likewise.
 235         (VEX_W_0F6C_P_2): Likewise.
 236         (VEX_W_0F6D_P_2): Likewise.
 237         (VEX_W_0F6F_P_1): Likewise.
 238         (VEX_W_0F6F_P_2): Likewise.
 239         (VEX_W_0F70_P_1): Likewise.
 240         (VEX_W_0F70_P_2): Likewise.
 241         (VEX_W_0F70_P_3): Likewise.
 242         (VEX_W_0F71_R_2_P_2): Likewise.
 243         (VEX_W_0F71_R_4_P_2): Likewise.
 244         (VEX_W_0F71_R_6_P_2): Likewise.
 245         (VEX_W_0F72_R_2_P_2): Likewise.
 246         (VEX_W_0F72_R_4_P_2): Likewise.
 247         (VEX_W_0F72_R_6_P_2): Likewise.
 248         (VEX_W_0F73_R_2_P_2): Likewise.
 249         (VEX_W_0F73_R_3_P_2): Likewise.
 250         (VEX_W_0F73_R_6_P_2): Likewise.
 251         (VEX_W_0F73_R_7_P_2): Likewise.
 252         (VEX_W_0F74_P_2): Likewise.
 253         (VEX_W_0F75_P_2): Likewise.
 254         (VEX_W_0F76_P_2): Likewise.
 255         (VEX_W_0F77_P_0): Likewise.
 256         (VEX_W_0F7C_P_2): Likewise.
 257         (VEX_W_0F7C_P_3): Likewise.
 258         (VEX_W_0F7D_P_2): Likewise.
 259         (VEX_W_0F7D_P_3): Likewise.
 260         (VEX_W_0F7E_P_1): Likewise.
 261         (VEX_W_0F7F_P_1): Likewise.
 262         (VEX_W_0F7F_P_2): Likewise.
 263         (VEX_W_0FAE_R_2_M_0): Likewise.
 264         (VEX_W_0FAE_R_3_M_0): Likewise.
 265         (VEX_W_0FC2_P_0): Likewise.
 266         (VEX_W_0FC2_P_1): Likewise.
 267         (VEX_W_0FC2_P_2): Likewise.
 268         (VEX_W_0FC2_P_3): Likewise.
 269         (VEX_W_0FD0_P_2): Likewise.
 270         (VEX_W_0FD0_P_3): Likewise.
 271         (VEX_W_0FD1_P_2): Likewise.
 272         (VEX_W_0FD2_P_2): Likewise.
 273         (VEX_W_0FD3_P_2): Likewise.
 274         (VEX_W_0FD4_P_2): Likewise.
 275         (VEX_W_0FD5_P_2): Likewise.
 276         (VEX_W_0FD6_P_2): Likewise.
 277         (VEX_W_0FD7_P_2_M_1): Likewise.
 278         (VEX_W_0FD8_P_2): Likewise.
 279         (VEX_W_0FD9_P_2): Likewise.
 280         (VEX_W_0FDA_P_2): Likewise.
 281         (VEX_W_0FDB_P_2): Likewise.
 282         (VEX_W_0FDC_P_2): Likewise.
 283         (VEX_W_0FDD_P_2): Likewise.
 284         (VEX_W_0FDE_P_2): Likewise.
 285         (VEX_W_0FDF_P_2): Likewise.
 286         (VEX_W_0FE0_P_2): Likewise.
 287         (VEX_W_0FE1_P_2): Likewise.
 288         (VEX_W_0FE2_P_2): Likewise.
 289         (VEX_W_0FE3_P_2): Likewise.
 290         (VEX_W_0FE4_P_2): Likewise.
 291         (VEX_W_0FE5_P_2): Likewise.
 292         (VEX_W_0FE6_P_1): Likewise.
 293         (VEX_W_0FE6_P_2): Likewise.
 294         (VEX_W_0FE6_P_3): Likewise.
 295         (VEX_W_0FE7_P_2_M_0): Likewise.
 296         (VEX_W_0FE8_P_2): Likewise.
 297         (VEX_W_0FE9_P_2): Likewise.
 298         (VEX_W_0FEA_P_2): Likewise.
 299         (VEX_W_0FEB_P_2): Likewise.
 300         (VEX_W_0FEC_P_2): Likewise.
 301         (VEX_W_0FED_P_2): Likewise.
 302         (VEX_W_0FEE_P_2): Likewise.
 303         (VEX_W_0FEF_P_2): Likewise.
 304         (VEX_W_0FF0_P_3_M_0): Likewise.
 305         (VEX_W_0FF1_P_2): Likewise.
 306         (VEX_W_0FF2_P_2): Likewise.
 307         (VEX_W_0FF3_P_2): Likewise.
 308         (VEX_W_0FF4_P_2): Likewise.
 309         (VEX_W_0FF5_P_2): Likewise.
 310         (VEX_W_0FF6_P_2): Likewise.
 311         (VEX_W_0FF7_P_2): Likewise.
 312         (VEX_W_0FF8_P_2): Likewise.
 313         (VEX_W_0FF9_P_2): Likewise.
 314         (VEX_W_0FFA_P_2): Likewise.
 315         (VEX_W_0FFB_P_2): Likewise.
 316         (VEX_W_0FFC_P_2): Likewise.
 317         (VEX_W_0FFD_P_2): Likewise.
 318         (VEX_W_0FFE_P_2): Likewise.
 319         (VEX_W_0F3800_P_2): Likewise.
 320         (VEX_W_0F3801_P_2): Likewise.
 321         (VEX_W_0F3802_P_2): Likewise.
 322         (VEX_W_0F3803_P_2): Likewise.
 323         (VEX_W_0F3804_P_2): Likewise.
 324         (VEX_W_0F3805_P_2): Likewise.
 325         (VEX_W_0F3806_P_2): Likewise.
 326         (VEX_W_0F3807_P_2): Likewise.
 327         (VEX_W_0F3808_P_2): Likewise.
 328         (VEX_W_0F3809_P_2): Likewise.
 329         (VEX_W_0F380A_P_2): Likewise.
 330         (VEX_W_0F380B_P_2): Likewise.
 331         (VEX_W_0F3817_P_2): Likewise.
 332         (VEX_W_0F381C_P_2): Likewise.
 333         (VEX_W_0F381D_P_2): Likewise.
 334         (VEX_W_0F381E_P_2): Likewise.
 335         (VEX_W_0F3820_P_2): Likewise.
 336         (VEX_W_0F3821_P_2): Likewise.
 337         (VEX_W_0F3822_P_2): Likewise.
 338         (VEX_W_0F3823_P_2): Likewise.
 339         (VEX_W_0F3824_P_2): Likewise.
 340         (VEX_W_0F3825_P_2): Likewise.
 341         (VEX_W_0F3828_P_2): Likewise.
 342         (VEX_W_0F3829_P_2): Likewise.
 343         (VEX_W_0F382A_P_2_M_0): Likewise.
 344         (VEX_W_0F382B_P_2): Likewise.
 345         (VEX_W_0F3830_P_2): Likewise.
 346         (VEX_W_0F3831_P_2): Likewise.
 347         (VEX_W_0F3832_P_2): Likewise.
 348         (VEX_W_0F3833_P_2): Likewise.
 349         (VEX_W_0F3834_P_2): Likewise.
 350         (VEX_W_0F3835_P_2): Likewise.
 351         (VEX_W_0F3837_P_2): Likewise.
 352         (VEX_W_0F3838_P_2): Likewise.
 353         (VEX_W_0F3839_P_2): Likewise.
 354         (VEX_W_0F383A_P_2): Likewise.
 355         (VEX_W_0F383B_P_2): Likewise.
 356         (VEX_W_0F383C_P_2): Likewise.
 357         (VEX_W_0F383D_P_2): Likewise.
 358         (VEX_W_0F383E_P_2): Likewise.
 359         (VEX_W_0F383F_P_2): Likewise.
 360         (VEX_W_0F3840_P_2): Likewise.
 361         (VEX_W_0F3841_P_2): Likewise.
 362         (VEX_W_0F38DB_P_2): Likewise.
 363         (VEX_W_0F3A08_P_2): Likewise.
 364         (VEX_W_0F3A09_P_2): Likewise.
 365         (VEX_W_0F3A0A_P_2): Likewise.
 366         (VEX_W_0F3A0B_P_2): Likewise.
 367         (VEX_W_0F3A0C_P_2): Likewise.
 368         (VEX_W_0F3A0D_P_2): Likewise.
 369         (VEX_W_0F3A0E_P_2): Likewise.
 370         (VEX_W_0F3A0F_P_2): Likewise.
 371         (VEX_W_0F3A21_P_2): Likewise.
 372         (VEX_W_0F3A40_P_2): Likewise.
 373         (VEX_W_0F3A41_P_2): Likewise.
 374         (VEX_W_0F3A42_P_2): Likewise.
 375         (VEX_W_0F3A62_P_2): Likewise.
 376         (VEX_W_0F3A63_P_2): Likewise.
 377         (VEX_W_0F3ADF_P_2): Likewise.
 378         (VEX_LEN_0F77_P_0): New.
 379         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 380         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 381         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 382         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 383         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 384         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 385         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 386         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 387         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 388         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 389         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 390         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 391         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 392         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 393         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 394         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 395         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 396         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 397         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 398         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 399         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 400         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 401         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 402         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 403         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 404         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 405         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 406         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 407         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 408         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 409         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 410         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 411         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 412         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 413         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 414         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 415         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 416         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 417         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 418         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 419         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 420         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 421         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 422         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 423         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 424         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 425         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 426         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 427         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 428         (vex_table): Update VEX 0F28 and 0F29 entries.
 429         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 430         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 431         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 432         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 433         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 434         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 435         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 436         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 437         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 438         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 439         VEX_LEN_0F3A0B_P_2 entries.
 440         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 441         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 442         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 443         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 444         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 445         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 446         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 447         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 448         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 449         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 450         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 451         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 452         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 453         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 454         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 455         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 456         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 457         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 458         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 459         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 460         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 461         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 462         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 463         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 464         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 465         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 466         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 467         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 468         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 469         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 470         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 471         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 472         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 473         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 474         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 475         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 476         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 477         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 478         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 479         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 480         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 481         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 482         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 483         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 484         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 485         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 486         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 487         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 488         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 489         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 490         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 491         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 492         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 493         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 494         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 495         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 496         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 497         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 498         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 499         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 500         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 501         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 502         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 503         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 504         VEX_W_0F3ADF_P_2 entries.
 505         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 506         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 507         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 508
 509 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 510
 511         * i386-opc.tbl (VexWIG): New.
 512         Replace VexW=3 with VexWIG.
 513
 514 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 515
 516         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 517         * i386-tbl.h: Regenerated.
 518
 519 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 520
 521         PR gas/23665
 522         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 523         VEX_LEN_0FD6_P_2 entries.
 524         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 525         * i386-tbl.h: Regenerated.
 526
 527 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         PR gas/23642
 530         * i386-opc.h (VEXWIG): New.
 531         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 532         * i386-tbl.h: Regenerated.
 533
 534 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 535
 536         PR binutils/23655
 537         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 538         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 539         * i386-dis.c (EXxEVexR64): New.
 540         (evex_rounding_64_mode): Likewise.
 541         (OP_Rounding): Handle evex_rounding_64_mode.
 542
 543 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 544
 545         PR binutils/23655
 546         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 547         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 548         * i386-dis.c (Edqa): New.
 549         (dqa_mode): Likewise.
 550         (intel_operand_size): Handle dqa_mode as m_mode.
 551         (OP_E_register): Handle dqa_mode as dq_mode.
 552         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 553
 554 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 555
 556         * i386-dis.c (OP_E_memory): Reformat.
 557
 558 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-opc.tbl (crc32): Fold byte and word forms.
 561         * i386-tbl.h: Re-generate.
 562
 563 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 564
 565         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 566         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 567         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 568         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 569         * i386-tbl.h: Regenerated.
 570
 571 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 574         meaningless.
 575         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 576         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 577         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 578         * i386-tbl.h: Re-generate.
 579
 580 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 581
 582         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 583         AVX512_4VNNIW insns.
 584         * i386-tbl.h: Re-generate.
 585
 586 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 587
 588         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 589         meaningless.
 590         * i386-tbl.h: Re-generate.
 591
 592 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 595         meaningless.
 596         * i386-tbl.h: Re-generate.
 597
 598 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 601         meaningless.
 602         * i386-tbl.h: Re-generate.
 603
 604 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 605
 606         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 607         meaningless.
 608         * i386-tbl.h: Re-generate.
 609
 610 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 611
 612         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 613         meaningless.
 614         * i386-tbl.h: Re-generate.
 615
 616 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 619         * i386-tbl.h: Re-generate.
 620
 621 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 624         * i386-tbl.h: Re-generate.
 625
 626 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 627
 628         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 629         meaningless.
 630         * i386-tbl.h: Re-generate.
 631
 632 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 633
 634         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 635         meaningless.
 636         * i386-tbl.h: Re-generate.
 637
 638 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 641         * i386-tbl.h: Re-generate.
 642
 643 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 644
 645         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 646         * i386-tbl.h: Re-generate.
 647
 648 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 649
 650         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 651         * i386-tbl.h: Re-generate.
 652
 653 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 654
 655         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 656         meaningless.
 657         * i386-tbl.h: Re-generate.
 658
 659 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 660
 661         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 662         meaningless.
 663         * i386-tbl.h: Re-generate.
 664
 665 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 666
 667         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 668         meaningless.
 669         * i386-tbl.h: Re-generate.
 670
 671 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 672
 673         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 674         * i386-tbl.h: Re-generate.
 675
 676 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 677
 678         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 679         * i386-tbl.h: Re-generate.
 680
 681 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 684         * i386-tbl.h: Re-generate.
 685
 686 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 687
 688         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 689         (vpbroadcastw, rdpid): Drop NoRex64.
 690         * i386-tbl.h: Re-generate.
 691
 692 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 695         store templates, adding D.
 696         * i386-tbl.h: Re-generate.
 697
 698 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 699
 700         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 701         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 702         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 703         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 704         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 705         Fold load and store templates where possible, adding D. Drop
 706         IgnoreSize where it was pointlessly present. Drop redundant
 707         *word.
 708         * i386-tbl.h: Re-generate.
 709
 710 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 713         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 714         (intel_operand_size): Handle v_bndmk_mode.
 715         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 716
 717 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 718
 719         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 720
 721 2018-08-31  Kito Cheng  <kito@andestech.com>
 722
 723         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 724         compressed floating point instructions.
 725
 726 2018-08-30  Kito Cheng  <kito@andestech.com>
 727
 728         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 729         riscv_opcode.xlen_requirement.
 730         * riscv-opc.c (riscv_opcodes): Update for struct change.
 731
 732 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 733
 734         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 735         psr (PWRPSR) instruction.
 736
 737 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 738
 739         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 740
 741 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 742
 743         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 744
 745 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 746
 747         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 748         loongson3a as an alias of gs464 for compatibility.
 749         * mips-opc.c (mips_opcodes): Change Comments.
 750
 751 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 752
 753         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 754         option.
 755         (print_mips_disassembler_options): Document -M loongson-ext.
 756         * mips-opc.c (LEXT2): New macro.
 757         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 758
 759 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 760
 761          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 762          descriptors.
 763          (parse_mips_ase_option): Handle -M loongson-ext option.
 764          (print_mips_disassembler_options): Document -M loongson-ext.
 765          * mips-opc.c (IL3A): Delete.
 766          * mips-opc.c (LEXT): New macro.
 767          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 768          instructions.
 769
 770 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 771
 772         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 773         descriptors.
 774         (parse_mips_ase_option): Handle -M loongson-cam option.
 775         (print_mips_disassembler_options): Document -M loongson-cam.
 776         * mips-opc.c (LCAM): New macro.
 777         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 778         instructions.
 779
 780 2018-08-21  Alan Modra  <amodra@gmail.com>
 781
 782         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 783         (skip_optional_operands): Count optional operands, and update
 784         ppc_optional_operand_value call.
 785         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 786         (extract_vlensi): Likewise.
 787         (extract_fxm): Return default value for missing optional operand.
 788         (extract_ls, extract_raq, extract_tbr): Likewise.
 789         (insert_sxl, extract_sxl): New functions.
 790         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 791         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 792         flag and extra entry.
 793         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 794         extract_sxl.
 795
 796 2018-08-20  Alan Modra  <amodra@gmail.com>
 797
 798         * sh-opc.h (MASK): Simplify.
 799
 800 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 801
 802         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 803         BM_RESERVED0 or BM_RESERVED1
 804         (bm_rel_decode, bm_n_bytes): Ditto.
 805
 806 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 807
 808         * s12z.h: Delete.
 809
 810 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 811
 812         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 813         address with the addr32 prefix and without base nor index
 814         registers.
 815
 816 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 819         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 820         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 821         (cpu_flags): Add CpuCMOV and CpuFXSR.
 822         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 823         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 824         * i386-init.h: Regenerated.
 825         * i386-tbl.h: Likewise.
 826
 827 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 828
 829         * arc-regs.h: Update auxiliary registers.
 830
 831 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 832
 833         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 834         (RegIP, RegIZ): Define.
 835         * i386-reg.tbl: Adjust comments.
 836         (rip): Use Qword instead of BaseIndex. Use RegIP.
 837         (eip): Use Dword instead of BaseIndex. Use RegIP.
 838         (riz): Add Qword. Use RegIZ.
 839         (eiz): Add Dword. Use RegIZ.
 840         * i386-tbl.h: Re-generate.
 841
 842 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 843
 844         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 845         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 846         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 847         * i386-tbl.h: Re-generate.
 848
 849 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 850
 851         * i386-gen.c (operand_types): Remove Mem field.
 852         * i386-opc.h (union i386_operand_type): Remove mem field.
 853         * i386-init.h, i386-tbl.h: Re-generate.
 854
 855 2018-08-01  Alan Modra  <amodra@gmail.com>
 856
 857         * po/POTFILES.in: Regenerate.
 858
 859 2018-07-31  Nick Clifton  <nickc@redhat.com>
 860
 861         * po/sv.po: Updated Swedish translation.
 862
 863 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 864
 865         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 866         * i386-init.h, i386-tbl.h: Re-generate.
 867
 868 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 869
 870         * i386-opc.h (ZEROING_MASKING) Rename to ...
 871         (DYNAMIC_MASKING): ... this. Adjust comment.
 872         * i386-opc.tbl (MaskingMorZ): Define.
 873         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 874         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 875         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 876         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 877         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 878         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 879         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 880         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 881         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 882
 883 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 884
 885         * i386-opc.tbl: Use element rather than vector size for AVX512*
 886         scatter/gather insns.
 887         * i386-tbl.h: Re-generate.
 888
 889 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 890
 891         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 892         (cpu_flags): Drop CpuVREX.
 893         * i386-opc.h (CpuVREX): Delete.
 894         (union i386_cpu_flags): Remove cpuvrex.
 895         * i386-init.h, i386-tbl.h: Re-generate.
 896
 897 2018-07-30  Jim Wilson  <jimw@sifive.com>
 898
 899         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 900         fields.
 901         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 902
 903 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 904
 905         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 906         * Makefile.in: Regenerated.
 907         * configure.ac: Add C-SKY.
 908         * configure: Regenerated.
 909         * csky-dis.c: New file.
 910         * csky-opc.h: New file.
 911         * disassemble.c (ARCH_csky): Define.
 912         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 913         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 914
 915 2018-07-27  Alan Modra  <amodra@gmail.com>
 916
 917         * ppc-opc.c (insert_sprbat): Correct function parameter and
 918         return type.
 919         (extract_sprbat): Likewise, variable too.
 920
 921 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 922             Alan Modra  <amodra@gmail.com>
 923
 924         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 925         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 926         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 927         support disjointed BAT.
 928         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 929         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 930         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 931
 932 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 933             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 934
 935         * i386-gen.c (adjust_broadcast_modifier): New function.
 936         (process_i386_opcode_modifier): Add an argument for operands.
 937         Adjust the Broadcast value based on operands.
 938         (output_i386_opcode): Pass operand_types to
 939         process_i386_opcode_modifier.
 940         (process_i386_opcodes): Pass NULL as operands to
 941         process_i386_opcode_modifier.
 942         * i386-opc.h (BYTE_BROADCAST): New.
 943         (WORD_BROADCAST): Likewise.
 944         (DWORD_BROADCAST): Likewise.
 945         (QWORD_BROADCAST): Likewise.
 946         (i386_opcode_modifier): Expand broadcast to 3 bits.
 947         * i386-tbl.h: Regenerated.
 948
 949 2018-07-24  Alan Modra  <amodra@gmail.com>
 950
 951         PR 23430
 952         * or1k-desc.h: Regenerate.
 953
 954 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 957         vcvtusi2ss, and vcvtusi2sd.
 958         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 959         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 960         * i386-tbl.h: Re-generate.
 961
 962 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 963
 964         * arc-opc.c (extract_w6): Fix extending the sign.
 965
 966 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 967
 968         * arc-tbl.h (vewt): Allow it for ARC EM family.
 969
 970 2018-07-23  Alan Modra  <amodra@gmail.com>
 971
 972         PR 23419
 973         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 974         opcode variants for mtspr/mfspr encodings.
 975
 976 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 977             Maciej W. Rozycki  <macro@mips.com>
 978
 979         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 980         loongson3a descriptors.
 981         (parse_mips_ase_option): Handle -M loongson-mmi option.
 982         (print_mips_disassembler_options): Document -M loongson-mmi.
 983         * mips-opc.c (LMMI): New macro.
 984         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 985         instructions.
 986
 987 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 990         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 991         IgnoreSize and [XYZ]MMword where applicable.
 992         * i386-tbl.h: Re-generate.
 993
 994 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 997         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 998         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 999         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1000         * i386-tbl.h: Re-generate.
1001
1002 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1003
1004         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1005         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1006         VPCLMULQDQ templates into their respective AVX512VL counterparts
1007         where possible, using Disp8ShiftVL and CheckRegSize instead of
1008         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1009         * i386-tbl.h: Re-generate.
1010
1011 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1012
1013         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1014         AVX512VL counterparts where possible, using Disp8ShiftVL and
1015         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1016         IgnoreSize) as appropriate.
1017         * i386-tbl.h: Re-generate.
1018
1019 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-opc.tbl: Fold AVX512BW templates into their respective
1022         AVX512VL counterparts where possible, using Disp8ShiftVL and
1023         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1024         IgnoreSize) as appropriate.
1025         * i386-tbl.h: Re-generate.
1026
1027 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-opc.tbl: Fold AVX512CD templates into their respective
1030         AVX512VL counterparts where possible, using Disp8ShiftVL and
1031         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1032         IgnoreSize) as appropriate.
1033         * i386-tbl.h: Re-generate.
1034
1035 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1036
1037         * i386-opc.h (DISP8_SHIFT_VL): New.
1038         * i386-opc.tbl (Disp8ShiftVL):  Define.
1039         (various): Fold AVX512VL templates into their respective
1040         AVX512F counterparts where possible, using Disp8ShiftVL and
1041         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1042         IgnoreSize) as appropriate.
1043         * i386-tbl.h: Re-generate.
1044
1045 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1046
1047         * Makefile.am: Change dependencies and rule for
1048         $(srcdir)/i386-init.h.
1049         * Makefile.in: Re-generate.
1050         * i386-gen.c (process_i386_opcodes): New local variable
1051         "marker". Drop opening of input file. Recognize marker and line
1052         number directives.
1053         * i386-opc.tbl (OPCODE_I386_H): Define.
1054         (i386-opc.h): Include it.
1055         (None): Undefine.
1056
1057 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1058
1059         PR gas/23418
1060         * i386-opc.h (Byte): Update comments.
1061         (Word): Likewise.
1062         (Dword): Likewise.
1063         (Fword): Likewise.
1064         (Qword): Likewise.
1065         (Tbyte): Likewise.
1066         (Xmmword): Likewise.
1067         (Ymmword): Likewise.
1068         (Zmmword): Likewise.
1069         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1070         vcvttps2uqq.
1071         * i386-tbl.h: Regenerated.
1072
1073 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1074
1075         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1076         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1077         * aarch64-asm-2.c: Regenerate.
1078         * aarch64-dis-2.c: Regenerate.
1079         * aarch64-opc-2.c: Regenerate.
1080
1081 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1082
1083         PR binutils/23192
1084         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1085         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1086         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1087         sqdmulh, sqrdmulh): Use Em16.
1088
1089 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1090
1091         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1092         csdb together with them.
1093         (thumb32_opcodes): Likewise.
1094
1095 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1096
1097         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1098         requiring 32-bit registers as operands 2 and 3. Improve
1099         comments.
1100         (mwait, mwaitx): Fold templates. Improve comments.
1101         OPERAND_TYPE_INOUTPORTREG.
1102         * i386-tbl.h: Re-generate.
1103
1104 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1105
1106         * i386-gen.c (operand_type_init): Remove
1107         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1108         OPERAND_TYPE_INOUTPORTREG.
1109         * i386-init.h: Re-generate.
1110
1111 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1112
1113         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1114         (wrssq, wrussq): Add Qword.
1115         * i386-tbl.h: Re-generate.
1116
1117 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1118
1119         * i386-opc.h: Rename OTMax to OTNum.
1120         (OTNumOfUints): Adjust calculation.
1121         (OTUnused): Directly alias to OTNum.
1122
1123 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1124
1125         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1126         `reg_xys'.
1127         (lea_reg_xys): Likewise.
1128         (print_insn_loop_primitive): Rename `reg' local variable to
1129         `reg_dxy'.
1130
1131 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1132
1133         PR binutils/23242
1134         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1135
1136 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1137
1138         PR binutils/23369
1139         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1140         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1141
1142 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1143
1144         PR tdep/8282
1145         * mips-dis.c (mips_option_arg_t): New enumeration.
1146         (mips_options): New variable.
1147         (disassembler_options_mips): New function.
1148         (print_mips_disassembler_options): Reimplement in terms of
1149         `disassembler_options_mips'.
1150         * arm-dis.c (disassembler_options_arm): Adapt to using the
1151         `disasm_options_and_args_t' structure.
1152         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1153         * s390-dis.c (disassembler_options_s390): Likewise.
1154
1155 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1156
1157         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1158         expected result.
1159         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1160         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1161         * testsuite/ld-arm/tls-longplt.d: Likewise.
1162
1163 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1164
1165         PR binutils/23192
1166         * aarch64-asm-2.c: Regenerate.
1167         * aarch64-dis-2.c: Likewise.
1168         * aarch64-opc-2.c: Likewise.
1169         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1170         * aarch64-opc.c (operand_general_constraint_met_p,
1171         aarch64_print_operand): Likewise.
1172         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1173         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1174         fmlal2, fmlsl2.
1175         (AARCH64_OPERANDS): Add Em2.
1176
1177 2018-06-26  Nick Clifton  <nickc@redhat.com>
1178
1179         * po/uk.po: Updated Ukranian translation.
1180         * po/de.po: Updated German translation.
1181         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1182
1183 2018-06-26  Nick Clifton  <nickc@redhat.com>
1184
1185         * nfp-dis.c: Fix spelling mistake.
1186
1187 2018-06-24  Nick Clifton  <nickc@redhat.com>
1188
1189         * configure: Regenerate.
1190         * po/opcodes.pot: Regenerate.
1191
1192 2018-06-24  Nick Clifton  <nickc@redhat.com>
1193
1194         2.31 branch created.
1195
1196 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1197
1198         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1199         * aarch64-asm-2.c: Regenerate.
1200         * aarch64-dis-2.c: Likewise.
1201
1202 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1203
1204         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1205         `-M ginv' option description.
1206
1207 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1208
1209         PR gas/23305
1210         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1211         la and lla.
1212
1213 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1214
1215         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1216         * configure.ac: Remove AC_PREREQ.
1217         * Makefile.in: Re-generate.
1218         * aclocal.m4: Re-generate.
1219         * configure: Re-generate.
1220
1221 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1222
1223         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1224         mips64r6 descriptors.
1225         (parse_mips_ase_option): Handle -Mginv option.
1226         (print_mips_disassembler_options): Document -Mginv.
1227         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1228         (GINV): New macro.
1229         (mips_opcodes): Define ginvi and ginvt.
1230
1231 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1232             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1233
1234         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1235         * mips-opc.c (CRC, CRC64): New macros.
1236         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1237         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1238         crc32cd for CRC64.
1239
1240 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1241
1242         PR 20319
1243         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1244         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1245
1246 2018-06-06  Alan Modra  <amodra@gmail.com>
1247
1248         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1249         setjmp.  Move init for some other vars later too.
1250
1251 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1252
1253         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1254         (dis_private): Add new fields for property section tracking.
1255         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1256         (xtensa_instruction_fits): New functions.
1257         (fetch_data): Bump minimal fetch size to 4.
1258         (print_insn_xtensa): Make struct dis_private static.
1259         Load and prepare property table on section change.
1260         Don't disassemble literals. Don't disassemble instructions that
1261         cross property table boundaries.
1262
1263 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1264
1265         * configure: Regenerated.
1266
1267 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1268
1269         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1270         * i386-tbl.h: Re-generate.
1271
1272 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1273
1274         * i386-opc.tbl (sldt, str): Add NoRex64.
1275         * i386-tbl.h: Re-generate.
1276
1277 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1278
1279         * i386-opc.tbl (invpcid): Add Oword.
1280         * i386-tbl.h: Re-generate.
1281
1282 2018-06-01  Alan Modra  <amodra@gmail.com>
1283
1284         * sysdep.h (_bfd_error_handler): Don't declare.
1285         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1286         * rl78-decode.opc: Likewise.
1287         * msp430-decode.c: Regenerate.
1288         * rl78-decode.c: Regenerate.
1289
1290 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1291
1292         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1293         * i386-init.h : Regenerated.
1294
1295 2018-05-25  Alan Modra  <amodra@gmail.com>
1296
1297         * Makefile.in: Regenerate.
1298         * po/POTFILES.in: Regenerate.
1299
1300 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1301
1302         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1303         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1304         (insert_bab, extract_bab, insert_btab, extract_btab,
1305         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1306         (BAT, BBA VBA RBS XB6S): Delete macros.
1307         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1308         (BB, BD, RBX, XC6): Update for new macros.
1309         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1310         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1311         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1312         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1313
1314 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1315
1316         * Makefile.am: Add support for s12z architecture.
1317         * configure.ac: Likewise.
1318         * disassemble.c: Likewise.
1319         * disassemble.h: Likewise.
1320         * Makefile.in: Regenerate.
1321         * configure: Regenerate.
1322         * s12z-dis.c: New file.
1323         * s12z.h: New file.
1324
1325 2018-05-18  Alan Modra  <amodra@gmail.com>
1326
1327         * nfp-dis.c: Don't #include libbfd.h.
1328         (init_nfp3200_priv): Use bfd_get_section_contents.
1329         (nit_nfp6000_mecsr_sec): Likewise.
1330
1331 2018-05-17  Nick Clifton  <nickc@redhat.com>
1332
1333         * po/zh_CN.po: Updated simplified Chinese translation.
1334
1335 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1336
1337         PR binutils/23109
1338         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1339         * aarch64-dis-2.c: Regenerate.
1340
1341 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1342
1343         PR binutils/21446
1344         * aarch64-asm.c (opintl.h): Include.
1345         (aarch64_ins_sysreg): Enforce read/write constraints.
1346         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1347         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1348         (F_REG_READ, F_REG_WRITE): New.
1349         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1350         AARCH64_OPND_SYSREG.
1351         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1352         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1353         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1354         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1355         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1356         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1357         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1358         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1359         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1360         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1361         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1362         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1363         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1364         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1365         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1366         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1367         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1368
1369 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1370
1371         PR binutils/21446
1372         * aarch64-dis.c (no_notes: New.
1373         (parse_aarch64_dis_option): Support notes.
1374         (aarch64_decode_insn, print_operands): Likewise.
1375         (print_aarch64_disassembler_options): Document notes.
1376         * aarch64-opc.c (aarch64_print_operand): Support notes.
1377
1378 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1379
1380         PR binutils/21446
1381         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1382         and take error struct.
1383         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1384         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1385         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1386         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1387         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1388         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1389         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1390         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1391         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1392         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1393         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1394         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1395         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1396         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1397         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1398         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1399         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1400         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1401         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1402         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1403         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1404         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1405         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1406         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1407         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1408         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1409         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1410         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1411         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1412         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1413         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1414         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1415         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1416         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1417         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1418         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1419         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1420         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1421         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1422         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1423         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1424         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1425         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1426         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1427         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1428         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1429         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1430         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1431         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1432         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1433         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1434         (determine_disassembling_preference, aarch64_decode_insn,
1435         print_insn_aarch64_word, print_insn_data): Take errors struct.
1436         (print_insn_aarch64): Use errors.
1437         * aarch64-asm-2.c: Regenerate.
1438         * aarch64-dis-2.c: Regenerate.
1439         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1440         boolean in aarch64_insert_operan.
1441         (print_operand_extractor): Likewise.
1442         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1443
1444 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1445
1446         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1447
1448 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1449
1450         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1451
1452 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1453
1454         * cr16-opc.c (cr16_instruction): Comment typo fix.
1455         * hppa-dis.c (print_insn_hppa): Likewise.
1456
1457 2018-05-08  Jim Wilson  <jimw@sifive.com>
1458
1459         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1460         (match_c_slli64, match_srxi_as_c_srxi): New.
1461         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1462         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1463         <c.slli, c.srli, c.srai>: Use match_s_slli.
1464         <c.slli64, c.srli64, c.srai64>: New.
1465
1466 2018-05-08  Alan Modra  <amodra@gmail.com>
1467
1468         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1469         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1470         partition opcode space for index lookup.
1471
1472 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1473
1474         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1475         <insn_length>: ...with this.  Update usage.
1476         Remove duplicate call to *info->memory_error_func.
1477
1478 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1479             H.J. Lu  <hongjiu.lu@intel.com>
1480
1481         * i386-dis.c (Gva): New.
1482         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1483         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1484         (prefix_table): New instructions (see prefix above).
1485         (mod_table): New instructions (see prefix above).
1486         (OP_G): Handle va_mode.
1487         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1488         CPU_MOVDIR64B_FLAGS.
1489         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1490         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1491         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1492         * i386-opc.tbl: Add movidir{i,64b}.
1493         * i386-init.h: Regenerated.
1494         * i386-tbl.h: Likewise.
1495
1496 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1497
1498         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1499         AddrPrefixOpReg.
1500         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1501         (AddrPrefixOpReg): This.
1502         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1503         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1504
1505 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1506
1507         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1508         (vle_num_opcodes): Likewise.
1509         (spe2_num_opcodes): Likewise.
1510         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1511         initialization loop.
1512         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1513         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1514         only once.
1515
1516 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1517
1518         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1519
1520 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1521
1522         Makefile.am: Added nfp-dis.c.
1523         configure.ac: Added bfd_nfp_arch.
1524         disassemble.h: Added print_insn_nfp prototype.
1525         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1526         nfp-dis.c: New, for NFP support.
1527         po/POTFILES.in: Added nfp-dis.c to the list.
1528         Makefile.in: Regenerate.
1529         configure: Regenerate.
1530
1531 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1532
1533         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1534         templates into their base ones.
1535         * i386-tlb.h: Re-generate.
1536
1537 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1538
1539         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1540         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1541         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1542         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1543         * i386-init.h: Re-generate.
1544
1545 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1546
1547         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1548         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1549         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1550         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1551         comment.
1552         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1553         and CpuRegMask.
1554         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1555         CpuRegMask: Delete.
1556         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1557         cpuregzmm, and cpuregmask.
1558         * i386-init.h: Re-generate.
1559         * i386-tbl.h: Re-generate.
1560
1561 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1562
1563         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1564         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1565         * i386-init.h: Re-generate.
1566
1567 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1568
1569         * i386-gen.c (VexImmExt): Delete.
1570         * i386-opc.h (VexImmExt, veximmext): Delete.
1571         * i386-opc.tbl: Drop all VexImmExt uses.
1572         * i386-tlb.h: Re-generate.
1573
1574 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1575
1576         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1577         register-only forms.
1578         * i386-tlb.h: Re-generate.
1579
1580 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1581
1582         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1583
1584 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1585
1586         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1587         PREFIX_0F1C.
1588         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1589         (cpu_flags): Add CpuCLDEMOTE.
1590         * i386-init.h: Regenerate.
1591         * i386-opc.h (enum): Add CpuCLDEMOTE,
1592         (i386_cpu_flags): Add cpucldemote.
1593         * i386-opc.tbl: Add cldemote.
1594         * i386-tbl.h: Regenerate.
1595
1596 2018-04-16  Alan Modra  <amodra@gmail.com>
1597
1598         * Makefile.am: Remove sh5 and sh64 support.
1599         * configure.ac: Likewise.
1600         * disassemble.c: Likewise.
1601         * disassemble.h: Likewise.
1602         * sh-dis.c: Likewise.
1603         * sh64-dis.c: Delete.
1604         * sh64-opc.c: Delete.
1605         * sh64-opc.h: Delete.
1606         * Makefile.in: Regenerate.
1607         * configure: Regenerate.
1608         * po/POTFILES.in: Regenerate.
1609
1610 2018-04-16  Alan Modra  <amodra@gmail.com>
1611
1612         * Makefile.am: Remove w65 support.
1613         * configure.ac: Likewise.
1614         * disassemble.c: Likewise.
1615         * disassemble.h: Likewise.
1616         * w65-dis.c: Delete.
1617         * w65-opc.h: Delete.
1618         * Makefile.in: Regenerate.
1619         * configure: Regenerate.
1620         * po/POTFILES.in: Regenerate.
1621
1622 2018-04-16  Alan Modra  <amodra@gmail.com>
1623
1624         * configure.ac: Remove we32k support.
1625         * configure: Regenerate.
1626
1627 2018-04-16  Alan Modra  <amodra@gmail.com>
1628
1629         * Makefile.am: Remove m88k support.
1630         * configure.ac: Likewise.
1631         * disassemble.c: Likewise.
1632         * disassemble.h: Likewise.
1633         * m88k-dis.c: Delete.
1634         * Makefile.in: Regenerate.
1635         * configure: Regenerate.
1636         * po/POTFILES.in: Regenerate.
1637
1638 2018-04-16  Alan Modra  <amodra@gmail.com>
1639
1640         * Makefile.am: Remove i370 support.
1641         * configure.ac: Likewise.
1642         * disassemble.c: Likewise.
1643         * disassemble.h: Likewise.
1644         * i370-dis.c: Delete.
1645         * i370-opc.c: Delete.
1646         * Makefile.in: Regenerate.
1647         * configure: Regenerate.
1648         * po/POTFILES.in: Regenerate.
1649
1650 2018-04-16  Alan Modra  <amodra@gmail.com>
1651
1652         * Makefile.am: Remove h8500 support.
1653         * configure.ac: Likewise.
1654         * disassemble.c: Likewise.
1655         * disassemble.h: Likewise.
1656         * h8500-dis.c: Delete.
1657         * h8500-opc.h: Delete.
1658         * Makefile.in: Regenerate.
1659         * configure: Regenerate.
1660         * po/POTFILES.in: Regenerate.
1661
1662 2018-04-16  Alan Modra  <amodra@gmail.com>
1663
1664         * configure.ac: Remove tahoe support.
1665         * configure: Regenerate.
1666
1667 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1668
1669         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1670         umwait.
1671         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1672         64-bit mode.
1673         * i386-tbl.h: Regenerated.
1674
1675 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1676
1677         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1678         PREFIX_MOD_1_0FAE_REG_6.
1679         (va_mode): New.
1680         (OP_E_register): Use va_mode.
1681         * i386-dis-evex.h (prefix_table):
1682         New instructions (see prefixes above).
1683         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1684         (cpu_flags): Likewise.
1685         * i386-opc.h (enum): Likewise.
1686         (i386_cpu_flags): Likewise.
1687         * i386-opc.tbl: Add umonitor, umwait, tpause.
1688         * i386-init.h: Regenerate.
1689         * i386-tbl.h: Likewise.
1690
1691 2018-04-11  Alan Modra  <amodra@gmail.com>
1692
1693         * opcodes/i860-dis.c: Delete.
1694         * opcodes/i960-dis.c: Delete.
1695         * Makefile.am: Remove i860 and i960 support.
1696         * configure.ac: Likewise.
1697         * disassemble.c: Likewise.
1698         * disassemble.h: Likewise.
1699         * Makefile.in: Regenerate.
1700         * configure: Regenerate.
1701         * po/POTFILES.in: Regenerate.
1702
1703 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1704
1705         PR binutils/23025
1706         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1707         to 0.
1708         (print_insn): Clear vex instead of vex.evex.
1709
1710 2018-04-04  Nick Clifton  <nickc@redhat.com>
1711
1712         * po/es.po: Updated Spanish translation.
1713
1714 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1715
1716         * i386-gen.c (opcode_modifiers): Delete VecESize.
1717         * i386-opc.h (VecESize): Delete.
1718         (struct i386_opcode_modifier): Delete vecesize.
1719         * i386-opc.tbl: Drop VecESize.
1720         * i386-tlb.h: Re-generate.
1721
1722 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1723
1724         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1725         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1726         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1727         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1728         * i386-tlb.h: Re-generate.
1729
1730 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1731
1732         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1733         Fold AVX512 forms
1734         * i386-tlb.h: Re-generate.
1735
1736 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1737
1738         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1739         (vex_len_table): Drop Y for vcvt*2si.
1740         (putop): Replace plain 'Y' handling by abort().
1741
1742 2018-03-28  Nick Clifton  <nickc@redhat.com>
1743
1744         PR 22988
1745         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1746         instructions with only a base address register.
1747         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1748         handle AARHC64_OPND_SVE_ADDR_R.
1749         (aarch64_print_operand): Likewise.
1750         * aarch64-asm-2.c: Regenerate.
1751         * aarch64_dis-2.c: Regenerate.
1752         * aarch64-opc-2.c: Regenerate.
1753
1754 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1755
1756         * i386-opc.tbl: Drop VecESize from register only insn forms and
1757         memory forms not allowing broadcast.
1758         * i386-tlb.h: Re-generate.
1759
1760 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1761
1762         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1763         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1764         sha256*): Drop Disp<N>.
1765
1766 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1767
1768         * i386-dis.c (EbndS, bnd_swap_mode): New.
1769         (prefix_table): Use EbndS.
1770         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1771         * i386-opc.tbl (bndmov): Move misplaced Load.
1772         * i386-tlb.h: Re-generate.
1773
1774 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1775
1776         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1777         templates allowing memory operands and folded ones for register
1778         only flavors.
1779         * i386-tlb.h: Re-generate.
1780
1781 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1782
1783         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1784         256-bit templates. Drop redundant leftover Disp<N>.
1785         * i386-tlb.h: Re-generate.
1786
1787 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1788
1789         * riscv-opc.c (riscv_insn_types): New.
1790
1791 2018-03-13  Nick Clifton  <nickc@redhat.com>
1792
1793         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1794
1795 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1796
1797         * i386-opc.tbl: Add Optimize to clr.
1798         * i386-tbl.h: Regenerated.
1799
1800 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1801
1802         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1803         * i386-opc.h (OldGcc): Removed.
1804         (i386_opcode_modifier): Remove oldgcc.
1805         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1806         instructions for old (<= 2.8.1) versions of gcc.
1807         * i386-tbl.h: Regenerated.
1808
1809 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1810
1811         * i386-opc.h (EVEXDYN): New.
1812         * i386-opc.tbl: Fold various AVX512VL templates.
1813         * i386-tlb.h: Re-generate.
1814
1815 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1816
1817         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1818         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1819         vpexpandd, vpexpandq): Fold AFX512VF templates.
1820         * i386-tlb.h: Re-generate.
1821
1822 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1823
1824         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1825         Fold 128- and 256-bit VEX-encoded templates.
1826         * i386-tlb.h: Re-generate.
1827
1828 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1829
1830         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1831         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1832         vpexpandd, vpexpandq): Fold AVX512F templates.
1833         * i386-tlb.h: Re-generate.
1834
1835 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1836
1837         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1838         64-bit templates. Drop Disp<N>.
1839         * i386-tlb.h: Re-generate.
1840
1841 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1842
1843         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1844         and 256-bit templates.
1845         * i386-tlb.h: Re-generate.
1846
1847 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1848
1849         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1850         * i386-tlb.h: Re-generate.
1851
1852 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1853
1854         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1855         Drop NoAVX.
1856         * i386-tlb.h: Re-generate.
1857
1858 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1859
1860         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1861         * i386-tlb.h: Re-generate.
1862
1863 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1864
1865         * i386-gen.c (opcode_modifiers): Delete FloatD.
1866         * i386-opc.h (FloatD): Delete.
1867         (struct i386_opcode_modifier): Delete floatd.
1868         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1869         FloatD by D.
1870         * i386-tlb.h: Re-generate.
1871
1872 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1873
1874         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1875
1876 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1877
1878         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1879         * i386-tlb.h: Re-generate.
1880
1881 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1882
1883         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1884         forms.
1885         * i386-tlb.h: Re-generate.
1886
1887 2018-03-07  Alan Modra  <amodra@gmail.com>
1888
1889         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1890         bfd_arch_rs6000.
1891         * disassemble.h (print_insn_rs6000): Delete.
1892         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1893         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1894         (print_insn_rs6000): Delete.
1895
1896 2018-03-03  Alan Modra  <amodra@gmail.com>
1897
1898         * sysdep.h (opcodes_error_handler): Define.
1899         (_bfd_error_handler): Declare.
1900         * Makefile.am: Remove stray #.
1901         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1902         EDIT" comment.
1903         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1904         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1905         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1906         opcodes_error_handler to print errors.  Standardize error messages.
1907         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1908         and include opintl.h.
1909         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1910         * i386-gen.c: Standardize error messages.
1911         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1912         * Makefile.in: Regenerate.
1913         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1914         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1915         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1916         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1917         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1918         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1919         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1920         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1921         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1922         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1923         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1924         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1925         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1926
1927 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1928
1929         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1930         vpsub[bwdq] instructions.
1931         * i386-tbl.h: Regenerated.
1932
1933 2018-03-01  Alan Modra  <amodra@gmail.com>
1934
1935         * configure.ac (ALL_LINGUAS): Sort.
1936         * configure: Regenerate.
1937
1938 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1939
1940         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1941         macro by assignements.
1942
1943 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1944
1945         PR gas/22871
1946         * i386-gen.c (opcode_modifiers): Add Optimize.
1947         * i386-opc.h (Optimize): New enum.
1948         (i386_opcode_modifier): Add optimize.
1949         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1950         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1951         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1952         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1953         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1954         vpxord and vpxorq.
1955         * i386-tbl.h: Regenerated.
1956
1957 2018-02-26  Alan Modra  <amodra@gmail.com>
1958
1959         * crx-dis.c (getregliststring): Allocate a large enough buffer
1960         to silence false positive gcc8 warning.
1961
1962 2018-02-22  Shea Levy <shea@shealevy.com>
1963
1964         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1965
1966 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1967
1968         * i386-opc.tbl: Add {rex},
1969         * i386-tbl.h: Regenerated.
1970
1971 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1972
1973         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1974         (mips16_opcodes): Replace `M' with `m' for "restore".
1975
1976 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1977
1978         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1979
1980 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1981
1982         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1983         variable to `function_index'.
1984
1985 2018-02-13  Nick Clifton  <nickc@redhat.com>
1986
1987         PR 22823
1988         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1989         about truncation of printing.
1990
1991 2018-02-12  Henry Wong <henry@stuffedcow.net>
1992
1993         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1994
1995 2018-02-05  Nick Clifton  <nickc@redhat.com>
1996
1997         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1998
1999 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2000
2001         * i386-dis.c (enum): Add pconfig.
2002         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2003         (cpu_flags): Add CpuPCONFIG.
2004         * i386-opc.h (enum): Add CpuPCONFIG.
2005         (i386_cpu_flags): Add cpupconfig.
2006         * i386-opc.tbl: Add PCONFIG instruction.
2007         * i386-init.h: Regenerate.
2008         * i386-tbl.h: Likewise.
2009
2010 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2011
2012         * i386-dis.c (enum): Add PREFIX_0F09.
2013         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2014         (cpu_flags): Add CpuWBNOINVD.
2015         * i386-opc.h (enum): Add CpuWBNOINVD.
2016         (i386_cpu_flags): Add cpuwbnoinvd.
2017         * i386-opc.tbl: Add WBNOINVD instruction.
2018         * i386-init.h: Regenerate.
2019         * i386-tbl.h: Likewise.
2020
2021 2018-01-17  Jim Wilson  <jimw@sifive.com>
2022
2023         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2024
2025 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2026
2027         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2028         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2029         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2030         (cpu_flags): Add CpuIBT, CpuSHSTK.
2031         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2032         (i386_cpu_flags): Add cpuibt, cpushstk.
2033         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2034         * i386-init.h: Regenerate.
2035         * i386-tbl.h: Likewise.
2036
2037 2018-01-16  Nick Clifton  <nickc@redhat.com>
2038
2039         * po/pt_BR.po: Updated Brazilian Portugese translation.
2040         * po/de.po: Updated German translation.
2041
2042 2018-01-15  Jim Wilson  <jimw@sifive.com>
2043
2044         * riscv-opc.c (match_c_nop): New.
2045         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2046
2047 2018-01-15  Nick Clifton  <nickc@redhat.com>
2048
2049         * po/uk.po: Updated Ukranian translation.
2050
2051 2018-01-13  Nick Clifton  <nickc@redhat.com>
2052
2053         * po/opcodes.pot: Regenerated.
2054
2055 2018-01-13  Nick Clifton  <nickc@redhat.com>
2056
2057         * configure: Regenerate.
2058
2059 2018-01-13  Nick Clifton  <nickc@redhat.com>
2060
2061         2.30 branch created.
2062
2063 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2064
2065         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2066         * i386-tbl.h: Regenerate.
2067
2068 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2069
2070         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2071         * i386-tbl.h: Re-generate.
2072
2073 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2074
2075         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2076         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2077         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2078         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2079         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2080         Disp8MemShift of AVX512VL forms.
2081         * i386-tbl.h: Re-generate.
2082
2083 2018-01-09  Jim Wilson  <jimw@sifive.com>
2084
2085         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2086         then the hi_addr value is zero.
2087
2088 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2089
2090         * arm-dis.c (arm_opcodes): Add csdb.
2091         (thumb32_opcodes): Add csdb.
2092
2093 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2094
2095         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2096         * aarch64-asm-2.c: Regenerate.
2097         * aarch64-dis-2.c: Regenerate.
2098         * aarch64-opc-2.c: Regenerate.
2099
2100 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2101
2102         PR gas/22681
2103         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2104         Remove AVX512 vmovd with 64-bit operands.
2105         * i386-tbl.h: Regenerated.
2106
2107 2018-01-05  Jim Wilson  <jimw@sifive.com>
2108
2109         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2110         jalr.
2111
2112 2018-01-03  Alan Modra  <amodra@gmail.com>
2113
2114         Update year range in copyright notice of all files.
2115
2116 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2117
2118         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2119         and OPERAND_TYPE_REGZMM entries.
2120
2121 For older changes see ChangeLog-2017
2122 \f
2123 Copyright (C) 2018 Free Software Foundation, Inc.
2124
2125 Copying and distribution of this file, with or without modification,
2126 are permitted in any medium without royalty provided the copyright
2127 notice and this notice are preserved.
2128
2129 Local Variables:
2130 mode: change-log
2131 left-margin: 8
2132 fill-column: 74
2133 version-control: never
2134 End: