opcodes/ChangeLog

   1 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/20754
   4         * i386-dis.c (REG_82): New.
   5         (X86_64_82_REG_0): Likewise.
   6         (X86_64_82_REG_1): Likewise.
   7         (X86_64_82_REG_2): Likewise.
   8         (X86_64_82_REG_3): Likewise.
   9         (X86_64_82_REG_4): Likewise.
  10         (X86_64_82_REG_5): Likewise.
  11         (X86_64_82_REG_6): Likewise.
  12         (X86_64_82_REG_7): Likewise.
  13         (dis386): Use REG_82.
  14         (reg_table): Add REG_82.
  15         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
  16         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
  17         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
  18
  19 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
  20
  21         * i386-dis.c (REG_82): Renamed to ...
  22         (REG_83): This.
  23         (dis386): Updated.
  24         (reg_table): Likewise.
  25
  26 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  27
  28         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
  29         * i386-dis-evex.h (evex_table): Updated.
  30         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
  31         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  32         (cpu_flags): Add CpuAVX512_4VNNIW.
  33         * i386-opc.h (enum): (AVX512_4VNNIW): New.
  34         (i386_cpu_flags): Add cpuavx512_4vnniw.
  35         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
  36         * i386-init.h: Regenerate.
  37         * i386-tbl.h: Ditto.
  38
  39 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  40
  41         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
  42         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
  43         * i386-dis-evex.h (evex_table): Updated.
  44         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
  45         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  46         (cpu_flags): Add CpuAVX512_4FMAPS.
  47         (opcode_modifiers): Add ImplicitQuadGroup modifier.
  48         * i386-opc.h (AVX512_4FMAP): New.
  49         (i386_cpu_flags): Add cpuavx512_4fmaps.
  50         (ImplicitQuadGroup): New.
  51         (i386_opcode_modifier): Add implicitquadgroup.
  52         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
  53         * i386-init.h: Regenerate.
  54         * i386-tbl.h: Ditto.
  55
  56 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
  57             Andrew Waterman <andrew@sifive.com>
  58
  59         Add support for RISC-V architecture.
  60         * configure.ac: Add entry for bfd_riscv_arch.
  61         * configure: Regenerate.
  62         * disassemble.c (disassembler): Add support for riscv.
  63         (disassembler_usage): Likewise.
  64         * riscv-dis.c: New file.
  65         * riscv-opc.c: New file.
  66
  67 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
  68
  69         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
  70         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
  71         (rm_table): Update the RM_0FAE_REG_7 entry.
  72         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
  73         (cpu_flags): Remove CpuPCOMMIT.
  74         * i386-opc.h (CpuPCOMMIT): Removed.
  75         (i386_cpu_flags): Remove cpupcommit.
  76         * i386-opc.tbl: Remove pcommit.
  77         * i386-init.h: Regenerated.
  78         * i386-tbl.h: Likewise.
  79
  80 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
  81
  82         PR binutis/20705
  83         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
  84         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
  85         32-bit mode.  Don't check vex.register_specifier in 32-bit
  86         mode.
  87         (OP_VEX): Check for invalid mask registers.
  88
  89 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
  90
  91         PR binutis/20699
  92         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
  93         sizeflag.
  94
  95 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
  96
  97         PR binutis/20704
  98         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
  99
 100 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 101
 102         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 103         local variable to `index_regno'.
 104
 105 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 106
 107         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 108
 109 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 110
 111         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 112         usage on ISA basis.
 113
 114 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 115
 116         PR target/20666
 117         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 118
 119 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 120
 121         PR target/20667
 122         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 123         available.
 124
 125 2016-10-07  Alan Modra  <amodra@gmail.com>
 126
 127         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 128
 129 2016-10-06  Alan Modra  <amodra@gmail.com>
 130
 131         * aarch64-opc.c: Spell fall through comments consistently.
 132         * i386-dis.c: Likewise.
 133         * aarch64-dis.c: Add missing fall through comments.
 134         * aarch64-opc.c: Likewise.
 135         * arc-dis.c: Likewise.
 136         * arm-dis.c: Likewise.
 137         * i386-dis.c: Likewise.
 138         * m68k-dis.c: Likewise.
 139         * mep-asm.c: Likewise.
 140         * ns32k-dis.c: Likewise.
 141         * sh-dis.c: Likewise.
 142         * tic4x-dis.c: Likewise.
 143         * tic6x-dis.c: Likewise.
 144         * vax-dis.c: Likewise.
 145
 146 2016-10-06  Alan Modra  <amodra@gmail.com>
 147
 148         * arc-ext.c (create_map): Add missing break.
 149         * msp430-decode.opc (encode_as): Likewise.
 150         * msp430-decode.c: Regenerate.
 151
 152 2016-10-06  Alan Modra  <amodra@gmail.com>
 153
 154         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 155         * crx-dis.c (print_insn_crx): Likewise.
 156
 157 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 158
 159         PR binutils/20657
 160         * i386-dis.c (putop): Don't assign alt twice.
 161
 162 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 163
 164         PR target/20553
 165         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 166
 167 2016-09-29  Alan Modra  <amodra@gmail.com>
 168
 169         * ppc-opc.c (L): Make compulsory.
 170         (LOPT): New, optional form of L.
 171         (HTM_R): Define as LOPT.
 172         (L0, L1): Delete.
 173         (L32OPT): New, optional for 32-bit L.
 174         (L2OPT): New, 2-bit L for dcbf.
 175         (SVC_LEC): Update.
 176         (L2): Define.
 177         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 178         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 179         <dcbf>: Use L2OPT.
 180         <tlbiel, tlbie>: Use LOPT.
 181         <wclr, wclrall>: Use L2.
 182
 183 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 184
 185         * Makefile.in: Regenerate.
 186         * configure: Likewise.
 187
 188 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 189
 190         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 191         (EXTINSN2OP): Use EXTINSN2OPF.
 192         (bspeekm, bspop, modapp): New extension instructions.
 193         * arc-opc.c (F_DNZ_ND): Define.
 194         (F_DNZ_D): Likewise.
 195         (F_SIZEB1): Changed.
 196         (C_DNZ_D): Define.
 197         (C_HARD): Changed.
 198         * arc-tbl.h (dbnz): New instruction.
 199         (prealloc): Allow it for ARC EM.
 200         (xbfu): Likewise.
 201
 202 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 203
 204         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 205         after commas in addresses.
 206         (aarch64_print_operand): Likewise.
 207
 208 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 209
 210         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 211         rather than "should be" or "expected to be" in error messages.
 212
 213 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 214
 215         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 216         (print_mnemonic_name): ...here.
 217         (print_comment): New function.
 218         (print_aarch64_insn): Call it.
 219         * aarch64-opc.c (aarch64_conds): Add SVE names.
 220         (aarch64_print_operand): Print alternative condition names in
 221         a comment.
 222
 223 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 224
 225         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 226         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 227         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 228         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 229         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 230         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 231         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 232         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 233         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 234         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 235         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 236         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 237         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 238         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 239         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 240         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 241         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 242         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 243         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 244         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 245         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 246         (aarch64_feature_sve): New variable.
 247         (SVE): New macro.
 248         (_SVE_INSN): Likewise.
 249         (aarch64_opcode_table): Add SVE instructions.
 250         * aarch64-opc.h (extract_fields): Declare.
 251         * aarch64-opc-2.c: Regenerate.
 252         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 253         * aarch64-asm-2.c: Regenerate.
 254         * aarch64-dis.c (extract_fields): Make global.
 255         (do_misc_decoding): Handle the new SVE aarch64_ops.
 256         * aarch64-dis-2.c: Regenerate.
 257
 258 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 259
 260         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 261         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 262         aarch64_field_kinds.
 263         * aarch64-opc.c (fields): Add corresponding entries.
 264         * aarch64-asm.c (aarch64_get_variant): New function.
 265         (aarch64_encode_variant_using_iclass): Likewise.
 266         (aarch64_opcode_encode): Call it.
 267         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 268         (aarch64_opcode_decode): Call it.
 269
 270 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 271
 272         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 273         and FP register operands.
 274         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 275         (FLD_SVE_Vn): New aarch64_field_kinds.
 276         * aarch64-opc.c (fields): Add corresponding entries.
 277         (aarch64_print_operand): Handle the new SVE core and FP register
 278         operands.
 279         * aarch64-opc-2.c: Regenerate.
 280         * aarch64-asm-2.c: Likewise.
 281         * aarch64-dis-2.c: Likewise.
 282
 283 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 284
 285         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 286         immediate operands.
 287         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 288         * aarch64-opc.c (fields): Add corresponding entry.
 289         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 290         operands.
 291         (aarch64_print_operand): Likewise.
 292         * aarch64-opc-2.c: Regenerate.
 293         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 294         (ins_sve_float_zero_one): New inserters.
 295         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 296         (aarch64_ins_sve_float_half_two): Likewise.
 297         (aarch64_ins_sve_float_zero_one): Likewise.
 298         * aarch64-asm-2.c: Regenerate.
 299         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 300         (ext_sve_float_zero_one): New extractors.
 301         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 302         (aarch64_ext_sve_float_half_two): Likewise.
 303         (aarch64_ext_sve_float_zero_one): Likewise.
 304         * aarch64-dis-2.c: Regenerate.
 305
 306 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 307
 308         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 309         integer immediate operands.
 310         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 311         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 312         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 313         * aarch64-opc.c (fields): Add corresponding entries.
 314         (operand_general_constraint_met_p): Handle the new SVE integer
 315         immediate operands.
 316         (aarch64_print_operand): Likewise.
 317         (aarch64_sve_dupm_mov_immediate_p): New function.
 318         * aarch64-opc-2.c: Regenerate.
 319         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 320         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 321         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 322         (aarch64_ins_limm): ...here.
 323         (aarch64_ins_inv_limm): New function.
 324         (aarch64_ins_sve_aimm): Likewise.
 325         (aarch64_ins_sve_asimm): Likewise.
 326         (aarch64_ins_sve_limm_mov): Likewise.
 327         (aarch64_ins_sve_shlimm): Likewise.
 328         (aarch64_ins_sve_shrimm): Likewise.
 329         * aarch64-asm-2.c: Regenerate.
 330         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 331         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 332         * aarch64-dis.c (decode_limm): New function, split out from...
 333         (aarch64_ext_limm): ...here.
 334         (aarch64_ext_inv_limm): New function.
 335         (decode_sve_aimm): Likewise.
 336         (aarch64_ext_sve_aimm): Likewise.
 337         (aarch64_ext_sve_asimm): Likewise.
 338         (aarch64_ext_sve_limm_mov): Likewise.
 339         (aarch64_top_bit): Likewise.
 340         (aarch64_ext_sve_shlimm): Likewise.
 341         (aarch64_ext_sve_shrimm): Likewise.
 342         * aarch64-dis-2.c: Regenerate.
 343
 344 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 345
 346         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 347         operands.
 348         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 349         the AARCH64_MOD_MUL_VL entry.
 350         (value_aligned_p): Cope with non-power-of-two alignments.
 351         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 352         (print_immediate_offset_address): Likewise.
 353         (aarch64_print_operand): Likewise.
 354         * aarch64-opc-2.c: Regenerate.
 355         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 356         (ins_sve_addr_ri_s9xvl): New inserters.
 357         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 358         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 359         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 360         * aarch64-asm-2.c: Regenerate.
 361         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 362         (ext_sve_addr_ri_s9xvl): New extractors.
 363         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 364         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 365         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 366         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 367         * aarch64-dis-2.c: Regenerate.
 368
 369 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 370
 371         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 372         address operands.
 373         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 374         (FLD_SVE_xs_22): New aarch64_field_kinds.
 375         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 376         (get_operand_specific_data): New function.
 377         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 378         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 379         (operand_general_constraint_met_p): Handle the new SVE address
 380         operands.
 381         (sve_reg): New array.
 382         (get_addr_sve_reg_name): New function.
 383         (aarch64_print_operand): Handle the new SVE address operands.
 384         * aarch64-opc-2.c: Regenerate.
 385         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 386         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 387         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 388         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 389         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 390         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 391         (aarch64_ins_sve_addr_zi_u5): Likewise.
 392         (aarch64_ins_sve_addr_zz): Likewise.
 393         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 394         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 395         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 396         * aarch64-asm-2.c: Regenerate.
 397         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 398         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 399         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 400         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 401         (aarch64_ext_sve_addr_ri_u6): Likewise.
 402         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 403         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 404         (aarch64_ext_sve_addr_zi_u5): Likewise.
 405         (aarch64_ext_sve_addr_zz): Likewise.
 406         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 407         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 408         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 409         * aarch64-dis-2.c: Regenerate.
 410
 411 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 412
 413         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 414         AARCH64_OPND_SVE_PATTERN_SCALED.
 415         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 416         * aarch64-opc.c (fields): Add a corresponding entry.
 417         (set_multiplier_out_of_range_error): New function.
 418         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 419         (operand_general_constraint_met_p): Handle
 420         AARCH64_OPND_SVE_PATTERN_SCALED.
 421         (print_register_offset_address): Use PRIi64 to print the
 422         shift amount.
 423         (aarch64_print_operand): Likewise.  Handle
 424         AARCH64_OPND_SVE_PATTERN_SCALED.
 425         * aarch64-opc-2.c: Regenerate.
 426         * aarch64-asm.h (ins_sve_scale): New inserter.
 427         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 428         * aarch64-asm-2.c: Regenerate.
 429         * aarch64-dis.h (ext_sve_scale): New inserter.
 430         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 431         * aarch64-dis-2.c: Regenerate.
 432
 433 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 434
 435         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 436         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 437         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 438         (FLD_SVE_prfop): Likewise.
 439         * aarch64-opc.c: Include libiberty.h.
 440         (aarch64_sve_pattern_array): New variable.
 441         (aarch64_sve_prfop_array): Likewise.
 442         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 443         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 444         AARCH64_OPND_SVE_PRFOP.
 445         * aarch64-asm-2.c: Regenerate.
 446         * aarch64-dis-2.c: Likewise.
 447         * aarch64-opc-2.c: Likewise.
 448
 449 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 450
 451         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 452         AARCH64_OPND_QLF_P_[ZM].
 453         (aarch64_print_operand): Print /z and /m where appropriate.
 454
 455 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 456
 457         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 458         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 459         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 460         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 461         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 462         * aarch64-opc.c (fields): Add corresponding entries here.
 463         (operand_general_constraint_met_p): Check that SVE register lists
 464         have the correct length.  Check the ranges of SVE index registers.
 465         Check for cases where p8-p15 are used in 3-bit predicate fields.
 466         (aarch64_print_operand): Handle the new SVE operands.
 467         * aarch64-opc-2.c: Regenerate.
 468         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 469         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 470         (aarch64_ins_sve_reglist): Likewise.
 471         * aarch64-asm-2.c: Regenerate.
 472         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 473         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 474         (aarch64_ext_sve_reglist): Likewise.
 475         * aarch64-dis-2.c: Regenerate.
 476
 477 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 478
 479         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 480         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 481         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 482         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 483         tied operands.
 484
 485 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 486
 487         * aarch64-opc.c (get_offset_int_reg_name): New function.
 488         (print_immediate_offset_address): Likewise.
 489         (print_register_offset_address): Take the base and offset
 490         registers as parameters.
 491         (aarch64_print_operand): Update caller accordingly.  Use
 492         print_immediate_offset_address.
 493
 494 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 495
 496         * aarch64-opc.c (BANK): New macro.
 497         (R32, R64): Take a register number as argument
 498         (int_reg): Use BANK.
 499
 500 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 501
 502         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 503         (aarch64_print_operand): Update accordingly.
 504
 505 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 506
 507         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 508         for FPIMM.
 509         * aarch64-asm.h (ins_fpimm): New inserter.
 510         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 511         * aarch64-asm-2.c: Regenerate.
 512         * aarch64-dis.h (ext_fpimm): New extractor.
 513         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 514         (aarch64_ext_fpimm): New function.
 515         * aarch64-dis-2.c: Regenerate.
 516
 517 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 518
 519         * aarch64-asm.c: Include libiberty.h.
 520         (insert_fields): New function.
 521         (aarch64_ins_imm): Use it.
 522         * aarch64-dis.c (extract_fields): New function.
 523         (aarch64_ext_imm): Use it.
 524
 525 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 526
 527         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 528         with an esize parameter.
 529         (operand_general_constraint_met_p): Update accordingly.
 530         Fix misindented code.
 531         * aarch64-asm.c (aarch64_ins_limm): Update call to
 532         aarch64_logical_immediate_p.
 533
 534 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 535
 536         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 537
 538 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 539
 540         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 541
 542 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 543
 544         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 545
 546 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 547
 548         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 549         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 550         xor3>: Delete mnemonics.
 551         <cp_abort>: Rename mnemonic from ...
 552         <cpabort>: ...to this.
 553         <setb>: Change to a X form instruction.
 554         <sync>: Change to 1 operand form.
 555         <copy>: Delete mnemonic.
 556         <copy_first>: Rename mnemonic from ...
 557         <copy>: ...to this.
 558         <paste, paste.>: Delete mnemonics.
 559         <paste_last>: Rename mnemonic from ...
 560         <paste.>: ...to this.
 561
 562 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 563
 564         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 565
 566 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 567
 568         * s390-mkopc.c (main): Support alternate arch strings.
 569
 570 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 571
 572         * s390-opc.txt: Fix kmctr instruction type.
 573
 574 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 575
 576         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 577         * i386-init.h: Regenerated.
 578
 579 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 580
 581         * opcodes/arc-dis.c (print_insn_arc): Changed.
 582
 583 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 584
 585         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 586         camellia_fl.
 587
 588 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 589
 590         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 591         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 592         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 593
 594 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 597         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 598         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 599         PREFIX_MOD_3_0FAE_REG_4.
 600         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 601         PREFIX_MOD_3_0FAE_REG_4.
 602         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 603         (cpu_flags): Add CpuPTWRITE.
 604         * i386-opc.h (CpuPTWRITE): New.
 605         (i386_cpu_flags): Add cpuptwrite.
 606         * i386-opc.tbl: Add ptwrite instruction.
 607         * i386-init.h: Regenerated.
 608         * i386-tbl.h: Likewise.
 609
 610 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 611
 612         * arc-dis.h: Wrap around in extern "C".
 613
 614 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 615
 616         * aarch64-tbl.h (V8_2_INSN): New macro.
 617         (aarch64_opcode_table): Use it.
 618
 619 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 620
 621         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 622         CORE_INSN, __FP_INSN and SIMD_INSN.
 623
 624 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 625
 626         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 627         (aarch64_opcode_table): Update uses accordingly.
 628
 629 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 630         Kwok Cheung Yeung  <kcy@codesourcery.com>
 631
 632         opcodes/
 633         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 634         'e_cmplwi' to 'e_cmpli' instead.
 635         (OPVUPRT, OPVUPRT_MASK): Define.
 636         (powerpc_opcodes): Add E200Z4 insns.
 637         (vle_opcodes): Add context save/restore insns.
 638
 639 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 640
 641         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 642         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 643         "j".
 644
 645 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 646
 647         * arc-nps400-tbl.h: Change block comments to GNU format.
 648         * arc-dis.c: Add new globals addrtypenames,
 649         addrtypenames_max, and addtypeunknown.
 650         (get_addrtype): New function.
 651         (print_insn_arc): Print colons and address types when
 652         required.
 653         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 654         define insert and extract functions for all address types.
 655         (arc_operands): Add operands for colon and all address
 656         types.
 657         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 658         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 659         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 660         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 661         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 662         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 663
 664 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 665
 666         * configure: Regenerated.
 667
 668 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 669
 670         * arc-dis.c (skipclass): New structure.
 671         (decodelist): New variable.
 672         (is_compatible_p): New function.
 673         (new_element): Likewise.
 674         (skip_class_p): Likewise.
 675         (find_format_from_table): Use skip_class_p function.
 676         (find_format): Decode first the extension instructions.
 677         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 678         e_flags.
 679         (parse_option): New function.
 680         (parse_disassembler_options): Likewise.
 681         (print_arc_disassembler_options): Likewise.
 682         (print_insn_arc): Use parse_disassembler_options function.  Proper
 683         select ARCv2 cpu variant.
 684         * disassemble.c (disassembler_usage): Add ARC disassembler
 685         options.
 686
 687 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 688
 689         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 690         annotation from the "nal" entry and reorder it beyond "bltzal".
 691
 692 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 693
 694         * sparc-opc.c (ldtxa): New macro.
 695         (sparc_opcodes): Use the macro defined above to add entries for
 696         the LDTXA instructions.
 697         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 698         instruction.
 699
 700 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 701
 702         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 703         and "jmpc".
 704
 705 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 708         (movzb): Adjust to cover all permitted suffixes.
 709         (movzw): New.
 710         * i386-tbl.h: Re-generate.
 711
 712 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 715         (lgdt): Remove Tbyte from non-64-bit variant.
 716         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 717         xsaves64, xsavec64): Remove Disp16.
 718         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 719         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 720         64-bit variants.
 721         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 722         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 723         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 724         64-bit variants.
 725         * i386-tbl.h: Re-generate.
 726
 727 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 728
 729         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 730         * i386-tbl.h: Re-generate.
 731
 732 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 733
 734         * arm-dis.c (print_insn): Fix typo in comment.
 735
 736 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 737
 738         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 739         range of ldst_elemlist operands.
 740         (print_register_list): Use PRIi64 to print the index.
 741         (aarch64_print_operand): Likewise.
 742
 743 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 744
 745         * mcore-opc.h: Remove sentinal.
 746         * mcore-dis.c (print_insn_mcore): Adjust.
 747
 748 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 749
 750         * arc-opc.c: Correct description of availability of NPS400
 751         features.
 752
 753 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 754
 755         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 756         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 757         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 758         xor3>: New mnemonics.
 759         <setb>: Change to a VX form instruction.
 760         (insert_sh6): Add support for rldixor.
 761         (extract_sh6): Likewise.
 762
 763 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 764
 765         * arc-ext.h: Wrap in extern C.
 766
 767 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 768
 769         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 770         Use same method for determining instruction length on ARC700 and
 771         NPS-400.
 772         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 773         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 774         with the NPS400 subclass.
 775         * arc-opc.c: Likewise.
 776
 777 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 778
 779         * sparc-opc.c (rdasr): New macro.
 780         (wrasr): Likewise.
 781         (rdpr): Likewise.
 782         (wrpr): Likewise.
 783         (rdhpr): Likewise.
 784         (wrhpr): Likewise.
 785         (sparc_opcodes): Use the macros above to fix and expand the
 786         definition of read/write instructions from/to
 787         asr/privileged/hyperprivileged instructions.
 788         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 789         %hva_mask_nz.  Prefer softint_set and softint_clear over
 790         set_softint and clear_softint.
 791         (print_insn_sparc): Support %ver in Rd.
 792
 793 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 794
 795         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 796         architecture according to the hardware capabilities they require.
 797
 798 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 799
 800         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 801         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 802         bfd_mach_sparc_v9{c,d,e,v,m}.
 803         * sparc-opc.c (MASK_V9C): Define.
 804         (MASK_V9D): Likewise.
 805         (MASK_V9E): Likewise.
 806         (MASK_V9V): Likewise.
 807         (MASK_V9M): Likewise.
 808         (v6): Add MASK_V9{C,D,E,V,M}.
 809         (v6notlet): Likewise.
 810         (v7): Likewise.
 811         (v8): Likewise.
 812         (v9): Likewise.
 813         (v9andleon): Likewise.
 814         (v9a): Likewise.
 815         (v9b): Likewise.
 816         (v9c): Define.
 817         (v9d): Likewise.
 818         (v9e): Likewise.
 819         (v9v): Likewise.
 820         (v9m): Likewise.
 821         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 822
 823 2016-06-15  Nick Clifton  <nickc@redhat.com>
 824
 825         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 826         constants to match expected behaviour.
 827         (nds32_parse_opcode): Likewise.  Also for whitespace.
 828
 829 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 830
 831         * arc-opc.c (extract_rhv1): Extract value from insn.
 832
 833 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 834
 835         * arc-nps400-tbl.h: Add ldbit instruction.
 836         * arc-opc.c: Add flag classes required for ldbit.
 837
 838 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 839
 840         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 841         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 842         support the above instructions.
 843
 844 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 845
 846         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 847         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 848         csma, cbba, zncv, and hofs.
 849         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 850         support the above instructions.
 851
 852 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 853
 854         * arc-nps400-tbl.h: Add andab and orab instructions.
 855
 856 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 857
 858         * arc-nps400-tbl.h: Add addl-like instructions.
 859
 860 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 861
 862         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 863
 864 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 865
 866         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 867         instructions.
 868
 869 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 870
 871         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 872         variable.
 873         (init_disasm): Handle new command line option "insnlength".
 874         (print_s390_disassembler_options): Mention new option in help
 875         output.
 876         (print_insn_s390): Use the encoded insn length when dumping
 877         unknown instructions.
 878
 879 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 880
 881         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 882          to the address and set as symbol address for LDS/ STS immediate operands.
 883
 884 2016-06-07  Alan Modra  <amodra@gmail.com>
 885
 886         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 887         cpu for "vle" to e500.
 888         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 889         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 890         (PPCNONE): Delete, substitute throughout.
 891         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 892         except for major opcode 4 and 31.
 893         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 894
 895 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 896
 897         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 898         ARM_EXT_RAS in relevant entries.
 899
 900 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 901
 902         PR binutils/20196
 903         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 904         opcodes for E6500.
 905
 906 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 907
 908         PR binutis/18386
 909         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 910         (indir_v_mode): New.
 911         Add comments for '&'.
 912         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 913         (putop): Handle '&'.
 914         (intel_operand_size): Handle indir_v_mode.
 915         (OP_E_register): Likewise.
 916         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 917         64-bit indirect call/jmp for AMD64.
 918         * i386-tbl.h: Regenerated
 919
 920 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 921
 922         * arc-dis.c (struct arc_operand_iterator): New structure.
 923         (find_format_from_table): All the old content from find_format,
 924         with some minor adjustments, and parameter renaming.
 925         (find_format_long_instructions): New function.
 926         (find_format): Rewritten.
 927         (arc_insn_length): Add LSB parameter.
 928         (extract_operand_value): New function.
 929         (operand_iterator_next): New function.
 930         (print_insn_arc): Use new functions to find opcode, and iterator
 931         over operands.
 932         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 933         (extract_nps_3bit_dst_short): New function.
 934         (insert_nps_3bit_src2_short): New function.
 935         (extract_nps_3bit_src2_short): New function.
 936         (insert_nps_bitop1_size): New function.
 937         (extract_nps_bitop1_size): New function.
 938         (insert_nps_bitop2_size): New function.
 939         (extract_nps_bitop2_size): New function.
 940         (insert_nps_bitop_mod4_msb): New function.
 941         (extract_nps_bitop_mod4_msb): New function.
 942         (insert_nps_bitop_mod4_lsb): New function.
 943         (extract_nps_bitop_mod4_lsb): New function.
 944         (insert_nps_bitop_dst_pos3_pos4): New function.
 945         (extract_nps_bitop_dst_pos3_pos4): New function.
 946         (insert_nps_bitop_ins_ext): New function.
 947         (extract_nps_bitop_ins_ext): New function.
 948         (arc_operands): Add new operands.
 949         (arc_long_opcodes): New global array.
 950         (arc_num_long_opcodes): New global.
 951         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 952
 953 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 954
 955         * nds32-asm.h: Add extern "C".
 956         * sh-opc.h: Likewise.
 957
 958 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 959
 960         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 961         0,b,limm to the rflt instruction.
 962
 963 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 964
 965         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 966         constant.
 967
 968 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 969
 970         PR gas/20145
 971         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 972         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 973         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 974         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 975         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 976         * i386-init.h: Regenerated.
 977
 978 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 979
 980         PR gas/20145
 981         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 982         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 983         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 984         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 985         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 986         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 987         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 988         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 989         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 990         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 991         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 992         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 993         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 994         CpuRegMask for AVX512.
 995         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 996         and CpuRegMask.
 997         (set_bitfield_from_cpu_flag_init): New function.
 998         (set_bitfield): Remove const on f.  Call
 999         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1000         * i386-opc.h (CpuRegMMX): New.
1001         (CpuRegXMM): Likewise.
1002         (CpuRegYMM): Likewise.
1003         (CpuRegZMM): Likewise.
1004         (CpuRegMask): Likewise.
1005         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1006         and cpuregmask.
1007         * i386-init.h: Regenerated.
1008         * i386-tbl.h: Likewise.
1009
1010 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1011
1012         PR gas/20154
1013         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1014         (opcode_modifiers): Add AMD64 and Intel64.
1015         (main): Properly verify CpuMax.
1016         * i386-opc.h (CpuAMD64): Removed.
1017         (CpuIntel64): Likewise.
1018         (CpuMax): Set to CpuNo64.
1019         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1020         (AMD64): New.
1021         (Intel64): Likewise.
1022         (i386_opcode_modifier): Add amd64 and intel64.
1023         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1024         on call and jmp.
1025         * i386-init.h: Regenerated.
1026         * i386-tbl.h: Likewise.
1027
1028 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1029
1030         PR gas/20154
1031         * i386-gen.c (main): Fail if CpuMax is incorrect.
1032         * i386-opc.h (CpuMax): Set to CpuIntel64.
1033         * i386-tbl.h: Regenerated.
1034
1035 2016-05-27  Nick Clifton  <nickc@redhat.com>
1036
1037         PR target/20150
1038         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1039         (msp430dis_opcode_unsigned): New function.
1040         (msp430dis_opcode_signed): New function.
1041         (msp430_singleoperand): Use the new opcode reading functions.
1042         Only disassenmble bytes if they were successfully read.
1043         (msp430_doubleoperand): Likewise.
1044         (msp430_branchinstr): Likewise.
1045         (msp430x_callx_instr): Likewise.
1046         (print_insn_msp430): Check that it is safe to read bytes before
1047         attempting disassembly.  Use the new opcode reading functions.
1048
1049 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1050
1051         * ppc-opc.c (CY): New define.  Document it.
1052         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1053
1054 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1055
1056         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1057         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1058         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1059         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1060         CPU_ANY_AVX_FLAGS.
1061         * i386-init.h: Regenerated.
1062
1063 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1064
1065         PR gas/20141
1066         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1067         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1068         * i386-init.h: Regenerated.
1069
1070 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1071
1072         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1073         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1074         * i386-init.h: Regenerated.
1075
1076 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1077
1078         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1079         information.
1080         (print_insn_arc): Set insn_type information.
1081         * arc-opc.c (C_CC): Add F_CLASS_COND.
1082         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1083         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1084         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1085         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1086         (brne, brne_s, jeq_s, jne_s): Likewise.
1087
1088 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1089
1090         * arc-tbl.h (neg): New instruction variant.
1091
1092 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1093
1094         * arc-dis.c (find_format, find_format, get_auxreg)
1095         (print_insn_arc): Changed.
1096         * arc-ext.h (INSERT_XOP): Likewise.
1097
1098 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1099
1100         * tic54x-dis.c (sprint_mmr): Adjust.
1101         * tic54x-opc.c: Likewise.
1102
1103 2016-05-19  Alan Modra  <amodra@gmail.com>
1104
1105         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1106
1107 2016-05-19  Alan Modra  <amodra@gmail.com>
1108
1109         * ppc-opc.c: Formatting.
1110         (NSISIGNOPT): Define.
1111         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1112
1113 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1114
1115         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1116         replacing references to `micromips_ase' throughout.
1117         (_print_insn_mips): Don't use file-level microMIPS annotation to
1118         determine the disassembly mode with the symbol table.
1119
1120 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1121
1122         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1123
1124 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1125
1126         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1127         mips64r6.
1128         * mips-opc.c (D34): New macro.
1129         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1130
1131 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1132
1133         * i386-dis.c (prefix_table): Add RDPID instruction.
1134         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1135         (cpu_flags): Add RDPID bitfield.
1136         * i386-opc.h (enum): Add RDPID element.
1137         (i386_cpu_flags): Add RDPID field.
1138         * i386-opc.tbl: Add RDPID instruction.
1139         * i386-init.h: Regenerate.
1140         * i386-tbl.h: Regenerate.
1141
1142 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1143
1144         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1145         branch type of a symbol.
1146         (print_insn): Likewise.
1147
1148 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1149
1150         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1151         Mainline Security Extensions instructions.
1152         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1153         Extensions instructions.
1154         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1155         instructions.
1156         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1157         special registers.
1158
1159 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1160
1161         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1162
1163 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1164
1165         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1166         (arcExtMap_genOpcode): Likewise.
1167         * arc-opc.c (arg_32bit_rc): Define new variable.
1168         (arg_32bit_u6): Likewise.
1169         (arg_32bit_limm): Likewise.
1170
1171 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1172
1173         * aarch64-gen.c (VERIFIER): Define.
1174         * aarch64-opc.c (VERIFIER): Define.
1175         (verify_ldpsw): Use static linkage.
1176         * aarch64-opc.h (verify_ldpsw): Remove.
1177         * aarch64-tbl.h: Use VERIFIER for verifiers.
1178
1179 2016-04-28  Nick Clifton  <nickc@redhat.com>
1180
1181         PR target/19722
1182         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1183         * aarch64-opc.c (verify_ldpsw): New function.
1184         * aarch64-opc.h (verify_ldpsw): New prototype.
1185         * aarch64-tbl.h: Add initialiser for verifier field.
1186         (LDPSW): Set verifier to verify_ldpsw.
1187
1188 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1189
1190         PR binutils/19983
1191         PR binutils/19984
1192         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1193         smaller than address size.
1194
1195 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1196
1197         * alpha-dis.c: Regenerate.
1198         * crx-dis.c: Likewise.
1199         * disassemble.c: Likewise.
1200         * epiphany-opc.c: Likewise.
1201         * fr30-opc.c: Likewise.
1202         * frv-opc.c: Likewise.
1203         * ip2k-opc.c: Likewise.
1204         * iq2000-opc.c: Likewise.
1205         * lm32-opc.c: Likewise.
1206         * lm32-opinst.c: Likewise.
1207         * m32c-opc.c: Likewise.
1208         * m32r-opc.c: Likewise.
1209         * m32r-opinst.c: Likewise.
1210         * mep-opc.c: Likewise.
1211         * mt-opc.c: Likewise.
1212         * or1k-opc.c: Likewise.
1213         * or1k-opinst.c: Likewise.
1214         * tic80-opc.c: Likewise.
1215         * xc16x-opc.c: Likewise.
1216         * xstormy16-opc.c: Likewise.
1217
1218 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1219
1220         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1221         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1222         calcsd, and calcxd instructions.
1223         * arc-opc.c (insert_nps_bitop_size): Delete.
1224         (extract_nps_bitop_size): Delete.
1225         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1226         (extract_nps_qcmp_m3): Define.
1227         (extract_nps_qcmp_m2): Define.
1228         (extract_nps_qcmp_m1): Define.
1229         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1230         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1231         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1232         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1233         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1234         NPS_QCMP_M3.
1235
1236 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1237
1238         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1239
1240 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1241
1242         * Makefile.in: Regenerated with automake 1.11.6.
1243         * aclocal.m4: Likewise.
1244
1245 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1246
1247         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1248         instructions.
1249         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1250         (extract_nps_cmem_uimm16): New function.
1251         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1252
1253 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1254
1255         * arc-dis.c (arc_insn_length): New function.
1256         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1257         (find_format): Change insnLen parameter to unsigned.
1258
1259 2016-04-13  Nick Clifton  <nickc@redhat.com>
1260
1261         PR target/19937
1262         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1263         the LD.B and LD.BU instructions.
1264
1265 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1266
1267         * arc-dis.c (find_format): Check for extension flags.
1268         (print_flags): New function.
1269         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1270         .extAuxRegister.
1271         * arc-ext.c (arcExtMap_coreRegName): Use
1272         LAST_EXTENSION_CORE_REGISTER.
1273         (arcExtMap_coreReadWrite): Likewise.
1274         (dump_ARC_extmap): Update printing.
1275         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1276         (arc_aux_regs): Add cpu field.
1277         * arc-regs.h: Add cpu field, lower case name aux registers.
1278
1279 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1280
1281         * arc-tbl.h: Add rtsc, sleep with no arguments.
1282
1283 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1284
1285         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1286         Initialize.
1287         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1288         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1289         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1290         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1291         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1292         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1293         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1294         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1295         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1296         (arc_opcode arc_opcodes): Null terminate the array.
1297         (arc_num_opcodes): Remove.
1298         * arc-ext.h (INSERT_XOP): Define.
1299         (extInstruction_t): Likewise.
1300         (arcExtMap_instName): Delete.
1301         (arcExtMap_insn): New function.
1302         (arcExtMap_genOpcode): Likewise.
1303         * arc-ext.c (ExtInstruction): Remove.
1304         (create_map): Zero initialize instruction fields.
1305         (arcExtMap_instName): Remove.
1306         (arcExtMap_insn): New function.
1307         (dump_ARC_extmap): More info while debuging.
1308         (arcExtMap_genOpcode): New function.
1309         * arc-dis.c (find_format): New function.
1310         (print_insn_arc): Use find_format.
1311         (arc_get_disassembler): Enable dump_ARC_extmap only when
1312         debugging.
1313
1314 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1315
1316         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1317         instruction bits out.
1318
1319 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1320
1321         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1322         * arc-opc.c (arc_flag_operands): Add new flags.
1323         (arc_flag_classes): Add new classes.
1324
1325 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1326
1327         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1328
1329 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1330
1331         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1332         encode1, rflt, crc16, and crc32 instructions.
1333         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1334         (arc_flag_classes): Add C_NPS_R.
1335         (insert_nps_bitop_size_2b): New function.
1336         (extract_nps_bitop_size_2b): Likewise.
1337         (insert_nps_bitop_uimm8): Likewise.
1338         (extract_nps_bitop_uimm8): Likewise.
1339         (arc_operands): Add new operand entries.
1340
1341 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1342
1343         * arc-regs.h: Add a new subclass field.  Add double assist
1344         accumulator register values.
1345         * arc-tbl.h: Use DPA subclass to mark the double assist
1346         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1347         * arc-opc.c (RSP): Define instead of SP.
1348         (arc_aux_regs): Add the subclass field.
1349
1350 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1351
1352         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1353
1354 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1355
1356         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1357         NPS_R_SRC1.
1358
1359 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1360
1361         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1362         issues.  No functional changes.
1363
1364 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1365
1366         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1367         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1368         (RTT): Remove duplicate.
1369         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1370         (PCT_CONFIG*): Remove.
1371         (D1L, D1H, D2H, D2L): Define.
1372
1373 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1374
1375         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1376
1377 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1378
1379         * arc-tbl.h (invld07): Remove.
1380         * arc-ext-tbl.h: New file.
1381         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1382         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1383
1384 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1385
1386         Fix -Wstack-usage warnings.
1387         * aarch64-dis.c (print_operands): Substitute size.
1388         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1389
1390 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1391
1392         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1393         to get a proper diagnostic when an invalid ASR register is used.
1394
1395 2016-03-22  Nick Clifton  <nickc@redhat.com>
1396
1397         * configure: Regenerate.
1398
1399 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1400
1401         * arc-nps400-tbl.h: New file.
1402         * arc-opc.c: Add top level comment.
1403         (insert_nps_3bit_dst): New function.
1404         (extract_nps_3bit_dst): New function.
1405         (insert_nps_3bit_src2): New function.
1406         (extract_nps_3bit_src2): New function.
1407         (insert_nps_bitop_size): New function.
1408         (extract_nps_bitop_size): New function.
1409         (arc_flag_operands): Add nps400 entries.
1410         (arc_flag_classes): Add nps400 entries.
1411         (arc_operands): Add nps400 entries.
1412         (arc_opcodes): Add nps400 include.
1413
1414 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1415
1416         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1417         the new class enum values.
1418
1419 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1420
1421         * arc-dis.c (print_insn_arc): Handle nps400.
1422
1423 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1424
1425         * arc-opc.c (BASE): Delete.
1426
1427 2016-03-18  Nick Clifton  <nickc@redhat.com>
1428
1429         PR target/19721
1430         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1431         of MOV insn that aliases an ORR insn.
1432
1433 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1434
1435         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1436
1437 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1438
1439         * mcore-opc.h: Add const qualifiers.
1440         * microblaze-opc.h (struct op_code_struct): Likewise.
1441         * sh-opc.h: Likewise.
1442         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1443         (tic4x_print_op): Likewise.
1444
1445 2016-03-02  Alan Modra  <amodra@gmail.com>
1446
1447         * or1k-desc.h: Regenerate.
1448         * fr30-ibld.c: Regenerate.
1449         * rl78-decode.c: Regenerate.
1450
1451 2016-03-01  Nick Clifton  <nickc@redhat.com>
1452
1453         PR target/19747
1454         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1455
1456 2016-02-24  Renlin Li  <renlin.li@arm.com>
1457
1458         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1459         (print_insn_coprocessor): Support fp16 instructions.
1460
1461 2016-02-24  Renlin Li  <renlin.li@arm.com>
1462
1463         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1464         vminnm, vrint(mpna).
1465
1466 2016-02-24  Renlin Li  <renlin.li@arm.com>
1467
1468         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1469         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1470
1471 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1472
1473         * i386-dis.c (print_insn): Parenthesize expression to prevent
1474         truncated addresses.
1475         (OP_J): Likewise.
1476
1477 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1478             Janek van Oirschot  <jvanoirs@synopsys.com>
1479
1480         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1481         variable.
1482
1483 2016-02-04  Nick Clifton  <nickc@redhat.com>
1484
1485         PR target/19561
1486         * msp430-dis.c (print_insn_msp430): Add a special case for
1487         decoding an RRC instruction with the ZC bit set in the extension
1488         word.
1489
1490 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1491
1492         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1493         * epiphany-ibld.c: Regenerate.
1494         * fr30-ibld.c: Regenerate.
1495         * frv-ibld.c: Regenerate.
1496         * ip2k-ibld.c: Regenerate.
1497         * iq2000-ibld.c: Regenerate.
1498         * lm32-ibld.c: Regenerate.
1499         * m32c-ibld.c: Regenerate.
1500         * m32r-ibld.c: Regenerate.
1501         * mep-ibld.c: Regenerate.
1502         * mt-ibld.c: Regenerate.
1503         * or1k-ibld.c: Regenerate.
1504         * xc16x-ibld.c: Regenerate.
1505         * xstormy16-ibld.c: Regenerate.
1506
1507 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1508
1509         * epiphany-dis.c: Regenerated from latest cpu files.
1510
1511 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1512
1513         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1514         test bit.
1515
1516 2016-01-25  Renlin Li  <renlin.li@arm.com>
1517
1518         * arm-dis.c (mapping_symbol_for_insn): New function.
1519         (find_ifthen_state): Call mapping_symbol_for_insn().
1520
1521 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1522
1523         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1524         of MSR UAO immediate operand.
1525
1526 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1527
1528         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1529         instruction support.
1530
1531 2016-01-17  Alan Modra  <amodra@gmail.com>
1532
1533         * configure: Regenerate.
1534
1535 2016-01-14  Nick Clifton  <nickc@redhat.com>
1536
1537         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1538         instructions that can support stack pointer operations.
1539         * rl78-decode.c: Regenerate.
1540         * rl78-dis.c: Fix display of stack pointer in MOVW based
1541         instructions.
1542
1543 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1544
1545         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1546         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1547         erxtatus_el1 and erxaddr_el1.
1548
1549 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1550
1551         * arm-dis.c (arm_opcodes): Add "esb".
1552         (thumb_opcodes): Likewise.
1553
1554 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1555
1556         * ppc-opc.c <xscmpnedp>: Delete.
1557         <xvcmpnedp>: Likewise.
1558         <xvcmpnedp.>: Likewise.
1559         <xvcmpnesp>: Likewise.
1560         <xvcmpnesp.>: Likewise.
1561
1562 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1563
1564         PR gas/13050
1565         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1566         addition to ISA_A.
1567
1568 2016-01-01  Alan Modra  <amodra@gmail.com>
1569
1570         Update year range in copyright notice of all files.
1571
1572 For older changes see ChangeLog-2015
1573 \f
1574 Copyright (C) 2016 Free Software Foundation, Inc.
1575
1576 Copying and distribution of this file, with or without modification,
1577 are permitted in any medium without royalty provided the copyright
1578 notice and this notice are preserved.
1579
1580 Local Variables:
1581 mode: change-log
1582 left-margin: 8
1583 fill-column: 74
1584 version-control: never
1585 End: