opcodes/ChangeLog

   1 2019-12-29  Alan Modra  <amodra@gmail.com>
   2
   3         PR 25319
   4         * tic4x-dis.c (tic4x_print_cond): Init all of condtable.
   5
   6 2019-12-27  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-dis.c (Jdqw): Define.
   9         (dqw_mode): Adjust associated comment.
  10         (rm_table): Use Jdqw for XBEGIN.
  11         (OP_J): Handle dqw_mode.
  12
  13 2019-12-27  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-gen.c (process_i386_operand_type): Don't set Disp32 for
  16         Cpu64 templates.
  17         * i386-opc.tbl (mov): Fold two templates.
  18         (jcxz, jecxz, jrcxz, loop, loope, loopne, loopnz, loopz): Drop
  19         Disp16, Disp32, and Disp32S.
  20         (xbegin): Add Disp32S.
  21         * i386-tbl.h: Re-generate.
  22
  23 2019-12-26  Alan Modra  <amodra@gmail.com>
  24
  25         * crx-dis.c (get_number_of_operands): Don't access operands[]
  26         out of bounds.
  27
  28 2019-12-26  Alan Modra  <amodra@gmail.com>
  29
  30         * v850-dis.c (disassemble): Avoid signed overflow.  Don't use
  31         long vars when unsigned int will do.
  32
  33 2019-12-24  Alan Modra  <amodra@gmail.com>
  34
  35         * arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
  36
  37 2019-12-23  Jan Beulich  <jbeulich@suse.com>
  38
  39         * ppc-dis.c (print_insn_powerpc): Rename local variable "spaces"
  40         to "blanks".
  41         * ppc-opc.c (D34, SI34, NSI34): Use UINT64_C().
  42
  43 2019-12-23  Alan Modra  <amodra@gmail.com>
  44
  45         * score-dis.c (print_insn_score32): Avoid signed overflow.
  46         (print_insn_score48): Likewise.  Don't cast to int when printing
  47         hex values.
  48
  49 2019-12-23  Alan Modra  <amodra@gmail.com>
  50
  51         * iq2000-ibld.c: Regenerate.
  52
  53 2019-12-23  Alan Modra  <amodra@gmail.com>
  54
  55         * d30v-dis.c (extract_value): Make num param a uint64_t, constify
  56         oper.  Use unsigned vars.
  57         (print_insn): Make num var uint64_t.  Constify oper and remove now
  58         unnecessary casts on extract_value calls.
  59         (print_insn_d30v): Use unsigned vars.  Adjust printf formats.
  60
  61 2019-12-23  Alan Modra  <amodra@gmail.com>
  62
  63         * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
  64         Catch value overflow.  Sign extend only on terminating byte.
  65
  66 2019-12-20  Alan Modra  <amodra@gmail.com>
  67
  68         PR 25281
  69         * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
  70         and MOVY_NOPX insns.  For invalid cases include 0xf000 in the word
  71         printed.  Print .word in more cases.
  72
  73 2019-12-20  Alan Modra  <amodra@gmail.com>
  74
  75         * or1k-ibld.c: Regenerate.
  76
  77 2019-12-20  Alan Modra  <amodra@gmail.com>
  78
  79         * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
  80         unsigned variables.
  81
  82 2019-12-20  Alan Modra  <amodra@gmail.com>
  83
  84         * m68hc11-dis.c (read_memory): Delete forward decls.
  85         (print_indexed_operand, print_insn): Likewise.
  86         (print_indexed_operand): Formatting.  Don't rely on short being
  87         exactly 16 bits, make sign extension explicit.
  88         (print_insn): Likewise.  Avoid signed overflow.
  89
  90 2019-12-19  Alan Modra  <amodra@gmail.com>
  91
  92         * vax-dis.c (print_insn_mode): Stop index mode recursion.
  93
  94 2019-12-19  Dr N.W. Filardo  <nwf20@cam.ac.uk>
  95
  96         PR 25277
  97         * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
  98         fdiv with "mbi_".
  99         * microblaze-opc.h (opcodes): Adjust to suit.
 100
 101 2019-12-18  Alan Modra  <amodra@gmail.com>
 102
 103         * alpha-opc.c (OP): Avoid signed overflow.
 104         * arm-dis.c (print_insn): Likewise.
 105         * mcore-dis.c (print_insn_mcore): Likewise.
 106         * pj-dis.c (get_int): Likewise.
 107         * ppc-opc.c (EBD15, EBD15BI): Likewise.
 108         * score7-dis.c (s7_print_insn): Likewise.
 109         * tic30-dis.c (print_insn_tic30): Likewise.
 110         * v850-opc.c (insert_SELID): Likewise.
 111         * vax-dis.c (print_insn_vax): Likewise.
 112         * arc-ext.c (create_map): Likewise.
 113         (struct ExtAuxRegister): Make "address" field unsigned int.
 114         (arcExtMap_auxRegName): Pass unsigned address.
 115         (dump_ARC_extmap): Adjust.
 116         * arc-ext.h (arcExtMap_auxRegName): Update prototype.
 117
 118 2019-12-17  Alan Modra  <amodra@gmail.com>
 119
 120         * visium-dis.c (print_insn_visium): Avoid signed overflow.
 121
 122 2019-12-17  Alan Modra  <amodra@gmail.com>
 123
 124         * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
 125         (value_fit_unsigned_field_p): Likewise.
 126         (aarch64_wide_constant_p): Likewise.
 127         (operand_general_constraint_met_p): Likewise.
 128         * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
 129
 130 2019-12-17  Alan Modra  <amodra@gmail.com>
 131
 132         * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
 133         (print_insn_nds32): Use uint64_t for "given" and "given1".
 134
 135 2019-12-17  Alan Modra  <amodra@gmail.com>
 136
 137         * tic80-dis.c: Delete file.
 138         * tic80-opc.c: Delete file.
 139         * disassemble.c: Remove tic80 support.
 140         * disassemble.h: Likewise.
 141         * Makefile.am: Likewise.
 142         * configure.ac: Likewise.
 143         * Makefile.in: Regenerate.
 144         * configure: Regenerate.
 145         * po/POTFILES.in: Regenerate.
 146
 147 2019-12-17  Alan Modra  <amodra@gmail.com>
 148
 149         * bpf-ibld.c: Regenerate.
 150
 151 2019-12-16  Alan Modra  <amodra@gmail.com>
 152
 153         * aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
 154         conditional.
 155         (aarch64_ext_imm): Avoid signed overflow.
 156
 157 2019-12-16  Alan Modra  <amodra@gmail.com>
 158
 159         * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
 160
 161 2019-12-16  Alan Modra  <amodra@gmail.com>
 162
 163         * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
 164
 165 2019-12-16  Alan Modra  <amodra@gmail.com>
 166
 167         * xstormy16-ibld.c: Regenerate.
 168
 169 2019-12-16  Alan Modra  <amodra@gmail.com>
 170
 171         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
 172         value adjustment so that it doesn't affect reg field too.
 173
 174 2019-12-16  Alan Modra  <amodra@gmail.com>
 175
 176         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
 177         (get_number_of_operands, getargtype, getbits, getregname),
 178         (getcopregname, getprocregname, gettrapstring, getcinvstring),
 179         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
 180         (powerof2, match_opcode, make_instruction, print_arguments),
 181         (print_arg): Delete forward declarations, moving static to..
 182         (getregname, getcopregname, getregliststring): ..these definitions.
 183         (build_mask): Return unsigned int mask.
 184         (match_opcode): Use unsigned int vars.
 185
 186 2019-12-16  Alan Modra  <amodra@gmail.com>
 187
 188         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
 189
 190 2019-12-16  Alan Modra  <amodra@gmail.com>
 191
 192         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
 193         (struct objdump_disasm_info): Delete.
 194         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
 195         N32_IMMS to unsigned before shifting left.
 196
 197 2019-12-16  Alan Modra  <amodra@gmail.com>
 198
 199         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
 200         (print_insn_moxie): Remove unnecessary cast.
 201
 202 2019-12-12  Alan Modra  <amodra@gmail.com>
 203
 204         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
 205         mask.
 206
 207 2019-12-11  Alan Modra  <amodra@gmail.com>
 208
 209         * arc-dis.c (BITS): Don't truncate high bits with shifts.
 210         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
 211         * tic54x-dis.c (print_instruction): Likewise.
 212         * tilegx-opc.c (parse_insn_tilegx): Likewise.
 213         * tilepro-opc.c (parse_insn_tilepro): Likewise.
 214         * visium-dis.c (disassem_class0): Likewise.
 215         * pdp11-dis.c (sign_extend): Likewise.
 216         (SIGN_BITS): Delete.
 217         * epiphany-ibld.c: Regenerate.
 218         * lm32-ibld.c: Regenerate.
 219         * m32c-ibld.c: Regenerate.
 220
 221 2019-12-11  Alan Modra  <amodra@gmail.com>
 222
 223         * ns32k-dis.c (sign_extend): Correct last patch.
 224
 225 2019-12-11  Alan Modra  <amodra@gmail.com>
 226
 227         * vax-dis.c (NEXTLONG): Avoid signed overflow.
 228
 229 2019-12-11  Alan Modra  <amodra@gmail.com>
 230
 231         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
 232         sign extend using shifts.
 233
 234 2019-12-11  Alan Modra  <amodra@gmail.com>
 235
 236         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
 237
 238 2019-12-11  Alan Modra  <amodra@gmail.com>
 239
 240         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
 241         on NULL registertable entry.
 242         (tic4x_hash_opcode): Use unsigned arithmetic.
 243
 244 2019-12-11  Alan Modra  <amodra@gmail.com>
 245
 246         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
 247
 248 2019-12-11  Alan Modra  <amodra@gmail.com>
 249
 250         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
 251         (bit_extract_simple, sign_extend): Likewise.
 252
 253 2019-12-11  Alan Modra  <amodra@gmail.com>
 254
 255         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
 256
 257 2019-12-11  Alan Modra  <amodra@gmail.com>
 258
 259         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
 260
 261 2019-12-11  Alan Modra  <amodra@gmail.com>
 262
 263         * m68k-dis.c (COERCE32): Cast value first.
 264         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 265
 266 2019-12-11  Alan Modra  <amodra@gmail.com>
 267
 268         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 269         (bfd_h8_disassemble): Likewise.
 270
 271 2019-12-11  Alan Modra  <amodra@gmail.com>
 272
 273         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 274         past end of operands array.
 275
 276 2019-12-11  Alan Modra  <amodra@gmail.com>
 277
 278         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 279         overflow when collecting bytes of a number.
 280
 281 2019-12-11  Alan Modra  <amodra@gmail.com>
 282
 283         * cris-dis.c (print_with_operands): Avoid signed integer
 284         overflow when collecting bytes of a 32-bit integer.
 285
 286 2019-12-11  Alan Modra  <amodra@gmail.com>
 287
 288         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 289         (cr16_match_opcode): Delete duplicate bcond test.
 290
 291 2019-12-11  Alan Modra  <amodra@gmail.com>
 292
 293         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 294         (SIGNBIT): New.
 295         (MASKBITS, SIGNEXTEND): Rewrite.
 296         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 297         unsigned arithmetic, instead assign result of SIGNEXTEND back
 298         to x.
 299         (fmtconst_val): Use 1u in shift expression.
 300
 301 2019-12-11  Alan Modra  <amodra@gmail.com>
 302
 303         * arc-dis.c (find_format_from_table): Use ull constant when
 304         shifting by up to 32.
 305
 306 2019-12-11  Alan Modra  <amodra@gmail.com>
 307
 308         PR 25270
 309         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 310         false when field is zero for sve_size_tsz_bhs.
 311
 312 2019-12-11  Alan Modra  <amodra@gmail.com>
 313
 314         * epiphany-ibld.c: Regenerate.
 315
 316 2019-12-10  Alan Modra  <amodra@gmail.com>
 317
 318         PR 24960
 319         * disassemble.c (disassemble_free_target): New function.
 320
 321 2019-12-10  Alan Modra  <amodra@gmail.com>
 322
 323         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 324         * disassemble.c (disassemble_init_for_target): Likewise.
 325         * bpf-dis.c: Regenerate.
 326         * epiphany-dis.c: Regenerate.
 327         * fr30-dis.c: Regenerate.
 328         * frv-dis.c: Regenerate.
 329         * ip2k-dis.c: Regenerate.
 330         * iq2000-dis.c: Regenerate.
 331         * lm32-dis.c: Regenerate.
 332         * m32c-dis.c: Regenerate.
 333         * m32r-dis.c: Regenerate.
 334         * mep-dis.c: Regenerate.
 335         * mt-dis.c: Regenerate.
 336         * or1k-dis.c: Regenerate.
 337         * xc16x-dis.c: Regenerate.
 338         * xstormy16-dis.c: Regenerate.
 339
 340 2019-12-10  Alan Modra  <amodra@gmail.com>
 341
 342         * ppc-dis.c (private): Delete variable.
 343         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 344         (powerpc_init_dialect): Don't use global private.
 345
 346 2019-12-10  Alan Modra  <amodra@gmail.com>
 347
 348         * s12z-opc.c: Formatting.
 349
 350 2019-12-08  Alan Modra  <amodra@gmail.com>
 351
 352         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 353         registers.
 354
 355 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 356
 357         * aarch64-tbl.h (aarch64_feature_crypto,
 358         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 359         CRYPTO_V8_2_INSN): Delete.
 360
 361 2019-12-05  Alan Modra  <amodra@gmail.com>
 362
 363         PR 25249
 364         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 365         (struct string_buf): New.
 366         (strbuf): New function.
 367         (get_field): Use strbuf rather than strdup of local temp.
 368         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 369         (get_field_rfsl, get_field_imm15): Likewise.
 370         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 371         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 372         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 373         get_field functions.
 374
 375 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 376
 377         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 378         * i386-tbl.h: Re-generate.
 379
 380 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 383
 384 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 387         forms.
 388         (xbegin): Drop DefaultSize.
 389         * i386-tbl.h: Re-generate.
 390
 391 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 392
 393         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 394         Change the coproc CRC conditions to use the extension
 395         feature set, second word, base on ARM_EXT2_CRC.
 396
 397 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 400         * i386-tbl.h: Re-generate.
 401
 402 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 403
 404         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 405         JumpInterSegment, and JumpAbsolute entries.
 406         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 407         JUMP_ABSOLUTE): Define.
 408         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 409         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 410         fields.
 411         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 412         JumpInterSegment): Define.
 413         * i386-tbl.h: Re-generate.
 414
 415 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-gen.c (operand_type_init): Remove
 418         OPERAND_TYPE_JUMPABSOLUTE entry.
 419         (opcode_modifiers): Add JumpAbsolute entry.
 420         (operand_types): Remove JumpAbsolute entry.
 421         * i386-opc.h (JumpAbsolute): Move between enums.
 422         (struct i386_opcode_modifier): Add jumpabsolute field.
 423         (union i386_operand_type): Remove jumpabsolute field.
 424         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 425         * i386-init.h, i386-tbl.h: Re-generate.
 426
 427 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 428
 429         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 430         (operand_types): Remove AnySize entry.
 431         * i386-opc.h (AnySize): Move between enums.
 432         (struct i386_opcode_modifier): Add anysize field.
 433         (OTUnused): Un-comment.
 434         (union i386_operand_type): Remove anysize field.
 435         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 436         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 437         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 438         AnySize.
 439         * i386-tbl.h: Re-generate.
 440
 441 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 442
 443         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 444         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 445         use the floating point register (FPR).
 446
 447 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 448
 449         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 450         cmode 1101.
 451         (is_mve_encoding_conflict): Update cmode conflict checks for
 452         MVE_VMVN_IMM.
 453
 454 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 455
 456         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 457         entry.
 458         (operand_types): Remove EsSeg entry.
 459         (main): Replace stale use of OTMax.
 460         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 461         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 462         (EsSeg): Delete.
 463         (OTUnused): Comment out.
 464         (union i386_operand_type): Remove esseg field.
 465         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 466         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 467         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 468         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 469         * i386-init.h, i386-tbl.h: Re-generate.
 470
 471 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 472
 473         * i386-gen.c (operand_instances): Add RegB entry.
 474         * i386-opc.h (enum operand_instance): Add RegB.
 475         * i386-opc.tbl (RegC, RegD, RegB): Define.
 476         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 477         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 478         monitorx, mwaitx): Drop ImmExt and convert encodings
 479         accordingly.
 480         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 481         (edx, rdx): Add Instance=RegD.
 482         (ebx, rbx): Add Instance=RegB.
 483         * i386-tbl.h: Re-generate.
 484
 485 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-gen.c (operand_type_init): Adjust
 488         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 489         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 490         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 491         (operand_instances): New.
 492         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 493         (output_operand_type): New parameter "instance". Process it.
 494         (process_i386_operand_type): New local variable "instance".
 495         (main): Adjust static assertions.
 496         * i386-opc.h (INSTANCE_WIDTH): Define.
 497         (enum operand_instance): New.
 498         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 499         (union i386_operand_type): Replace acc, inoutportreg, and
 500         shiftcount by instance.
 501         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 502         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 503         Add Instance=.
 504         * i386-init.h, i386-tbl.h: Re-generate.
 505
 506 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 507
 508         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 509         smaxp/sminp entries' "tied_operand" field to 2.
 510
 511 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 512
 513         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 514         "index" local variable by that of the already existing "num".
 515
 516 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 517
 518         PR gas/25167
 519         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 520         * i386-tbl.h: Regenerated.
 521
 522 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 523
 524         * i386-gen.c (operand_type_init): Add Class= to
 525         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 526         OPERAND_TYPE_REGBND entry.
 527         (operand_classes): Add RegMask and RegBND entries.
 528         (operand_types): Drop RegMask and RegBND entry.
 529         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 530         (RegMask, RegBND): Delete.
 531         (union i386_operand_type): Remove regmask and regbnd fields.
 532         * i386-opc.tbl (RegMask, RegBND): Define.
 533         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 534         Class=RegBND.
 535         * i386-init.h, i386-tbl.h: Re-generate.
 536
 537 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 538
 539         * i386-gen.c (operand_type_init): Add Class= to
 540         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 541         OPERAND_TYPE_REGZMM entries.
 542         (operand_classes): Add RegMMX and RegSIMD entries.
 543         (operand_types): Drop RegMMX and RegSIMD entries.
 544         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 545         (RegMMX, RegSIMD): Delete.
 546         (union i386_operand_type): Remove regmmx and regsimd fields.
 547         * i386-opc.tbl (RegMMX): Define.
 548         (RegXMM, RegYMM, RegZMM): Add Class=.
 549         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 550         Class=RegSIMD.
 551         * i386-init.h, i386-tbl.h: Re-generate.
 552
 553 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 554
 555         * i386-gen.c (operand_type_init): Add Class= to
 556         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 557         entries.
 558         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 559         (operand_types): Drop Control, Debug, and Test entries.
 560         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 561         (Control, Debug, Test): Delete.
 562         (union i386_operand_type): Remove control, debug, and test
 563         fields.
 564         * i386-opc.tbl (Control, Debug, Test): Define.
 565         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 566         Class=RegDR, and Test by Class=RegTR.
 567         * i386-init.h, i386-tbl.h: Re-generate.
 568
 569 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 570
 571         * i386-gen.c (operand_type_init): Add Class= to
 572         OPERAND_TYPE_SREG entry.
 573         (operand_classes): Add SReg entry.
 574         (operand_types): Drop SReg entry.
 575         * i386-opc.h (enum operand_class): Add SReg.
 576         (SReg): Delete.
 577         (union i386_operand_type): Remove sreg field.
 578         * i386-opc.tbl (SReg): Define.
 579         * i386-reg.tbl: Replace SReg by Class=SReg.
 580         * i386-init.h, i386-tbl.h: Re-generate.
 581
 582 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-gen.c (operand_type_init): Add Class=. New
 585         OPERAND_TYPE_ANYIMM entry.
 586         (operand_classes): New.
 587         (operand_types): Drop Reg entry.
 588         (output_operand_type): New parameter "class". Process it.
 589         (process_i386_operand_type): New local variable "class".
 590         (main): Adjust static assertions.
 591         * i386-opc.h (CLASS_WIDTH): Define.
 592         (enum operand_class): New.
 593         (Reg): Replace by Class. Adjust comment.
 594         (union i386_operand_type): Replace reg by class.
 595         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 596         Class=.
 597         * i386-reg.tbl: Replace Reg by Class=Reg.
 598         * i386-init.h: Re-generate.
 599
 600 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 601
 602         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 603         (aarch64_opcode_table): Add data gathering hint mnemonic.
 604         * opcodes/aarch64-dis-2.c: Account for new instruction.
 605
 606 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 607
 608         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 609
 610
 611 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 612
 613         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 614         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 615         aarch64_feature_f64mm): New feature sets.
 616         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 617         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 618         instructions.
 619         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 620         macros.
 621         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 622         (OP_SVE_QQQ): New qualifier.
 623         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 624         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 625         the movprfx constraint.
 626         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 627         (aarch64_opcode_table): Define new instructions smmla,
 628         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 629         uzip{1/2}, trn{1/2}.
 630         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 631         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 632         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 633         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 634         Account for new instructions.
 635         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 636         S4x32 operand.
 637         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 638
 639 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 640 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 641
 642         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 643         Armv8.6-A.
 644         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 645         (neon_opcodes): Add bfloat SIMD instructions.
 646         (print_insn_coprocessor): Add new control character %b to print
 647         condition code without checking cp_num.
 648         (print_insn_neon): Account for BFloat16 instructions that have no
 649         special top-byte handling.
 650
 651 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 652 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 653
 654         * arm-dis.c (print_insn_coprocessor,
 655         print_insn_generic_coprocessor): Create wrapper functions around
 656         the implementation of the print_insn_coprocessor control codes.
 657         (print_insn_coprocessor_1): Original print_insn_coprocessor
 658         function that now takes which array to look at as an argument.
 659         (print_insn_arm): Use both print_insn_coprocessor and
 660         print_insn_generic_coprocessor.
 661         (print_insn_thumb32): As above.
 662
 663 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 664 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 665
 666         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 667         in reglane special case.
 668         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 669         aarch64_find_next_opcode): Account for new instructions.
 670         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 671         in reglane special case.
 672         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 673         new AARCH64_OPND_QLF_S_2H qualifier.
 674         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 675         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 676         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 677         sets.
 678         (BFLOAT_SVE, BFLOAT): New feature set macros.
 679         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 680         instructions.
 681         (aarch64_opcode_table): Define new instructions bfdot,
 682         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 683         bfcvtn2, bfcvt.
 684
 685 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 686 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 687
 688         * aarch64-tbl.h (ARMV8_6): New macro.
 689
 690 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-dis.c (prefix_table): Add mcommit.
 693         (rm_table): Add rdpru.
 694         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 695         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 696         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 697         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 698         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 699         * i386-opc.tbl (mcommit, rdpru): New.
 700         * i386-init.h, i386-tbl.h: Re-generate.
 701
 702 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 703
 704         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 705         "names32" instead.
 706         (OP_Monitor): Drop local variable "op1_names", re-purpose
 707         "names" for it instead, and replace former "names" uses by
 708         "names32" ones.
 709
 710 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 711
 712         PR/gas 25167
 713         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 714         operand-less forms.
 715         * opcodes/i386-tbl.h: Re-generate.
 716
 717 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 718
 719         * i386-dis.c (OP_Mwaitx): Delete.
 720         (prefix_table): Use OP_Mwait for mwaitx entry.
 721         (OP_Mwait): Also handle mwaitx.
 722
 723 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 724
 725         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 726         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 727         (prefix_table): Add respective entries.
 728         (rm_table): Link to those entries.
 729
 730 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 733         (REG_0F1C_P_0_MOD_0): ... this.
 734         (REG_0F1E_MOD_3): Rename to ...
 735         (REG_0F1E_P_1_MOD_3): ... this.
 736         (RM_0F01_REG_5): Rename to ...
 737         (RM_0F01_REG_5_MOD_3): ... this.
 738         (RM_0F01_REG_7): Rename to ...
 739         (RM_0F01_REG_7_MOD_3): ... this.
 740         (RM_0F1E_MOD_3_REG_7): Rename to ...
 741         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 742         (RM_0FAE_REG_6): Rename to ...
 743         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 744         (RM_0FAE_REG_7): Rename to ...
 745         (RM_0FAE_REG_7_MOD_3): ... this.
 746         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 747         (PREFIX_0F01_REG_5_MOD_0): ... this.
 748         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 749         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 750         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 751         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 752         (PREFIX_0FAE_REG_0): Rename to ...
 753         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 754         (PREFIX_0FAE_REG_1): Rename to ...
 755         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 756         (PREFIX_0FAE_REG_2): Rename to ...
 757         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 758         (PREFIX_0FAE_REG_3): Rename to ...
 759         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 760         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 761         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 762         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 763         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 764         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 765         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 766         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 767         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 768         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 769         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 770         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 771         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 772         (PREFIX_0FAE_REG_7): Rename to ...
 773         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 774         (PREFIX_MOD_0_0FC3): Rename to ...
 775         (PREFIX_0FC3_MOD_0): ... this.
 776         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 777         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 778         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 779         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 780         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 781         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 782         (reg_table, prefix_table, mod_table, rm_table): Adjust
 783         accordingly.
 784
 785 2019-11-04  Nick Clifton  <nickc@redhat.com>
 786
 787         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 788         of a v850 system register.  Move the v850_sreg_names array into
 789         this function.
 790         (get_v850_reg_name): Likewise for ordinary register names.
 791         (get_v850_vreg_name): Likewise for vector register names.
 792         (get_v850_cc_name): Likewise for condition codes.
 793         * get_v850_float_cc_name): Likewise for floating point condition
 794         codes.
 795         (get_v850_cacheop_name): Likewise for cache-ops.
 796         (get_v850_prefop_name): Likewise for pref-ops.
 797         (disassemble): Use the new accessor functions.
 798
 799 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 800
 801         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 802         immediate for the writeback form of ldraa/ldrab if it is 0.
 803         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 804         * aarch64-opc-2.c: Regenerated.
 805
 806 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 807
 808         * i386-gen.c (operand_type_shorthands): Delete.
 809         (operand_type_init): Expand previous shorthands.
 810         (set_bitfield_from_shorthand): Rename back to ...
 811         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 812         of operand_type_init[].
 813         (set_bitfield): Adjust call to the above function.
 814         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 815         RegXMM, RegYMM, RegZMM): Define.
 816         * i386-reg.tbl: Expand prior shorthands.
 817
 818 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 819
 820         * i386-gen.c (output_i386_opcode): Change order of fields
 821         emitted to output.
 822         * i386-opc.h (struct insn_template): Move operands field.
 823         Convert extension_opcode field to unsigned short.
 824         * i386-tbl.h: Re-generate.
 825
 826 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 829         of W.
 830         * i386-opc.h (W): Extend comment.
 831         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 832         general purpose variants not allowing for byte operands.
 833         * i386-tbl.h: Re-generate.
 834
 835 2019-10-29  Nick Clifton  <nickc@redhat.com>
 836
 837         * tic30-dis.c (print_branch): Correct size of operand array.
 838
 839 2019-10-29  Nick Clifton  <nickc@redhat.com>
 840
 841         * d30v-dis.c (print_insn): Check that operand index is valid
 842         before attempting to access the operands array.
 843
 844 2019-10-29  Nick Clifton  <nickc@redhat.com>
 845
 846         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 847         locating the bit to be tested.
 848
 849 2019-10-29  Nick Clifton  <nickc@redhat.com>
 850
 851         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 852         values.
 853         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 854         (print_insn_s12z):  Check for illegal size values.
 855
 856 2019-10-28  Nick Clifton  <nickc@redhat.com>
 857
 858         * csky-dis.c (csky_chars_to_number): Check for a negative
 859         count. Use an unsigned integer to construct the return value.
 860
 861 2019-10-28  Nick Clifton  <nickc@redhat.com>
 862
 863         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 864         operand buffer.  Set value to 15 not 13.
 865         (get_register_operand): Use OPERAND_BUFFER_LEN.
 866         (get_indirect_operand): Likewise.
 867         (print_two_operand): Likewise.
 868         (print_three_operand): Likewise.
 869         (print_oar_insn): Likewise.
 870
 871 2019-10-28  Nick Clifton  <nickc@redhat.com>
 872
 873         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 874         (bit_extract_simple): Likewise.
 875         (bit_copy): Likewise.
 876         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 877         index_offset array are not accessed.
 878
 879 2019-10-28  Nick Clifton  <nickc@redhat.com>
 880
 881         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 882         operand.
 883
 884 2019-10-25  Nick Clifton  <nickc@redhat.com>
 885
 886         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 887         access to opcodes.op array element.
 888
 889 2019-10-23  Nick Clifton  <nickc@redhat.com>
 890
 891         * rx-dis.c (get_register_name): Fix spelling typo in error
 892         message.
 893         (get_condition_name, get_flag_name, get_double_register_name)
 894         (get_double_register_high_name, get_double_register_low_name)
 895         (get_double_control_register_name, get_double_condition_name)
 896         (get_opsize_name, get_size_name): Likewise.
 897
 898 2019-10-22  Nick Clifton  <nickc@redhat.com>
 899
 900         * rx-dis.c (get_size_name): New function.  Provides safe
 901         access to name array.
 902         (get_opsize_name): Likewise.
 903         (print_insn_rx): Use the accessor functions.
 904
 905 2019-10-16  Nick Clifton  <nickc@redhat.com>
 906
 907         * rx-dis.c (get_register_name): New function.  Provides safe
 908         access to name array.
 909         (get_condition_name, get_flag_name, get_double_register_name)
 910         (get_double_register_high_name, get_double_register_low_name)
 911         (get_double_control_register_name, get_double_condition_name):
 912         Likewise.
 913         (print_insn_rx): Use the accessor functions.
 914
 915 2019-10-09  Nick Clifton  <nickc@redhat.com>
 916
 917         PR 25041
 918         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 919         instructions.
 920
 921 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 922
 923         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 924         (cmpsd): Likewise. Move EsSeg to other operand.
 925         * opcodes/i386-tbl.h: Re-generate.
 926
 927 2019-09-23  Alan Modra  <amodra@gmail.com>
 928
 929         * m68k-dis.c: Include cpu-m68k.h
 930
 931 2019-09-23  Alan Modra  <amodra@gmail.com>
 932
 933         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 934         "elf/mips.h" earlier.
 935
 936 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 937
 938         PR gas/25012
 939         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 940         with SReg operand.
 941         * i386-tbl.h: Re-generate.
 942
 943 2019-09-18  Alan Modra  <amodra@gmail.com>
 944
 945         * arc-ext.c: Update throughout for bfd section macro changes.
 946
 947 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 948
 949         * Makefile.in: Re-generate.
 950         * configure: Re-generate.
 951
 952 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 953
 954         * riscv-opc.c (riscv_opcodes): Change subset field
 955         to insn_class field for all instructions.
 956         (riscv_insn_types): Likewise.
 957
 958 2019-09-16  Phil Blundell  <pb@pbcl.net>
 959
 960         * configure: Regenerated.
 961
 962 2019-09-10  Miod Vallat  <miod@online.fr>
 963
 964         PR 24982
 965         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 966
 967 2019-09-09  Phil Blundell  <pb@pbcl.net>
 968
 969         binutils 2.33 branch created.
 970
 971 2019-09-03  Nick Clifton  <nickc@redhat.com>
 972
 973         PR 24961
 974         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 975         greater than zero before indexing via (bufcnt -1).
 976
 977 2019-09-03  Nick Clifton  <nickc@redhat.com>
 978
 979         PR 24958
 980         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 981         (MAX_SPEC_REG_NAME_LEN): Define.
 982         (struct mmix_dis_info): Use defined constants for array lengths.
 983         (get_reg_name): New function.
 984         (get_sprec_reg_name): New function.
 985         (print_insn_mmix): Use new functions.
 986
 987 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 988
 989         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 990         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 991         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 992
 993 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 994
 995         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 996         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 997         (aarch64_sys_reg_supported_p): Update checks for the above.
 998
 999 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
1000
1001         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
1002         cases MVE_SQRSHRL and MVE_UQRSHLL.
1003         (print_insn_mve): Add case for specifier 'k' to check
1004         specific bit of the instruction.
1005
1006 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
1007
1008         PR 24854
1009         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
1010         encountering an unknown machine type.
1011         (print_insn_arc): Handle arc_insn_length returning 0.  In error
1012         cases return -1 rather than calling abort.
1013
1014 2019-08-07  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
1017         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
1018         IgnoreSize.
1019         * i386-tbl.h: Re-generate.
1020
1021 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
1022
1023         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
1024         instructions.
1025
1026 2019-07-30  Mel Chen <mel.chen@sifive.com>
1027
1028         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
1029         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
1030
1031         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
1032         fscsr.
1033
1034 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
1035
1036         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
1037         and MPY class instructions.
1038         (parse_option): Add nps400 option.
1039         (print_arc_disassembler_options): Add nps400 info.
1040
1041 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
1042
1043         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
1044         (bspop): Likewise.
1045         (modapp): Likewise.
1046         * arc-opc.c (RAD_CHK): Add.
1047         * arc-tbl.h: Regenerate.
1048
1049 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1050
1051         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1052         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1053
1054 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
1055
1056         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1057         instructions as UNPREDICTABLE.
1058
1059 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1060
1061         * bpf-desc.c: Regenerated.
1062
1063 2019-07-17  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-gen.c (static_assert): Define.
1066         (main): Use it.
1067         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1068         (Opcode_Modifier_Num): ... this.
1069         (Mem): Delete.
1070
1071 2019-07-16  Jan Beulich  <jbeulich@suse.com>
1072
1073         * i386-gen.c (operand_types): Move RegMem ...
1074         (opcode_modifiers): ... here.
1075         * i386-opc.h (RegMem): Move to opcode modifer enum.
1076         (union i386_operand_type): Move regmem field ...
1077         (struct i386_opcode_modifier): ... here.
1078         * i386-opc.tbl (RegMem): Define.
1079         (mov, movq): Move RegMem on segment, control, debug, and test
1080         register flavors.
1081         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1082         to non-SSE2AVX flavor.
1083         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1084         Move RegMem on register only flavors. Drop IgnoreSize from
1085         legacy encoding flavors.
1086         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1087         flavors.
1088         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1089         register only flavors.
1090         (vmovd): Move RegMem and drop IgnoreSize on register only
1091         flavor. Change opcode and operand order to store form.
1092         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1093
1094 2019-07-16  Jan Beulich  <jbeulich@suse.com>
1095
1096         * i386-gen.c (operand_type_init, operand_types): Replace SReg
1097         entries.
1098         * i386-opc.h (SReg2, SReg3): Replace by ...
1099         (SReg): ... this.
1100         (union i386_operand_type): Replace sreg fields.
1101         * i386-opc.tbl (mov, ): Use SReg.
1102         (push, pop): Likewies. Drop i386 and x86-64 specific segment
1103         register flavors.
1104         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1105         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1106
1107 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
1108
1109         * bpf-desc.c: Regenerate.
1110         * bpf-opc.c: Likewise.
1111         * bpf-opc.h: Likewise.
1112
1113 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
1114
1115         * bpf-desc.c: Regenerate.
1116         * bpf-opc.c: Likewise.
1117
1118 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
1119
1120         * arm-dis.c (print_insn_coprocessor): Rename index to
1121         index_operand.
1122
1123 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
1124
1125         * riscv-opc.c (riscv_insn_types): Add r4 type.
1126
1127         * riscv-opc.c (riscv_insn_types): Add b and j type.
1128
1129         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1130         format for sb type and correct s type.
1131
1132 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1133
1134         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1135         SVE FMOV alias of FCPY.
1136
1137 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1138
1139         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1140         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1141
1142 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1143
1144         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1145         registers in an instruction prefixed by MOVPRFX.
1146
1147 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
1148
1149         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1150         sve_size_13 icode to account for variant behaviour of
1151         pmull{t,b}.
1152         * aarch64-dis-2.c: Regenerate.
1153         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1154         sve_size_13 icode to account for variant behaviour of
1155         pmull{t,b}.
1156         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1157         (OP_SVE_VVV_Q_D): Add new qualifier.
1158         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1159         (struct aarch64_opcode): Split pmull{t,b} into those requiring
1160         AES and those not.
1161
1162 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1163
1164         * opcodes/i386-gen.c (operand_type_init): Remove
1165         OPERAND_TYPE_VEC_IMM4 entry.
1166         (operand_types): Remove Vec_Imm4.
1167         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1168         (union i386_operand_type): Remove vec_imm4.
1169         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1170         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1171
1172 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1173
1174         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1175         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1176         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1177         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1178         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1179         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1180         * i386-tbl.h: Re-generate.
1181
1182 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1183
1184         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1185         register operands.
1186         * i386-tbl.h: Re-generate.
1187
1188 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-opc.tbl (C): New.
1191         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1192         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1193         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1194         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1195         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1196         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1197         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1198         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1199         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1200         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1201         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1202         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1203         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1204         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1205         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1206         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1207         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1208         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1209         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1210         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1211         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1212         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1213         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1214         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1215         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1216         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1217         flavors.
1218         * i386-tbl.h: Re-generate.
1219
1220 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1221
1222         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1223         register operands.
1224         * i386-tbl.h: Re-generate.
1225
1226 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1227
1228         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1229         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1230         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1231         * i386-tbl.h: Re-generate.
1232
1233 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1234
1235         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1236         Disp8MemShift from register only templates.
1237         * i386-tbl.h: Re-generate.
1238
1239 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1240
1241         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1242         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1243         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1244         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1245         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1246         EVEX_W_0F11_P_3_M_1): Delete.
1247         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1248         EVEX_W_0F11_P_3): New.
1249         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1250         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1251         MOD_EVEX_0F11_PREFIX_3 table entries.
1252         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1253         PREFIX_EVEX_0F11 table entries.
1254         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1255         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1256         EVEX_W_0F11_P_3_M_{0,1} table entries.
1257
1258 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1259
1260         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1261         Delete.
1262
1263 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1264
1265         PR binutils/24719
1266         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1267         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1268         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1269         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1270         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1271         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1272         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1273         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1274         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1275         PREFIX_EVEX_0F38C6_REG_6 entries.
1276         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1277         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1278         EVEX_W_0F38C7_R_6_P_2 entries.
1279         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1280         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1281         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1282         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1283         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1284         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1285         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1286
1287 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1288
1289         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1290         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1291         VEX_LEN_0F2D_P_3): Delete.
1292         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1293         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1294         (prefix_table): ... here.
1295
1296 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1297
1298         * i386-dis.c (Iq): Delete.
1299         (Id): New.
1300         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1301         TBM insns.
1302         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1303         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1304         (OP_E_memory): Also honor needindex when deciding whether an
1305         address size prefix needs printing.
1306         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1307
1308 2019-06-26  Jim Wilson  <jimw@sifive.com>
1309
1310         PR binutils/24739
1311         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1312         Set info->display_endian to info->endian_code.
1313
1314 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1315
1316         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1317         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1318         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1319         OPERAND_TYPE_ACC64 entries.
1320         * i386-init.h: Re-generate.
1321
1322 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1323
1324         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1325         Delete.
1326         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1327         of dqa_mode.
1328         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1329         entries here.
1330         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1331         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1332
1333 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1334
1335         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1336         variables.
1337
1338 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1339
1340         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1341         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1342         movnti.
1343         * i386-opc.tbl (movnti): Add IgnoreSize.
1344         * i386-tbl.h: Re-generate.
1345
1346 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1347
1348         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1349         * i386-tbl.h: Re-generate.
1350
1351 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1352
1353         * i386-dis-evex.h: Break into ...
1354         * i386-dis-evex-len.h: New file.
1355         * i386-dis-evex-mod.h: Likewise.
1356         * i386-dis-evex-prefix.h: Likewise.
1357         * i386-dis-evex-reg.h: Likewise.
1358         * i386-dis-evex-w.h: Likewise.
1359         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1360         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1361         i386-dis-evex-mod.h.
1362
1363 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1364
1365         PR binutils/24700
1366         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1367         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1368         EVEX_W_0F385B_P_2.
1369         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1370         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1371         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1372         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1373         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1374         EVEX_LEN_0F385B_P_2_W_1.
1375         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1376         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1377         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1378         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1379         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1380         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1381         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1382         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1383         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1384         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1385
1386 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1387
1388         PR binutils/24691
1389         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1390         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1391         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1392         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1393         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1394         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1395         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1396         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1397         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1398         EVEX_LEN_0F3A43_P_2_W_1.
1399         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1400         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1401         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1402         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1403         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1404         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1405         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1406         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1407         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1408         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1409         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1410         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1411
1412 2019-06-14  Nick Clifton  <nickc@redhat.com>
1413
1414         * po/fr.po; Updated French translation.
1415
1416 2019-06-13  Stafford Horne  <shorne@gmail.com>
1417
1418         * or1k-asm.c: Regenerated.
1419         * or1k-desc.c: Regenerated.
1420         * or1k-desc.h: Regenerated.
1421         * or1k-dis.c: Regenerated.
1422         * or1k-ibld.c: Regenerated.
1423         * or1k-opc.c: Regenerated.
1424         * or1k-opc.h: Regenerated.
1425         * or1k-opinst.c: Regenerated.
1426
1427 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1428
1429         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1430
1431 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1432
1433         PR binutils/24633
1434         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1435         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1436         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1437         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1438         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1439         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1440         EVEX_LEN_0F3A1B_P_2_W_1.
1441         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1442         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1443         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1444         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1445         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1446         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1447         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1448         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1449
1450 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1451
1452         PR binutils/24626
1453         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1454         EVEX.vvvv when disassembling VEX and EVEX instructions.
1455         (OP_VEX): Set vex.register_specifier to 0 after readding
1456         vex.register_specifier.
1457         (OP_Vex_2src_1): Likewise.
1458         (OP_Vex_2src_2): Likewise.
1459         (OP_LWP_E): Likewise.
1460         (OP_EX_Vex): Don't check vex.register_specifier.
1461         (OP_XMM_Vex): Likewise.
1462
1463 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1464             Lili Cui  <lili.cui@intel.com>
1465
1466         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1467         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1468         instructions.
1469         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1470         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1471         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1472         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1473         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1474         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1475         * i386-init.h: Regenerated.
1476         * i386-tbl.h: Likewise.
1477
1478 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1479             Lili Cui  <lili.cui@intel.com>
1480
1481         * doc/c-i386.texi: Document enqcmd.
1482         * testsuite/gas/i386/enqcmd-intel.d: New file.
1483         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1484         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1485         * testsuite/gas/i386/enqcmd.d: Likewise.
1486         * testsuite/gas/i386/enqcmd.s: Likewise.
1487         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1488         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1489         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1490         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1491         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1492         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1493         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1494         and x86-64-enqcmd.
1495
1496 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1497
1498         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1499
1500 2019-06-03  Alan Modra  <amodra@gmail.com>
1501
1502         * ppc-dis.c (prefix_opcd_indices): Correct size.
1503
1504 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1505
1506         PR gas/24625
1507         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1508         Disp8ShiftVL.
1509         * i386-tbl.h: Regenerated.
1510
1511 2019-05-24  Alan Modra  <amodra@gmail.com>
1512
1513         * po/POTFILES.in: Regenerate.
1514
1515 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1516             Alan Modra  <amodra@gmail.com>
1517
1518         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1519         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1520         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1521         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1522         XTOP>): Define and add entries.
1523         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1524         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1525         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1526         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1527
1528 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1529             Alan Modra  <amodra@gmail.com>
1530
1531         * ppc-dis.c (ppc_opts): Add "future" entry.
1532         (PREFIX_OPCD_SEGS): Define.
1533         (prefix_opcd_indices): New array.
1534         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1535         (lookup_prefix): New function.
1536         (print_insn_powerpc): Handle 64-bit prefix instructions.
1537         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1538         (PMRR, POWERXX): Define.
1539         (prefix_opcodes): New instruction table.
1540         (prefix_num_opcodes): New constant.
1541
1542 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1543
1544         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1545         * configure: Regenerated.
1546         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1547         and cpu/bpf.opc.
1548         (HFILES): Add bpf-desc.h and bpf-opc.h.
1549         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1550         bpf-ibld.c and bpf-opc.c.
1551         (BPF_DEPS): Define.
1552         * Makefile.in: Regenerated.
1553         * disassemble.c (ARCH_bpf): Define.
1554         (disassembler): Add case for bfd_arch_bpf.
1555         (disassemble_init_for_target): Likewise.
1556         (enum epbf_isa_attr): Define.
1557         * disassemble.h: extern print_insn_bpf.
1558         * bpf-asm.c: Generated.
1559         * bpf-opc.h: Likewise.
1560         * bpf-opc.c: Likewise.
1561         * bpf-ibld.c: Likewise.
1562         * bpf-dis.c: Likewise.
1563         * bpf-desc.h: Likewise.
1564         * bpf-desc.c: Likewise.
1565
1566 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1567
1568         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1569         and VMSR with the new operands.
1570
1571 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1572
1573         * arm-dis.c (enum mve_instructions): New enum
1574         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1575         and cneg.
1576         (mve_opcodes): New instructions as above.
1577         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1578         csneg and csel.
1579         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1580
1581 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1582
1583         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1584         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1585         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1586         uqshl, urshrl and urshr.
1587         (is_mve_okay_in_it): Add new instructions to TRUE list.
1588         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1589         (print_insn_mve): Updated to accept new %j,
1590         %<bitfield>m and %<bitfield>n patterns.
1591
1592 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1593
1594         * mips-opc.c (mips_builtin_opcodes): Change source register
1595         constraint for DAUI.
1596
1597 2019-05-20  Nick Clifton  <nickc@redhat.com>
1598
1599         * po/fr.po: Updated French translation.
1600
1601 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1602             Michael Collison <michael.collison@arm.com>
1603
1604         * arm-dis.c (thumb32_opcodes): Add new instructions.
1605         (enum mve_instructions): Likewise.
1606         (enum mve_undefined): Add new reasons.
1607         (is_mve_encoding_conflict): Handle new instructions.
1608         (is_mve_undefined): Likewise.
1609         (is_mve_unpredictable): Likewise.
1610         (print_mve_undefined): Likewise.
1611         (print_mve_size): Likewise.
1612
1613 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1614             Michael Collison <michael.collison@arm.com>
1615
1616         * arm-dis.c (thumb32_opcodes): Add new instructions.
1617         (enum mve_instructions): Likewise.
1618         (is_mve_encoding_conflict): Handle new instructions.
1619         (is_mve_undefined): Likewise.
1620         (is_mve_unpredictable): Likewise.
1621         (print_mve_size): Likewise.
1622
1623 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1624             Michael Collison <michael.collison@arm.com>
1625
1626         * arm-dis.c (thumb32_opcodes): Add new instructions.
1627         (enum mve_instructions): Likewise.
1628         (is_mve_encoding_conflict): Likewise.
1629         (is_mve_unpredictable): Likewise.
1630         (print_mve_size): Likewise.
1631
1632 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1633             Michael Collison <michael.collison@arm.com>
1634
1635         * arm-dis.c (thumb32_opcodes): Add new instructions.
1636         (enum mve_instructions): Likewise.
1637         (is_mve_encoding_conflict): Handle new instructions.
1638         (is_mve_undefined): Likewise.
1639         (is_mve_unpredictable): Likewise.
1640         (print_mve_size): Likewise.
1641
1642 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1643             Michael Collison <michael.collison@arm.com>
1644
1645         * arm-dis.c (thumb32_opcodes): Add new instructions.
1646         (enum mve_instructions): Likewise.
1647         (is_mve_encoding_conflict): Handle new instructions.
1648         (is_mve_undefined): Likewise.
1649         (is_mve_unpredictable): Likewise.
1650         (print_mve_size): Likewise.
1651         (print_insn_mve): Likewise.
1652
1653 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1654             Michael Collison <michael.collison@arm.com>
1655
1656         * arm-dis.c (thumb32_opcodes): Add new instructions.
1657         (print_insn_thumb32): Handle new instructions.
1658
1659 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1660             Michael Collison <michael.collison@arm.com>
1661
1662         * arm-dis.c (enum mve_instructions): Add new instructions.
1663         (enum mve_undefined): Add new reasons.
1664         (is_mve_encoding_conflict): Handle new instructions.
1665         (is_mve_undefined): Likewise.
1666         (is_mve_unpredictable): Likewise.
1667         (print_mve_undefined): Likewise.
1668         (print_mve_size): Likewise.
1669         (print_mve_shift_n): Likewise.
1670         (print_insn_mve): Likewise.
1671
1672 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1673             Michael Collison <michael.collison@arm.com>
1674
1675         * arm-dis.c (enum mve_instructions): Add new instructions.
1676         (is_mve_encoding_conflict): Handle new instructions.
1677         (is_mve_unpredictable): Likewise.
1678         (print_mve_rotate): Likewise.
1679         (print_mve_size): Likewise.
1680         (print_insn_mve): Likewise.
1681
1682 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1683             Michael Collison <michael.collison@arm.com>
1684
1685         * arm-dis.c (enum mve_instructions): Add new instructions.
1686         (is_mve_encoding_conflict): Handle new instructions.
1687         (is_mve_unpredictable): Likewise.
1688         (print_mve_size): Likewise.
1689         (print_insn_mve): Likewise.
1690
1691 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1692             Michael Collison <michael.collison@arm.com>
1693
1694         * arm-dis.c (enum mve_instructions): Add new instructions.
1695         (enum mve_undefined): Add new reasons.
1696         (is_mve_encoding_conflict): Handle new instructions.
1697         (is_mve_undefined): Likewise.
1698         (is_mve_unpredictable): Likewise.
1699         (print_mve_undefined): Likewise.
1700         (print_mve_size): Likewise.
1701         (print_insn_mve): Likewise.
1702
1703 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1704             Michael Collison <michael.collison@arm.com>
1705
1706         * arm-dis.c (enum mve_instructions): Add new instructions.
1707         (is_mve_encoding_conflict): Handle new instructions.
1708         (is_mve_undefined): Likewise.
1709         (is_mve_unpredictable): Likewise.
1710         (print_mve_size): Likewise.
1711         (print_insn_mve): Likewise.
1712
1713 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1714             Michael Collison <michael.collison@arm.com>
1715
1716         * arm-dis.c (enum mve_instructions): Add new instructions.
1717         (enum mve_unpredictable): Add new reasons.
1718         (enum mve_undefined): Likewise.
1719         (is_mve_okay_in_it): Handle new isntructions.
1720         (is_mve_encoding_conflict): Likewise.
1721         (is_mve_undefined): Likewise.
1722         (is_mve_unpredictable): Likewise.
1723         (print_mve_vmov_index): Likewise.
1724         (print_simd_imm8): Likewise.
1725         (print_mve_undefined): Likewise.
1726         (print_mve_unpredictable): Likewise.
1727         (print_mve_size): Likewise.
1728         (print_insn_mve): Likewise.
1729
1730 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1731             Michael Collison <michael.collison@arm.com>
1732
1733         * arm-dis.c (enum mve_instructions): Add new instructions.
1734         (enum mve_unpredictable): Add new reasons.
1735         (enum mve_undefined): Likewise.
1736         (is_mve_encoding_conflict): Handle new instructions.
1737         (is_mve_undefined): Likewise.
1738         (is_mve_unpredictable): Likewise.
1739         (print_mve_undefined): Likewise.
1740         (print_mve_unpredictable): Likewise.
1741         (print_mve_rounding_mode): Likewise.
1742         (print_mve_vcvt_size): Likewise.
1743         (print_mve_size): Likewise.
1744         (print_insn_mve): Likewise.
1745
1746 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1747             Michael Collison <michael.collison@arm.com>
1748
1749         * arm-dis.c (enum mve_instructions): Add new instructions.
1750         (enum mve_unpredictable): Add new reasons.
1751         (enum mve_undefined): Likewise.
1752         (is_mve_undefined): Handle new instructions.
1753         (is_mve_unpredictable): Likewise.
1754         (print_mve_undefined): Likewise.
1755         (print_mve_unpredictable): Likewise.
1756         (print_mve_size): Likewise.
1757         (print_insn_mve): Likewise.
1758
1759 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1760             Michael Collison <michael.collison@arm.com>
1761
1762         * arm-dis.c (enum mve_instructions): Add new instructions.
1763         (enum mve_undefined): Add new reasons.
1764         (insns): Add new instructions.
1765         (is_mve_encoding_conflict):
1766         (print_mve_vld_str_addr): New print function.
1767         (is_mve_undefined): Handle new instructions.
1768         (is_mve_unpredictable): Likewise.
1769         (print_mve_undefined): Likewise.
1770         (print_mve_size): Likewise.
1771         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1772         (print_insn_mve):  Handle new operands.
1773
1774 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1775             Michael Collison <michael.collison@arm.com>
1776
1777         * arm-dis.c (enum mve_instructions): Add new instructions.
1778         (enum mve_unpredictable): Add new reasons.
1779         (is_mve_encoding_conflict): Handle new instructions.
1780         (is_mve_unpredictable): Likewise.
1781         (mve_opcodes): Add new instructions.
1782         (print_mve_unpredictable): Handle new reasons.
1783         (print_mve_register_blocks): New print function.
1784         (print_mve_size): Handle new instructions.
1785         (print_insn_mve): Likewise.
1786
1787 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1788             Michael Collison <michael.collison@arm.com>
1789
1790         * arm-dis.c (enum mve_instructions): Add new instructions.
1791         (enum mve_unpredictable): Add new reasons.
1792         (enum mve_undefined): Likewise.
1793         (is_mve_encoding_conflict): Handle new instructions.
1794         (is_mve_undefined): Likewise.
1795         (is_mve_unpredictable): Likewise.
1796         (coprocessor_opcodes): Move NEON VDUP from here...
1797         (neon_opcodes): ... to here.
1798         (mve_opcodes): Add new instructions.
1799         (print_mve_undefined):  Handle new reasons.
1800         (print_mve_unpredictable): Likewise.
1801         (print_mve_size): Handle new instructions.
1802         (print_insn_neon): Handle vdup.
1803         (print_insn_mve): Handle new operands.
1804
1805 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1806             Michael Collison <michael.collison@arm.com>
1807
1808         * arm-dis.c (enum mve_instructions): Add new instructions.
1809         (enum mve_unpredictable): Add new values.
1810         (mve_opcodes): Add new instructions.
1811         (vec_condnames): New array with vector conditions.
1812         (mve_predicatenames): New array with predicate suffixes.
1813         (mve_vec_sizename): New array with vector sizes.
1814         (enum vpt_pred_state): New enum with vector predication states.
1815         (struct vpt_block): New struct type for vpt blocks.
1816         (vpt_block_state): Global struct to keep track of state.
1817         (mve_extract_pred_mask): New helper function.
1818         (num_instructions_vpt_block): Likewise.
1819         (mark_outside_vpt_block): Likewise.
1820         (mark_inside_vpt_block): Likewise.
1821         (invert_next_predicate_state): Likewise.
1822         (update_next_predicate_state): Likewise.
1823         (update_vpt_block_state): Likewise.
1824         (is_vpt_instruction): Likewise.
1825         (is_mve_encoding_conflict): Add entries for new instructions.
1826         (is_mve_unpredictable): Likewise.
1827         (print_mve_unpredictable): Handle new cases.
1828         (print_instruction_predicate): Likewise.
1829         (print_mve_size): New function.
1830         (print_vec_condition): New function.
1831         (print_insn_mve): Handle vpt blocks and new print operands.
1832
1833 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1834
1835         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1836         8, 14 and 15 for Armv8.1-M Mainline.
1837
1838 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1839             Michael Collison <michael.collison@arm.com>
1840
1841         * arm-dis.c (enum mve_instructions): New enum.
1842         (enum mve_unpredictable): Likewise.
1843         (enum mve_undefined): Likewise.
1844         (struct mopcode32): New struct.
1845         (is_mve_okay_in_it): New function.
1846         (is_mve_architecture): Likewise.
1847         (arm_decode_field): Likewise.
1848         (arm_decode_field_multiple): Likewise.
1849         (is_mve_encoding_conflict): Likewise.
1850         (is_mve_undefined): Likewise.
1851         (is_mve_unpredictable): Likewise.
1852         (print_mve_undefined): Likewise.
1853         (print_mve_unpredictable): Likewise.
1854         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1855         (print_insn_mve): New function.
1856         (print_insn_thumb32): Handle MVE architecture.
1857         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1858
1859 2019-05-10  Nick Clifton  <nickc@redhat.com>
1860
1861         PR 24538
1862         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1863         end of the table prematurely.
1864
1865 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1866
1867         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1868         macros for R6.
1869
1870 2019-05-11  Alan Modra  <amodra@gmail.com>
1871
1872         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1873         when -Mraw is in effect.
1874
1875 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1876
1877         * aarch64-dis-2.c: Regenerate.
1878         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1879         (OP_SVE_BBB): New variant set.
1880         (OP_SVE_DDDD): New variant set.
1881         (OP_SVE_HHH): New variant set.
1882         (OP_SVE_HHHU): New variant set.
1883         (OP_SVE_SSS): New variant set.
1884         (OP_SVE_SSSU): New variant set.
1885         (OP_SVE_SHH): New variant set.
1886         (OP_SVE_SBBU): New variant set.
1887         (OP_SVE_DSS): New variant set.
1888         (OP_SVE_DHHU): New variant set.
1889         (OP_SVE_VMV_HSD_BHS): New variant set.
1890         (OP_SVE_VVU_HSD_BHS): New variant set.
1891         (OP_SVE_VVVU_SD_BH): New variant set.
1892         (OP_SVE_VVVU_BHSD): New variant set.
1893         (OP_SVE_VVV_QHD_DBS): New variant set.
1894         (OP_SVE_VVV_HSD_BHS): New variant set.
1895         (OP_SVE_VVV_HSD_BHS2): New variant set.
1896         (OP_SVE_VVV_BHS_HSD): New variant set.
1897         (OP_SVE_VV_BHS_HSD): New variant set.
1898         (OP_SVE_VVV_SD): New variant set.
1899         (OP_SVE_VVU_BHS_HSD): New variant set.
1900         (OP_SVE_VZVV_SD): New variant set.
1901         (OP_SVE_VZVV_BH): New variant set.
1902         (OP_SVE_VZV_SD): New variant set.
1903         (aarch64_opcode_table): Add sve2 instructions.
1904
1905 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1906
1907         * aarch64-asm-2.c: Regenerated.
1908         * aarch64-dis-2.c: Regenerated.
1909         * aarch64-opc-2.c: Regenerated.
1910         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1911         for SVE_SHLIMM_UNPRED_22.
1912         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1913         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1914         operand.
1915
1916 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1917
1918         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1919         sve_size_tsz_bhs iclass encode.
1920         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1921         sve_size_tsz_bhs iclass decode.
1922
1923 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1924
1925         * aarch64-asm-2.c: Regenerated.
1926         * aarch64-dis-2.c: Regenerated.
1927         * aarch64-opc-2.c: Regenerated.
1928         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1929         for SVE_Zm4_11_INDEX.
1930         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1931         (fields): Handle SVE_i2h field.
1932         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1933         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1934
1935 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1936
1937         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1938         sve_shift_tsz_bhsd iclass encode.
1939         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1940         sve_shift_tsz_bhsd iclass decode.
1941
1942 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1943
1944         * aarch64-asm-2.c: Regenerated.
1945         * aarch64-dis-2.c: Regenerated.
1946         * aarch64-opc-2.c: Regenerated.
1947         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1948         (aarch64_encode_variant_using_iclass): Handle
1949         sve_shift_tsz_hsd iclass encode.
1950         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1951         sve_shift_tsz_hsd iclass decode.
1952         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1953         for SVE_SHRIMM_UNPRED_22.
1954         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1955         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1956         operand.
1957
1958 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1959
1960         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1961         sve_size_013 iclass encode.
1962         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1963         sve_size_013 iclass decode.
1964
1965 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1966
1967         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1968         sve_size_bh iclass encode.
1969         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1970         sve_size_bh iclass decode.
1971
1972 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1973
1974         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1975         sve_size_sd2 iclass encode.
1976         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1977         sve_size_sd2 iclass decode.
1978         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1979         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1980
1981 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1982
1983         * aarch64-asm-2.c: Regenerated.
1984         * aarch64-dis-2.c: Regenerated.
1985         * aarch64-opc-2.c: Regenerated.
1986         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1987         for SVE_ADDR_ZX.
1988         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1989         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1990
1991 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1992
1993         * aarch64-asm-2.c: Regenerated.
1994         * aarch64-dis-2.c: Regenerated.
1995         * aarch64-opc-2.c: Regenerated.
1996         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1997         for SVE_Zm3_11_INDEX.
1998         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1999         (fields): Handle SVE_i3l and SVE_i3h2 fields.
2000         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
2001         fields.
2002         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
2003
2004 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
2005
2006         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
2007         sve_size_hsd2 iclass encode.
2008         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
2009         sve_size_hsd2 iclass decode.
2010         * aarch64-opc.c (fields): Handle SVE_size field.
2011         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
2012
2013 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
2014
2015         * aarch64-asm-2.c: Regenerated.
2016         * aarch64-dis-2.c: Regenerated.
2017         * aarch64-opc-2.c: Regenerated.
2018         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
2019         for SVE_IMM_ROT3.
2020         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
2021         (fields): Handle SVE_rot3 field.
2022         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
2023         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2024
2025 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
2026
2027         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
2028         instructions.
2029
2030 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
2031
2032         * aarch64-tbl.h
2033         (aarch64_feature_sve2, aarch64_feature_sve2aes,
2034         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
2035         aarch64_feature_sve2bitperm): New feature sets.
2036         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
2037         for feature set addresses.
2038         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
2039         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2040
2041 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
2042             Faraz Shahbazker  <fshahbazker@wavecomp.com>
2043
2044         * mips-dis.c (mips_calculate_combination_ases): Add ISA
2045         argument and set ASE_EVA_R6 appropriately.
2046         (set_default_mips_dis_options): Pass ISA to above.
2047         (parse_mips_dis_option): Likewise.
2048         * mips-opc.c (EVAR6): New macro.
2049         (mips_builtin_opcodes): Add llwpe, scwpe.
2050
2051 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
2052
2053         * aarch64-asm-2.c: Regenerated.
2054         * aarch64-dis-2.c: Regenerated.
2055         * aarch64-opc-2.c: Regenerated.
2056         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2057         AARCH64_OPND_TME_UIMM16.
2058         (aarch64_print_operand): Likewise.
2059         * aarch64-tbl.h (QL_IMM_NIL): New.
2060         (TME): New.
2061         (_TME_INSN): New.
2062         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2063
2064 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
2065
2066         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2067
2068 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
2069             Faraz Shahbazker  <fshahbazker@wavecomp.com>
2070
2071         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2072
2073 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
2074
2075         * s12z-opc.h: Add extern "C" bracketing to help
2076         users who wish to use this interface in c++ code.
2077
2078 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
2079
2080         * s12z-opc.c (bm_decode): Handle bit map operations with the
2081         "reserved0" mode.
2082
2083 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2084
2085         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2086         specifier.  Add entries for VLDR and VSTR of system registers.
2087         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2088         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
2089         of %J and %K format specifier.
2090
2091 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2092
2093         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2094         Add new entries for VSCCLRM instruction.
2095         (print_insn_coprocessor): Handle new %C format control code.
2096
2097 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2098
2099         * arm-dis.c (enum isa): New enum.
2100         (struct sopcode32): New structure.
2101         (coprocessor_opcodes): change type of entries to struct sopcode32 and
2102         set isa field of all current entries to ANY.
2103         (print_insn_coprocessor): Change type of insn to struct sopcode32.
2104         Only match an entry if its isa field allows the current mode.
2105
2106 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2107
2108         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
2109         CLRM.
2110         (print_insn_thumb32): Add logic to print %n CLRM register list.
2111
2112 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2113
2114         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2115         and %Q patterns.
2116
2117 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2118
2119         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2120         (print_insn_thumb32): Edit the switch case for %Z.
2121
2122 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2123
2124         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2125
2126 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2127
2128         * arm-dis.c (thumb32_opcodes): New instruction bfl.
2129
2130 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2131
2132         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2133
2134 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2135
2136         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2137         Arm register with r13 and r15 unpredictable.
2138         (thumb32_opcodes): New instructions for bfx and bflx.
2139
2140 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2141
2142         * arm-dis.c (thumb32_opcodes): New instructions for bf.
2143
2144 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2145
2146         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2147
2148 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2149
2150         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2151
2152 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2153
2154         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2155
2156 2019-04-12  John Darrington <john@darrington.wattle.id.au>
2157
2158         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2159         "optr". ("operator" is a reserved word in c++).
2160
2161 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2162
2163         * aarch64-opc.c (aarch64_print_operand): Add case for
2164         AARCH64_OPND_Rt_SP.
2165         (verify_constraints): Likewise.
2166         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2167         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2168         to accept Rt|SP as first operand.
2169         (AARCH64_OPERANDS): Add new Rt_SP.
2170         * aarch64-asm-2.c: Regenerated.
2171         * aarch64-dis-2.c: Regenerated.
2172         * aarch64-opc-2.c: Regenerated.
2173
2174 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2175
2176         * aarch64-asm-2.c: Regenerated.
2177         * aarch64-dis-2.c: Likewise.
2178         * aarch64-opc-2.c: Likewise.
2179         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2180
2181 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2182
2183         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2184
2185 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2186
2187         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2188         * i386-init.h: Regenerated.
2189
2190 2019-04-07  Alan Modra  <amodra@gmail.com>
2191
2192         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2193         op_separator to control printing of spaces, comma and parens
2194         rather than need_comma, need_paren and spaces vars.
2195
2196 2019-04-07  Alan Modra  <amodra@gmail.com>
2197
2198         PR 24421
2199         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2200         (print_insn_neon, print_insn_arm): Likewise.
2201
2202 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2203
2204         * i386-dis-evex.h (evex_table): Updated to support BF16
2205         instructions.
2206         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2207         and EVEX_W_0F3872_P_3.
2208         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2209         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2210         * i386-opc.h (enum): Add CpuAVX512_BF16.
2211         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2212         * i386-opc.tbl: Add AVX512 BF16 instructions.
2213         * i386-init.h: Regenerated.
2214         * i386-tbl.h: Likewise.
2215
2216 2019-04-05  Alan Modra  <amodra@gmail.com>
2217
2218         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2219         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2220         to favour printing of "-" branch hint when using the "y" bit.
2221         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2222
2223 2019-04-05  Alan Modra  <amodra@gmail.com>
2224
2225         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2226         opcode until first operand is output.
2227
2228 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2229
2230         PR gas/24349
2231         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2232         (valid_bo_post_v2): Add support for 'at' branch hints.
2233         (insert_bo): Only error on branch on ctr.
2234         (get_bo_hint_mask): New function.
2235         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2236         for inserting 'at' branch hints.
2237         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2238         for extracting 'at' branch hints.
2239         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2240         (BOE): Delete operand.
2241         (BOM, BOP): New operands.
2242         (RM): Update value.
2243         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2244         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2245         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2246         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2247         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2248         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2249         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2250         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2251         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2252         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2253         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2254         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2255         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2256         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2257         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2258         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2259         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2260         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2261         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2262         bttarl+>: New extended mnemonics.
2263
2264 2019-03-28  Alan Modra  <amodra@gmail.com>
2265
2266         PR 24390
2267         * ppc-opc.c (BTF): Define.
2268         (powerpc_opcodes): Use for mtfsb*.
2269         * ppc-dis.c (print_insn_powerpc): Print fields with both
2270         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2271
2272 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2273
2274         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2275         (mapping_symbol_for_insn): Implement new algorithm.
2276         (print_insn): Remove duplicate code.
2277
2278 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2279
2280         * aarch64-dis.c (print_insn_aarch64):
2281         Implement override.
2282
2283 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2284
2285         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2286         order.
2287
2288 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2289
2290         * aarch64-dis.c (last_stop_offset): New.
2291         (print_insn_aarch64): Use stop_offset.
2292
2293 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2294
2295         PR gas/24359
2296         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2297         CPU_ANY_AVX2_FLAGS.
2298         * i386-init.h: Regenerated.
2299
2300 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2301
2302         PR gas/24348
2303         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2304         vmovdqu16, vmovdqu32 and vmovdqu64.
2305         * i386-tbl.h: Regenerated.
2306
2307 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2308
2309         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2310         from vstrszb, vstrszh, and vstrszf.
2311
2312 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2313
2314         * s390-opc.txt: Add instruction descriptions.
2315
2316 2019-02-08  Jim Wilson  <jimw@sifive.com>
2317
2318         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2319         <bne>: Likewise.
2320
2321 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2322
2323         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2324
2325 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2326
2327         PR binutils/23212
2328         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2329         * aarch64-opc.c (verify_elem_sd): New.
2330         (fields): Add FLD_sz entr.
2331         * aarch64-tbl.h (_SIMD_INSN): New.
2332         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2333         fmulx scalar and vector by element isns.
2334
2335 2019-02-07  Nick Clifton  <nickc@redhat.com>
2336
2337         * po/sv.po: Updated Swedish translation.
2338
2339 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2340
2341         * s390-mkopc.c (main): Accept arch13 as cpu string.
2342         * s390-opc.c: Add new instruction formats and instruction opcode
2343         masks.
2344         * s390-opc.txt: Add new arch13 instructions.
2345
2346 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2347
2348         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2349         (aarch64_opcode): Change encoding for stg, stzg
2350         st2g and st2zg.
2351         * aarch64-asm-2.c: Regenerated.
2352         * aarch64-dis-2.c: Regenerated.
2353         * aarch64-opc-2.c: Regenerated.
2354
2355 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2356
2357         * aarch64-asm-2.c: Regenerated.
2358         * aarch64-dis-2.c: Likewise.
2359         * aarch64-opc-2.c: Likewise.
2360         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2361
2362 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2363             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2364
2365         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2366         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2367         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2368         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2369         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2370         case for ldstgv_indexed.
2371         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2372         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2373         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2374         * aarch64-asm-2.c: Regenerated.
2375         * aarch64-dis-2.c: Regenerated.
2376         * aarch64-opc-2.c: Regenerated.
2377
2378 2019-01-23  Nick Clifton  <nickc@redhat.com>
2379
2380         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2381
2382 2019-01-21  Nick Clifton  <nickc@redhat.com>
2383
2384         * po/de.po: Updated German translation.
2385         * po/uk.po: Updated Ukranian translation.
2386
2387 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2388         * mips-dis.c (mips_arch_choices): Fix typo in
2389         gs464, gs464e and gs264e descriptors.
2390
2391 2019-01-19  Nick Clifton  <nickc@redhat.com>
2392
2393         * configure: Regenerate.
2394         * po/opcodes.pot: Regenerate.
2395
2396 2018-06-24  Nick Clifton  <nickc@redhat.com>
2397
2398         2.32 branch created.
2399
2400 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2401
2402         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2403         if it is null.
2404         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2405         zero.
2406
2407 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2408
2409         * configure: Regenerate.
2410
2411 2019-01-07  Alan Modra  <amodra@gmail.com>
2412
2413         * configure: Regenerate.
2414         * po/POTFILES.in: Regenerate.
2415
2416 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2417
2418         * s12z-opc.c: New file.
2419         * s12z-opc.h: New file.
2420         * s12z-dis.c: Removed all code not directly related to display
2421         of instructions.  Used the interface provided by the new files
2422         instead.
2423         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2424         * Makefile.in: Regenerate.
2425         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2426         * configure: Regenerate.
2427
2428 2019-01-01  Alan Modra  <amodra@gmail.com>
2429
2430         Update year range in copyright notice of all files.
2431
2432 For older changes see ChangeLog-2018
2433 \f
2434 Copyright (C) 2019 Free Software Foundation, Inc.
2435
2436 Copying and distribution of this file, with or without modification,
2437 are permitted in any medium without royalty provided the copyright
2438 notice and this notice are preserved.
2439
2440 Local Variables:
2441 mode: change-log
2442 left-margin: 8
2443 fill-column: 74
2444 version-control: never
2445 End: