opcodes/ChangeLog

   1 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
   2
   3         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
   4
   5 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
   6
   7         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
   8         with arc_opcode_len.
   9         (find_format_long_instructions): Likewise.
  10         * arc-opc.c (arc_opcode_len): New function.
  11
  12 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
  13
  14         * arc-nps400-tbl.h: Fix some instruction masks.
  15
  16 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
  17
  18         * i386-dis.c (REG_82): Removed.
  19         (X86_64_82_REG_0): Likewise.
  20         (X86_64_82_REG_1): Likewise.
  21         (X86_64_82_REG_2): Likewise.
  22         (X86_64_82_REG_3): Likewise.
  23         (X86_64_82_REG_4): Likewise.
  24         (X86_64_82_REG_5): Likewise.
  25         (X86_64_82_REG_6): Likewise.
  26         (X86_64_82_REG_7): Likewise.
  27         (X86_64_82): New.
  28         (dis386): Use X86_64_82 instead of REG_82.
  29         (reg_table): Remove REG_82.
  30         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
  31         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
  32         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
  33         X86_64_82_REG_7.
  34
  35 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
  36
  37         PR binutils/20754
  38         * i386-dis.c (REG_82): New.
  39         (X86_64_82_REG_0): Likewise.
  40         (X86_64_82_REG_1): Likewise.
  41         (X86_64_82_REG_2): Likewise.
  42         (X86_64_82_REG_3): Likewise.
  43         (X86_64_82_REG_4): Likewise.
  44         (X86_64_82_REG_5): Likewise.
  45         (X86_64_82_REG_6): Likewise.
  46         (X86_64_82_REG_7): Likewise.
  47         (dis386): Use REG_82.
  48         (reg_table): Add REG_82.
  49         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
  50         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
  51         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
  52
  53 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
  54
  55         * i386-dis.c (REG_82): Renamed to ...
  56         (REG_83): This.
  57         (dis386): Updated.
  58         (reg_table): Likewise.
  59
  60 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  61
  62         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
  63         * i386-dis-evex.h (evex_table): Updated.
  64         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
  65         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  66         (cpu_flags): Add CpuAVX512_4VNNIW.
  67         * i386-opc.h (enum): (AVX512_4VNNIW): New.
  68         (i386_cpu_flags): Add cpuavx512_4vnniw.
  69         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
  70         * i386-init.h: Regenerate.
  71         * i386-tbl.h: Ditto.
  72
  73 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  74
  75         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
  76         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
  77         * i386-dis-evex.h (evex_table): Updated.
  78         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
  79         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  80         (cpu_flags): Add CpuAVX512_4FMAPS.
  81         (opcode_modifiers): Add ImplicitQuadGroup modifier.
  82         * i386-opc.h (AVX512_4FMAP): New.
  83         (i386_cpu_flags): Add cpuavx512_4fmaps.
  84         (ImplicitQuadGroup): New.
  85         (i386_opcode_modifier): Add implicitquadgroup.
  86         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
  87         * i386-init.h: Regenerate.
  88         * i386-tbl.h: Ditto.
  89
  90 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
  91             Andrew Waterman <andrew@sifive.com>
  92
  93         Add support for RISC-V architecture.
  94         * configure.ac: Add entry for bfd_riscv_arch.
  95         * configure: Regenerate.
  96         * disassemble.c (disassembler): Add support for riscv.
  97         (disassembler_usage): Likewise.
  98         * riscv-dis.c: New file.
  99         * riscv-opc.c: New file.
 100
 101 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 102
 103         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 104         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 105         (rm_table): Update the RM_0FAE_REG_7 entry.
 106         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 107         (cpu_flags): Remove CpuPCOMMIT.
 108         * i386-opc.h (CpuPCOMMIT): Removed.
 109         (i386_cpu_flags): Remove cpupcommit.
 110         * i386-opc.tbl: Remove pcommit.
 111         * i386-init.h: Regenerated.
 112         * i386-tbl.h: Likewise.
 113
 114 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 115
 116         PR binutis/20705
 117         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 118         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 119         32-bit mode.  Don't check vex.register_specifier in 32-bit
 120         mode.
 121         (OP_VEX): Check for invalid mask registers.
 122
 123 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         PR binutis/20699
 126         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 127         sizeflag.
 128
 129 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 130
 131         PR binutis/20704
 132         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 133
 134 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 135
 136         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 137         local variable to `index_regno'.
 138
 139 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 140
 141         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 142
 143 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 144
 145         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 146         usage on ISA basis.
 147
 148 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 149
 150         PR target/20666
 151         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 152
 153 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 154
 155         PR target/20667
 156         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 157         available.
 158
 159 2016-10-07  Alan Modra  <amodra@gmail.com>
 160
 161         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 162
 163 2016-10-06  Alan Modra  <amodra@gmail.com>
 164
 165         * aarch64-opc.c: Spell fall through comments consistently.
 166         * i386-dis.c: Likewise.
 167         * aarch64-dis.c: Add missing fall through comments.
 168         * aarch64-opc.c: Likewise.
 169         * arc-dis.c: Likewise.
 170         * arm-dis.c: Likewise.
 171         * i386-dis.c: Likewise.
 172         * m68k-dis.c: Likewise.
 173         * mep-asm.c: Likewise.
 174         * ns32k-dis.c: Likewise.
 175         * sh-dis.c: Likewise.
 176         * tic4x-dis.c: Likewise.
 177         * tic6x-dis.c: Likewise.
 178         * vax-dis.c: Likewise.
 179
 180 2016-10-06  Alan Modra  <amodra@gmail.com>
 181
 182         * arc-ext.c (create_map): Add missing break.
 183         * msp430-decode.opc (encode_as): Likewise.
 184         * msp430-decode.c: Regenerate.
 185
 186 2016-10-06  Alan Modra  <amodra@gmail.com>
 187
 188         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 189         * crx-dis.c (print_insn_crx): Likewise.
 190
 191 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         PR binutils/20657
 194         * i386-dis.c (putop): Don't assign alt twice.
 195
 196 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 197
 198         PR target/20553
 199         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 200
 201 2016-09-29  Alan Modra  <amodra@gmail.com>
 202
 203         * ppc-opc.c (L): Make compulsory.
 204         (LOPT): New, optional form of L.
 205         (HTM_R): Define as LOPT.
 206         (L0, L1): Delete.
 207         (L32OPT): New, optional for 32-bit L.
 208         (L2OPT): New, 2-bit L for dcbf.
 209         (SVC_LEC): Update.
 210         (L2): Define.
 211         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 212         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 213         <dcbf>: Use L2OPT.
 214         <tlbiel, tlbie>: Use LOPT.
 215         <wclr, wclrall>: Use L2.
 216
 217 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 218
 219         * Makefile.in: Regenerate.
 220         * configure: Likewise.
 221
 222 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 223
 224         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 225         (EXTINSN2OP): Use EXTINSN2OPF.
 226         (bspeekm, bspop, modapp): New extension instructions.
 227         * arc-opc.c (F_DNZ_ND): Define.
 228         (F_DNZ_D): Likewise.
 229         (F_SIZEB1): Changed.
 230         (C_DNZ_D): Define.
 231         (C_HARD): Changed.
 232         * arc-tbl.h (dbnz): New instruction.
 233         (prealloc): Allow it for ARC EM.
 234         (xbfu): Likewise.
 235
 236 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 237
 238         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 239         after commas in addresses.
 240         (aarch64_print_operand): Likewise.
 241
 242 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 243
 244         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 245         rather than "should be" or "expected to be" in error messages.
 246
 247 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 248
 249         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 250         (print_mnemonic_name): ...here.
 251         (print_comment): New function.
 252         (print_aarch64_insn): Call it.
 253         * aarch64-opc.c (aarch64_conds): Add SVE names.
 254         (aarch64_print_operand): Print alternative condition names in
 255         a comment.
 256
 257 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 258
 259         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 260         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 261         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 262         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 263         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 264         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 265         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 266         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 267         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 268         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 269         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 270         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 271         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 272         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 273         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 274         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 275         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 276         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 277         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 278         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 279         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 280         (aarch64_feature_sve): New variable.
 281         (SVE): New macro.
 282         (_SVE_INSN): Likewise.
 283         (aarch64_opcode_table): Add SVE instructions.
 284         * aarch64-opc.h (extract_fields): Declare.
 285         * aarch64-opc-2.c: Regenerate.
 286         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 287         * aarch64-asm-2.c: Regenerate.
 288         * aarch64-dis.c (extract_fields): Make global.
 289         (do_misc_decoding): Handle the new SVE aarch64_ops.
 290         * aarch64-dis-2.c: Regenerate.
 291
 292 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 293
 294         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 295         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 296         aarch64_field_kinds.
 297         * aarch64-opc.c (fields): Add corresponding entries.
 298         * aarch64-asm.c (aarch64_get_variant): New function.
 299         (aarch64_encode_variant_using_iclass): Likewise.
 300         (aarch64_opcode_encode): Call it.
 301         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 302         (aarch64_opcode_decode): Call it.
 303
 304 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 305
 306         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 307         and FP register operands.
 308         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 309         (FLD_SVE_Vn): New aarch64_field_kinds.
 310         * aarch64-opc.c (fields): Add corresponding entries.
 311         (aarch64_print_operand): Handle the new SVE core and FP register
 312         operands.
 313         * aarch64-opc-2.c: Regenerate.
 314         * aarch64-asm-2.c: Likewise.
 315         * aarch64-dis-2.c: Likewise.
 316
 317 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 318
 319         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 320         immediate operands.
 321         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 322         * aarch64-opc.c (fields): Add corresponding entry.
 323         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 324         operands.
 325         (aarch64_print_operand): Likewise.
 326         * aarch64-opc-2.c: Regenerate.
 327         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 328         (ins_sve_float_zero_one): New inserters.
 329         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 330         (aarch64_ins_sve_float_half_two): Likewise.
 331         (aarch64_ins_sve_float_zero_one): Likewise.
 332         * aarch64-asm-2.c: Regenerate.
 333         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 334         (ext_sve_float_zero_one): New extractors.
 335         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 336         (aarch64_ext_sve_float_half_two): Likewise.
 337         (aarch64_ext_sve_float_zero_one): Likewise.
 338         * aarch64-dis-2.c: Regenerate.
 339
 340 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 341
 342         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 343         integer immediate operands.
 344         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 345         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 346         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 347         * aarch64-opc.c (fields): Add corresponding entries.
 348         (operand_general_constraint_met_p): Handle the new SVE integer
 349         immediate operands.
 350         (aarch64_print_operand): Likewise.
 351         (aarch64_sve_dupm_mov_immediate_p): New function.
 352         * aarch64-opc-2.c: Regenerate.
 353         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 354         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 355         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 356         (aarch64_ins_limm): ...here.
 357         (aarch64_ins_inv_limm): New function.
 358         (aarch64_ins_sve_aimm): Likewise.
 359         (aarch64_ins_sve_asimm): Likewise.
 360         (aarch64_ins_sve_limm_mov): Likewise.
 361         (aarch64_ins_sve_shlimm): Likewise.
 362         (aarch64_ins_sve_shrimm): Likewise.
 363         * aarch64-asm-2.c: Regenerate.
 364         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 365         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 366         * aarch64-dis.c (decode_limm): New function, split out from...
 367         (aarch64_ext_limm): ...here.
 368         (aarch64_ext_inv_limm): New function.
 369         (decode_sve_aimm): Likewise.
 370         (aarch64_ext_sve_aimm): Likewise.
 371         (aarch64_ext_sve_asimm): Likewise.
 372         (aarch64_ext_sve_limm_mov): Likewise.
 373         (aarch64_top_bit): Likewise.
 374         (aarch64_ext_sve_shlimm): Likewise.
 375         (aarch64_ext_sve_shrimm): Likewise.
 376         * aarch64-dis-2.c: Regenerate.
 377
 378 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 379
 380         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 381         operands.
 382         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 383         the AARCH64_MOD_MUL_VL entry.
 384         (value_aligned_p): Cope with non-power-of-two alignments.
 385         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 386         (print_immediate_offset_address): Likewise.
 387         (aarch64_print_operand): Likewise.
 388         * aarch64-opc-2.c: Regenerate.
 389         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 390         (ins_sve_addr_ri_s9xvl): New inserters.
 391         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 392         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 393         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 394         * aarch64-asm-2.c: Regenerate.
 395         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 396         (ext_sve_addr_ri_s9xvl): New extractors.
 397         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 398         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 399         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 400         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 401         * aarch64-dis-2.c: Regenerate.
 402
 403 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 404
 405         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 406         address operands.
 407         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 408         (FLD_SVE_xs_22): New aarch64_field_kinds.
 409         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 410         (get_operand_specific_data): New function.
 411         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 412         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 413         (operand_general_constraint_met_p): Handle the new SVE address
 414         operands.
 415         (sve_reg): New array.
 416         (get_addr_sve_reg_name): New function.
 417         (aarch64_print_operand): Handle the new SVE address operands.
 418         * aarch64-opc-2.c: Regenerate.
 419         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 420         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 421         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 422         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 423         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 424         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 425         (aarch64_ins_sve_addr_zi_u5): Likewise.
 426         (aarch64_ins_sve_addr_zz): Likewise.
 427         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 428         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 429         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 430         * aarch64-asm-2.c: Regenerate.
 431         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 432         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 433         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 434         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 435         (aarch64_ext_sve_addr_ri_u6): Likewise.
 436         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 437         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 438         (aarch64_ext_sve_addr_zi_u5): Likewise.
 439         (aarch64_ext_sve_addr_zz): Likewise.
 440         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 441         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 442         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 443         * aarch64-dis-2.c: Regenerate.
 444
 445 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 446
 447         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 448         AARCH64_OPND_SVE_PATTERN_SCALED.
 449         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 450         * aarch64-opc.c (fields): Add a corresponding entry.
 451         (set_multiplier_out_of_range_error): New function.
 452         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 453         (operand_general_constraint_met_p): Handle
 454         AARCH64_OPND_SVE_PATTERN_SCALED.
 455         (print_register_offset_address): Use PRIi64 to print the
 456         shift amount.
 457         (aarch64_print_operand): Likewise.  Handle
 458         AARCH64_OPND_SVE_PATTERN_SCALED.
 459         * aarch64-opc-2.c: Regenerate.
 460         * aarch64-asm.h (ins_sve_scale): New inserter.
 461         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 462         * aarch64-asm-2.c: Regenerate.
 463         * aarch64-dis.h (ext_sve_scale): New inserter.
 464         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 465         * aarch64-dis-2.c: Regenerate.
 466
 467 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 468
 469         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 470         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 471         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 472         (FLD_SVE_prfop): Likewise.
 473         * aarch64-opc.c: Include libiberty.h.
 474         (aarch64_sve_pattern_array): New variable.
 475         (aarch64_sve_prfop_array): Likewise.
 476         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 477         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 478         AARCH64_OPND_SVE_PRFOP.
 479         * aarch64-asm-2.c: Regenerate.
 480         * aarch64-dis-2.c: Likewise.
 481         * aarch64-opc-2.c: Likewise.
 482
 483 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 484
 485         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 486         AARCH64_OPND_QLF_P_[ZM].
 487         (aarch64_print_operand): Print /z and /m where appropriate.
 488
 489 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 490
 491         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 492         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 493         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 494         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 495         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 496         * aarch64-opc.c (fields): Add corresponding entries here.
 497         (operand_general_constraint_met_p): Check that SVE register lists
 498         have the correct length.  Check the ranges of SVE index registers.
 499         Check for cases where p8-p15 are used in 3-bit predicate fields.
 500         (aarch64_print_operand): Handle the new SVE operands.
 501         * aarch64-opc-2.c: Regenerate.
 502         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 503         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 504         (aarch64_ins_sve_reglist): Likewise.
 505         * aarch64-asm-2.c: Regenerate.
 506         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 507         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 508         (aarch64_ext_sve_reglist): Likewise.
 509         * aarch64-dis-2.c: Regenerate.
 510
 511 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 512
 513         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 514         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 515         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 516         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 517         tied operands.
 518
 519 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 520
 521         * aarch64-opc.c (get_offset_int_reg_name): New function.
 522         (print_immediate_offset_address): Likewise.
 523         (print_register_offset_address): Take the base and offset
 524         registers as parameters.
 525         (aarch64_print_operand): Update caller accordingly.  Use
 526         print_immediate_offset_address.
 527
 528 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 529
 530         * aarch64-opc.c (BANK): New macro.
 531         (R32, R64): Take a register number as argument
 532         (int_reg): Use BANK.
 533
 534 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 535
 536         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 537         (aarch64_print_operand): Update accordingly.
 538
 539 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 540
 541         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 542         for FPIMM.
 543         * aarch64-asm.h (ins_fpimm): New inserter.
 544         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 545         * aarch64-asm-2.c: Regenerate.
 546         * aarch64-dis.h (ext_fpimm): New extractor.
 547         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 548         (aarch64_ext_fpimm): New function.
 549         * aarch64-dis-2.c: Regenerate.
 550
 551 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 552
 553         * aarch64-asm.c: Include libiberty.h.
 554         (insert_fields): New function.
 555         (aarch64_ins_imm): Use it.
 556         * aarch64-dis.c (extract_fields): New function.
 557         (aarch64_ext_imm): Use it.
 558
 559 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 560
 561         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 562         with an esize parameter.
 563         (operand_general_constraint_met_p): Update accordingly.
 564         Fix misindented code.
 565         * aarch64-asm.c (aarch64_ins_limm): Update call to
 566         aarch64_logical_immediate_p.
 567
 568 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 569
 570         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 571
 572 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 573
 574         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 575
 576 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 577
 578         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 579
 580 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 581
 582         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 583         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 584         xor3>: Delete mnemonics.
 585         <cp_abort>: Rename mnemonic from ...
 586         <cpabort>: ...to this.
 587         <setb>: Change to a X form instruction.
 588         <sync>: Change to 1 operand form.
 589         <copy>: Delete mnemonic.
 590         <copy_first>: Rename mnemonic from ...
 591         <copy>: ...to this.
 592         <paste, paste.>: Delete mnemonics.
 593         <paste_last>: Rename mnemonic from ...
 594         <paste.>: ...to this.
 595
 596 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 597
 598         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 599
 600 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 601
 602         * s390-mkopc.c (main): Support alternate arch strings.
 603
 604 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 605
 606         * s390-opc.txt: Fix kmctr instruction type.
 607
 608 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 609
 610         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 611         * i386-init.h: Regenerated.
 612
 613 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 614
 615         * opcodes/arc-dis.c (print_insn_arc): Changed.
 616
 617 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 618
 619         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 620         camellia_fl.
 621
 622 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 623
 624         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 625         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 626         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 627
 628 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 629
 630         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 631         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 632         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 633         PREFIX_MOD_3_0FAE_REG_4.
 634         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 635         PREFIX_MOD_3_0FAE_REG_4.
 636         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 637         (cpu_flags): Add CpuPTWRITE.
 638         * i386-opc.h (CpuPTWRITE): New.
 639         (i386_cpu_flags): Add cpuptwrite.
 640         * i386-opc.tbl: Add ptwrite instruction.
 641         * i386-init.h: Regenerated.
 642         * i386-tbl.h: Likewise.
 643
 644 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 645
 646         * arc-dis.h: Wrap around in extern "C".
 647
 648 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 649
 650         * aarch64-tbl.h (V8_2_INSN): New macro.
 651         (aarch64_opcode_table): Use it.
 652
 653 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 654
 655         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 656         CORE_INSN, __FP_INSN and SIMD_INSN.
 657
 658 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 659
 660         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 661         (aarch64_opcode_table): Update uses accordingly.
 662
 663 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 664         Kwok Cheung Yeung  <kcy@codesourcery.com>
 665
 666         opcodes/
 667         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 668         'e_cmplwi' to 'e_cmpli' instead.
 669         (OPVUPRT, OPVUPRT_MASK): Define.
 670         (powerpc_opcodes): Add E200Z4 insns.
 671         (vle_opcodes): Add context save/restore insns.
 672
 673 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 674
 675         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 676         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 677         "j".
 678
 679 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 680
 681         * arc-nps400-tbl.h: Change block comments to GNU format.
 682         * arc-dis.c: Add new globals addrtypenames,
 683         addrtypenames_max, and addtypeunknown.
 684         (get_addrtype): New function.
 685         (print_insn_arc): Print colons and address types when
 686         required.
 687         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 688         define insert and extract functions for all address types.
 689         (arc_operands): Add operands for colon and all address
 690         types.
 691         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 692         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 693         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 694         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 695         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 696         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 697
 698 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 699
 700         * configure: Regenerated.
 701
 702 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 703
 704         * arc-dis.c (skipclass): New structure.
 705         (decodelist): New variable.
 706         (is_compatible_p): New function.
 707         (new_element): Likewise.
 708         (skip_class_p): Likewise.
 709         (find_format_from_table): Use skip_class_p function.
 710         (find_format): Decode first the extension instructions.
 711         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 712         e_flags.
 713         (parse_option): New function.
 714         (parse_disassembler_options): Likewise.
 715         (print_arc_disassembler_options): Likewise.
 716         (print_insn_arc): Use parse_disassembler_options function.  Proper
 717         select ARCv2 cpu variant.
 718         * disassemble.c (disassembler_usage): Add ARC disassembler
 719         options.
 720
 721 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 722
 723         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 724         annotation from the "nal" entry and reorder it beyond "bltzal".
 725
 726 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 727
 728         * sparc-opc.c (ldtxa): New macro.
 729         (sparc_opcodes): Use the macro defined above to add entries for
 730         the LDTXA instructions.
 731         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 732         instruction.
 733
 734 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 735
 736         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 737         and "jmpc".
 738
 739 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 742         (movzb): Adjust to cover all permitted suffixes.
 743         (movzw): New.
 744         * i386-tbl.h: Re-generate.
 745
 746 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 749         (lgdt): Remove Tbyte from non-64-bit variant.
 750         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 751         xsaves64, xsavec64): Remove Disp16.
 752         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 753         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 754         64-bit variants.
 755         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 756         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 757         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 758         64-bit variants.
 759         * i386-tbl.h: Re-generate.
 760
 761 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 764         * i386-tbl.h: Re-generate.
 765
 766 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 767
 768         * arm-dis.c (print_insn): Fix typo in comment.
 769
 770 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 771
 772         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 773         range of ldst_elemlist operands.
 774         (print_register_list): Use PRIi64 to print the index.
 775         (aarch64_print_operand): Likewise.
 776
 777 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 778
 779         * mcore-opc.h: Remove sentinal.
 780         * mcore-dis.c (print_insn_mcore): Adjust.
 781
 782 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 783
 784         * arc-opc.c: Correct description of availability of NPS400
 785         features.
 786
 787 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 788
 789         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 790         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 791         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 792         xor3>: New mnemonics.
 793         <setb>: Change to a VX form instruction.
 794         (insert_sh6): Add support for rldixor.
 795         (extract_sh6): Likewise.
 796
 797 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 798
 799         * arc-ext.h: Wrap in extern C.
 800
 801 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 802
 803         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 804         Use same method for determining instruction length on ARC700 and
 805         NPS-400.
 806         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 807         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 808         with the NPS400 subclass.
 809         * arc-opc.c: Likewise.
 810
 811 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 812
 813         * sparc-opc.c (rdasr): New macro.
 814         (wrasr): Likewise.
 815         (rdpr): Likewise.
 816         (wrpr): Likewise.
 817         (rdhpr): Likewise.
 818         (wrhpr): Likewise.
 819         (sparc_opcodes): Use the macros above to fix and expand the
 820         definition of read/write instructions from/to
 821         asr/privileged/hyperprivileged instructions.
 822         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 823         %hva_mask_nz.  Prefer softint_set and softint_clear over
 824         set_softint and clear_softint.
 825         (print_insn_sparc): Support %ver in Rd.
 826
 827 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 828
 829         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 830         architecture according to the hardware capabilities they require.
 831
 832 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 833
 834         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 835         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 836         bfd_mach_sparc_v9{c,d,e,v,m}.
 837         * sparc-opc.c (MASK_V9C): Define.
 838         (MASK_V9D): Likewise.
 839         (MASK_V9E): Likewise.
 840         (MASK_V9V): Likewise.
 841         (MASK_V9M): Likewise.
 842         (v6): Add MASK_V9{C,D,E,V,M}.
 843         (v6notlet): Likewise.
 844         (v7): Likewise.
 845         (v8): Likewise.
 846         (v9): Likewise.
 847         (v9andleon): Likewise.
 848         (v9a): Likewise.
 849         (v9b): Likewise.
 850         (v9c): Define.
 851         (v9d): Likewise.
 852         (v9e): Likewise.
 853         (v9v): Likewise.
 854         (v9m): Likewise.
 855         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 856
 857 2016-06-15  Nick Clifton  <nickc@redhat.com>
 858
 859         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 860         constants to match expected behaviour.
 861         (nds32_parse_opcode): Likewise.  Also for whitespace.
 862
 863 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 864
 865         * arc-opc.c (extract_rhv1): Extract value from insn.
 866
 867 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 868
 869         * arc-nps400-tbl.h: Add ldbit instruction.
 870         * arc-opc.c: Add flag classes required for ldbit.
 871
 872 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 873
 874         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 875         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 876         support the above instructions.
 877
 878 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 879
 880         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 881         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 882         csma, cbba, zncv, and hofs.
 883         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 884         support the above instructions.
 885
 886 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 887
 888         * arc-nps400-tbl.h: Add andab and orab instructions.
 889
 890 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 891
 892         * arc-nps400-tbl.h: Add addl-like instructions.
 893
 894 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 895
 896         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 897
 898 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 899
 900         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 901         instructions.
 902
 903 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 904
 905         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 906         variable.
 907         (init_disasm): Handle new command line option "insnlength".
 908         (print_s390_disassembler_options): Mention new option in help
 909         output.
 910         (print_insn_s390): Use the encoded insn length when dumping
 911         unknown instructions.
 912
 913 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 914
 915         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 916          to the address and set as symbol address for LDS/ STS immediate operands.
 917
 918 2016-06-07  Alan Modra  <amodra@gmail.com>
 919
 920         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 921         cpu for "vle" to e500.
 922         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 923         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 924         (PPCNONE): Delete, substitute throughout.
 925         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 926         except for major opcode 4 and 31.
 927         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 928
 929 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 930
 931         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 932         ARM_EXT_RAS in relevant entries.
 933
 934 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 935
 936         PR binutils/20196
 937         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 938         opcodes for E6500.
 939
 940 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 941
 942         PR binutis/18386
 943         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 944         (indir_v_mode): New.
 945         Add comments for '&'.
 946         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 947         (putop): Handle '&'.
 948         (intel_operand_size): Handle indir_v_mode.
 949         (OP_E_register): Likewise.
 950         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 951         64-bit indirect call/jmp for AMD64.
 952         * i386-tbl.h: Regenerated
 953
 954 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 955
 956         * arc-dis.c (struct arc_operand_iterator): New structure.
 957         (find_format_from_table): All the old content from find_format,
 958         with some minor adjustments, and parameter renaming.
 959         (find_format_long_instructions): New function.
 960         (find_format): Rewritten.
 961         (arc_insn_length): Add LSB parameter.
 962         (extract_operand_value): New function.
 963         (operand_iterator_next): New function.
 964         (print_insn_arc): Use new functions to find opcode, and iterator
 965         over operands.
 966         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 967         (extract_nps_3bit_dst_short): New function.
 968         (insert_nps_3bit_src2_short): New function.
 969         (extract_nps_3bit_src2_short): New function.
 970         (insert_nps_bitop1_size): New function.
 971         (extract_nps_bitop1_size): New function.
 972         (insert_nps_bitop2_size): New function.
 973         (extract_nps_bitop2_size): New function.
 974         (insert_nps_bitop_mod4_msb): New function.
 975         (extract_nps_bitop_mod4_msb): New function.
 976         (insert_nps_bitop_mod4_lsb): New function.
 977         (extract_nps_bitop_mod4_lsb): New function.
 978         (insert_nps_bitop_dst_pos3_pos4): New function.
 979         (extract_nps_bitop_dst_pos3_pos4): New function.
 980         (insert_nps_bitop_ins_ext): New function.
 981         (extract_nps_bitop_ins_ext): New function.
 982         (arc_operands): Add new operands.
 983         (arc_long_opcodes): New global array.
 984         (arc_num_long_opcodes): New global.
 985         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 986
 987 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 988
 989         * nds32-asm.h: Add extern "C".
 990         * sh-opc.h: Likewise.
 991
 992 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 993
 994         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 995         0,b,limm to the rflt instruction.
 996
 997 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 998
 999         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1000         constant.
1001
1002 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1003
1004         PR gas/20145
1005         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1006         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1007         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1008         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1009         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1010         * i386-init.h: Regenerated.
1011
1012 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1013
1014         PR gas/20145
1015         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1016         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1017         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1018         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1019         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1020         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1021         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1022         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1023         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1024         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1025         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1026         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1027         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1028         CpuRegMask for AVX512.
1029         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1030         and CpuRegMask.
1031         (set_bitfield_from_cpu_flag_init): New function.
1032         (set_bitfield): Remove const on f.  Call
1033         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1034         * i386-opc.h (CpuRegMMX): New.
1035         (CpuRegXMM): Likewise.
1036         (CpuRegYMM): Likewise.
1037         (CpuRegZMM): Likewise.
1038         (CpuRegMask): Likewise.
1039         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1040         and cpuregmask.
1041         * i386-init.h: Regenerated.
1042         * i386-tbl.h: Likewise.
1043
1044 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1045
1046         PR gas/20154
1047         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1048         (opcode_modifiers): Add AMD64 and Intel64.
1049         (main): Properly verify CpuMax.
1050         * i386-opc.h (CpuAMD64): Removed.
1051         (CpuIntel64): Likewise.
1052         (CpuMax): Set to CpuNo64.
1053         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1054         (AMD64): New.
1055         (Intel64): Likewise.
1056         (i386_opcode_modifier): Add amd64 and intel64.
1057         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1058         on call and jmp.
1059         * i386-init.h: Regenerated.
1060         * i386-tbl.h: Likewise.
1061
1062 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1063
1064         PR gas/20154
1065         * i386-gen.c (main): Fail if CpuMax is incorrect.
1066         * i386-opc.h (CpuMax): Set to CpuIntel64.
1067         * i386-tbl.h: Regenerated.
1068
1069 2016-05-27  Nick Clifton  <nickc@redhat.com>
1070
1071         PR target/20150
1072         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1073         (msp430dis_opcode_unsigned): New function.
1074         (msp430dis_opcode_signed): New function.
1075         (msp430_singleoperand): Use the new opcode reading functions.
1076         Only disassenmble bytes if they were successfully read.
1077         (msp430_doubleoperand): Likewise.
1078         (msp430_branchinstr): Likewise.
1079         (msp430x_callx_instr): Likewise.
1080         (print_insn_msp430): Check that it is safe to read bytes before
1081         attempting disassembly.  Use the new opcode reading functions.
1082
1083 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1084
1085         * ppc-opc.c (CY): New define.  Document it.
1086         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1087
1088 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1089
1090         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1091         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1092         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1093         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1094         CPU_ANY_AVX_FLAGS.
1095         * i386-init.h: Regenerated.
1096
1097 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1098
1099         PR gas/20141
1100         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1101         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1102         * i386-init.h: Regenerated.
1103
1104 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1105
1106         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1107         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1108         * i386-init.h: Regenerated.
1109
1110 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1111
1112         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1113         information.
1114         (print_insn_arc): Set insn_type information.
1115         * arc-opc.c (C_CC): Add F_CLASS_COND.
1116         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1117         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1118         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1119         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1120         (brne, brne_s, jeq_s, jne_s): Likewise.
1121
1122 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1123
1124         * arc-tbl.h (neg): New instruction variant.
1125
1126 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1127
1128         * arc-dis.c (find_format, find_format, get_auxreg)
1129         (print_insn_arc): Changed.
1130         * arc-ext.h (INSERT_XOP): Likewise.
1131
1132 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1133
1134         * tic54x-dis.c (sprint_mmr): Adjust.
1135         * tic54x-opc.c: Likewise.
1136
1137 2016-05-19  Alan Modra  <amodra@gmail.com>
1138
1139         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1140
1141 2016-05-19  Alan Modra  <amodra@gmail.com>
1142
1143         * ppc-opc.c: Formatting.
1144         (NSISIGNOPT): Define.
1145         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1146
1147 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1148
1149         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1150         replacing references to `micromips_ase' throughout.
1151         (_print_insn_mips): Don't use file-level microMIPS annotation to
1152         determine the disassembly mode with the symbol table.
1153
1154 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1155
1156         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1157
1158 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1159
1160         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1161         mips64r6.
1162         * mips-opc.c (D34): New macro.
1163         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1164
1165 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1166
1167         * i386-dis.c (prefix_table): Add RDPID instruction.
1168         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1169         (cpu_flags): Add RDPID bitfield.
1170         * i386-opc.h (enum): Add RDPID element.
1171         (i386_cpu_flags): Add RDPID field.
1172         * i386-opc.tbl: Add RDPID instruction.
1173         * i386-init.h: Regenerate.
1174         * i386-tbl.h: Regenerate.
1175
1176 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1177
1178         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1179         branch type of a symbol.
1180         (print_insn): Likewise.
1181
1182 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1183
1184         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1185         Mainline Security Extensions instructions.
1186         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1187         Extensions instructions.
1188         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1189         instructions.
1190         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1191         special registers.
1192
1193 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1194
1195         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1196
1197 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1198
1199         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1200         (arcExtMap_genOpcode): Likewise.
1201         * arc-opc.c (arg_32bit_rc): Define new variable.
1202         (arg_32bit_u6): Likewise.
1203         (arg_32bit_limm): Likewise.
1204
1205 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1206
1207         * aarch64-gen.c (VERIFIER): Define.
1208         * aarch64-opc.c (VERIFIER): Define.
1209         (verify_ldpsw): Use static linkage.
1210         * aarch64-opc.h (verify_ldpsw): Remove.
1211         * aarch64-tbl.h: Use VERIFIER for verifiers.
1212
1213 2016-04-28  Nick Clifton  <nickc@redhat.com>
1214
1215         PR target/19722
1216         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1217         * aarch64-opc.c (verify_ldpsw): New function.
1218         * aarch64-opc.h (verify_ldpsw): New prototype.
1219         * aarch64-tbl.h: Add initialiser for verifier field.
1220         (LDPSW): Set verifier to verify_ldpsw.
1221
1222 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1223
1224         PR binutils/19983
1225         PR binutils/19984
1226         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1227         smaller than address size.
1228
1229 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1230
1231         * alpha-dis.c: Regenerate.
1232         * crx-dis.c: Likewise.
1233         * disassemble.c: Likewise.
1234         * epiphany-opc.c: Likewise.
1235         * fr30-opc.c: Likewise.
1236         * frv-opc.c: Likewise.
1237         * ip2k-opc.c: Likewise.
1238         * iq2000-opc.c: Likewise.
1239         * lm32-opc.c: Likewise.
1240         * lm32-opinst.c: Likewise.
1241         * m32c-opc.c: Likewise.
1242         * m32r-opc.c: Likewise.
1243         * m32r-opinst.c: Likewise.
1244         * mep-opc.c: Likewise.
1245         * mt-opc.c: Likewise.
1246         * or1k-opc.c: Likewise.
1247         * or1k-opinst.c: Likewise.
1248         * tic80-opc.c: Likewise.
1249         * xc16x-opc.c: Likewise.
1250         * xstormy16-opc.c: Likewise.
1251
1252 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1253
1254         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1255         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1256         calcsd, and calcxd instructions.
1257         * arc-opc.c (insert_nps_bitop_size): Delete.
1258         (extract_nps_bitop_size): Delete.
1259         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1260         (extract_nps_qcmp_m3): Define.
1261         (extract_nps_qcmp_m2): Define.
1262         (extract_nps_qcmp_m1): Define.
1263         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1264         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1265         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1266         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1267         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1268         NPS_QCMP_M3.
1269
1270 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1271
1272         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1273
1274 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1275
1276         * Makefile.in: Regenerated with automake 1.11.6.
1277         * aclocal.m4: Likewise.
1278
1279 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1280
1281         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1282         instructions.
1283         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1284         (extract_nps_cmem_uimm16): New function.
1285         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1286
1287 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1288
1289         * arc-dis.c (arc_insn_length): New function.
1290         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1291         (find_format): Change insnLen parameter to unsigned.
1292
1293 2016-04-13  Nick Clifton  <nickc@redhat.com>
1294
1295         PR target/19937
1296         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1297         the LD.B and LD.BU instructions.
1298
1299 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1300
1301         * arc-dis.c (find_format): Check for extension flags.
1302         (print_flags): New function.
1303         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1304         .extAuxRegister.
1305         * arc-ext.c (arcExtMap_coreRegName): Use
1306         LAST_EXTENSION_CORE_REGISTER.
1307         (arcExtMap_coreReadWrite): Likewise.
1308         (dump_ARC_extmap): Update printing.
1309         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1310         (arc_aux_regs): Add cpu field.
1311         * arc-regs.h: Add cpu field, lower case name aux registers.
1312
1313 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1314
1315         * arc-tbl.h: Add rtsc, sleep with no arguments.
1316
1317 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1318
1319         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1320         Initialize.
1321         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1322         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1323         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1324         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1325         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1326         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1327         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1328         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1329         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1330         (arc_opcode arc_opcodes): Null terminate the array.
1331         (arc_num_opcodes): Remove.
1332         * arc-ext.h (INSERT_XOP): Define.
1333         (extInstruction_t): Likewise.
1334         (arcExtMap_instName): Delete.
1335         (arcExtMap_insn): New function.
1336         (arcExtMap_genOpcode): Likewise.
1337         * arc-ext.c (ExtInstruction): Remove.
1338         (create_map): Zero initialize instruction fields.
1339         (arcExtMap_instName): Remove.
1340         (arcExtMap_insn): New function.
1341         (dump_ARC_extmap): More info while debuging.
1342         (arcExtMap_genOpcode): New function.
1343         * arc-dis.c (find_format): New function.
1344         (print_insn_arc): Use find_format.
1345         (arc_get_disassembler): Enable dump_ARC_extmap only when
1346         debugging.
1347
1348 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1349
1350         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1351         instruction bits out.
1352
1353 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1354
1355         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1356         * arc-opc.c (arc_flag_operands): Add new flags.
1357         (arc_flag_classes): Add new classes.
1358
1359 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1360
1361         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1362
1363 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1364
1365         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1366         encode1, rflt, crc16, and crc32 instructions.
1367         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1368         (arc_flag_classes): Add C_NPS_R.
1369         (insert_nps_bitop_size_2b): New function.
1370         (extract_nps_bitop_size_2b): Likewise.
1371         (insert_nps_bitop_uimm8): Likewise.
1372         (extract_nps_bitop_uimm8): Likewise.
1373         (arc_operands): Add new operand entries.
1374
1375 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1376
1377         * arc-regs.h: Add a new subclass field.  Add double assist
1378         accumulator register values.
1379         * arc-tbl.h: Use DPA subclass to mark the double assist
1380         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1381         * arc-opc.c (RSP): Define instead of SP.
1382         (arc_aux_regs): Add the subclass field.
1383
1384 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1385
1386         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1387
1388 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1389
1390         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1391         NPS_R_SRC1.
1392
1393 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1394
1395         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1396         issues.  No functional changes.
1397
1398 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1399
1400         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1401         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1402         (RTT): Remove duplicate.
1403         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1404         (PCT_CONFIG*): Remove.
1405         (D1L, D1H, D2H, D2L): Define.
1406
1407 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1408
1409         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1410
1411 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1412
1413         * arc-tbl.h (invld07): Remove.
1414         * arc-ext-tbl.h: New file.
1415         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1416         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1417
1418 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1419
1420         Fix -Wstack-usage warnings.
1421         * aarch64-dis.c (print_operands): Substitute size.
1422         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1423
1424 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1425
1426         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1427         to get a proper diagnostic when an invalid ASR register is used.
1428
1429 2016-03-22  Nick Clifton  <nickc@redhat.com>
1430
1431         * configure: Regenerate.
1432
1433 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1434
1435         * arc-nps400-tbl.h: New file.
1436         * arc-opc.c: Add top level comment.
1437         (insert_nps_3bit_dst): New function.
1438         (extract_nps_3bit_dst): New function.
1439         (insert_nps_3bit_src2): New function.
1440         (extract_nps_3bit_src2): New function.
1441         (insert_nps_bitop_size): New function.
1442         (extract_nps_bitop_size): New function.
1443         (arc_flag_operands): Add nps400 entries.
1444         (arc_flag_classes): Add nps400 entries.
1445         (arc_operands): Add nps400 entries.
1446         (arc_opcodes): Add nps400 include.
1447
1448 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1449
1450         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1451         the new class enum values.
1452
1453 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1454
1455         * arc-dis.c (print_insn_arc): Handle nps400.
1456
1457 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1458
1459         * arc-opc.c (BASE): Delete.
1460
1461 2016-03-18  Nick Clifton  <nickc@redhat.com>
1462
1463         PR target/19721
1464         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1465         of MOV insn that aliases an ORR insn.
1466
1467 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1468
1469         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1470
1471 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1472
1473         * mcore-opc.h: Add const qualifiers.
1474         * microblaze-opc.h (struct op_code_struct): Likewise.
1475         * sh-opc.h: Likewise.
1476         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1477         (tic4x_print_op): Likewise.
1478
1479 2016-03-02  Alan Modra  <amodra@gmail.com>
1480
1481         * or1k-desc.h: Regenerate.
1482         * fr30-ibld.c: Regenerate.
1483         * rl78-decode.c: Regenerate.
1484
1485 2016-03-01  Nick Clifton  <nickc@redhat.com>
1486
1487         PR target/19747
1488         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1489
1490 2016-02-24  Renlin Li  <renlin.li@arm.com>
1491
1492         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1493         (print_insn_coprocessor): Support fp16 instructions.
1494
1495 2016-02-24  Renlin Li  <renlin.li@arm.com>
1496
1497         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1498         vminnm, vrint(mpna).
1499
1500 2016-02-24  Renlin Li  <renlin.li@arm.com>
1501
1502         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1503         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1504
1505 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1506
1507         * i386-dis.c (print_insn): Parenthesize expression to prevent
1508         truncated addresses.
1509         (OP_J): Likewise.
1510
1511 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1512             Janek van Oirschot  <jvanoirs@synopsys.com>
1513
1514         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1515         variable.
1516
1517 2016-02-04  Nick Clifton  <nickc@redhat.com>
1518
1519         PR target/19561
1520         * msp430-dis.c (print_insn_msp430): Add a special case for
1521         decoding an RRC instruction with the ZC bit set in the extension
1522         word.
1523
1524 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1525
1526         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1527         * epiphany-ibld.c: Regenerate.
1528         * fr30-ibld.c: Regenerate.
1529         * frv-ibld.c: Regenerate.
1530         * ip2k-ibld.c: Regenerate.
1531         * iq2000-ibld.c: Regenerate.
1532         * lm32-ibld.c: Regenerate.
1533         * m32c-ibld.c: Regenerate.
1534         * m32r-ibld.c: Regenerate.
1535         * mep-ibld.c: Regenerate.
1536         * mt-ibld.c: Regenerate.
1537         * or1k-ibld.c: Regenerate.
1538         * xc16x-ibld.c: Regenerate.
1539         * xstormy16-ibld.c: Regenerate.
1540
1541 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1542
1543         * epiphany-dis.c: Regenerated from latest cpu files.
1544
1545 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1546
1547         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1548         test bit.
1549
1550 2016-01-25  Renlin Li  <renlin.li@arm.com>
1551
1552         * arm-dis.c (mapping_symbol_for_insn): New function.
1553         (find_ifthen_state): Call mapping_symbol_for_insn().
1554
1555 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1556
1557         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1558         of MSR UAO immediate operand.
1559
1560 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1561
1562         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1563         instruction support.
1564
1565 2016-01-17  Alan Modra  <amodra@gmail.com>
1566
1567         * configure: Regenerate.
1568
1569 2016-01-14  Nick Clifton  <nickc@redhat.com>
1570
1571         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1572         instructions that can support stack pointer operations.
1573         * rl78-decode.c: Regenerate.
1574         * rl78-dis.c: Fix display of stack pointer in MOVW based
1575         instructions.
1576
1577 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1578
1579         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1580         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1581         erxtatus_el1 and erxaddr_el1.
1582
1583 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1584
1585         * arm-dis.c (arm_opcodes): Add "esb".
1586         (thumb_opcodes): Likewise.
1587
1588 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1589
1590         * ppc-opc.c <xscmpnedp>: Delete.
1591         <xvcmpnedp>: Likewise.
1592         <xvcmpnedp.>: Likewise.
1593         <xvcmpnesp>: Likewise.
1594         <xvcmpnesp.>: Likewise.
1595
1596 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1597
1598         PR gas/13050
1599         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1600         addition to ISA_A.
1601
1602 2016-01-01  Alan Modra  <amodra@gmail.com>
1603
1604         Update year range in copyright notice of all files.
1605
1606 For older changes see ChangeLog-2015
1607 \f
1608 Copyright (C) 2016 Free Software Foundation, Inc.
1609
1610 Copying and distribution of this file, with or without modification,
1611 are permitted in any medium without royalty provided the copyright
1612 notice and this notice are preserved.
1613
1614 Local Variables:
1615 mode: change-log
1616 left-margin: 8
1617 fill-column: 74
1618 version-control: never
1619 End: