opcodes/ChangeLog

   1 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
   4         Only examine ELF file structures here.
   5
   6 2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
   7
   8         * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
   9         `bfd_mips_elf_get_abiflags' here.
  10
  11 2016-12-16  Nick Clifton  <nickc@redhat.com>
  12
  13         * arm-dis.c (print_insn_thumb32): Fix compile time warning
  14         computing value_in_comment.
  15
  16 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  17
  18         * mips-dis.c (mips_convert_abiflags_ases): New function.
  19         (set_default_mips_dis_options): Also infer ASE flags from ELF
  20         file structures.
  21
  22 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  23
  24         * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
  25         header flag interpretation code.
  26
  27 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  28
  29         * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
  30         `pinfo2' with SP-relative "sd" entries.
  31
  32 2016-12-14  Maciej W. Rozycki  <macro@imgtec.com>
  33
  34         * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
  35         compact jumps.
  36
  37 2016-12-13 Renlin Li <renlin.li@arm.com>
  38
  39         * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
  40         qualifier.
  41         (operand_general_constraint_met_p): Remove case for CP_REG.
  42         (aarch64_print_operand): Print CRn, CRm operand using imm field.
  43         * aarch64-tbl.h (QL_SYS): Use CR qualifier.
  44         (QL_SYSL): Likewise.
  45         (aarch64_opcode_table): Change CRn, CRm operand class and type.
  46         * aarch64-opc-2.c : Regenerate.
  47         * aarch64-asm-2.c : Likewise.
  48         * aarch64-dis-2.c : Likewise.
  49
  50 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  51
  52         * rx-dis.c: Include <setjmp.h>
  53         (struct private): New.
  54         (rx_get_byte): Check return value of read_memory_func, and
  55         call memory_error_func and OPCODES_SIGLONGJMP on error.
  56         (print_insn_rx): Call OPCODES_SIGSETJMP.
  57
  58 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  59
  60         * rl78-dis.c: Include <setjmp.h>.
  61         (struct private): New.
  62         (rl78_get_byte): Check return value of read_memory_func, and
  63         call memory_error_func and OPCODES_SIGLONGJMP on error.
  64         (print_insn_rl78_common): Call OPCODES_SIGJMP.
  65
  66 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  67
  68         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
  69
  70 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  71
  72         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
  73         than UINT.
  74
  75 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  76
  77         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
  78         to separate `extend' and its uninterpreted argument output.
  79         Separate hexadecimal halves of undecoded extended instructions
  80         output.
  81
  82 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  83
  84         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
  85         indentation space across.
  86
  87 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  88
  89         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
  90         adjustment for PC-relative operations following MIPS16e compact
  91         jumps or undefined RR/J(AL)R(C) encodings.
  92
  93 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  94
  95         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
  96         variable to `reglane_index'.
  97
  98 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
  99
 100         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
 101
 102 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 103
 104         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
 105
 106 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 107
 108         * mips16-opc.c (mips16_opcodes): Update comment naming structure
 109         members.
 110
 111 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
 112
 113         * mips-dis.c (print_mips_disassembler_options): Reformat output.
 114
 115 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 116
 117         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
 118         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
 119
 120 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 121
 122         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
 123
 124 2016-12-01  Nick Clifton  <nickc@redhat.com>
 125
 126         PR binutils/20893
 127         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
 128         opcode designator.
 129
 130 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 131
 132         * arc-opc.c (insert_ra_chk): New function.
 133         (insert_rb_chk): Likewise.
 134         (insert_rad): Update text error message.
 135         (insert_rcd): Likewise.
 136         (insert_rhv2): Likewise.
 137         (insert_r0): Likewise.
 138         (insert_r1): Likewise.
 139         (insert_r2): Likewise.
 140         (insert_r3): Likewise.
 141         (insert_sp): Likewise.
 142         (insert_gp): Likewise.
 143         (insert_pcl): Likewise.
 144         (insert_blink): Likewise.
 145         (insert_ilink1): Likewise.
 146         (insert_ilink2): Likewise.
 147         (insert_ras): Likewise.
 148         (insert_rbs): Likewise.
 149         (insert_rcs): Likewise.
 150         (insert_simm3s): Likewise.
 151         (insert_rrange): Likewise.
 152         (insert_fpel): Likewise.
 153         (insert_blinkel): Likewise.
 154         (insert_pcel): Likewise.
 155         (insert_nps_3bit_dst): Likewise.
 156         (insert_nps_3bit_dst_short): Likewise.
 157         (insert_nps_3bit_src2_short): Likewise.
 158         (insert_nps_bitop_size_2b): Likewise.
 159         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 160         (RA_CHK): Define.
 161         (RB): Adjust.
 162         (RB_CHK): Define.
 163         (RC): Adjust.
 164         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 165         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 166         Change first insn argument to check for LP_COUNT usage.
 167         (rem): Likewise.
 168         (ld, ldd): All instructions are LOAD class.  Change first insn
 169         argument to check for LP_COUNT usage.
 170         (st, std): All instructions are STORE class.
 171         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 172         Change first insn argument to check for LP_COUNT usage.
 173         (mov): All instructions are MOVE class.  Change first insn
 174         argument to check for LP_COUNT usage.
 175
 176 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 177
 178         * arc-dis.c (is_compatible_p): Remove function.
 179         (skip_this_opcode): Don't add any decoding class to decode list.
 180         Remove warning.
 181         (find_format_from_table): Go through all opcodes, and warn if we
 182         use a guessed mnemonic.
 183
 184 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 185             Amit Pawar  <amit.pawar@amd.com>
 186
 187         PR binutils/20637
 188         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 189         instructions.
 190
 191 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 192
 193         * configure: Regenerate.
 194
 195 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 196
 197         * sparc-opc.c (HWS_V8): Definition moved from
 198         gas/config/tc-sparc.c.
 199         (HWS_V9): Likewise.
 200         (HWS_VA): Likewise.
 201         (HWS_VB): Likewise.
 202         (HWS_VC): Likewise.
 203         (HWS_VD): Likewise.
 204         (HWS_VE): Likewise.
 205         (HWS_VV): Likewise.
 206         (HWS_VM): Likewise.
 207         (HWS2_VM): Likewise.
 208         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 209         existing entries.
 210
 211 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 212
 213         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 214         instructions.
 215
 216 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 217
 218         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 219         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 220         (aarch64_opcode_table): Add fcmla and fcadd.
 221         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 222         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 223         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 224         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 225         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 226         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 227         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 228         (operand_general_constraint_met_p): Rotate and index range check.
 229         (aarch64_print_operand): Handle rotate operand.
 230         * aarch64-asm-2.c: Regenerate.
 231         * aarch64-dis-2.c: Likewise.
 232         * aarch64-opc-2.c: Likewise.
 233
 234 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 235
 236         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 237         * aarch64-asm-2.c: Regenerate.
 238         * aarch64-dis-2.c: Regenerate.
 239         * aarch64-opc-2.c: Regenerate.
 240
 241 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 242
 243         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 244         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 245         * aarch64-asm-2.c: Regenerate.
 246         * aarch64-dis-2.c: Regenerate.
 247         * aarch64-opc-2.c: Regenerate.
 248
 249 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 250
 251         * aarch64-tbl.h (QL_X1NIL): New.
 252         (arch64_opcode_table): Add ldraa, ldrab.
 253         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 254         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 255         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 256         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 257         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 258         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 259         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 260         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 261         (aarch64_print_operand): Likewise.
 262         * aarch64-asm-2.c: Regenerate.
 263         * aarch64-dis-2.c: Regenerate.
 264         * aarch64-opc-2.c: Regenerate.
 265
 266 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 267
 268         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 269         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 270         * aarch64-asm-2.c: Regenerate.
 271         * aarch64-dis-2.c: Regenerate.
 272         * aarch64-opc-2.c: Regenerate.
 273
 274 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 275
 276         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 277         (AARCH64_OPERANDS): Add Rm_SP.
 278         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 279         * aarch64-asm-2.c: Regenerate.
 280         * aarch64-dis-2.c: Regenerate.
 281         * aarch64-opc-2.c: Regenerate.
 282
 283 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 284
 285         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 286         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 287         autdzb, xpaci, xpacd.
 288         * aarch64-asm-2.c: Regenerate.
 289         * aarch64-dis-2.c: Regenerate.
 290         * aarch64-opc-2.c: Regenerate.
 291
 292 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 293
 294         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 295         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 296         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 297         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 298
 299 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 300
 301         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 302         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 303         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 304         autibsp.
 305         * aarch64-asm-2.c: Regenerate.
 306         * aarch64-dis-2.c: Regenerate.
 307
 308 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 309
 310         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 311
 312 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         PR binutils/20799
 315         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 316         * i386-dis.c (EdqwS): Removed.
 317         (dqw_swap_mode): Likewise.
 318         (intel_operand_size): Don't check dqw_swap_mode.
 319         (OP_E_register): Likewise.
 320         (OP_E_memory): Likewise.
 321         (OP_G): Likewise.
 322         (OP_EX): Likewise.
 323         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 324         * i386-tbl.h: Regerated.
 325
 326 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         * i386-opc.tbl: Merge AVX512F vmovq.
 329         * i386-tbl.h: Regerated.
 330
 331 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 332
 333         PR binutils/20701
 334         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 335         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 336         (three_byte_table): Remove THREE_BYTE_0F7A.
 337
 338 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 339
 340         PR binutils/20775
 341         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 342         (FGRPd9_4): Replace 1 with 2.
 343         (FGRPd9_5): Replace 2 with 3.
 344         (FGRPd9_6): Replace 3 with 4.
 345         (FGRPd9_7): Replace 4 with 5.
 346         (FGRPda_5): Replace 5 with 6.
 347         (FGRPdb_4): Replace 6 with 7.
 348         (FGRPde_3): Replace 7 with 8.
 349         (FGRPdf_4): Replace 8 with 9.
 350         (fgrps): Add an entry for Bad_Opcode.
 351
 352 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 353
 354         * arc-opc.c (arc_flag_operands): Add F_DI14.
 355         (arc_flag_classes): Add C_DI14.
 356         * arc-nps400-tbl.h: Add new exc instructions.
 357
 358 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 359
 360         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 361         major opcode 0xa.
 362         * arc-nps-400-tbl.h: Add dcmac instruction.
 363         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 364         (insert_nps_rbdouble_64): Added.
 365         (extract_nps_rbdouble_64): Added.
 366         (insert_nps_proto_size): Added.
 367         (extract_nps_proto_size): Added.
 368
 369 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 370
 371         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 372         relating to long instruction processing, add new limm field.
 373         (OPCODE): Rename to...
 374         (OPCODE_32BIT_INSN): ...this.
 375         (OPCODE_AC): Delete.
 376         (skip_this_opcode): Handle different instruction lengths, update
 377         macro name.
 378         (special_flag_p): Update parameter type.
 379         (find_format_from_table): Update for more instruction lengths.
 380         (find_format_long_instructions): Delete.
 381         (find_format): Update for more instruction lengths.
 382         (arc_insn_length): Likewise.
 383         (extract_operand_value): Update for more instruction lengths.
 384         (operand_iterator_next): Remove code relating to long
 385         instructions.
 386         (arc_opcode_to_insn_type): New function.
 387         (print_insn_arc):Update for more instructions lengths.
 388         * arc-ext.c (extInstruction_t): Change argument type.
 389         * arc-ext.h (extInstruction_t): Change argument type.
 390         * arc-fxi.h: Change type unsigned to unsigned long long
 391         extensively throughout.
 392         * arc-nps400-tbl.h: Add long instructions taken from
 393         arc_long_opcodes table in arc-opc.c.
 394         * arc-opc.c: Update parameter types on insert/extract handlers.
 395         (arc_long_opcodes): Delete.
 396         (arc_num_long_opcodes): Delete.
 397         (arc_opcode_len): Update for more instruction lengths.
 398
 399 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 400
 401         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 402
 403 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 404
 405         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 406         with arc_opcode_len.
 407         (find_format_long_instructions): Likewise.
 408         * arc-opc.c (arc_opcode_len): New function.
 409
 410 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 411
 412         * arc-nps400-tbl.h: Fix some instruction masks.
 413
 414 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 415
 416         * i386-dis.c (REG_82): Removed.
 417         (X86_64_82_REG_0): Likewise.
 418         (X86_64_82_REG_1): Likewise.
 419         (X86_64_82_REG_2): Likewise.
 420         (X86_64_82_REG_3): Likewise.
 421         (X86_64_82_REG_4): Likewise.
 422         (X86_64_82_REG_5): Likewise.
 423         (X86_64_82_REG_6): Likewise.
 424         (X86_64_82_REG_7): Likewise.
 425         (X86_64_82): New.
 426         (dis386): Use X86_64_82 instead of REG_82.
 427         (reg_table): Remove REG_82.
 428         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 429         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 430         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 431         X86_64_82_REG_7.
 432
 433 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         PR binutils/20754
 436         * i386-dis.c (REG_82): New.
 437         (X86_64_82_REG_0): Likewise.
 438         (X86_64_82_REG_1): Likewise.
 439         (X86_64_82_REG_2): Likewise.
 440         (X86_64_82_REG_3): Likewise.
 441         (X86_64_82_REG_4): Likewise.
 442         (X86_64_82_REG_5): Likewise.
 443         (X86_64_82_REG_6): Likewise.
 444         (X86_64_82_REG_7): Likewise.
 445         (dis386): Use REG_82.
 446         (reg_table): Add REG_82.
 447         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 448         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 449         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 450
 451 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 452
 453         * i386-dis.c (REG_82): Renamed to ...
 454         (REG_83): This.
 455         (dis386): Updated.
 456         (reg_table): Likewise.
 457
 458 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 459
 460         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 461         * i386-dis-evex.h (evex_table): Updated.
 462         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 463         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 464         (cpu_flags): Add CpuAVX512_4VNNIW.
 465         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 466         (i386_cpu_flags): Add cpuavx512_4vnniw.
 467         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 468         * i386-init.h: Regenerate.
 469         * i386-tbl.h: Ditto.
 470
 471 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 472
 473         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 474         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 475         * i386-dis-evex.h (evex_table): Updated.
 476         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 477         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 478         (cpu_flags): Add CpuAVX512_4FMAPS.
 479         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 480         * i386-opc.h (AVX512_4FMAP): New.
 481         (i386_cpu_flags): Add cpuavx512_4fmaps.
 482         (ImplicitQuadGroup): New.
 483         (i386_opcode_modifier): Add implicitquadgroup.
 484         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 485         * i386-init.h: Regenerate.
 486         * i386-tbl.h: Ditto.
 487
 488 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 489             Andrew Waterman <andrew@sifive.com>
 490
 491         Add support for RISC-V architecture.
 492         * configure.ac: Add entry for bfd_riscv_arch.
 493         * configure: Regenerate.
 494         * disassemble.c (disassembler): Add support for riscv.
 495         (disassembler_usage): Likewise.
 496         * riscv-dis.c: New file.
 497         * riscv-opc.c: New file.
 498
 499 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 500
 501         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 502         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 503         (rm_table): Update the RM_0FAE_REG_7 entry.
 504         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 505         (cpu_flags): Remove CpuPCOMMIT.
 506         * i386-opc.h (CpuPCOMMIT): Removed.
 507         (i386_cpu_flags): Remove cpupcommit.
 508         * i386-opc.tbl: Remove pcommit.
 509         * i386-init.h: Regenerated.
 510         * i386-tbl.h: Likewise.
 511
 512 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 513
 514         PR binutis/20705
 515         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 516         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 517         32-bit mode.  Don't check vex.register_specifier in 32-bit
 518         mode.
 519         (OP_VEX): Check for invalid mask registers.
 520
 521 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 522
 523         PR binutis/20699
 524         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 525         sizeflag.
 526
 527 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         PR binutis/20704
 530         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 531
 532 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 533
 534         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 535         local variable to `index_regno'.
 536
 537 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 538
 539         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 540
 541 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 542
 543         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 544         usage on ISA basis.
 545
 546 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 547
 548         PR target/20666
 549         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 550
 551 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 552
 553         PR target/20667
 554         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 555         available.
 556
 557 2016-10-07  Alan Modra  <amodra@gmail.com>
 558
 559         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 560
 561 2016-10-06  Alan Modra  <amodra@gmail.com>
 562
 563         * aarch64-opc.c: Spell fall through comments consistently.
 564         * i386-dis.c: Likewise.
 565         * aarch64-dis.c: Add missing fall through comments.
 566         * aarch64-opc.c: Likewise.
 567         * arc-dis.c: Likewise.
 568         * arm-dis.c: Likewise.
 569         * i386-dis.c: Likewise.
 570         * m68k-dis.c: Likewise.
 571         * mep-asm.c: Likewise.
 572         * ns32k-dis.c: Likewise.
 573         * sh-dis.c: Likewise.
 574         * tic4x-dis.c: Likewise.
 575         * tic6x-dis.c: Likewise.
 576         * vax-dis.c: Likewise.
 577
 578 2016-10-06  Alan Modra  <amodra@gmail.com>
 579
 580         * arc-ext.c (create_map): Add missing break.
 581         * msp430-decode.opc (encode_as): Likewise.
 582         * msp430-decode.c: Regenerate.
 583
 584 2016-10-06  Alan Modra  <amodra@gmail.com>
 585
 586         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 587         * crx-dis.c (print_insn_crx): Likewise.
 588
 589 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 590
 591         PR binutils/20657
 592         * i386-dis.c (putop): Don't assign alt twice.
 593
 594 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 595
 596         PR target/20553
 597         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 598
 599 2016-09-29  Alan Modra  <amodra@gmail.com>
 600
 601         * ppc-opc.c (L): Make compulsory.
 602         (LOPT): New, optional form of L.
 603         (HTM_R): Define as LOPT.
 604         (L0, L1): Delete.
 605         (L32OPT): New, optional for 32-bit L.
 606         (L2OPT): New, 2-bit L for dcbf.
 607         (SVC_LEC): Update.
 608         (L2): Define.
 609         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 610         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 611         <dcbf>: Use L2OPT.
 612         <tlbiel, tlbie>: Use LOPT.
 613         <wclr, wclrall>: Use L2.
 614
 615 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 616
 617         * Makefile.in: Regenerate.
 618         * configure: Likewise.
 619
 620 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 621
 622         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 623         (EXTINSN2OP): Use EXTINSN2OPF.
 624         (bspeekm, bspop, modapp): New extension instructions.
 625         * arc-opc.c (F_DNZ_ND): Define.
 626         (F_DNZ_D): Likewise.
 627         (F_SIZEB1): Changed.
 628         (C_DNZ_D): Define.
 629         (C_HARD): Changed.
 630         * arc-tbl.h (dbnz): New instruction.
 631         (prealloc): Allow it for ARC EM.
 632         (xbfu): Likewise.
 633
 634 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 635
 636         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 637         after commas in addresses.
 638         (aarch64_print_operand): Likewise.
 639
 640 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 641
 642         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 643         rather than "should be" or "expected to be" in error messages.
 644
 645 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 646
 647         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 648         (print_mnemonic_name): ...here.
 649         (print_comment): New function.
 650         (print_aarch64_insn): Call it.
 651         * aarch64-opc.c (aarch64_conds): Add SVE names.
 652         (aarch64_print_operand): Print alternative condition names in
 653         a comment.
 654
 655 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 656
 657         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 658         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 659         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 660         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 661         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 662         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 663         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 664         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 665         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 666         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 667         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 668         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 669         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 670         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 671         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 672         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 673         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 674         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 675         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 676         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 677         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 678         (aarch64_feature_sve): New variable.
 679         (SVE): New macro.
 680         (_SVE_INSN): Likewise.
 681         (aarch64_opcode_table): Add SVE instructions.
 682         * aarch64-opc.h (extract_fields): Declare.
 683         * aarch64-opc-2.c: Regenerate.
 684         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 685         * aarch64-asm-2.c: Regenerate.
 686         * aarch64-dis.c (extract_fields): Make global.
 687         (do_misc_decoding): Handle the new SVE aarch64_ops.
 688         * aarch64-dis-2.c: Regenerate.
 689
 690 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 691
 692         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 693         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 694         aarch64_field_kinds.
 695         * aarch64-opc.c (fields): Add corresponding entries.
 696         * aarch64-asm.c (aarch64_get_variant): New function.
 697         (aarch64_encode_variant_using_iclass): Likewise.
 698         (aarch64_opcode_encode): Call it.
 699         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 700         (aarch64_opcode_decode): Call it.
 701
 702 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 703
 704         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 705         and FP register operands.
 706         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 707         (FLD_SVE_Vn): New aarch64_field_kinds.
 708         * aarch64-opc.c (fields): Add corresponding entries.
 709         (aarch64_print_operand): Handle the new SVE core and FP register
 710         operands.
 711         * aarch64-opc-2.c: Regenerate.
 712         * aarch64-asm-2.c: Likewise.
 713         * aarch64-dis-2.c: Likewise.
 714
 715 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 716
 717         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 718         immediate operands.
 719         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 720         * aarch64-opc.c (fields): Add corresponding entry.
 721         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 722         operands.
 723         (aarch64_print_operand): Likewise.
 724         * aarch64-opc-2.c: Regenerate.
 725         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 726         (ins_sve_float_zero_one): New inserters.
 727         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 728         (aarch64_ins_sve_float_half_two): Likewise.
 729         (aarch64_ins_sve_float_zero_one): Likewise.
 730         * aarch64-asm-2.c: Regenerate.
 731         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 732         (ext_sve_float_zero_one): New extractors.
 733         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 734         (aarch64_ext_sve_float_half_two): Likewise.
 735         (aarch64_ext_sve_float_zero_one): Likewise.
 736         * aarch64-dis-2.c: Regenerate.
 737
 738 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 739
 740         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 741         integer immediate operands.
 742         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 743         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 744         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 745         * aarch64-opc.c (fields): Add corresponding entries.
 746         (operand_general_constraint_met_p): Handle the new SVE integer
 747         immediate operands.
 748         (aarch64_print_operand): Likewise.
 749         (aarch64_sve_dupm_mov_immediate_p): New function.
 750         * aarch64-opc-2.c: Regenerate.
 751         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 752         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 753         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 754         (aarch64_ins_limm): ...here.
 755         (aarch64_ins_inv_limm): New function.
 756         (aarch64_ins_sve_aimm): Likewise.
 757         (aarch64_ins_sve_asimm): Likewise.
 758         (aarch64_ins_sve_limm_mov): Likewise.
 759         (aarch64_ins_sve_shlimm): Likewise.
 760         (aarch64_ins_sve_shrimm): Likewise.
 761         * aarch64-asm-2.c: Regenerate.
 762         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 763         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 764         * aarch64-dis.c (decode_limm): New function, split out from...
 765         (aarch64_ext_limm): ...here.
 766         (aarch64_ext_inv_limm): New function.
 767         (decode_sve_aimm): Likewise.
 768         (aarch64_ext_sve_aimm): Likewise.
 769         (aarch64_ext_sve_asimm): Likewise.
 770         (aarch64_ext_sve_limm_mov): Likewise.
 771         (aarch64_top_bit): Likewise.
 772         (aarch64_ext_sve_shlimm): Likewise.
 773         (aarch64_ext_sve_shrimm): Likewise.
 774         * aarch64-dis-2.c: Regenerate.
 775
 776 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 777
 778         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 779         operands.
 780         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 781         the AARCH64_MOD_MUL_VL entry.
 782         (value_aligned_p): Cope with non-power-of-two alignments.
 783         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 784         (print_immediate_offset_address): Likewise.
 785         (aarch64_print_operand): Likewise.
 786         * aarch64-opc-2.c: Regenerate.
 787         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 788         (ins_sve_addr_ri_s9xvl): New inserters.
 789         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 790         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 791         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 792         * aarch64-asm-2.c: Regenerate.
 793         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 794         (ext_sve_addr_ri_s9xvl): New extractors.
 795         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 796         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 797         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 798         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 799         * aarch64-dis-2.c: Regenerate.
 800
 801 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 802
 803         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 804         address operands.
 805         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 806         (FLD_SVE_xs_22): New aarch64_field_kinds.
 807         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 808         (get_operand_specific_data): New function.
 809         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 810         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 811         (operand_general_constraint_met_p): Handle the new SVE address
 812         operands.
 813         (sve_reg): New array.
 814         (get_addr_sve_reg_name): New function.
 815         (aarch64_print_operand): Handle the new SVE address operands.
 816         * aarch64-opc-2.c: Regenerate.
 817         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 818         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 819         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 820         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 821         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 822         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 823         (aarch64_ins_sve_addr_zi_u5): Likewise.
 824         (aarch64_ins_sve_addr_zz): Likewise.
 825         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 826         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 827         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 828         * aarch64-asm-2.c: Regenerate.
 829         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 830         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 831         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 832         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 833         (aarch64_ext_sve_addr_ri_u6): Likewise.
 834         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 835         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 836         (aarch64_ext_sve_addr_zi_u5): Likewise.
 837         (aarch64_ext_sve_addr_zz): Likewise.
 838         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 839         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 840         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 841         * aarch64-dis-2.c: Regenerate.
 842
 843 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 844
 845         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 846         AARCH64_OPND_SVE_PATTERN_SCALED.
 847         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 848         * aarch64-opc.c (fields): Add a corresponding entry.
 849         (set_multiplier_out_of_range_error): New function.
 850         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 851         (operand_general_constraint_met_p): Handle
 852         AARCH64_OPND_SVE_PATTERN_SCALED.
 853         (print_register_offset_address): Use PRIi64 to print the
 854         shift amount.
 855         (aarch64_print_operand): Likewise.  Handle
 856         AARCH64_OPND_SVE_PATTERN_SCALED.
 857         * aarch64-opc-2.c: Regenerate.
 858         * aarch64-asm.h (ins_sve_scale): New inserter.
 859         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 860         * aarch64-asm-2.c: Regenerate.
 861         * aarch64-dis.h (ext_sve_scale): New inserter.
 862         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 863         * aarch64-dis-2.c: Regenerate.
 864
 865 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 866
 867         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 868         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 869         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 870         (FLD_SVE_prfop): Likewise.
 871         * aarch64-opc.c: Include libiberty.h.
 872         (aarch64_sve_pattern_array): New variable.
 873         (aarch64_sve_prfop_array): Likewise.
 874         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 875         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 876         AARCH64_OPND_SVE_PRFOP.
 877         * aarch64-asm-2.c: Regenerate.
 878         * aarch64-dis-2.c: Likewise.
 879         * aarch64-opc-2.c: Likewise.
 880
 881 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 882
 883         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 884         AARCH64_OPND_QLF_P_[ZM].
 885         (aarch64_print_operand): Print /z and /m where appropriate.
 886
 887 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 888
 889         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 890         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 891         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 892         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 893         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 894         * aarch64-opc.c (fields): Add corresponding entries here.
 895         (operand_general_constraint_met_p): Check that SVE register lists
 896         have the correct length.  Check the ranges of SVE index registers.
 897         Check for cases where p8-p15 are used in 3-bit predicate fields.
 898         (aarch64_print_operand): Handle the new SVE operands.
 899         * aarch64-opc-2.c: Regenerate.
 900         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 901         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 902         (aarch64_ins_sve_reglist): Likewise.
 903         * aarch64-asm-2.c: Regenerate.
 904         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 905         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 906         (aarch64_ext_sve_reglist): Likewise.
 907         * aarch64-dis-2.c: Regenerate.
 908
 909 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 910
 911         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 912         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 913         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 914         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 915         tied operands.
 916
 917 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 918
 919         * aarch64-opc.c (get_offset_int_reg_name): New function.
 920         (print_immediate_offset_address): Likewise.
 921         (print_register_offset_address): Take the base and offset
 922         registers as parameters.
 923         (aarch64_print_operand): Update caller accordingly.  Use
 924         print_immediate_offset_address.
 925
 926 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 927
 928         * aarch64-opc.c (BANK): New macro.
 929         (R32, R64): Take a register number as argument
 930         (int_reg): Use BANK.
 931
 932 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 933
 934         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 935         (aarch64_print_operand): Update accordingly.
 936
 937 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 938
 939         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 940         for FPIMM.
 941         * aarch64-asm.h (ins_fpimm): New inserter.
 942         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 943         * aarch64-asm-2.c: Regenerate.
 944         * aarch64-dis.h (ext_fpimm): New extractor.
 945         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 946         (aarch64_ext_fpimm): New function.
 947         * aarch64-dis-2.c: Regenerate.
 948
 949 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 950
 951         * aarch64-asm.c: Include libiberty.h.
 952         (insert_fields): New function.
 953         (aarch64_ins_imm): Use it.
 954         * aarch64-dis.c (extract_fields): New function.
 955         (aarch64_ext_imm): Use it.
 956
 957 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 958
 959         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 960         with an esize parameter.
 961         (operand_general_constraint_met_p): Update accordingly.
 962         Fix misindented code.
 963         * aarch64-asm.c (aarch64_ins_limm): Update call to
 964         aarch64_logical_immediate_p.
 965
 966 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 967
 968         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 969
 970 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 971
 972         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 973
 974 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 975
 976         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 977
 978 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 979
 980         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 981         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 982         xor3>: Delete mnemonics.
 983         <cp_abort>: Rename mnemonic from ...
 984         <cpabort>: ...to this.
 985         <setb>: Change to a X form instruction.
 986         <sync>: Change to 1 operand form.
 987         <copy>: Delete mnemonic.
 988         <copy_first>: Rename mnemonic from ...
 989         <copy>: ...to this.
 990         <paste, paste.>: Delete mnemonics.
 991         <paste_last>: Rename mnemonic from ...
 992         <paste.>: ...to this.
 993
 994 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 995
 996         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 997
 998 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 999
1000         * s390-mkopc.c (main): Support alternate arch strings.
1001
1002 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
1003
1004         * s390-opc.txt: Fix kmctr instruction type.
1005
1006 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
1007
1008         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1009         * i386-init.h: Regenerated.
1010
1011 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
1012
1013         * opcodes/arc-dis.c (print_insn_arc): Changed.
1014
1015 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
1016
1017         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1018         camellia_fl.
1019
1020 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1021
1022         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
1023         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1024         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1025
1026 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
1027
1028         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1029         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1030         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1031         PREFIX_MOD_3_0FAE_REG_4.
1032         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1033         PREFIX_MOD_3_0FAE_REG_4.
1034         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1035         (cpu_flags): Add CpuPTWRITE.
1036         * i386-opc.h (CpuPTWRITE): New.
1037         (i386_cpu_flags): Add cpuptwrite.
1038         * i386-opc.tbl: Add ptwrite instruction.
1039         * i386-init.h: Regenerated.
1040         * i386-tbl.h: Likewise.
1041
1042 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
1043
1044         * arc-dis.h: Wrap around in extern "C".
1045
1046 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1047
1048         * aarch64-tbl.h (V8_2_INSN): New macro.
1049         (aarch64_opcode_table): Use it.
1050
1051 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1052
1053         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1054         CORE_INSN, __FP_INSN and SIMD_INSN.
1055
1056 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1057
1058         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1059         (aarch64_opcode_table): Update uses accordingly.
1060
1061 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1062         Kwok Cheung Yeung  <kcy@codesourcery.com>
1063
1064         opcodes/
1065         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1066         'e_cmplwi' to 'e_cmpli' instead.
1067         (OPVUPRT, OPVUPRT_MASK): Define.
1068         (powerpc_opcodes): Add E200Z4 insns.
1069         (vle_opcodes): Add context save/restore insns.
1070
1071 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1072
1073         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1074         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1075         "j".
1076
1077 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1078
1079         * arc-nps400-tbl.h: Change block comments to GNU format.
1080         * arc-dis.c: Add new globals addrtypenames,
1081         addrtypenames_max, and addtypeunknown.
1082         (get_addrtype): New function.
1083         (print_insn_arc): Print colons and address types when
1084         required.
1085         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1086         define insert and extract functions for all address types.
1087         (arc_operands): Add operands for colon and all address
1088         types.
1089         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1090         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1091         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1092         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1093         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1094         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1095
1096 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1097
1098         * configure: Regenerated.
1099
1100 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1101
1102         * arc-dis.c (skipclass): New structure.
1103         (decodelist): New variable.
1104         (is_compatible_p): New function.
1105         (new_element): Likewise.
1106         (skip_class_p): Likewise.
1107         (find_format_from_table): Use skip_class_p function.
1108         (find_format): Decode first the extension instructions.
1109         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1110         e_flags.
1111         (parse_option): New function.
1112         (parse_disassembler_options): Likewise.
1113         (print_arc_disassembler_options): Likewise.
1114         (print_insn_arc): Use parse_disassembler_options function.  Proper
1115         select ARCv2 cpu variant.
1116         * disassemble.c (disassembler_usage): Add ARC disassembler
1117         options.
1118
1119 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1120
1121         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1122         annotation from the "nal" entry and reorder it beyond "bltzal".
1123
1124 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1125
1126         * sparc-opc.c (ldtxa): New macro.
1127         (sparc_opcodes): Use the macro defined above to add entries for
1128         the LDTXA instructions.
1129         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1130         instruction.
1131
1132 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1133
1134         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1135         and "jmpc".
1136
1137 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1140         (movzb): Adjust to cover all permitted suffixes.
1141         (movzw): New.
1142         * i386-tbl.h: Re-generate.
1143
1144 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1145
1146         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1147         (lgdt): Remove Tbyte from non-64-bit variant.
1148         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1149         xsaves64, xsavec64): Remove Disp16.
1150         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1151         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1152         64-bit variants.
1153         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1154         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1155         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1156         64-bit variants.
1157         * i386-tbl.h: Re-generate.
1158
1159 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1160
1161         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1162         * i386-tbl.h: Re-generate.
1163
1164 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1165
1166         * arm-dis.c (print_insn): Fix typo in comment.
1167
1168 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1169
1170         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1171         range of ldst_elemlist operands.
1172         (print_register_list): Use PRIi64 to print the index.
1173         (aarch64_print_operand): Likewise.
1174
1175 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1176
1177         * mcore-opc.h: Remove sentinal.
1178         * mcore-dis.c (print_insn_mcore): Adjust.
1179
1180 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1181
1182         * arc-opc.c: Correct description of availability of NPS400
1183         features.
1184
1185 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1186
1187         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1188         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1189         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1190         xor3>: New mnemonics.
1191         <setb>: Change to a VX form instruction.
1192         (insert_sh6): Add support for rldixor.
1193         (extract_sh6): Likewise.
1194
1195 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1196
1197         * arc-ext.h: Wrap in extern C.
1198
1199 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1200
1201         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1202         Use same method for determining instruction length on ARC700 and
1203         NPS-400.
1204         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1205         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1206         with the NPS400 subclass.
1207         * arc-opc.c: Likewise.
1208
1209 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1210
1211         * sparc-opc.c (rdasr): New macro.
1212         (wrasr): Likewise.
1213         (rdpr): Likewise.
1214         (wrpr): Likewise.
1215         (rdhpr): Likewise.
1216         (wrhpr): Likewise.
1217         (sparc_opcodes): Use the macros above to fix and expand the
1218         definition of read/write instructions from/to
1219         asr/privileged/hyperprivileged instructions.
1220         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1221         %hva_mask_nz.  Prefer softint_set and softint_clear over
1222         set_softint and clear_softint.
1223         (print_insn_sparc): Support %ver in Rd.
1224
1225 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1226
1227         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1228         architecture according to the hardware capabilities they require.
1229
1230 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1231
1232         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1233         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1234         bfd_mach_sparc_v9{c,d,e,v,m}.
1235         * sparc-opc.c (MASK_V9C): Define.
1236         (MASK_V9D): Likewise.
1237         (MASK_V9E): Likewise.
1238         (MASK_V9V): Likewise.
1239         (MASK_V9M): Likewise.
1240         (v6): Add MASK_V9{C,D,E,V,M}.
1241         (v6notlet): Likewise.
1242         (v7): Likewise.
1243         (v8): Likewise.
1244         (v9): Likewise.
1245         (v9andleon): Likewise.
1246         (v9a): Likewise.
1247         (v9b): Likewise.
1248         (v9c): Define.
1249         (v9d): Likewise.
1250         (v9e): Likewise.
1251         (v9v): Likewise.
1252         (v9m): Likewise.
1253         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1254
1255 2016-06-15  Nick Clifton  <nickc@redhat.com>
1256
1257         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1258         constants to match expected behaviour.
1259         (nds32_parse_opcode): Likewise.  Also for whitespace.
1260
1261 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1262
1263         * arc-opc.c (extract_rhv1): Extract value from insn.
1264
1265 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1266
1267         * arc-nps400-tbl.h: Add ldbit instruction.
1268         * arc-opc.c: Add flag classes required for ldbit.
1269
1270 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1271
1272         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1273         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1274         support the above instructions.
1275
1276 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1277
1278         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1279         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1280         csma, cbba, zncv, and hofs.
1281         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1282         support the above instructions.
1283
1284 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1285
1286         * arc-nps400-tbl.h: Add andab and orab instructions.
1287
1288 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1289
1290         * arc-nps400-tbl.h: Add addl-like instructions.
1291
1292 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1293
1294         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1295
1296 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1297
1298         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1299         instructions.
1300
1301 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1302
1303         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1304         variable.
1305         (init_disasm): Handle new command line option "insnlength".
1306         (print_s390_disassembler_options): Mention new option in help
1307         output.
1308         (print_insn_s390): Use the encoded insn length when dumping
1309         unknown instructions.
1310
1311 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1312
1313         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1314          to the address and set as symbol address for LDS/ STS immediate operands.
1315
1316 2016-06-07  Alan Modra  <amodra@gmail.com>
1317
1318         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1319         cpu for "vle" to e500.
1320         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1321         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1322         (PPCNONE): Delete, substitute throughout.
1323         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1324         except for major opcode 4 and 31.
1325         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1326
1327 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1328
1329         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1330         ARM_EXT_RAS in relevant entries.
1331
1332 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1333
1334         PR binutils/20196
1335         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1336         opcodes for E6500.
1337
1338 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1339
1340         PR binutis/18386
1341         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1342         (indir_v_mode): New.
1343         Add comments for '&'.
1344         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1345         (putop): Handle '&'.
1346         (intel_operand_size): Handle indir_v_mode.
1347         (OP_E_register): Likewise.
1348         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1349         64-bit indirect call/jmp for AMD64.
1350         * i386-tbl.h: Regenerated
1351
1352 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1353
1354         * arc-dis.c (struct arc_operand_iterator): New structure.
1355         (find_format_from_table): All the old content from find_format,
1356         with some minor adjustments, and parameter renaming.
1357         (find_format_long_instructions): New function.
1358         (find_format): Rewritten.
1359         (arc_insn_length): Add LSB parameter.
1360         (extract_operand_value): New function.
1361         (operand_iterator_next): New function.
1362         (print_insn_arc): Use new functions to find opcode, and iterator
1363         over operands.
1364         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1365         (extract_nps_3bit_dst_short): New function.
1366         (insert_nps_3bit_src2_short): New function.
1367         (extract_nps_3bit_src2_short): New function.
1368         (insert_nps_bitop1_size): New function.
1369         (extract_nps_bitop1_size): New function.
1370         (insert_nps_bitop2_size): New function.
1371         (extract_nps_bitop2_size): New function.
1372         (insert_nps_bitop_mod4_msb): New function.
1373         (extract_nps_bitop_mod4_msb): New function.
1374         (insert_nps_bitop_mod4_lsb): New function.
1375         (extract_nps_bitop_mod4_lsb): New function.
1376         (insert_nps_bitop_dst_pos3_pos4): New function.
1377         (extract_nps_bitop_dst_pos3_pos4): New function.
1378         (insert_nps_bitop_ins_ext): New function.
1379         (extract_nps_bitop_ins_ext): New function.
1380         (arc_operands): Add new operands.
1381         (arc_long_opcodes): New global array.
1382         (arc_num_long_opcodes): New global.
1383         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1384
1385 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1386
1387         * nds32-asm.h: Add extern "C".
1388         * sh-opc.h: Likewise.
1389
1390 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1391
1392         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1393         0,b,limm to the rflt instruction.
1394
1395 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1396
1397         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1398         constant.
1399
1400 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1401
1402         PR gas/20145
1403         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1404         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1405         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1406         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1407         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1408         * i386-init.h: Regenerated.
1409
1410 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1411
1412         PR gas/20145
1413         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1414         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1415         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1416         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1417         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1418         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1419         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1420         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1421         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1422         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1423         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1424         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1425         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1426         CpuRegMask for AVX512.
1427         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1428         and CpuRegMask.
1429         (set_bitfield_from_cpu_flag_init): New function.
1430         (set_bitfield): Remove const on f.  Call
1431         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1432         * i386-opc.h (CpuRegMMX): New.
1433         (CpuRegXMM): Likewise.
1434         (CpuRegYMM): Likewise.
1435         (CpuRegZMM): Likewise.
1436         (CpuRegMask): Likewise.
1437         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1438         and cpuregmask.
1439         * i386-init.h: Regenerated.
1440         * i386-tbl.h: Likewise.
1441
1442 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1443
1444         PR gas/20154
1445         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1446         (opcode_modifiers): Add AMD64 and Intel64.
1447         (main): Properly verify CpuMax.
1448         * i386-opc.h (CpuAMD64): Removed.
1449         (CpuIntel64): Likewise.
1450         (CpuMax): Set to CpuNo64.
1451         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1452         (AMD64): New.
1453         (Intel64): Likewise.
1454         (i386_opcode_modifier): Add amd64 and intel64.
1455         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1456         on call and jmp.
1457         * i386-init.h: Regenerated.
1458         * i386-tbl.h: Likewise.
1459
1460 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1461
1462         PR gas/20154
1463         * i386-gen.c (main): Fail if CpuMax is incorrect.
1464         * i386-opc.h (CpuMax): Set to CpuIntel64.
1465         * i386-tbl.h: Regenerated.
1466
1467 2016-05-27  Nick Clifton  <nickc@redhat.com>
1468
1469         PR target/20150
1470         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1471         (msp430dis_opcode_unsigned): New function.
1472         (msp430dis_opcode_signed): New function.
1473         (msp430_singleoperand): Use the new opcode reading functions.
1474         Only disassenmble bytes if they were successfully read.
1475         (msp430_doubleoperand): Likewise.
1476         (msp430_branchinstr): Likewise.
1477         (msp430x_callx_instr): Likewise.
1478         (print_insn_msp430): Check that it is safe to read bytes before
1479         attempting disassembly.  Use the new opcode reading functions.
1480
1481 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1482
1483         * ppc-opc.c (CY): New define.  Document it.
1484         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1485
1486 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1487
1488         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1489         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1490         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1491         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1492         CPU_ANY_AVX_FLAGS.
1493         * i386-init.h: Regenerated.
1494
1495 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1496
1497         PR gas/20141
1498         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1499         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1500         * i386-init.h: Regenerated.
1501
1502 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1503
1504         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1505         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1506         * i386-init.h: Regenerated.
1507
1508 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1509
1510         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1511         information.
1512         (print_insn_arc): Set insn_type information.
1513         * arc-opc.c (C_CC): Add F_CLASS_COND.
1514         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1515         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1516         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1517         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1518         (brne, brne_s, jeq_s, jne_s): Likewise.
1519
1520 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1521
1522         * arc-tbl.h (neg): New instruction variant.
1523
1524 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1525
1526         * arc-dis.c (find_format, find_format, get_auxreg)
1527         (print_insn_arc): Changed.
1528         * arc-ext.h (INSERT_XOP): Likewise.
1529
1530 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1531
1532         * tic54x-dis.c (sprint_mmr): Adjust.
1533         * tic54x-opc.c: Likewise.
1534
1535 2016-05-19  Alan Modra  <amodra@gmail.com>
1536
1537         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1538
1539 2016-05-19  Alan Modra  <amodra@gmail.com>
1540
1541         * ppc-opc.c: Formatting.
1542         (NSISIGNOPT): Define.
1543         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1544
1545 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1546
1547         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1548         replacing references to `micromips_ase' throughout.
1549         (_print_insn_mips): Don't use file-level microMIPS annotation to
1550         determine the disassembly mode with the symbol table.
1551
1552 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1553
1554         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1555
1556 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1557
1558         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1559         mips64r6.
1560         * mips-opc.c (D34): New macro.
1561         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1562
1563 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1564
1565         * i386-dis.c (prefix_table): Add RDPID instruction.
1566         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1567         (cpu_flags): Add RDPID bitfield.
1568         * i386-opc.h (enum): Add RDPID element.
1569         (i386_cpu_flags): Add RDPID field.
1570         * i386-opc.tbl: Add RDPID instruction.
1571         * i386-init.h: Regenerate.
1572         * i386-tbl.h: Regenerate.
1573
1574 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1575
1576         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1577         branch type of a symbol.
1578         (print_insn): Likewise.
1579
1580 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1581
1582         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1583         Mainline Security Extensions instructions.
1584         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1585         Extensions instructions.
1586         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1587         instructions.
1588         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1589         special registers.
1590
1591 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1592
1593         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1594
1595 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1596
1597         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1598         (arcExtMap_genOpcode): Likewise.
1599         * arc-opc.c (arg_32bit_rc): Define new variable.
1600         (arg_32bit_u6): Likewise.
1601         (arg_32bit_limm): Likewise.
1602
1603 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1604
1605         * aarch64-gen.c (VERIFIER): Define.
1606         * aarch64-opc.c (VERIFIER): Define.
1607         (verify_ldpsw): Use static linkage.
1608         * aarch64-opc.h (verify_ldpsw): Remove.
1609         * aarch64-tbl.h: Use VERIFIER for verifiers.
1610
1611 2016-04-28  Nick Clifton  <nickc@redhat.com>
1612
1613         PR target/19722
1614         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1615         * aarch64-opc.c (verify_ldpsw): New function.
1616         * aarch64-opc.h (verify_ldpsw): New prototype.
1617         * aarch64-tbl.h: Add initialiser for verifier field.
1618         (LDPSW): Set verifier to verify_ldpsw.
1619
1620 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1621
1622         PR binutils/19983
1623         PR binutils/19984
1624         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1625         smaller than address size.
1626
1627 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1628
1629         * alpha-dis.c: Regenerate.
1630         * crx-dis.c: Likewise.
1631         * disassemble.c: Likewise.
1632         * epiphany-opc.c: Likewise.
1633         * fr30-opc.c: Likewise.
1634         * frv-opc.c: Likewise.
1635         * ip2k-opc.c: Likewise.
1636         * iq2000-opc.c: Likewise.
1637         * lm32-opc.c: Likewise.
1638         * lm32-opinst.c: Likewise.
1639         * m32c-opc.c: Likewise.
1640         * m32r-opc.c: Likewise.
1641         * m32r-opinst.c: Likewise.
1642         * mep-opc.c: Likewise.
1643         * mt-opc.c: Likewise.
1644         * or1k-opc.c: Likewise.
1645         * or1k-opinst.c: Likewise.
1646         * tic80-opc.c: Likewise.
1647         * xc16x-opc.c: Likewise.
1648         * xstormy16-opc.c: Likewise.
1649
1650 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1651
1652         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1653         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1654         calcsd, and calcxd instructions.
1655         * arc-opc.c (insert_nps_bitop_size): Delete.
1656         (extract_nps_bitop_size): Delete.
1657         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1658         (extract_nps_qcmp_m3): Define.
1659         (extract_nps_qcmp_m2): Define.
1660         (extract_nps_qcmp_m1): Define.
1661         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1662         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1663         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1664         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1665         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1666         NPS_QCMP_M3.
1667
1668 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1669
1670         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1671
1672 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1673
1674         * Makefile.in: Regenerated with automake 1.11.6.
1675         * aclocal.m4: Likewise.
1676
1677 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1678
1679         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1680         instructions.
1681         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1682         (extract_nps_cmem_uimm16): New function.
1683         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1684
1685 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1686
1687         * arc-dis.c (arc_insn_length): New function.
1688         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1689         (find_format): Change insnLen parameter to unsigned.
1690
1691 2016-04-13  Nick Clifton  <nickc@redhat.com>
1692
1693         PR target/19937
1694         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1695         the LD.B and LD.BU instructions.
1696
1697 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1698
1699         * arc-dis.c (find_format): Check for extension flags.
1700         (print_flags): New function.
1701         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1702         .extAuxRegister.
1703         * arc-ext.c (arcExtMap_coreRegName): Use
1704         LAST_EXTENSION_CORE_REGISTER.
1705         (arcExtMap_coreReadWrite): Likewise.
1706         (dump_ARC_extmap): Update printing.
1707         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1708         (arc_aux_regs): Add cpu field.
1709         * arc-regs.h: Add cpu field, lower case name aux registers.
1710
1711 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1712
1713         * arc-tbl.h: Add rtsc, sleep with no arguments.
1714
1715 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1716
1717         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1718         Initialize.
1719         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1720         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1721         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1722         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1723         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1724         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1725         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1726         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1727         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1728         (arc_opcode arc_opcodes): Null terminate the array.
1729         (arc_num_opcodes): Remove.
1730         * arc-ext.h (INSERT_XOP): Define.
1731         (extInstruction_t): Likewise.
1732         (arcExtMap_instName): Delete.
1733         (arcExtMap_insn): New function.
1734         (arcExtMap_genOpcode): Likewise.
1735         * arc-ext.c (ExtInstruction): Remove.
1736         (create_map): Zero initialize instruction fields.
1737         (arcExtMap_instName): Remove.
1738         (arcExtMap_insn): New function.
1739         (dump_ARC_extmap): More info while debuging.
1740         (arcExtMap_genOpcode): New function.
1741         * arc-dis.c (find_format): New function.
1742         (print_insn_arc): Use find_format.
1743         (arc_get_disassembler): Enable dump_ARC_extmap only when
1744         debugging.
1745
1746 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1747
1748         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1749         instruction bits out.
1750
1751 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1752
1753         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1754         * arc-opc.c (arc_flag_operands): Add new flags.
1755         (arc_flag_classes): Add new classes.
1756
1757 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1758
1759         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1760
1761 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1762
1763         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1764         encode1, rflt, crc16, and crc32 instructions.
1765         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1766         (arc_flag_classes): Add C_NPS_R.
1767         (insert_nps_bitop_size_2b): New function.
1768         (extract_nps_bitop_size_2b): Likewise.
1769         (insert_nps_bitop_uimm8): Likewise.
1770         (extract_nps_bitop_uimm8): Likewise.
1771         (arc_operands): Add new operand entries.
1772
1773 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1774
1775         * arc-regs.h: Add a new subclass field.  Add double assist
1776         accumulator register values.
1777         * arc-tbl.h: Use DPA subclass to mark the double assist
1778         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1779         * arc-opc.c (RSP): Define instead of SP.
1780         (arc_aux_regs): Add the subclass field.
1781
1782 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1783
1784         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1785
1786 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1787
1788         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1789         NPS_R_SRC1.
1790
1791 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1792
1793         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1794         issues.  No functional changes.
1795
1796 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1797
1798         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1799         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1800         (RTT): Remove duplicate.
1801         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1802         (PCT_CONFIG*): Remove.
1803         (D1L, D1H, D2H, D2L): Define.
1804
1805 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1806
1807         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1808
1809 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1810
1811         * arc-tbl.h (invld07): Remove.
1812         * arc-ext-tbl.h: New file.
1813         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1814         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1815
1816 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1817
1818         Fix -Wstack-usage warnings.
1819         * aarch64-dis.c (print_operands): Substitute size.
1820         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1821
1822 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1823
1824         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1825         to get a proper diagnostic when an invalid ASR register is used.
1826
1827 2016-03-22  Nick Clifton  <nickc@redhat.com>
1828
1829         * configure: Regenerate.
1830
1831 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1832
1833         * arc-nps400-tbl.h: New file.
1834         * arc-opc.c: Add top level comment.
1835         (insert_nps_3bit_dst): New function.
1836         (extract_nps_3bit_dst): New function.
1837         (insert_nps_3bit_src2): New function.
1838         (extract_nps_3bit_src2): New function.
1839         (insert_nps_bitop_size): New function.
1840         (extract_nps_bitop_size): New function.
1841         (arc_flag_operands): Add nps400 entries.
1842         (arc_flag_classes): Add nps400 entries.
1843         (arc_operands): Add nps400 entries.
1844         (arc_opcodes): Add nps400 include.
1845
1846 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1847
1848         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1849         the new class enum values.
1850
1851 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1852
1853         * arc-dis.c (print_insn_arc): Handle nps400.
1854
1855 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1856
1857         * arc-opc.c (BASE): Delete.
1858
1859 2016-03-18  Nick Clifton  <nickc@redhat.com>
1860
1861         PR target/19721
1862         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1863         of MOV insn that aliases an ORR insn.
1864
1865 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1866
1867         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1868
1869 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1870
1871         * mcore-opc.h: Add const qualifiers.
1872         * microblaze-opc.h (struct op_code_struct): Likewise.
1873         * sh-opc.h: Likewise.
1874         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1875         (tic4x_print_op): Likewise.
1876
1877 2016-03-02  Alan Modra  <amodra@gmail.com>
1878
1879         * or1k-desc.h: Regenerate.
1880         * fr30-ibld.c: Regenerate.
1881         * rl78-decode.c: Regenerate.
1882
1883 2016-03-01  Nick Clifton  <nickc@redhat.com>
1884
1885         PR target/19747
1886         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1887
1888 2016-02-24  Renlin Li  <renlin.li@arm.com>
1889
1890         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1891         (print_insn_coprocessor): Support fp16 instructions.
1892
1893 2016-02-24  Renlin Li  <renlin.li@arm.com>
1894
1895         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1896         vminnm, vrint(mpna).
1897
1898 2016-02-24  Renlin Li  <renlin.li@arm.com>
1899
1900         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1901         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1902
1903 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1904
1905         * i386-dis.c (print_insn): Parenthesize expression to prevent
1906         truncated addresses.
1907         (OP_J): Likewise.
1908
1909 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1910             Janek van Oirschot  <jvanoirs@synopsys.com>
1911
1912         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1913         variable.
1914
1915 2016-02-04  Nick Clifton  <nickc@redhat.com>
1916
1917         PR target/19561
1918         * msp430-dis.c (print_insn_msp430): Add a special case for
1919         decoding an RRC instruction with the ZC bit set in the extension
1920         word.
1921
1922 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1923
1924         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1925         * epiphany-ibld.c: Regenerate.
1926         * fr30-ibld.c: Regenerate.
1927         * frv-ibld.c: Regenerate.
1928         * ip2k-ibld.c: Regenerate.
1929         * iq2000-ibld.c: Regenerate.
1930         * lm32-ibld.c: Regenerate.
1931         * m32c-ibld.c: Regenerate.
1932         * m32r-ibld.c: Regenerate.
1933         * mep-ibld.c: Regenerate.
1934         * mt-ibld.c: Regenerate.
1935         * or1k-ibld.c: Regenerate.
1936         * xc16x-ibld.c: Regenerate.
1937         * xstormy16-ibld.c: Regenerate.
1938
1939 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1940
1941         * epiphany-dis.c: Regenerated from latest cpu files.
1942
1943 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1944
1945         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1946         test bit.
1947
1948 2016-01-25  Renlin Li  <renlin.li@arm.com>
1949
1950         * arm-dis.c (mapping_symbol_for_insn): New function.
1951         (find_ifthen_state): Call mapping_symbol_for_insn().
1952
1953 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1954
1955         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1956         of MSR UAO immediate operand.
1957
1958 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1959
1960         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1961         instruction support.
1962
1963 2016-01-17  Alan Modra  <amodra@gmail.com>
1964
1965         * configure: Regenerate.
1966
1967 2016-01-14  Nick Clifton  <nickc@redhat.com>
1968
1969         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1970         instructions that can support stack pointer operations.
1971         * rl78-decode.c: Regenerate.
1972         * rl78-dis.c: Fix display of stack pointer in MOVW based
1973         instructions.
1974
1975 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1976
1977         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1978         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1979         erxtatus_el1 and erxaddr_el1.
1980
1981 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1982
1983         * arm-dis.c (arm_opcodes): Add "esb".
1984         (thumb_opcodes): Likewise.
1985
1986 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1987
1988         * ppc-opc.c <xscmpnedp>: Delete.
1989         <xvcmpnedp>: Likewise.
1990         <xvcmpnedp.>: Likewise.
1991         <xvcmpnesp>: Likewise.
1992         <xvcmpnesp.>: Likewise.
1993
1994 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1995
1996         PR gas/13050
1997         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1998         addition to ISA_A.
1999
2000 2016-01-01  Alan Modra  <amodra@gmail.com>
2001
2002         Update year range in copyright notice of all files.
2003
2004 For older changes see ChangeLog-2015
2005 \f
2006 Copyright (C) 2016 Free Software Foundation, Inc.
2007
2008 Copying and distribution of this file, with or without modification,
2009 are permitted in any medium without royalty provided the copyright
2010 notice and this notice are preserved.
2011
2012 Local Variables:
2013 mode: change-log
2014 left-margin: 8
2015 fill-column: 74
2016 version-control: never
2017 End: