opcodes/ChangeLog

   1 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
   2
   3         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
   4         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
   5         * i386-dis-evex.h (evex_table): Updated.
   6         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
   7         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
   8         (cpu_flags): Add CpuAVX512_4FMAPS.
   9         (opcode_modifiers): Add ImplicitQuadGroup modifier.
  10         * i386-opc.h (AVX512_4FMAP): New.
  11         (i386_cpu_flags): Add cpuavx512_4fmaps.
  12         (ImplicitQuadGroup): New.
  13         (i386_opcode_modifier): Add implicitquadgroup.
  14         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
  15         * i386-init.h: Regenerate.
  16         * i386-tbl.h: Ditto.
  17
  18 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
  19             Andrew Waterman <andrew@sifive.com>
  20
  21         Add support for RISC-V architecture.
  22         * configure.ac: Add entry for bfd_riscv_arch.
  23         * configure: Regenerate.
  24         * disassemble.c (disassembler): Add support for riscv.
  25         (disassembler_usage): Likewise.
  26         * riscv-dis.c: New file.
  27         * riscv-opc.c: New file.
  28
  29 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
  32         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
  33         (rm_table): Update the RM_0FAE_REG_7 entry.
  34         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
  35         (cpu_flags): Remove CpuPCOMMIT.
  36         * i386-opc.h (CpuPCOMMIT): Removed.
  37         (i386_cpu_flags): Remove cpupcommit.
  38         * i386-opc.tbl: Remove pcommit.
  39         * i386-init.h: Regenerated.
  40         * i386-tbl.h: Likewise.
  41
  42 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         PR binutis/20705
  45         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
  46         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
  47         32-bit mode.  Don't check vex.register_specifier in 32-bit
  48         mode.
  49         (OP_VEX): Check for invalid mask registers.
  50
  51 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
  52
  53         PR binutis/20699
  54         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
  55         sizeflag.
  56
  57 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
  58
  59         PR binutis/20704
  60         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
  61
  62 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
  63
  64         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
  65         local variable to `index_regno'.
  66
  67 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
  68
  69         * arc-tbl.h: Removed any "inv.+" instructions from the table.
  70
  71 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
  72
  73         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
  74         usage on ISA basis.
  75
  76 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
  77
  78         PR target/20666
  79         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
  80
  81 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
  82
  83         PR target/20667
  84         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
  85         available.
  86
  87 2016-10-07  Alan Modra  <amodra@gmail.com>
  88
  89         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
  90
  91 2016-10-06  Alan Modra  <amodra@gmail.com>
  92
  93         * aarch64-opc.c: Spell fall through comments consistently.
  94         * i386-dis.c: Likewise.
  95         * aarch64-dis.c: Add missing fall through comments.
  96         * aarch64-opc.c: Likewise.
  97         * arc-dis.c: Likewise.
  98         * arm-dis.c: Likewise.
  99         * i386-dis.c: Likewise.
 100         * m68k-dis.c: Likewise.
 101         * mep-asm.c: Likewise.
 102         * ns32k-dis.c: Likewise.
 103         * sh-dis.c: Likewise.
 104         * tic4x-dis.c: Likewise.
 105         * tic6x-dis.c: Likewise.
 106         * vax-dis.c: Likewise.
 107
 108 2016-10-06  Alan Modra  <amodra@gmail.com>
 109
 110         * arc-ext.c (create_map): Add missing break.
 111         * msp430-decode.opc (encode_as): Likewise.
 112         * msp430-decode.c: Regenerate.
 113
 114 2016-10-06  Alan Modra  <amodra@gmail.com>
 115
 116         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 117         * crx-dis.c (print_insn_crx): Likewise.
 118
 119 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         PR binutils/20657
 122         * i386-dis.c (putop): Don't assign alt twice.
 123
 124 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 125
 126         PR target/20553
 127         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 128
 129 2016-09-29  Alan Modra  <amodra@gmail.com>
 130
 131         * ppc-opc.c (L): Make compulsory.
 132         (LOPT): New, optional form of L.
 133         (HTM_R): Define as LOPT.
 134         (L0, L1): Delete.
 135         (L32OPT): New, optional for 32-bit L.
 136         (L2OPT): New, 2-bit L for dcbf.
 137         (SVC_LEC): Update.
 138         (L2): Define.
 139         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 140         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 141         <dcbf>: Use L2OPT.
 142         <tlbiel, tlbie>: Use LOPT.
 143         <wclr, wclrall>: Use L2.
 144
 145 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 146
 147         * Makefile.in: Regenerate.
 148         * configure: Likewise.
 149
 150 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 151
 152         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 153         (EXTINSN2OP): Use EXTINSN2OPF.
 154         (bspeekm, bspop, modapp): New extension instructions.
 155         * arc-opc.c (F_DNZ_ND): Define.
 156         (F_DNZ_D): Likewise.
 157         (F_SIZEB1): Changed.
 158         (C_DNZ_D): Define.
 159         (C_HARD): Changed.
 160         * arc-tbl.h (dbnz): New instruction.
 161         (prealloc): Allow it for ARC EM.
 162         (xbfu): Likewise.
 163
 164 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 165
 166         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 167         after commas in addresses.
 168         (aarch64_print_operand): Likewise.
 169
 170 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 171
 172         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 173         rather than "should be" or "expected to be" in error messages.
 174
 175 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 176
 177         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 178         (print_mnemonic_name): ...here.
 179         (print_comment): New function.
 180         (print_aarch64_insn): Call it.
 181         * aarch64-opc.c (aarch64_conds): Add SVE names.
 182         (aarch64_print_operand): Print alternative condition names in
 183         a comment.
 184
 185 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 186
 187         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 188         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 189         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 190         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 191         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 192         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 193         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 194         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 195         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 196         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 197         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 198         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 199         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 200         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 201         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 202         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 203         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 204         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 205         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 206         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 207         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 208         (aarch64_feature_sve): New variable.
 209         (SVE): New macro.
 210         (_SVE_INSN): Likewise.
 211         (aarch64_opcode_table): Add SVE instructions.
 212         * aarch64-opc.h (extract_fields): Declare.
 213         * aarch64-opc-2.c: Regenerate.
 214         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 215         * aarch64-asm-2.c: Regenerate.
 216         * aarch64-dis.c (extract_fields): Make global.
 217         (do_misc_decoding): Handle the new SVE aarch64_ops.
 218         * aarch64-dis-2.c: Regenerate.
 219
 220 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 221
 222         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 223         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 224         aarch64_field_kinds.
 225         * aarch64-opc.c (fields): Add corresponding entries.
 226         * aarch64-asm.c (aarch64_get_variant): New function.
 227         (aarch64_encode_variant_using_iclass): Likewise.
 228         (aarch64_opcode_encode): Call it.
 229         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 230         (aarch64_opcode_decode): Call it.
 231
 232 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 233
 234         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 235         and FP register operands.
 236         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 237         (FLD_SVE_Vn): New aarch64_field_kinds.
 238         * aarch64-opc.c (fields): Add corresponding entries.
 239         (aarch64_print_operand): Handle the new SVE core and FP register
 240         operands.
 241         * aarch64-opc-2.c: Regenerate.
 242         * aarch64-asm-2.c: Likewise.
 243         * aarch64-dis-2.c: Likewise.
 244
 245 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 246
 247         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 248         immediate operands.
 249         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 250         * aarch64-opc.c (fields): Add corresponding entry.
 251         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 252         operands.
 253         (aarch64_print_operand): Likewise.
 254         * aarch64-opc-2.c: Regenerate.
 255         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 256         (ins_sve_float_zero_one): New inserters.
 257         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 258         (aarch64_ins_sve_float_half_two): Likewise.
 259         (aarch64_ins_sve_float_zero_one): Likewise.
 260         * aarch64-asm-2.c: Regenerate.
 261         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 262         (ext_sve_float_zero_one): New extractors.
 263         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 264         (aarch64_ext_sve_float_half_two): Likewise.
 265         (aarch64_ext_sve_float_zero_one): Likewise.
 266         * aarch64-dis-2.c: Regenerate.
 267
 268 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 269
 270         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 271         integer immediate operands.
 272         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 273         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 274         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 275         * aarch64-opc.c (fields): Add corresponding entries.
 276         (operand_general_constraint_met_p): Handle the new SVE integer
 277         immediate operands.
 278         (aarch64_print_operand): Likewise.
 279         (aarch64_sve_dupm_mov_immediate_p): New function.
 280         * aarch64-opc-2.c: Regenerate.
 281         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 282         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 283         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 284         (aarch64_ins_limm): ...here.
 285         (aarch64_ins_inv_limm): New function.
 286         (aarch64_ins_sve_aimm): Likewise.
 287         (aarch64_ins_sve_asimm): Likewise.
 288         (aarch64_ins_sve_limm_mov): Likewise.
 289         (aarch64_ins_sve_shlimm): Likewise.
 290         (aarch64_ins_sve_shrimm): Likewise.
 291         * aarch64-asm-2.c: Regenerate.
 292         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 293         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 294         * aarch64-dis.c (decode_limm): New function, split out from...
 295         (aarch64_ext_limm): ...here.
 296         (aarch64_ext_inv_limm): New function.
 297         (decode_sve_aimm): Likewise.
 298         (aarch64_ext_sve_aimm): Likewise.
 299         (aarch64_ext_sve_asimm): Likewise.
 300         (aarch64_ext_sve_limm_mov): Likewise.
 301         (aarch64_top_bit): Likewise.
 302         (aarch64_ext_sve_shlimm): Likewise.
 303         (aarch64_ext_sve_shrimm): Likewise.
 304         * aarch64-dis-2.c: Regenerate.
 305
 306 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 307
 308         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 309         operands.
 310         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 311         the AARCH64_MOD_MUL_VL entry.
 312         (value_aligned_p): Cope with non-power-of-two alignments.
 313         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 314         (print_immediate_offset_address): Likewise.
 315         (aarch64_print_operand): Likewise.
 316         * aarch64-opc-2.c: Regenerate.
 317         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 318         (ins_sve_addr_ri_s9xvl): New inserters.
 319         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 320         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 321         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 322         * aarch64-asm-2.c: Regenerate.
 323         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 324         (ext_sve_addr_ri_s9xvl): New extractors.
 325         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 326         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 327         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 328         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 329         * aarch64-dis-2.c: Regenerate.
 330
 331 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 332
 333         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 334         address operands.
 335         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 336         (FLD_SVE_xs_22): New aarch64_field_kinds.
 337         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 338         (get_operand_specific_data): New function.
 339         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 340         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 341         (operand_general_constraint_met_p): Handle the new SVE address
 342         operands.
 343         (sve_reg): New array.
 344         (get_addr_sve_reg_name): New function.
 345         (aarch64_print_operand): Handle the new SVE address operands.
 346         * aarch64-opc-2.c: Regenerate.
 347         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 348         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 349         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 350         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 351         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 352         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 353         (aarch64_ins_sve_addr_zi_u5): Likewise.
 354         (aarch64_ins_sve_addr_zz): Likewise.
 355         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 356         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 357         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 358         * aarch64-asm-2.c: Regenerate.
 359         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 360         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 361         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 362         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 363         (aarch64_ext_sve_addr_ri_u6): Likewise.
 364         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 365         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 366         (aarch64_ext_sve_addr_zi_u5): Likewise.
 367         (aarch64_ext_sve_addr_zz): Likewise.
 368         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 369         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 370         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 371         * aarch64-dis-2.c: Regenerate.
 372
 373 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 374
 375         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 376         AARCH64_OPND_SVE_PATTERN_SCALED.
 377         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 378         * aarch64-opc.c (fields): Add a corresponding entry.
 379         (set_multiplier_out_of_range_error): New function.
 380         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 381         (operand_general_constraint_met_p): Handle
 382         AARCH64_OPND_SVE_PATTERN_SCALED.
 383         (print_register_offset_address): Use PRIi64 to print the
 384         shift amount.
 385         (aarch64_print_operand): Likewise.  Handle
 386         AARCH64_OPND_SVE_PATTERN_SCALED.
 387         * aarch64-opc-2.c: Regenerate.
 388         * aarch64-asm.h (ins_sve_scale): New inserter.
 389         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 390         * aarch64-asm-2.c: Regenerate.
 391         * aarch64-dis.h (ext_sve_scale): New inserter.
 392         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 393         * aarch64-dis-2.c: Regenerate.
 394
 395 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 396
 397         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 398         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 399         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 400         (FLD_SVE_prfop): Likewise.
 401         * aarch64-opc.c: Include libiberty.h.
 402         (aarch64_sve_pattern_array): New variable.
 403         (aarch64_sve_prfop_array): Likewise.
 404         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 405         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 406         AARCH64_OPND_SVE_PRFOP.
 407         * aarch64-asm-2.c: Regenerate.
 408         * aarch64-dis-2.c: Likewise.
 409         * aarch64-opc-2.c: Likewise.
 410
 411 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 412
 413         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 414         AARCH64_OPND_QLF_P_[ZM].
 415         (aarch64_print_operand): Print /z and /m where appropriate.
 416
 417 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 418
 419         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 420         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 421         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 422         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 423         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 424         * aarch64-opc.c (fields): Add corresponding entries here.
 425         (operand_general_constraint_met_p): Check that SVE register lists
 426         have the correct length.  Check the ranges of SVE index registers.
 427         Check for cases where p8-p15 are used in 3-bit predicate fields.
 428         (aarch64_print_operand): Handle the new SVE operands.
 429         * aarch64-opc-2.c: Regenerate.
 430         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 431         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 432         (aarch64_ins_sve_reglist): Likewise.
 433         * aarch64-asm-2.c: Regenerate.
 434         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 435         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 436         (aarch64_ext_sve_reglist): Likewise.
 437         * aarch64-dis-2.c: Regenerate.
 438
 439 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 440
 441         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 442         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 443         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 444         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 445         tied operands.
 446
 447 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 448
 449         * aarch64-opc.c (get_offset_int_reg_name): New function.
 450         (print_immediate_offset_address): Likewise.
 451         (print_register_offset_address): Take the base and offset
 452         registers as parameters.
 453         (aarch64_print_operand): Update caller accordingly.  Use
 454         print_immediate_offset_address.
 455
 456 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 457
 458         * aarch64-opc.c (BANK): New macro.
 459         (R32, R64): Take a register number as argument
 460         (int_reg): Use BANK.
 461
 462 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 463
 464         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 465         (aarch64_print_operand): Update accordingly.
 466
 467 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 468
 469         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 470         for FPIMM.
 471         * aarch64-asm.h (ins_fpimm): New inserter.
 472         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 473         * aarch64-asm-2.c: Regenerate.
 474         * aarch64-dis.h (ext_fpimm): New extractor.
 475         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 476         (aarch64_ext_fpimm): New function.
 477         * aarch64-dis-2.c: Regenerate.
 478
 479 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 480
 481         * aarch64-asm.c: Include libiberty.h.
 482         (insert_fields): New function.
 483         (aarch64_ins_imm): Use it.
 484         * aarch64-dis.c (extract_fields): New function.
 485         (aarch64_ext_imm): Use it.
 486
 487 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 488
 489         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 490         with an esize parameter.
 491         (operand_general_constraint_met_p): Update accordingly.
 492         Fix misindented code.
 493         * aarch64-asm.c (aarch64_ins_limm): Update call to
 494         aarch64_logical_immediate_p.
 495
 496 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 497
 498         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 499
 500 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 501
 502         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 503
 504 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 505
 506         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 507
 508 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 509
 510         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 511         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 512         xor3>: Delete mnemonics.
 513         <cp_abort>: Rename mnemonic from ...
 514         <cpabort>: ...to this.
 515         <setb>: Change to a X form instruction.
 516         <sync>: Change to 1 operand form.
 517         <copy>: Delete mnemonic.
 518         <copy_first>: Rename mnemonic from ...
 519         <copy>: ...to this.
 520         <paste, paste.>: Delete mnemonics.
 521         <paste_last>: Rename mnemonic from ...
 522         <paste.>: ...to this.
 523
 524 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 525
 526         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 527
 528 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 529
 530         * s390-mkopc.c (main): Support alternate arch strings.
 531
 532 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 533
 534         * s390-opc.txt: Fix kmctr instruction type.
 535
 536 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 537
 538         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 539         * i386-init.h: Regenerated.
 540
 541 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 542
 543         * opcodes/arc-dis.c (print_insn_arc): Changed.
 544
 545 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 546
 547         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 548         camellia_fl.
 549
 550 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 551
 552         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 553         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 554         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 555
 556 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 557
 558         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 559         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 560         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 561         PREFIX_MOD_3_0FAE_REG_4.
 562         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 563         PREFIX_MOD_3_0FAE_REG_4.
 564         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 565         (cpu_flags): Add CpuPTWRITE.
 566         * i386-opc.h (CpuPTWRITE): New.
 567         (i386_cpu_flags): Add cpuptwrite.
 568         * i386-opc.tbl: Add ptwrite instruction.
 569         * i386-init.h: Regenerated.
 570         * i386-tbl.h: Likewise.
 571
 572 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 573
 574         * arc-dis.h: Wrap around in extern "C".
 575
 576 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 577
 578         * aarch64-tbl.h (V8_2_INSN): New macro.
 579         (aarch64_opcode_table): Use it.
 580
 581 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 582
 583         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 584         CORE_INSN, __FP_INSN and SIMD_INSN.
 585
 586 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 587
 588         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 589         (aarch64_opcode_table): Update uses accordingly.
 590
 591 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 592         Kwok Cheung Yeung  <kcy@codesourcery.com>
 593
 594         opcodes/
 595         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 596         'e_cmplwi' to 'e_cmpli' instead.
 597         (OPVUPRT, OPVUPRT_MASK): Define.
 598         (powerpc_opcodes): Add E200Z4 insns.
 599         (vle_opcodes): Add context save/restore insns.
 600
 601 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 602
 603         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 604         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 605         "j".
 606
 607 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 608
 609         * arc-nps400-tbl.h: Change block comments to GNU format.
 610         * arc-dis.c: Add new globals addrtypenames,
 611         addrtypenames_max, and addtypeunknown.
 612         (get_addrtype): New function.
 613         (print_insn_arc): Print colons and address types when
 614         required.
 615         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 616         define insert and extract functions for all address types.
 617         (arc_operands): Add operands for colon and all address
 618         types.
 619         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 620         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 621         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 622         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 623         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 624         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 625
 626 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 627
 628         * configure: Regenerated.
 629
 630 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 631
 632         * arc-dis.c (skipclass): New structure.
 633         (decodelist): New variable.
 634         (is_compatible_p): New function.
 635         (new_element): Likewise.
 636         (skip_class_p): Likewise.
 637         (find_format_from_table): Use skip_class_p function.
 638         (find_format): Decode first the extension instructions.
 639         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 640         e_flags.
 641         (parse_option): New function.
 642         (parse_disassembler_options): Likewise.
 643         (print_arc_disassembler_options): Likewise.
 644         (print_insn_arc): Use parse_disassembler_options function.  Proper
 645         select ARCv2 cpu variant.
 646         * disassemble.c (disassembler_usage): Add ARC disassembler
 647         options.
 648
 649 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 650
 651         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 652         annotation from the "nal" entry and reorder it beyond "bltzal".
 653
 654 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 655
 656         * sparc-opc.c (ldtxa): New macro.
 657         (sparc_opcodes): Use the macro defined above to add entries for
 658         the LDTXA instructions.
 659         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 660         instruction.
 661
 662 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 663
 664         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 665         and "jmpc".
 666
 667 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 668
 669         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 670         (movzb): Adjust to cover all permitted suffixes.
 671         (movzw): New.
 672         * i386-tbl.h: Re-generate.
 673
 674 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 675
 676         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 677         (lgdt): Remove Tbyte from non-64-bit variant.
 678         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 679         xsaves64, xsavec64): Remove Disp16.
 680         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 681         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 682         64-bit variants.
 683         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 684         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 685         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 686         64-bit variants.
 687         * i386-tbl.h: Re-generate.
 688
 689 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 692         * i386-tbl.h: Re-generate.
 693
 694 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 695
 696         * arm-dis.c (print_insn): Fix typo in comment.
 697
 698 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 699
 700         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 701         range of ldst_elemlist operands.
 702         (print_register_list): Use PRIi64 to print the index.
 703         (aarch64_print_operand): Likewise.
 704
 705 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 706
 707         * mcore-opc.h: Remove sentinal.
 708         * mcore-dis.c (print_insn_mcore): Adjust.
 709
 710 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 711
 712         * arc-opc.c: Correct description of availability of NPS400
 713         features.
 714
 715 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 716
 717         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 718         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 719         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 720         xor3>: New mnemonics.
 721         <setb>: Change to a VX form instruction.
 722         (insert_sh6): Add support for rldixor.
 723         (extract_sh6): Likewise.
 724
 725 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 726
 727         * arc-ext.h: Wrap in extern C.
 728
 729 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 730
 731         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 732         Use same method for determining instruction length on ARC700 and
 733         NPS-400.
 734         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 735         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 736         with the NPS400 subclass.
 737         * arc-opc.c: Likewise.
 738
 739 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 740
 741         * sparc-opc.c (rdasr): New macro.
 742         (wrasr): Likewise.
 743         (rdpr): Likewise.
 744         (wrpr): Likewise.
 745         (rdhpr): Likewise.
 746         (wrhpr): Likewise.
 747         (sparc_opcodes): Use the macros above to fix and expand the
 748         definition of read/write instructions from/to
 749         asr/privileged/hyperprivileged instructions.
 750         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 751         %hva_mask_nz.  Prefer softint_set and softint_clear over
 752         set_softint and clear_softint.
 753         (print_insn_sparc): Support %ver in Rd.
 754
 755 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 756
 757         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 758         architecture according to the hardware capabilities they require.
 759
 760 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 761
 762         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 763         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 764         bfd_mach_sparc_v9{c,d,e,v,m}.
 765         * sparc-opc.c (MASK_V9C): Define.
 766         (MASK_V9D): Likewise.
 767         (MASK_V9E): Likewise.
 768         (MASK_V9V): Likewise.
 769         (MASK_V9M): Likewise.
 770         (v6): Add MASK_V9{C,D,E,V,M}.
 771         (v6notlet): Likewise.
 772         (v7): Likewise.
 773         (v8): Likewise.
 774         (v9): Likewise.
 775         (v9andleon): Likewise.
 776         (v9a): Likewise.
 777         (v9b): Likewise.
 778         (v9c): Define.
 779         (v9d): Likewise.
 780         (v9e): Likewise.
 781         (v9v): Likewise.
 782         (v9m): Likewise.
 783         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 784
 785 2016-06-15  Nick Clifton  <nickc@redhat.com>
 786
 787         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 788         constants to match expected behaviour.
 789         (nds32_parse_opcode): Likewise.  Also for whitespace.
 790
 791 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 792
 793         * arc-opc.c (extract_rhv1): Extract value from insn.
 794
 795 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 796
 797         * arc-nps400-tbl.h: Add ldbit instruction.
 798         * arc-opc.c: Add flag classes required for ldbit.
 799
 800 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 801
 802         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 803         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 804         support the above instructions.
 805
 806 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 807
 808         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 809         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 810         csma, cbba, zncv, and hofs.
 811         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 812         support the above instructions.
 813
 814 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 815
 816         * arc-nps400-tbl.h: Add andab and orab instructions.
 817
 818 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 819
 820         * arc-nps400-tbl.h: Add addl-like instructions.
 821
 822 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 823
 824         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 825
 826 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 827
 828         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 829         instructions.
 830
 831 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 832
 833         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 834         variable.
 835         (init_disasm): Handle new command line option "insnlength".
 836         (print_s390_disassembler_options): Mention new option in help
 837         output.
 838         (print_insn_s390): Use the encoded insn length when dumping
 839         unknown instructions.
 840
 841 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 842
 843         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 844          to the address and set as symbol address for LDS/ STS immediate operands.
 845
 846 2016-06-07  Alan Modra  <amodra@gmail.com>
 847
 848         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 849         cpu for "vle" to e500.
 850         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 851         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 852         (PPCNONE): Delete, substitute throughout.
 853         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 854         except for major opcode 4 and 31.
 855         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 856
 857 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 858
 859         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 860         ARM_EXT_RAS in relevant entries.
 861
 862 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 863
 864         PR binutils/20196
 865         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 866         opcodes for E6500.
 867
 868 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 869
 870         PR binutis/18386
 871         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 872         (indir_v_mode): New.
 873         Add comments for '&'.
 874         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 875         (putop): Handle '&'.
 876         (intel_operand_size): Handle indir_v_mode.
 877         (OP_E_register): Likewise.
 878         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 879         64-bit indirect call/jmp for AMD64.
 880         * i386-tbl.h: Regenerated
 881
 882 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 883
 884         * arc-dis.c (struct arc_operand_iterator): New structure.
 885         (find_format_from_table): All the old content from find_format,
 886         with some minor adjustments, and parameter renaming.
 887         (find_format_long_instructions): New function.
 888         (find_format): Rewritten.
 889         (arc_insn_length): Add LSB parameter.
 890         (extract_operand_value): New function.
 891         (operand_iterator_next): New function.
 892         (print_insn_arc): Use new functions to find opcode, and iterator
 893         over operands.
 894         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 895         (extract_nps_3bit_dst_short): New function.
 896         (insert_nps_3bit_src2_short): New function.
 897         (extract_nps_3bit_src2_short): New function.
 898         (insert_nps_bitop1_size): New function.
 899         (extract_nps_bitop1_size): New function.
 900         (insert_nps_bitop2_size): New function.
 901         (extract_nps_bitop2_size): New function.
 902         (insert_nps_bitop_mod4_msb): New function.
 903         (extract_nps_bitop_mod4_msb): New function.
 904         (insert_nps_bitop_mod4_lsb): New function.
 905         (extract_nps_bitop_mod4_lsb): New function.
 906         (insert_nps_bitop_dst_pos3_pos4): New function.
 907         (extract_nps_bitop_dst_pos3_pos4): New function.
 908         (insert_nps_bitop_ins_ext): New function.
 909         (extract_nps_bitop_ins_ext): New function.
 910         (arc_operands): Add new operands.
 911         (arc_long_opcodes): New global array.
 912         (arc_num_long_opcodes): New global.
 913         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 914
 915 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 916
 917         * nds32-asm.h: Add extern "C".
 918         * sh-opc.h: Likewise.
 919
 920 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 921
 922         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 923         0,b,limm to the rflt instruction.
 924
 925 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 926
 927         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 928         constant.
 929
 930 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 931
 932         PR gas/20145
 933         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 934         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 935         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 936         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 937         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 938         * i386-init.h: Regenerated.
 939
 940 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 941
 942         PR gas/20145
 943         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 944         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 945         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 946         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 947         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 948         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 949         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 950         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 951         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 952         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 953         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 954         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 955         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 956         CpuRegMask for AVX512.
 957         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 958         and CpuRegMask.
 959         (set_bitfield_from_cpu_flag_init): New function.
 960         (set_bitfield): Remove const on f.  Call
 961         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 962         * i386-opc.h (CpuRegMMX): New.
 963         (CpuRegXMM): Likewise.
 964         (CpuRegYMM): Likewise.
 965         (CpuRegZMM): Likewise.
 966         (CpuRegMask): Likewise.
 967         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 968         and cpuregmask.
 969         * i386-init.h: Regenerated.
 970         * i386-tbl.h: Likewise.
 971
 972 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 973
 974         PR gas/20154
 975         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 976         (opcode_modifiers): Add AMD64 and Intel64.
 977         (main): Properly verify CpuMax.
 978         * i386-opc.h (CpuAMD64): Removed.
 979         (CpuIntel64): Likewise.
 980         (CpuMax): Set to CpuNo64.
 981         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 982         (AMD64): New.
 983         (Intel64): Likewise.
 984         (i386_opcode_modifier): Add amd64 and intel64.
 985         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 986         on call and jmp.
 987         * i386-init.h: Regenerated.
 988         * i386-tbl.h: Likewise.
 989
 990 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 991
 992         PR gas/20154
 993         * i386-gen.c (main): Fail if CpuMax is incorrect.
 994         * i386-opc.h (CpuMax): Set to CpuIntel64.
 995         * i386-tbl.h: Regenerated.
 996
 997 2016-05-27  Nick Clifton  <nickc@redhat.com>
 998
 999         PR target/20150
1000         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1001         (msp430dis_opcode_unsigned): New function.
1002         (msp430dis_opcode_signed): New function.
1003         (msp430_singleoperand): Use the new opcode reading functions.
1004         Only disassenmble bytes if they were successfully read.
1005         (msp430_doubleoperand): Likewise.
1006         (msp430_branchinstr): Likewise.
1007         (msp430x_callx_instr): Likewise.
1008         (print_insn_msp430): Check that it is safe to read bytes before
1009         attempting disassembly.  Use the new opcode reading functions.
1010
1011 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1012
1013         * ppc-opc.c (CY): New define.  Document it.
1014         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1015
1016 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1017
1018         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1019         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1020         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1021         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1022         CPU_ANY_AVX_FLAGS.
1023         * i386-init.h: Regenerated.
1024
1025 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1026
1027         PR gas/20141
1028         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1029         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1030         * i386-init.h: Regenerated.
1031
1032 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1033
1034         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1035         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1036         * i386-init.h: Regenerated.
1037
1038 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1039
1040         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1041         information.
1042         (print_insn_arc): Set insn_type information.
1043         * arc-opc.c (C_CC): Add F_CLASS_COND.
1044         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1045         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1046         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1047         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1048         (brne, brne_s, jeq_s, jne_s): Likewise.
1049
1050 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1051
1052         * arc-tbl.h (neg): New instruction variant.
1053
1054 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1055
1056         * arc-dis.c (find_format, find_format, get_auxreg)
1057         (print_insn_arc): Changed.
1058         * arc-ext.h (INSERT_XOP): Likewise.
1059
1060 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1061
1062         * tic54x-dis.c (sprint_mmr): Adjust.
1063         * tic54x-opc.c: Likewise.
1064
1065 2016-05-19  Alan Modra  <amodra@gmail.com>
1066
1067         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1068
1069 2016-05-19  Alan Modra  <amodra@gmail.com>
1070
1071         * ppc-opc.c: Formatting.
1072         (NSISIGNOPT): Define.
1073         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1074
1075 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1076
1077         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1078         replacing references to `micromips_ase' throughout.
1079         (_print_insn_mips): Don't use file-level microMIPS annotation to
1080         determine the disassembly mode with the symbol table.
1081
1082 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1083
1084         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1085
1086 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1087
1088         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1089         mips64r6.
1090         * mips-opc.c (D34): New macro.
1091         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1092
1093 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1094
1095         * i386-dis.c (prefix_table): Add RDPID instruction.
1096         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1097         (cpu_flags): Add RDPID bitfield.
1098         * i386-opc.h (enum): Add RDPID element.
1099         (i386_cpu_flags): Add RDPID field.
1100         * i386-opc.tbl: Add RDPID instruction.
1101         * i386-init.h: Regenerate.
1102         * i386-tbl.h: Regenerate.
1103
1104 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1105
1106         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1107         branch type of a symbol.
1108         (print_insn): Likewise.
1109
1110 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1111
1112         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1113         Mainline Security Extensions instructions.
1114         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1115         Extensions instructions.
1116         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1117         instructions.
1118         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1119         special registers.
1120
1121 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1122
1123         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1124
1125 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1126
1127         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1128         (arcExtMap_genOpcode): Likewise.
1129         * arc-opc.c (arg_32bit_rc): Define new variable.
1130         (arg_32bit_u6): Likewise.
1131         (arg_32bit_limm): Likewise.
1132
1133 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1134
1135         * aarch64-gen.c (VERIFIER): Define.
1136         * aarch64-opc.c (VERIFIER): Define.
1137         (verify_ldpsw): Use static linkage.
1138         * aarch64-opc.h (verify_ldpsw): Remove.
1139         * aarch64-tbl.h: Use VERIFIER for verifiers.
1140
1141 2016-04-28  Nick Clifton  <nickc@redhat.com>
1142
1143         PR target/19722
1144         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1145         * aarch64-opc.c (verify_ldpsw): New function.
1146         * aarch64-opc.h (verify_ldpsw): New prototype.
1147         * aarch64-tbl.h: Add initialiser for verifier field.
1148         (LDPSW): Set verifier to verify_ldpsw.
1149
1150 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1151
1152         PR binutils/19983
1153         PR binutils/19984
1154         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1155         smaller than address size.
1156
1157 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1158
1159         * alpha-dis.c: Regenerate.
1160         * crx-dis.c: Likewise.
1161         * disassemble.c: Likewise.
1162         * epiphany-opc.c: Likewise.
1163         * fr30-opc.c: Likewise.
1164         * frv-opc.c: Likewise.
1165         * ip2k-opc.c: Likewise.
1166         * iq2000-opc.c: Likewise.
1167         * lm32-opc.c: Likewise.
1168         * lm32-opinst.c: Likewise.
1169         * m32c-opc.c: Likewise.
1170         * m32r-opc.c: Likewise.
1171         * m32r-opinst.c: Likewise.
1172         * mep-opc.c: Likewise.
1173         * mt-opc.c: Likewise.
1174         * or1k-opc.c: Likewise.
1175         * or1k-opinst.c: Likewise.
1176         * tic80-opc.c: Likewise.
1177         * xc16x-opc.c: Likewise.
1178         * xstormy16-opc.c: Likewise.
1179
1180 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1181
1182         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1183         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1184         calcsd, and calcxd instructions.
1185         * arc-opc.c (insert_nps_bitop_size): Delete.
1186         (extract_nps_bitop_size): Delete.
1187         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1188         (extract_nps_qcmp_m3): Define.
1189         (extract_nps_qcmp_m2): Define.
1190         (extract_nps_qcmp_m1): Define.
1191         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1192         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1193         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1194         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1195         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1196         NPS_QCMP_M3.
1197
1198 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1199
1200         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1201
1202 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1203
1204         * Makefile.in: Regenerated with automake 1.11.6.
1205         * aclocal.m4: Likewise.
1206
1207 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1208
1209         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1210         instructions.
1211         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1212         (extract_nps_cmem_uimm16): New function.
1213         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1214
1215 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1216
1217         * arc-dis.c (arc_insn_length): New function.
1218         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1219         (find_format): Change insnLen parameter to unsigned.
1220
1221 2016-04-13  Nick Clifton  <nickc@redhat.com>
1222
1223         PR target/19937
1224         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1225         the LD.B and LD.BU instructions.
1226
1227 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1228
1229         * arc-dis.c (find_format): Check for extension flags.
1230         (print_flags): New function.
1231         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1232         .extAuxRegister.
1233         * arc-ext.c (arcExtMap_coreRegName): Use
1234         LAST_EXTENSION_CORE_REGISTER.
1235         (arcExtMap_coreReadWrite): Likewise.
1236         (dump_ARC_extmap): Update printing.
1237         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1238         (arc_aux_regs): Add cpu field.
1239         * arc-regs.h: Add cpu field, lower case name aux registers.
1240
1241 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1242
1243         * arc-tbl.h: Add rtsc, sleep with no arguments.
1244
1245 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1246
1247         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1248         Initialize.
1249         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1250         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1251         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1252         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1253         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1254         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1255         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1256         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1257         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1258         (arc_opcode arc_opcodes): Null terminate the array.
1259         (arc_num_opcodes): Remove.
1260         * arc-ext.h (INSERT_XOP): Define.
1261         (extInstruction_t): Likewise.
1262         (arcExtMap_instName): Delete.
1263         (arcExtMap_insn): New function.
1264         (arcExtMap_genOpcode): Likewise.
1265         * arc-ext.c (ExtInstruction): Remove.
1266         (create_map): Zero initialize instruction fields.
1267         (arcExtMap_instName): Remove.
1268         (arcExtMap_insn): New function.
1269         (dump_ARC_extmap): More info while debuging.
1270         (arcExtMap_genOpcode): New function.
1271         * arc-dis.c (find_format): New function.
1272         (print_insn_arc): Use find_format.
1273         (arc_get_disassembler): Enable dump_ARC_extmap only when
1274         debugging.
1275
1276 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1277
1278         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1279         instruction bits out.
1280
1281 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1282
1283         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1284         * arc-opc.c (arc_flag_operands): Add new flags.
1285         (arc_flag_classes): Add new classes.
1286
1287 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1288
1289         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1290
1291 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1292
1293         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1294         encode1, rflt, crc16, and crc32 instructions.
1295         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1296         (arc_flag_classes): Add C_NPS_R.
1297         (insert_nps_bitop_size_2b): New function.
1298         (extract_nps_bitop_size_2b): Likewise.
1299         (insert_nps_bitop_uimm8): Likewise.
1300         (extract_nps_bitop_uimm8): Likewise.
1301         (arc_operands): Add new operand entries.
1302
1303 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1304
1305         * arc-regs.h: Add a new subclass field.  Add double assist
1306         accumulator register values.
1307         * arc-tbl.h: Use DPA subclass to mark the double assist
1308         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1309         * arc-opc.c (RSP): Define instead of SP.
1310         (arc_aux_regs): Add the subclass field.
1311
1312 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1313
1314         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1315
1316 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1317
1318         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1319         NPS_R_SRC1.
1320
1321 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1322
1323         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1324         issues.  No functional changes.
1325
1326 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1327
1328         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1329         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1330         (RTT): Remove duplicate.
1331         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1332         (PCT_CONFIG*): Remove.
1333         (D1L, D1H, D2H, D2L): Define.
1334
1335 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1336
1337         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1338
1339 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1340
1341         * arc-tbl.h (invld07): Remove.
1342         * arc-ext-tbl.h: New file.
1343         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1344         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1345
1346 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1347
1348         Fix -Wstack-usage warnings.
1349         * aarch64-dis.c (print_operands): Substitute size.
1350         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1351
1352 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1353
1354         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1355         to get a proper diagnostic when an invalid ASR register is used.
1356
1357 2016-03-22  Nick Clifton  <nickc@redhat.com>
1358
1359         * configure: Regenerate.
1360
1361 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1362
1363         * arc-nps400-tbl.h: New file.
1364         * arc-opc.c: Add top level comment.
1365         (insert_nps_3bit_dst): New function.
1366         (extract_nps_3bit_dst): New function.
1367         (insert_nps_3bit_src2): New function.
1368         (extract_nps_3bit_src2): New function.
1369         (insert_nps_bitop_size): New function.
1370         (extract_nps_bitop_size): New function.
1371         (arc_flag_operands): Add nps400 entries.
1372         (arc_flag_classes): Add nps400 entries.
1373         (arc_operands): Add nps400 entries.
1374         (arc_opcodes): Add nps400 include.
1375
1376 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1377
1378         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1379         the new class enum values.
1380
1381 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1382
1383         * arc-dis.c (print_insn_arc): Handle nps400.
1384
1385 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1386
1387         * arc-opc.c (BASE): Delete.
1388
1389 2016-03-18  Nick Clifton  <nickc@redhat.com>
1390
1391         PR target/19721
1392         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1393         of MOV insn that aliases an ORR insn.
1394
1395 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1396
1397         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1398
1399 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1400
1401         * mcore-opc.h: Add const qualifiers.
1402         * microblaze-opc.h (struct op_code_struct): Likewise.
1403         * sh-opc.h: Likewise.
1404         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1405         (tic4x_print_op): Likewise.
1406
1407 2016-03-02  Alan Modra  <amodra@gmail.com>
1408
1409         * or1k-desc.h: Regenerate.
1410         * fr30-ibld.c: Regenerate.
1411         * rl78-decode.c: Regenerate.
1412
1413 2016-03-01  Nick Clifton  <nickc@redhat.com>
1414
1415         PR target/19747
1416         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1417
1418 2016-02-24  Renlin Li  <renlin.li@arm.com>
1419
1420         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1421         (print_insn_coprocessor): Support fp16 instructions.
1422
1423 2016-02-24  Renlin Li  <renlin.li@arm.com>
1424
1425         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1426         vminnm, vrint(mpna).
1427
1428 2016-02-24  Renlin Li  <renlin.li@arm.com>
1429
1430         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1431         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1432
1433 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1434
1435         * i386-dis.c (print_insn): Parenthesize expression to prevent
1436         truncated addresses.
1437         (OP_J): Likewise.
1438
1439 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1440             Janek van Oirschot  <jvanoirs@synopsys.com>
1441
1442         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1443         variable.
1444
1445 2016-02-04  Nick Clifton  <nickc@redhat.com>
1446
1447         PR target/19561
1448         * msp430-dis.c (print_insn_msp430): Add a special case for
1449         decoding an RRC instruction with the ZC bit set in the extension
1450         word.
1451
1452 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1453
1454         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1455         * epiphany-ibld.c: Regenerate.
1456         * fr30-ibld.c: Regenerate.
1457         * frv-ibld.c: Regenerate.
1458         * ip2k-ibld.c: Regenerate.
1459         * iq2000-ibld.c: Regenerate.
1460         * lm32-ibld.c: Regenerate.
1461         * m32c-ibld.c: Regenerate.
1462         * m32r-ibld.c: Regenerate.
1463         * mep-ibld.c: Regenerate.
1464         * mt-ibld.c: Regenerate.
1465         * or1k-ibld.c: Regenerate.
1466         * xc16x-ibld.c: Regenerate.
1467         * xstormy16-ibld.c: Regenerate.
1468
1469 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1470
1471         * epiphany-dis.c: Regenerated from latest cpu files.
1472
1473 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1474
1475         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1476         test bit.
1477
1478 2016-01-25  Renlin Li  <renlin.li@arm.com>
1479
1480         * arm-dis.c (mapping_symbol_for_insn): New function.
1481         (find_ifthen_state): Call mapping_symbol_for_insn().
1482
1483 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1484
1485         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1486         of MSR UAO immediate operand.
1487
1488 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1489
1490         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1491         instruction support.
1492
1493 2016-01-17  Alan Modra  <amodra@gmail.com>
1494
1495         * configure: Regenerate.
1496
1497 2016-01-14  Nick Clifton  <nickc@redhat.com>
1498
1499         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1500         instructions that can support stack pointer operations.
1501         * rl78-decode.c: Regenerate.
1502         * rl78-dis.c: Fix display of stack pointer in MOVW based
1503         instructions.
1504
1505 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1506
1507         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1508         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1509         erxtatus_el1 and erxaddr_el1.
1510
1511 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1512
1513         * arm-dis.c (arm_opcodes): Add "esb".
1514         (thumb_opcodes): Likewise.
1515
1516 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1517
1518         * ppc-opc.c <xscmpnedp>: Delete.
1519         <xvcmpnedp>: Likewise.
1520         <xvcmpnedp.>: Likewise.
1521         <xvcmpnesp>: Likewise.
1522         <xvcmpnesp.>: Likewise.
1523
1524 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1525
1526         PR gas/13050
1527         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1528         addition to ISA_A.
1529
1530 2016-01-01  Alan Modra  <amodra@gmail.com>
1531
1532         Update year range in copyright notice of all files.
1533
1534 For older changes see ChangeLog-2015
1535 \f
1536 Copyright (C) 2016 Free Software Foundation, Inc.
1537
1538 Copying and distribution of this file, with or without modification,
1539 are permitted in any medium without royalty provided the copyright
1540 notice and this notice are preserved.
1541
1542 Local Variables:
1543 mode: change-log
1544 left-margin: 8
1545 fill-column: 74
1546 version-control: never
1547 End: