opcodes/ChangeLog

   1 2018-11-13  Francois H. Theron <francois.theron@netronome.com>
   2
   3         * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
   4
   5 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
   6
   7         * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
   8         IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
   9         IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
  10         CIGDVAC and GZVA.
  11         (aarch64_sys_ins_reg_supported_p): New check for above.
  12
  13 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  14
  15         * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
  16         TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
  17         RGSR_EL1 and GCR_EL1.
  18         (aarch64_sys_reg_supported_p): New check for above.
  19         (aarch64_pstatefields): New entry for TCO.
  20         (aarch64_pstatefield_supported_p): New check for above.
  21
  22 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  23
  24         * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
  25         * aarch64-asm.h (ins_addr_simple_2): Declare the above.
  26         * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
  27         * aarch64-dis.h (ext_addr_simple_2): Declare the above.
  28         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
  29         AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
  30         (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
  31         * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
  32         (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
  33         * aarch64-asm-2.c: Regenerated.
  34         * aarch64-dis-2.c: Regenerated.
  35         * aarch64-opc-2.c: Regenerated.
  36
  37 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  38
  39         * aarch64-tbl.h (QL_LDG): New.
  40         (aarch64_opcode_table): Add ldg.
  41         * aarch64-asm-2.c: Regenerated.
  42         * aarch64-dis-2.c: Regenerated.
  43         * aarch64-opc-2.c: Regenerated.
  44
  45 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  46
  47         * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
  48         for AARCH64_OPND_QLF_imm_tag.
  49         (operand_general_constraint_met_p): Add case for
  50         AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
  51         (aarch64_print_operand): Likewise.
  52         * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
  53         (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
  54         for both offset and pre/post indexed versions.
  55         (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
  56         * aarch64-asm-2.c: Regenerated.
  57         * aarch64-dis-2.c: Regenerated.
  58         * aarch64-opc-2.c: Regenerated.
  59
  60 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  61
  62         * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
  63         * aarch64-asm-2.c: Regenerated.
  64         * aarch64-dis-2.c: Regenerated.
  65         * aarch64-opc-2.c: Regenerated.
  66
  67 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  68
  69         * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
  70         (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
  71         * aarch64-opc.c (fields): Add entry for imm4_3.
  72         (operand_general_constraint_met_p): Add cases for
  73         AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
  74         (aarch64_print_operand): Likewise.
  75         * aarch64-tbl.h (QL_ADDG): New.
  76         (aarch64_opcode_table): Add addg, subg, irg and gmi.
  77         (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
  78         * aarch64-asm.c (aarch64_ins_imm): Add case for
  79         operand_need_shift_by_four.
  80         * aarch64-asm-2.c: Regenerated.
  81         * aarch64-dis-2.c: Regenerated.
  82         * aarch64-opc-2.c: Regenerated.
  83
  84 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  85
  86         * aarch64-tbl.h (aarch64_feature_memtag): New.
  87         (MEMTAG, MEMTAG_INSN): New.
  88
  89 2018-11-06  Sudakshina Das  <sudi.das@arm.com>
  90
  91         * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
  92         with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
  93
  94 2018-11-06  Alan Modra  <amodra@gmail.com>
  95
  96         * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
  97         (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
  98         (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
  99         (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
 100         Don't return zero on error, insert mask bits instead.
 101         (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
 102         (insert_sh6, extract_sh6): Delete dead code.
 103         (insert_sprbat, insert_sprg): Use unsigned comparisions.
 104         (powerpc_operands <OIMM>): Set shift count rather than using
 105         PPC_OPSHIFT_INV.
 106         <SE_SDH, SE_SDW>: Likewise.  Don't use insert/extract functions.
 107
 108 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
 111         vpbroadcast{d,q} with GPR operand.
 112
 113 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
 116         * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
 117         cases up one level in the hierarchy.
 118
 119 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 120
 121         * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
 122         MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
 123         (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
 124         into MOD_VEX_0F93_P_3_LEN_0.
 125         (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
 126         operand cases up one level in the hierarchy.
 127
 128 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 129
 130         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
 131         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
 132         EVEX_W_0F3A22_P_2): Delete.
 133         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
 134         entries up one level in the hierarchy.
 135         (OP_E_memory): Handle dq_mode when determining Disp8 shift
 136         value.
 137         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
 138         entries up one level in the hierarchy.
 139         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
 140         VexWIG for AVX flavors.
 141         * i386-tbl.h: Re-generate.
 142
 143 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
 146         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
 147         vcvtusi2ss, kmovd): Drop VexW=1.
 148         * i386-tbl.h: Re-generate.
 149
 150 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
 153         EVex512, EVexLIG, EVexDYN): New.
 154         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
 155         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
 156         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
 157         of EVex=4 (aka EVexLIG).
 158         * i386-tbl.h: Re-generate.
 159
 160 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 161
 162         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
 163         (vpmaxub): Re-order attributes on AVX512BW flavor.
 164         * i386-tbl.h: Re-generate.
 165
 166 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
 169         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
 170         Vex=1 on AVX / AVX2 flavors.
 171         (vpmaxub): Re-order attributes on AVX512BW flavor.
 172         * i386-tbl.h: Re-generate.
 173
 174 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-opc.tbl (VexW0, VexW1): New.
 177         (vphadd*, vphsub*): Use VexW0 on XOP variants.
 178         * i386-tbl.h: Re-generate.
 179
 180 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
 181
 182         * s12z-dis.c (decode_possible_symbol): Add fallback case.
 183         (rel_15_7): Likewise.
 184
 185 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
 186
 187         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
 188         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
 189         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
 190
 191 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
 192
 193         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
 194         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
 195
 196 2018-10-10  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
 199         Size64. Add Size.
 200         * i386-opc.h (Size16, Size32, Size64): Delete.
 201         (Size): New.
 202         (SIZE16, SIZE32, SIZE64): Define.
 203         (struct i386_opcode_modifier): Drop size16, size32, and size64.
 204         Add size.
 205         * i386-opc.tbl (Size16, Size32, Size64): Define.
 206         * i386-tbl.h: Re-generate.
 207
 208 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 209
 210         * aarch64-opc.c (operand_general_constraint_met_p): Add
 211         SSBS in the check for one-bit immediate.
 212         (aarch64_sys_regs): New entry for SSBS.
 213         (aarch64_sys_reg_supported_p): New check for above.
 214         (aarch64_pstatefields): New entry for SSBS.
 215         (aarch64_pstatefield_supported_p): New check for above.
 216
 217 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 218
 219         * aarch64-opc.c (aarch64_sys_regs): New entries for
 220         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
 221         (aarch64_sys_reg_supported_p): New checks for above.
 222
 223 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 224
 225         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
 226         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 227         with the hint immediate.
 228         * aarch64-opc.c (aarch64_hint_options): New entries for
 229         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 230         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 231         while checking for HINT_OPD_F_NOPRINT flag.
 232         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 233         extract value.
 234         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 235         (aarch64_opcode_table): Add entry for BTI.
 236         (AARCH64_OPERANDS): Add new description for BTI targets.
 237         * aarch64-asm-2.c: Regenerate.
 238         * aarch64-dis-2.c: Regenerate.
 239         * aarch64-opc-2.c: Regenerate.
 240
 241 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 242
 243         * aarch64-opc.c (aarch64_sys_regs): New entries for
 244         rndr and rndrrs.
 245         (aarch64_sys_reg_supported_p): New check for above.
 246
 247 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 248
 249         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 250         (aarch64_sys_ins_reg_supported_p): New check for above.
 251
 252 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 253
 254         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 255         AARCH64_OPND_SYSREG_SR.
 256         * aarch64-opc.c (aarch64_print_operand): Likewise.
 257         (aarch64_sys_regs_sr): Define table.
 258         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 259         AARCH64_FEATURE_PREDRES.
 260         * aarch64-tbl.h (aarch64_feature_predres): New.
 261         (PREDRES, PREDRES_INSN): New.
 262         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 263         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 264         * aarch64-asm-2.c: Regenerate.
 265         * aarch64-dis-2.c: Regenerate.
 266         * aarch64-opc-2.c: Regenerate.
 267
 268 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 269
 270         * aarch64-tbl.h (aarch64_feature_sb): New.
 271         (SB, SB_INSN): New.
 272         (aarch64_opcode_table): Add entry for sb.
 273         * aarch64-asm-2.c: Regenerate.
 274         * aarch64-dis-2.c: Regenerate.
 275         * aarch64-opc-2.c: Regenerate.
 276
 277 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 278
 279         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 280         (aarch64_feature_frintts): New.
 281         (FLAGMANIP, FRINTTS): New.
 282         (aarch64_opcode_table): Add entries for xaflag, axflag
 283         and frint[32,64][x,z] instructions.
 284         * aarch64-asm-2.c: Regenerate.
 285         * aarch64-dis-2.c: Regenerate.
 286         * aarch64-opc-2.c: Regenerate.
 287
 288 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 289
 290         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 291         (ARMV8_5, V8_5_INSN): New.
 292
 293 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 294
 295         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 296
 297 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 298
 299         * i386-dis.c (rm_table): Add enclv.
 300         * i386-opc.tbl: Add enclv.
 301         * i386-tbl.h: Regenerated.
 302
 303 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 304
 305         * arm-dis.c (arm_opcodes): Add sb.
 306         (thumb32_opcodes): Likewise.
 307
 308 2018-10-05  Richard Henderson  <rth@twiddle.net>
 309             Stafford Horne  <shorne@gmail.com>
 310
 311         * or1k-desc.c: Regenerate.
 312         * or1k-desc.h: Regenerate.
 313         * or1k-opc.c: Regenerate.
 314         * or1k-opc.h: Regenerate.
 315         * or1k-opinst.c: Regenerate.
 316
 317 2018-10-05  Richard Henderson  <rth@twiddle.net>
 318
 319         * or1k-asm.c: Regenerated.
 320         * or1k-desc.c: Regenerated.
 321         * or1k-desc.h: Regenerated.
 322         * or1k-dis.c: Regenerated.
 323         * or1k-ibld.c: Regenerated.
 324         * or1k-opc.c: Regenerated.
 325         * or1k-opc.h: Regenerated.
 326         * or1k-opinst.c: Regenerated.
 327
 328 2018-10-05  Richard Henderson  <rth@twiddle.net>
 329
 330         * or1k-asm.c: Regenerate.
 331
 332 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 333
 334         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 335         * aarch64-dis.c (print_operands): Refactor to take notes.
 336         (print_verifier_notes): New.
 337         (print_aarch64_insn): Apply constraint verifier.
 338         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 339         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 340
 341 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 342
 343         * aarch64-opc.c (init_insn_block): New.
 344         (verify_constraints, aarch64_is_destructive_by_operands): New.
 345         * aarch64-opc.h (verify_constraints): New.
 346
 347 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 348
 349         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 350         * aarch64-opc.c (verify_ldpsw): Update arguments.
 351
 352 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 353
 354         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 355         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 356
 357 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 358
 359         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 360         * aarch64-dis.c (insn_sequence): New.
 361
 362 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 363
 364         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 365         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 366         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 367         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 368         constraints.
 369         (_SVE_INSNC): New.
 370         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 371         constraints.
 372         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 373         F_SCAN flags.
 374         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 375         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 376         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 377         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 378         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 379         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 380         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 381
 382 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 383
 384         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 385
 386 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 387
 388         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 389         are used when extracting signed fields and converting them to
 390         potentially 64-bit types.
 391
 392 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 393
 394         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 395         * Makefile.in: Re-generate.
 396         * aclocal.m4: Re-generate.
 397         * configure: Re-generate.
 398         * configure.ac: Remove check for -Wno-missing-field-initializers.
 399         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 400         (csky_v2_opcodes): Likewise.
 401
 402 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 403
 404         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 405
 406 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 407
 408         * nds32-asm.c (operand_fields): Remove the unused fields.
 409         (nds32_opcodes): Remove the unused instructions.
 410         * nds32-dis.c (nds32_ex9_info): Removed.
 411         (nds32_parse_opcode): Updated.
 412         (print_insn_nds32): Likewise.
 413         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 414         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 415         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 416         build_opcode_hash_table): New functions.
 417         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 418         nds32_opcode_table): New.
 419         (hw_ktabs): Declare it to a pointer rather than an array.
 420         (build_hash_table): Removed.
 421         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 422         SYN_ROPT and upadte HW_GPR and HW_INT.
 423         * nds32-dis.c (keywords): Remove const.
 424         (match_field): New function.
 425         (nds32_parse_opcode): Updated.
 426         * disassemble.c (disassemble_init_for_target):
 427         Add disassemble_init_nds32.
 428         * nds32-dis.c (eum map_type): New.
 429         (nds32_private_data): Likewise.
 430         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 431         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 432         (print_insn_nds32): Updated.
 433         * nds32-asm.c (parse_aext_reg): Add new parameter.
 434         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 435         are allowed to use.
 436         All callers changed.
 437         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 438         (operand_fields): Add new fields.
 439         (nds32_opcodes): Add new instructions.
 440         (keyword_aridxi_mx): New keyword.
 441         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 442         and NASM_ATTR_ZOL.
 443         (ALU2_1, ALU2_2, ALU2_3): New macros.
 444         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 445
 446 2018-09-17  Kito Cheng  <kito@andestech.com>
 447
 448         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 449
 450 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         PR gas/23670
 453         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 454         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 455         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 456         (EVEX_LEN_0F7E_P_1): Likewise.
 457         (EVEX_LEN_0F7E_P_2): Likewise.
 458         (EVEX_LEN_0FD6_P_2): Likewise.
 459         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 460         (EVEX_LEN_TABLE): Likewise.
 461         (EVEX_LEN_0F6E_P_2): New enum.
 462         (EVEX_LEN_0F7E_P_1): Likewise.
 463         (EVEX_LEN_0F7E_P_2): Likewise.
 464         (EVEX_LEN_0FD6_P_2): Likewise.
 465         (evex_len_table): New.
 466         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 467         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 468         * i386-tbl.h: Regenerated.
 469
 470 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 471
 472         PR gas/23665
 473         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 474         VEX_LEN_0F7E_P_2 entries.
 475         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 476         * i386-tbl.h: Regenerated.
 477
 478 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 479
 480         * i386-dis.c (VZERO_Fixup): Removed.
 481         (VZERO): Likewise.
 482         (VEX_LEN_0F10_P_1): Likewise.
 483         (VEX_LEN_0F10_P_3): Likewise.
 484         (VEX_LEN_0F11_P_1): Likewise.
 485         (VEX_LEN_0F11_P_3): Likewise.
 486         (VEX_LEN_0F2E_P_0): Likewise.
 487         (VEX_LEN_0F2E_P_2): Likewise.
 488         (VEX_LEN_0F2F_P_0): Likewise.
 489         (VEX_LEN_0F2F_P_2): Likewise.
 490         (VEX_LEN_0F51_P_1): Likewise.
 491         (VEX_LEN_0F51_P_3): Likewise.
 492         (VEX_LEN_0F52_P_1): Likewise.
 493         (VEX_LEN_0F53_P_1): Likewise.
 494         (VEX_LEN_0F58_P_1): Likewise.
 495         (VEX_LEN_0F58_P_3): Likewise.
 496         (VEX_LEN_0F59_P_1): Likewise.
 497         (VEX_LEN_0F59_P_3): Likewise.
 498         (VEX_LEN_0F5A_P_1): Likewise.
 499         (VEX_LEN_0F5A_P_3): Likewise.
 500         (VEX_LEN_0F5C_P_1): Likewise.
 501         (VEX_LEN_0F5C_P_3): Likewise.
 502         (VEX_LEN_0F5D_P_1): Likewise.
 503         (VEX_LEN_0F5D_P_3): Likewise.
 504         (VEX_LEN_0F5E_P_1): Likewise.
 505         (VEX_LEN_0F5E_P_3): Likewise.
 506         (VEX_LEN_0F5F_P_1): Likewise.
 507         (VEX_LEN_0F5F_P_3): Likewise.
 508         (VEX_LEN_0FC2_P_1): Likewise.
 509         (VEX_LEN_0FC2_P_3): Likewise.
 510         (VEX_LEN_0F3A0A_P_2): Likewise.
 511         (VEX_LEN_0F3A0B_P_2): Likewise.
 512         (VEX_W_0F10_P_0): Likewise.
 513         (VEX_W_0F10_P_1): Likewise.
 514         (VEX_W_0F10_P_2): Likewise.
 515         (VEX_W_0F10_P_3): Likewise.
 516         (VEX_W_0F11_P_0): Likewise.
 517         (VEX_W_0F11_P_1): Likewise.
 518         (VEX_W_0F11_P_2): Likewise.
 519         (VEX_W_0F11_P_3): Likewise.
 520         (VEX_W_0F12_P_0_M_0): Likewise.
 521         (VEX_W_0F12_P_0_M_1): Likewise.
 522         (VEX_W_0F12_P_1): Likewise.
 523         (VEX_W_0F12_P_2): Likewise.
 524         (VEX_W_0F12_P_3): Likewise.
 525         (VEX_W_0F13_M_0): Likewise.
 526         (VEX_W_0F14): Likewise.
 527         (VEX_W_0F15): Likewise.
 528         (VEX_W_0F16_P_0_M_0): Likewise.
 529         (VEX_W_0F16_P_0_M_1): Likewise.
 530         (VEX_W_0F16_P_1): Likewise.
 531         (VEX_W_0F16_P_2): Likewise.
 532         (VEX_W_0F17_M_0): Likewise.
 533         (VEX_W_0F28): Likewise.
 534         (VEX_W_0F29): Likewise.
 535         (VEX_W_0F2B_M_0): Likewise.
 536         (VEX_W_0F2E_P_0): Likewise.
 537         (VEX_W_0F2E_P_2): Likewise.
 538         (VEX_W_0F2F_P_0): Likewise.
 539         (VEX_W_0F2F_P_2): Likewise.
 540         (VEX_W_0F50_M_0): Likewise.
 541         (VEX_W_0F51_P_0): Likewise.
 542         (VEX_W_0F51_P_1): Likewise.
 543         (VEX_W_0F51_P_2): Likewise.
 544         (VEX_W_0F51_P_3): Likewise.
 545         (VEX_W_0F52_P_0): Likewise.
 546         (VEX_W_0F52_P_1): Likewise.
 547         (VEX_W_0F53_P_0): Likewise.
 548         (VEX_W_0F53_P_1): Likewise.
 549         (VEX_W_0F58_P_0): Likewise.
 550         (VEX_W_0F58_P_1): Likewise.
 551         (VEX_W_0F58_P_2): Likewise.
 552         (VEX_W_0F58_P_3): Likewise.
 553         (VEX_W_0F59_P_0): Likewise.
 554         (VEX_W_0F59_P_1): Likewise.
 555         (VEX_W_0F59_P_2): Likewise.
 556         (VEX_W_0F59_P_3): Likewise.
 557         (VEX_W_0F5A_P_0): Likewise.
 558         (VEX_W_0F5A_P_1): Likewise.
 559         (VEX_W_0F5A_P_3): Likewise.
 560         (VEX_W_0F5B_P_0): Likewise.
 561         (VEX_W_0F5B_P_1): Likewise.
 562         (VEX_W_0F5B_P_2): Likewise.
 563         (VEX_W_0F5C_P_0): Likewise.
 564         (VEX_W_0F5C_P_1): Likewise.
 565         (VEX_W_0F5C_P_2): Likewise.
 566         (VEX_W_0F5C_P_3): Likewise.
 567         (VEX_W_0F5D_P_0): Likewise.
 568         (VEX_W_0F5D_P_1): Likewise.
 569         (VEX_W_0F5D_P_2): Likewise.
 570         (VEX_W_0F5D_P_3): Likewise.
 571         (VEX_W_0F5E_P_0): Likewise.
 572         (VEX_W_0F5E_P_1): Likewise.
 573         (VEX_W_0F5E_P_2): Likewise.
 574         (VEX_W_0F5E_P_3): Likewise.
 575         (VEX_W_0F5F_P_0): Likewise.
 576         (VEX_W_0F5F_P_1): Likewise.
 577         (VEX_W_0F5F_P_2): Likewise.
 578         (VEX_W_0F5F_P_3): Likewise.
 579         (VEX_W_0F60_P_2): Likewise.
 580         (VEX_W_0F61_P_2): Likewise.
 581         (VEX_W_0F62_P_2): Likewise.
 582         (VEX_W_0F63_P_2): Likewise.
 583         (VEX_W_0F64_P_2): Likewise.
 584         (VEX_W_0F65_P_2): Likewise.
 585         (VEX_W_0F66_P_2): Likewise.
 586         (VEX_W_0F67_P_2): Likewise.
 587         (VEX_W_0F68_P_2): Likewise.
 588         (VEX_W_0F69_P_2): Likewise.
 589         (VEX_W_0F6A_P_2): Likewise.
 590         (VEX_W_0F6B_P_2): Likewise.
 591         (VEX_W_0F6C_P_2): Likewise.
 592         (VEX_W_0F6D_P_2): Likewise.
 593         (VEX_W_0F6F_P_1): Likewise.
 594         (VEX_W_0F6F_P_2): Likewise.
 595         (VEX_W_0F70_P_1): Likewise.
 596         (VEX_W_0F70_P_2): Likewise.
 597         (VEX_W_0F70_P_3): Likewise.
 598         (VEX_W_0F71_R_2_P_2): Likewise.
 599         (VEX_W_0F71_R_4_P_2): Likewise.
 600         (VEX_W_0F71_R_6_P_2): Likewise.
 601         (VEX_W_0F72_R_2_P_2): Likewise.
 602         (VEX_W_0F72_R_4_P_2): Likewise.
 603         (VEX_W_0F72_R_6_P_2): Likewise.
 604         (VEX_W_0F73_R_2_P_2): Likewise.
 605         (VEX_W_0F73_R_3_P_2): Likewise.
 606         (VEX_W_0F73_R_6_P_2): Likewise.
 607         (VEX_W_0F73_R_7_P_2): Likewise.
 608         (VEX_W_0F74_P_2): Likewise.
 609         (VEX_W_0F75_P_2): Likewise.
 610         (VEX_W_0F76_P_2): Likewise.
 611         (VEX_W_0F77_P_0): Likewise.
 612         (VEX_W_0F7C_P_2): Likewise.
 613         (VEX_W_0F7C_P_3): Likewise.
 614         (VEX_W_0F7D_P_2): Likewise.
 615         (VEX_W_0F7D_P_3): Likewise.
 616         (VEX_W_0F7E_P_1): Likewise.
 617         (VEX_W_0F7F_P_1): Likewise.
 618         (VEX_W_0F7F_P_2): Likewise.
 619         (VEX_W_0FAE_R_2_M_0): Likewise.
 620         (VEX_W_0FAE_R_3_M_0): Likewise.
 621         (VEX_W_0FC2_P_0): Likewise.
 622         (VEX_W_0FC2_P_1): Likewise.
 623         (VEX_W_0FC2_P_2): Likewise.
 624         (VEX_W_0FC2_P_3): Likewise.
 625         (VEX_W_0FD0_P_2): Likewise.
 626         (VEX_W_0FD0_P_3): Likewise.
 627         (VEX_W_0FD1_P_2): Likewise.
 628         (VEX_W_0FD2_P_2): Likewise.
 629         (VEX_W_0FD3_P_2): Likewise.
 630         (VEX_W_0FD4_P_2): Likewise.
 631         (VEX_W_0FD5_P_2): Likewise.
 632         (VEX_W_0FD6_P_2): Likewise.
 633         (VEX_W_0FD7_P_2_M_1): Likewise.
 634         (VEX_W_0FD8_P_2): Likewise.
 635         (VEX_W_0FD9_P_2): Likewise.
 636         (VEX_W_0FDA_P_2): Likewise.
 637         (VEX_W_0FDB_P_2): Likewise.
 638         (VEX_W_0FDC_P_2): Likewise.
 639         (VEX_W_0FDD_P_2): Likewise.
 640         (VEX_W_0FDE_P_2): Likewise.
 641         (VEX_W_0FDF_P_2): Likewise.
 642         (VEX_W_0FE0_P_2): Likewise.
 643         (VEX_W_0FE1_P_2): Likewise.
 644         (VEX_W_0FE2_P_2): Likewise.
 645         (VEX_W_0FE3_P_2): Likewise.
 646         (VEX_W_0FE4_P_2): Likewise.
 647         (VEX_W_0FE5_P_2): Likewise.
 648         (VEX_W_0FE6_P_1): Likewise.
 649         (VEX_W_0FE6_P_2): Likewise.
 650         (VEX_W_0FE6_P_3): Likewise.
 651         (VEX_W_0FE7_P_2_M_0): Likewise.
 652         (VEX_W_0FE8_P_2): Likewise.
 653         (VEX_W_0FE9_P_2): Likewise.
 654         (VEX_W_0FEA_P_2): Likewise.
 655         (VEX_W_0FEB_P_2): Likewise.
 656         (VEX_W_0FEC_P_2): Likewise.
 657         (VEX_W_0FED_P_2): Likewise.
 658         (VEX_W_0FEE_P_2): Likewise.
 659         (VEX_W_0FEF_P_2): Likewise.
 660         (VEX_W_0FF0_P_3_M_0): Likewise.
 661         (VEX_W_0FF1_P_2): Likewise.
 662         (VEX_W_0FF2_P_2): Likewise.
 663         (VEX_W_0FF3_P_2): Likewise.
 664         (VEX_W_0FF4_P_2): Likewise.
 665         (VEX_W_0FF5_P_2): Likewise.
 666         (VEX_W_0FF6_P_2): Likewise.
 667         (VEX_W_0FF7_P_2): Likewise.
 668         (VEX_W_0FF8_P_2): Likewise.
 669         (VEX_W_0FF9_P_2): Likewise.
 670         (VEX_W_0FFA_P_2): Likewise.
 671         (VEX_W_0FFB_P_2): Likewise.
 672         (VEX_W_0FFC_P_2): Likewise.
 673         (VEX_W_0FFD_P_2): Likewise.
 674         (VEX_W_0FFE_P_2): Likewise.
 675         (VEX_W_0F3800_P_2): Likewise.
 676         (VEX_W_0F3801_P_2): Likewise.
 677         (VEX_W_0F3802_P_2): Likewise.
 678         (VEX_W_0F3803_P_2): Likewise.
 679         (VEX_W_0F3804_P_2): Likewise.
 680         (VEX_W_0F3805_P_2): Likewise.
 681         (VEX_W_0F3806_P_2): Likewise.
 682         (VEX_W_0F3807_P_2): Likewise.
 683         (VEX_W_0F3808_P_2): Likewise.
 684         (VEX_W_0F3809_P_2): Likewise.
 685         (VEX_W_0F380A_P_2): Likewise.
 686         (VEX_W_0F380B_P_2): Likewise.
 687         (VEX_W_0F3817_P_2): Likewise.
 688         (VEX_W_0F381C_P_2): Likewise.
 689         (VEX_W_0F381D_P_2): Likewise.
 690         (VEX_W_0F381E_P_2): Likewise.
 691         (VEX_W_0F3820_P_2): Likewise.
 692         (VEX_W_0F3821_P_2): Likewise.
 693         (VEX_W_0F3822_P_2): Likewise.
 694         (VEX_W_0F3823_P_2): Likewise.
 695         (VEX_W_0F3824_P_2): Likewise.
 696         (VEX_W_0F3825_P_2): Likewise.
 697         (VEX_W_0F3828_P_2): Likewise.
 698         (VEX_W_0F3829_P_2): Likewise.
 699         (VEX_W_0F382A_P_2_M_0): Likewise.
 700         (VEX_W_0F382B_P_2): Likewise.
 701         (VEX_W_0F3830_P_2): Likewise.
 702         (VEX_W_0F3831_P_2): Likewise.
 703         (VEX_W_0F3832_P_2): Likewise.
 704         (VEX_W_0F3833_P_2): Likewise.
 705         (VEX_W_0F3834_P_2): Likewise.
 706         (VEX_W_0F3835_P_2): Likewise.
 707         (VEX_W_0F3837_P_2): Likewise.
 708         (VEX_W_0F3838_P_2): Likewise.
 709         (VEX_W_0F3839_P_2): Likewise.
 710         (VEX_W_0F383A_P_2): Likewise.
 711         (VEX_W_0F383B_P_2): Likewise.
 712         (VEX_W_0F383C_P_2): Likewise.
 713         (VEX_W_0F383D_P_2): Likewise.
 714         (VEX_W_0F383E_P_2): Likewise.
 715         (VEX_W_0F383F_P_2): Likewise.
 716         (VEX_W_0F3840_P_2): Likewise.
 717         (VEX_W_0F3841_P_2): Likewise.
 718         (VEX_W_0F38DB_P_2): Likewise.
 719         (VEX_W_0F3A08_P_2): Likewise.
 720         (VEX_W_0F3A09_P_2): Likewise.
 721         (VEX_W_0F3A0A_P_2): Likewise.
 722         (VEX_W_0F3A0B_P_2): Likewise.
 723         (VEX_W_0F3A0C_P_2): Likewise.
 724         (VEX_W_0F3A0D_P_2): Likewise.
 725         (VEX_W_0F3A0E_P_2): Likewise.
 726         (VEX_W_0F3A0F_P_2): Likewise.
 727         (VEX_W_0F3A21_P_2): Likewise.
 728         (VEX_W_0F3A40_P_2): Likewise.
 729         (VEX_W_0F3A41_P_2): Likewise.
 730         (VEX_W_0F3A42_P_2): Likewise.
 731         (VEX_W_0F3A62_P_2): Likewise.
 732         (VEX_W_0F3A63_P_2): Likewise.
 733         (VEX_W_0F3ADF_P_2): Likewise.
 734         (VEX_LEN_0F77_P_0): New.
 735         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 736         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 737         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 738         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 739         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 740         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 741         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 742         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 743         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 744         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 745         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 746         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 747         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 748         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 749         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 750         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 751         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 752         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 753         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 754         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 755         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 756         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 757         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 758         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 759         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 760         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 761         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 762         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 763         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 764         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 765         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 766         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 767         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 768         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 769         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 770         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 771         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 772         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 773         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 774         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 775         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 776         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 777         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 778         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 779         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 780         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 781         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 782         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 783         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 784         (vex_table): Update VEX 0F28 and 0F29 entries.
 785         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 786         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 787         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 788         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 789         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 790         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 791         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 792         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 793         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 794         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 795         VEX_LEN_0F3A0B_P_2 entries.
 796         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 797         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 798         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 799         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 800         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 801         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 802         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 803         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 804         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 805         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 806         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 807         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 808         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 809         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 810         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 811         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 812         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 813         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 814         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 815         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 816         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 817         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 818         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 819         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 820         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 821         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 822         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 823         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 824         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 825         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 826         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 827         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 828         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 829         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 830         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 831         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 832         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 833         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 834         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 835         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 836         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 837         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 838         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 839         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 840         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 841         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 842         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 843         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 844         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 845         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 846         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 847         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 848         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 849         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 850         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 851         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 852         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 853         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 854         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 855         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 856         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 857         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 858         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 859         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 860         VEX_W_0F3ADF_P_2 entries.
 861         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 862         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 863         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 864
 865 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 866
 867         * i386-opc.tbl (VexWIG): New.
 868         Replace VexW=3 with VexWIG.
 869
 870 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 873         * i386-tbl.h: Regenerated.
 874
 875 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 876
 877         PR gas/23665
 878         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 879         VEX_LEN_0FD6_P_2 entries.
 880         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 881         * i386-tbl.h: Regenerated.
 882
 883 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 884
 885         PR gas/23642
 886         * i386-opc.h (VEXWIG): New.
 887         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 888         * i386-tbl.h: Regenerated.
 889
 890 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 891
 892         PR binutils/23655
 893         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 894         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 895         * i386-dis.c (EXxEVexR64): New.
 896         (evex_rounding_64_mode): Likewise.
 897         (OP_Rounding): Handle evex_rounding_64_mode.
 898
 899 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 900
 901         PR binutils/23655
 902         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 903         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 904         * i386-dis.c (Edqa): New.
 905         (dqa_mode): Likewise.
 906         (intel_operand_size): Handle dqa_mode as m_mode.
 907         (OP_E_register): Handle dqa_mode as dq_mode.
 908         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 909
 910 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 911
 912         * i386-dis.c (OP_E_memory): Reformat.
 913
 914 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 915
 916         * i386-opc.tbl (crc32): Fold byte and word forms.
 917         * i386-tbl.h: Re-generate.
 918
 919 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 920
 921         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 922         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 923         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 924         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 925         * i386-tbl.h: Regenerated.
 926
 927 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 928
 929         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 930         meaningless.
 931         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 932         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 933         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 934         * i386-tbl.h: Re-generate.
 935
 936 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 937
 938         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 939         AVX512_4VNNIW insns.
 940         * i386-tbl.h: Re-generate.
 941
 942 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 943
 944         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 945         meaningless.
 946         * i386-tbl.h: Re-generate.
 947
 948 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 949
 950         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 951         meaningless.
 952         * i386-tbl.h: Re-generate.
 953
 954 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 957         meaningless.
 958         * i386-tbl.h: Re-generate.
 959
 960 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 963         meaningless.
 964         * i386-tbl.h: Re-generate.
 965
 966 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 967
 968         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 969         meaningless.
 970         * i386-tbl.h: Re-generate.
 971
 972 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 973
 974         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 975         * i386-tbl.h: Re-generate.
 976
 977 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 978
 979         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 980         * i386-tbl.h: Re-generate.
 981
 982 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 985         meaningless.
 986         * i386-tbl.h: Re-generate.
 987
 988 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 989
 990         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 991         meaningless.
 992         * i386-tbl.h: Re-generate.
 993
 994 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 997         * i386-tbl.h: Re-generate.
 998
 999 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
1002         * i386-tbl.h: Re-generate.
1003
1004 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1005
1006         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1007         * i386-tbl.h: Re-generate.
1008
1009 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1012         meaningless.
1013         * i386-tbl.h: Re-generate.
1014
1015 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1016
1017         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1018         meaningless.
1019         * i386-tbl.h: Re-generate.
1020
1021 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1022
1023         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1024         meaningless.
1025         * i386-tbl.h: Re-generate.
1026
1027 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1030         * i386-tbl.h: Re-generate.
1031
1032 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1035         * i386-tbl.h: Re-generate.
1036
1037 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1038
1039         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1040         * i386-tbl.h: Re-generate.
1041
1042 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1045         (vpbroadcastw, rdpid): Drop NoRex64.
1046         * i386-tbl.h: Re-generate.
1047
1048 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1049
1050         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1051         store templates, adding D.
1052         * i386-tbl.h: Re-generate.
1053
1054 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1057         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1058         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1059         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1060         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1061         Fold load and store templates where possible, adding D. Drop
1062         IgnoreSize where it was pointlessly present. Drop redundant
1063         *word.
1064         * i386-tbl.h: Re-generate.
1065
1066 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1067
1068         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1069         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1070         (intel_operand_size): Handle v_bndmk_mode.
1071         (OP_E_memory): Likewise. Produce (bad) when also riprel.
1072
1073 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
1074
1075         * disassemble.c (ARCH_s12z): Define if ARCH_all.
1076
1077 2018-08-31  Kito Cheng  <kito@andestech.com>
1078
1079         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1080         compressed floating point instructions.
1081
1082 2018-08-30  Kito Cheng  <kito@andestech.com>
1083
1084         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1085         riscv_opcode.xlen_requirement.
1086         * riscv-opc.c (riscv_opcodes): Update for struct change.
1087
1088 2018-08-29  Martin Aberg  <maberg@gaisler.com>
1089
1090         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1091         psr (PWRPSR) instruction.
1092
1093 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1094
1095         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1096
1097 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1098
1099         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1100
1101 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1102
1103         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1104         loongson3a as an alias of gs464 for compatibility.
1105         * mips-opc.c (mips_opcodes): Change Comments.
1106
1107 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1108
1109         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1110         option.
1111         (print_mips_disassembler_options): Document -M loongson-ext.
1112         * mips-opc.c (LEXT2): New macro.
1113         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1114
1115 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1116
1117          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1118          descriptors.
1119          (parse_mips_ase_option): Handle -M loongson-ext option.
1120          (print_mips_disassembler_options): Document -M loongson-ext.
1121          * mips-opc.c (IL3A): Delete.
1122          * mips-opc.c (LEXT): New macro.
1123          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1124          instructions.
1125
1126 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1127
1128         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1129         descriptors.
1130         (parse_mips_ase_option): Handle -M loongson-cam option.
1131         (print_mips_disassembler_options): Document -M loongson-cam.
1132         * mips-opc.c (LCAM): New macro.
1133         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1134         instructions.
1135
1136 2018-08-21  Alan Modra  <amodra@gmail.com>
1137
1138         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1139         (skip_optional_operands): Count optional operands, and update
1140         ppc_optional_operand_value call.
1141         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1142         (extract_vlensi): Likewise.
1143         (extract_fxm): Return default value for missing optional operand.
1144         (extract_ls, extract_raq, extract_tbr): Likewise.
1145         (insert_sxl, extract_sxl): New functions.
1146         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1147         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1148         flag and extra entry.
1149         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1150         extract_sxl.
1151
1152 2018-08-20  Alan Modra  <amodra@gmail.com>
1153
1154         * sh-opc.h (MASK): Simplify.
1155
1156 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1157
1158         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1159         BM_RESERVED0 or BM_RESERVED1
1160         (bm_rel_decode, bm_n_bytes): Ditto.
1161
1162 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1163
1164         * s12z.h: Delete.
1165
1166 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1167
1168         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1169         address with the addr32 prefix and without base nor index
1170         registers.
1171
1172 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1173
1174         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1175         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1176         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1177         (cpu_flags): Add CpuCMOV and CpuFXSR.
1178         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1179         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1180         * i386-init.h: Regenerated.
1181         * i386-tbl.h: Likewise.
1182
1183 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1184
1185         * arc-regs.h: Update auxiliary registers.
1186
1187 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1188
1189         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1190         (RegIP, RegIZ): Define.
1191         * i386-reg.tbl: Adjust comments.
1192         (rip): Use Qword instead of BaseIndex. Use RegIP.
1193         (eip): Use Dword instead of BaseIndex. Use RegIP.
1194         (riz): Add Qword. Use RegIZ.
1195         (eiz): Add Dword. Use RegIZ.
1196         * i386-tbl.h: Re-generate.
1197
1198 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1199
1200         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1201         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1202         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1203         * i386-tbl.h: Re-generate.
1204
1205 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1206
1207         * i386-gen.c (operand_types): Remove Mem field.
1208         * i386-opc.h (union i386_operand_type): Remove mem field.
1209         * i386-init.h, i386-tbl.h: Re-generate.
1210
1211 2018-08-01  Alan Modra  <amodra@gmail.com>
1212
1213         * po/POTFILES.in: Regenerate.
1214
1215 2018-07-31  Nick Clifton  <nickc@redhat.com>
1216
1217         * po/sv.po: Updated Swedish translation.
1218
1219 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1220
1221         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1222         * i386-init.h, i386-tbl.h: Re-generate.
1223
1224 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1225
1226         * i386-opc.h (ZEROING_MASKING) Rename to ...
1227         (DYNAMIC_MASKING): ... this. Adjust comment.
1228         * i386-opc.tbl (MaskingMorZ): Define.
1229         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1230         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1231         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1232         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1233         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1234         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1235         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1236         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1237         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1238
1239 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1240
1241         * i386-opc.tbl: Use element rather than vector size for AVX512*
1242         scatter/gather insns.
1243         * i386-tbl.h: Re-generate.
1244
1245 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1246
1247         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1248         (cpu_flags): Drop CpuVREX.
1249         * i386-opc.h (CpuVREX): Delete.
1250         (union i386_cpu_flags): Remove cpuvrex.
1251         * i386-init.h, i386-tbl.h: Re-generate.
1252
1253 2018-07-30  Jim Wilson  <jimw@sifive.com>
1254
1255         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1256         fields.
1257         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1258
1259 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1260
1261         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1262         * Makefile.in: Regenerated.
1263         * configure.ac: Add C-SKY.
1264         * configure: Regenerated.
1265         * csky-dis.c: New file.
1266         * csky-opc.h: New file.
1267         * disassemble.c (ARCH_csky): Define.
1268         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1269         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1270
1271 2018-07-27  Alan Modra  <amodra@gmail.com>
1272
1273         * ppc-opc.c (insert_sprbat): Correct function parameter and
1274         return type.
1275         (extract_sprbat): Likewise, variable too.
1276
1277 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1278             Alan Modra  <amodra@gmail.com>
1279
1280         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1281         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1282         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1283         support disjointed BAT.
1284         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1285         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1286         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1287
1288 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1289             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1290
1291         * i386-gen.c (adjust_broadcast_modifier): New function.
1292         (process_i386_opcode_modifier): Add an argument for operands.
1293         Adjust the Broadcast value based on operands.
1294         (output_i386_opcode): Pass operand_types to
1295         process_i386_opcode_modifier.
1296         (process_i386_opcodes): Pass NULL as operands to
1297         process_i386_opcode_modifier.
1298         * i386-opc.h (BYTE_BROADCAST): New.
1299         (WORD_BROADCAST): Likewise.
1300         (DWORD_BROADCAST): Likewise.
1301         (QWORD_BROADCAST): Likewise.
1302         (i386_opcode_modifier): Expand broadcast to 3 bits.
1303         * i386-tbl.h: Regenerated.
1304
1305 2018-07-24  Alan Modra  <amodra@gmail.com>
1306
1307         PR 23430
1308         * or1k-desc.h: Regenerate.
1309
1310 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1311
1312         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1313         vcvtusi2ss, and vcvtusi2sd.
1314         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1315         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1316         * i386-tbl.h: Re-generate.
1317
1318 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1319
1320         * arc-opc.c (extract_w6): Fix extending the sign.
1321
1322 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1323
1324         * arc-tbl.h (vewt): Allow it for ARC EM family.
1325
1326 2018-07-23  Alan Modra  <amodra@gmail.com>
1327
1328         PR 23419
1329         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1330         opcode variants for mtspr/mfspr encodings.
1331
1332 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1333             Maciej W. Rozycki  <macro@mips.com>
1334
1335         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1336         loongson3a descriptors.
1337         (parse_mips_ase_option): Handle -M loongson-mmi option.
1338         (print_mips_disassembler_options): Document -M loongson-mmi.
1339         * mips-opc.c (LMMI): New macro.
1340         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1341         instructions.
1342
1343 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1344
1345         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1346         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1347         IgnoreSize and [XYZ]MMword where applicable.
1348         * i386-tbl.h: Re-generate.
1349
1350 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1351
1352         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1353         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1354         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1355         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1356         * i386-tbl.h: Re-generate.
1357
1358 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1359
1360         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1361         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1362         VPCLMULQDQ templates into their respective AVX512VL counterparts
1363         where possible, using Disp8ShiftVL and CheckRegSize instead of
1364         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1365         * i386-tbl.h: Re-generate.
1366
1367 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1368
1369         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1370         AVX512VL counterparts where possible, using Disp8ShiftVL and
1371         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1372         IgnoreSize) as appropriate.
1373         * i386-tbl.h: Re-generate.
1374
1375 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1376
1377         * i386-opc.tbl: Fold AVX512BW templates into their respective
1378         AVX512VL counterparts where possible, using Disp8ShiftVL and
1379         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1380         IgnoreSize) as appropriate.
1381         * i386-tbl.h: Re-generate.
1382
1383 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1384
1385         * i386-opc.tbl: Fold AVX512CD templates into their respective
1386         AVX512VL counterparts where possible, using Disp8ShiftVL and
1387         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1388         IgnoreSize) as appropriate.
1389         * i386-tbl.h: Re-generate.
1390
1391 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1392
1393         * i386-opc.h (DISP8_SHIFT_VL): New.
1394         * i386-opc.tbl (Disp8ShiftVL):  Define.
1395         (various): Fold AVX512VL templates into their respective
1396         AVX512F counterparts where possible, using Disp8ShiftVL and
1397         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1398         IgnoreSize) as appropriate.
1399         * i386-tbl.h: Re-generate.
1400
1401 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1402
1403         * Makefile.am: Change dependencies and rule for
1404         $(srcdir)/i386-init.h.
1405         * Makefile.in: Re-generate.
1406         * i386-gen.c (process_i386_opcodes): New local variable
1407         "marker". Drop opening of input file. Recognize marker and line
1408         number directives.
1409         * i386-opc.tbl (OPCODE_I386_H): Define.
1410         (i386-opc.h): Include it.
1411         (None): Undefine.
1412
1413 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1414
1415         PR gas/23418
1416         * i386-opc.h (Byte): Update comments.
1417         (Word): Likewise.
1418         (Dword): Likewise.
1419         (Fword): Likewise.
1420         (Qword): Likewise.
1421         (Tbyte): Likewise.
1422         (Xmmword): Likewise.
1423         (Ymmword): Likewise.
1424         (Zmmword): Likewise.
1425         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1426         vcvttps2uqq.
1427         * i386-tbl.h: Regenerated.
1428
1429 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1430
1431         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1432         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1433         * aarch64-asm-2.c: Regenerate.
1434         * aarch64-dis-2.c: Regenerate.
1435         * aarch64-opc-2.c: Regenerate.
1436
1437 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1438
1439         PR binutils/23192
1440         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1441         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1442         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1443         sqdmulh, sqrdmulh): Use Em16.
1444
1445 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1446
1447         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1448         csdb together with them.
1449         (thumb32_opcodes): Likewise.
1450
1451 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1452
1453         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1454         requiring 32-bit registers as operands 2 and 3. Improve
1455         comments.
1456         (mwait, mwaitx): Fold templates. Improve comments.
1457         OPERAND_TYPE_INOUTPORTREG.
1458         * i386-tbl.h: Re-generate.
1459
1460 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1461
1462         * i386-gen.c (operand_type_init): Remove
1463         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1464         OPERAND_TYPE_INOUTPORTREG.
1465         * i386-init.h: Re-generate.
1466
1467 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1468
1469         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1470         (wrssq, wrussq): Add Qword.
1471         * i386-tbl.h: Re-generate.
1472
1473 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1474
1475         * i386-opc.h: Rename OTMax to OTNum.
1476         (OTNumOfUints): Adjust calculation.
1477         (OTUnused): Directly alias to OTNum.
1478
1479 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1480
1481         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1482         `reg_xys'.
1483         (lea_reg_xys): Likewise.
1484         (print_insn_loop_primitive): Rename `reg' local variable to
1485         `reg_dxy'.
1486
1487 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1488
1489         PR binutils/23242
1490         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1491
1492 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1493
1494         PR binutils/23369
1495         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1496         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1497
1498 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1499
1500         PR tdep/8282
1501         * mips-dis.c (mips_option_arg_t): New enumeration.
1502         (mips_options): New variable.
1503         (disassembler_options_mips): New function.
1504         (print_mips_disassembler_options): Reimplement in terms of
1505         `disassembler_options_mips'.
1506         * arm-dis.c (disassembler_options_arm): Adapt to using the
1507         `disasm_options_and_args_t' structure.
1508         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1509         * s390-dis.c (disassembler_options_s390): Likewise.
1510
1511 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1512
1513         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1514         expected result.
1515         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1516         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1517         * testsuite/ld-arm/tls-longplt.d: Likewise.
1518
1519 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1520
1521         PR binutils/23192
1522         * aarch64-asm-2.c: Regenerate.
1523         * aarch64-dis-2.c: Likewise.
1524         * aarch64-opc-2.c: Likewise.
1525         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1526         * aarch64-opc.c (operand_general_constraint_met_p,
1527         aarch64_print_operand): Likewise.
1528         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1529         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1530         fmlal2, fmlsl2.
1531         (AARCH64_OPERANDS): Add Em2.
1532
1533 2018-06-26  Nick Clifton  <nickc@redhat.com>
1534
1535         * po/uk.po: Updated Ukranian translation.
1536         * po/de.po: Updated German translation.
1537         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1538
1539 2018-06-26  Nick Clifton  <nickc@redhat.com>
1540
1541         * nfp-dis.c: Fix spelling mistake.
1542
1543 2018-06-24  Nick Clifton  <nickc@redhat.com>
1544
1545         * configure: Regenerate.
1546         * po/opcodes.pot: Regenerate.
1547
1548 2018-06-24  Nick Clifton  <nickc@redhat.com>
1549
1550         2.31 branch created.
1551
1552 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1553
1554         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1555         * aarch64-asm-2.c: Regenerate.
1556         * aarch64-dis-2.c: Likewise.
1557
1558 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1559
1560         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1561         `-M ginv' option description.
1562
1563 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1564
1565         PR gas/23305
1566         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1567         la and lla.
1568
1569 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1570
1571         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1572         * configure.ac: Remove AC_PREREQ.
1573         * Makefile.in: Re-generate.
1574         * aclocal.m4: Re-generate.
1575         * configure: Re-generate.
1576
1577 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1578
1579         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1580         mips64r6 descriptors.
1581         (parse_mips_ase_option): Handle -Mginv option.
1582         (print_mips_disassembler_options): Document -Mginv.
1583         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1584         (GINV): New macro.
1585         (mips_opcodes): Define ginvi and ginvt.
1586
1587 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1588             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1589
1590         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1591         * mips-opc.c (CRC, CRC64): New macros.
1592         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1593         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1594         crc32cd for CRC64.
1595
1596 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1597
1598         PR 20319
1599         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1600         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1601
1602 2018-06-06  Alan Modra  <amodra@gmail.com>
1603
1604         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1605         setjmp.  Move init for some other vars later too.
1606
1607 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1608
1609         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1610         (dis_private): Add new fields for property section tracking.
1611         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1612         (xtensa_instruction_fits): New functions.
1613         (fetch_data): Bump minimal fetch size to 4.
1614         (print_insn_xtensa): Make struct dis_private static.
1615         Load and prepare property table on section change.
1616         Don't disassemble literals. Don't disassemble instructions that
1617         cross property table boundaries.
1618
1619 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1620
1621         * configure: Regenerated.
1622
1623 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1624
1625         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1626         * i386-tbl.h: Re-generate.
1627
1628 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1629
1630         * i386-opc.tbl (sldt, str): Add NoRex64.
1631         * i386-tbl.h: Re-generate.
1632
1633 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1634
1635         * i386-opc.tbl (invpcid): Add Oword.
1636         * i386-tbl.h: Re-generate.
1637
1638 2018-06-01  Alan Modra  <amodra@gmail.com>
1639
1640         * sysdep.h (_bfd_error_handler): Don't declare.
1641         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1642         * rl78-decode.opc: Likewise.
1643         * msp430-decode.c: Regenerate.
1644         * rl78-decode.c: Regenerate.
1645
1646 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1647
1648         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1649         * i386-init.h : Regenerated.
1650
1651 2018-05-25  Alan Modra  <amodra@gmail.com>
1652
1653         * Makefile.in: Regenerate.
1654         * po/POTFILES.in: Regenerate.
1655
1656 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1657
1658         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1659         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1660         (insert_bab, extract_bab, insert_btab, extract_btab,
1661         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1662         (BAT, BBA VBA RBS XB6S): Delete macros.
1663         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1664         (BB, BD, RBX, XC6): Update for new macros.
1665         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1666         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1667         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1668         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1669
1670 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1671
1672         * Makefile.am: Add support for s12z architecture.
1673         * configure.ac: Likewise.
1674         * disassemble.c: Likewise.
1675         * disassemble.h: Likewise.
1676         * Makefile.in: Regenerate.
1677         * configure: Regenerate.
1678         * s12z-dis.c: New file.
1679         * s12z.h: New file.
1680
1681 2018-05-18  Alan Modra  <amodra@gmail.com>
1682
1683         * nfp-dis.c: Don't #include libbfd.h.
1684         (init_nfp3200_priv): Use bfd_get_section_contents.
1685         (nit_nfp6000_mecsr_sec): Likewise.
1686
1687 2018-05-17  Nick Clifton  <nickc@redhat.com>
1688
1689         * po/zh_CN.po: Updated simplified Chinese translation.
1690
1691 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1692
1693         PR binutils/23109
1694         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1695         * aarch64-dis-2.c: Regenerate.
1696
1697 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1698
1699         PR binutils/21446
1700         * aarch64-asm.c (opintl.h): Include.
1701         (aarch64_ins_sysreg): Enforce read/write constraints.
1702         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1703         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1704         (F_REG_READ, F_REG_WRITE): New.
1705         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1706         AARCH64_OPND_SYSREG.
1707         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1708         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1709         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1710         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1711         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1712         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1713         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1714         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1715         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1716         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1717         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1718         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1719         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1720         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1721         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1722         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1723         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1724
1725 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1726
1727         PR binutils/21446
1728         * aarch64-dis.c (no_notes: New.
1729         (parse_aarch64_dis_option): Support notes.
1730         (aarch64_decode_insn, print_operands): Likewise.
1731         (print_aarch64_disassembler_options): Document notes.
1732         * aarch64-opc.c (aarch64_print_operand): Support notes.
1733
1734 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1735
1736         PR binutils/21446
1737         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1738         and take error struct.
1739         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1740         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1741         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1742         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1743         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1744         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1745         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1746         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1747         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1748         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1749         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1750         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1751         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1752         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1753         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1754         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1755         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1756         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1757         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1758         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1759         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1760         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1761         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1762         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1763         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1764         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1765         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1766         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1767         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1768         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1769         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1770         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1771         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1772         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1773         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1774         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1775         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1776         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1777         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1778         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1779         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1780         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1781         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1782         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1783         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1784         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1785         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1786         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1787         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1788         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1789         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1790         (determine_disassembling_preference, aarch64_decode_insn,
1791         print_insn_aarch64_word, print_insn_data): Take errors struct.
1792         (print_insn_aarch64): Use errors.
1793         * aarch64-asm-2.c: Regenerate.
1794         * aarch64-dis-2.c: Regenerate.
1795         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1796         boolean in aarch64_insert_operan.
1797         (print_operand_extractor): Likewise.
1798         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1799
1800 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1801
1802         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1803
1804 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1805
1806         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1807
1808 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1809
1810         * cr16-opc.c (cr16_instruction): Comment typo fix.
1811         * hppa-dis.c (print_insn_hppa): Likewise.
1812
1813 2018-05-08  Jim Wilson  <jimw@sifive.com>
1814
1815         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1816         (match_c_slli64, match_srxi_as_c_srxi): New.
1817         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1818         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1819         <c.slli, c.srli, c.srai>: Use match_s_slli.
1820         <c.slli64, c.srli64, c.srai64>: New.
1821
1822 2018-05-08  Alan Modra  <amodra@gmail.com>
1823
1824         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1825         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1826         partition opcode space for index lookup.
1827
1828 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1829
1830         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1831         <insn_length>: ...with this.  Update usage.
1832         Remove duplicate call to *info->memory_error_func.
1833
1834 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1835             H.J. Lu  <hongjiu.lu@intel.com>
1836
1837         * i386-dis.c (Gva): New.
1838         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1839         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1840         (prefix_table): New instructions (see prefix above).
1841         (mod_table): New instructions (see prefix above).
1842         (OP_G): Handle va_mode.
1843         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1844         CPU_MOVDIR64B_FLAGS.
1845         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1846         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1847         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1848         * i386-opc.tbl: Add movidir{i,64b}.
1849         * i386-init.h: Regenerated.
1850         * i386-tbl.h: Likewise.
1851
1852 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1853
1854         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1855         AddrPrefixOpReg.
1856         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1857         (AddrPrefixOpReg): This.
1858         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1859         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1860
1861 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1862
1863         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1864         (vle_num_opcodes): Likewise.
1865         (spe2_num_opcodes): Likewise.
1866         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1867         initialization loop.
1868         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1869         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1870         only once.
1871
1872 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1873
1874         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1875
1876 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1877
1878         Makefile.am: Added nfp-dis.c.
1879         configure.ac: Added bfd_nfp_arch.
1880         disassemble.h: Added print_insn_nfp prototype.
1881         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1882         nfp-dis.c: New, for NFP support.
1883         po/POTFILES.in: Added nfp-dis.c to the list.
1884         Makefile.in: Regenerate.
1885         configure: Regenerate.
1886
1887 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1888
1889         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1890         templates into their base ones.
1891         * i386-tlb.h: Re-generate.
1892
1893 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1894
1895         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1896         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1897         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1898         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1899         * i386-init.h: Re-generate.
1900
1901 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1902
1903         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1904         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1905         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1906         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1907         comment.
1908         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1909         and CpuRegMask.
1910         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1911         CpuRegMask: Delete.
1912         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1913         cpuregzmm, and cpuregmask.
1914         * i386-init.h: Re-generate.
1915         * i386-tbl.h: Re-generate.
1916
1917 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1918
1919         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1920         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1921         * i386-init.h: Re-generate.
1922
1923 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1924
1925         * i386-gen.c (VexImmExt): Delete.
1926         * i386-opc.h (VexImmExt, veximmext): Delete.
1927         * i386-opc.tbl: Drop all VexImmExt uses.
1928         * i386-tlb.h: Re-generate.
1929
1930 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1931
1932         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1933         register-only forms.
1934         * i386-tlb.h: Re-generate.
1935
1936 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1937
1938         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1939
1940 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1941
1942         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1943         PREFIX_0F1C.
1944         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1945         (cpu_flags): Add CpuCLDEMOTE.
1946         * i386-init.h: Regenerate.
1947         * i386-opc.h (enum): Add CpuCLDEMOTE,
1948         (i386_cpu_flags): Add cpucldemote.
1949         * i386-opc.tbl: Add cldemote.
1950         * i386-tbl.h: Regenerate.
1951
1952 2018-04-16  Alan Modra  <amodra@gmail.com>
1953
1954         * Makefile.am: Remove sh5 and sh64 support.
1955         * configure.ac: Likewise.
1956         * disassemble.c: Likewise.
1957         * disassemble.h: Likewise.
1958         * sh-dis.c: Likewise.
1959         * sh64-dis.c: Delete.
1960         * sh64-opc.c: Delete.
1961         * sh64-opc.h: Delete.
1962         * Makefile.in: Regenerate.
1963         * configure: Regenerate.
1964         * po/POTFILES.in: Regenerate.
1965
1966 2018-04-16  Alan Modra  <amodra@gmail.com>
1967
1968         * Makefile.am: Remove w65 support.
1969         * configure.ac: Likewise.
1970         * disassemble.c: Likewise.
1971         * disassemble.h: Likewise.
1972         * w65-dis.c: Delete.
1973         * w65-opc.h: Delete.
1974         * Makefile.in: Regenerate.
1975         * configure: Regenerate.
1976         * po/POTFILES.in: Regenerate.
1977
1978 2018-04-16  Alan Modra  <amodra@gmail.com>
1979
1980         * configure.ac: Remove we32k support.
1981         * configure: Regenerate.
1982
1983 2018-04-16  Alan Modra  <amodra@gmail.com>
1984
1985         * Makefile.am: Remove m88k support.
1986         * configure.ac: Likewise.
1987         * disassemble.c: Likewise.
1988         * disassemble.h: Likewise.
1989         * m88k-dis.c: Delete.
1990         * Makefile.in: Regenerate.
1991         * configure: Regenerate.
1992         * po/POTFILES.in: Regenerate.
1993
1994 2018-04-16  Alan Modra  <amodra@gmail.com>
1995
1996         * Makefile.am: Remove i370 support.
1997         * configure.ac: Likewise.
1998         * disassemble.c: Likewise.
1999         * disassemble.h: Likewise.
2000         * i370-dis.c: Delete.
2001         * i370-opc.c: Delete.
2002         * Makefile.in: Regenerate.
2003         * configure: Regenerate.
2004         * po/POTFILES.in: Regenerate.
2005
2006 2018-04-16  Alan Modra  <amodra@gmail.com>
2007
2008         * Makefile.am: Remove h8500 support.
2009         * configure.ac: Likewise.
2010         * disassemble.c: Likewise.
2011         * disassemble.h: Likewise.
2012         * h8500-dis.c: Delete.
2013         * h8500-opc.h: Delete.
2014         * Makefile.in: Regenerate.
2015         * configure: Regenerate.
2016         * po/POTFILES.in: Regenerate.
2017
2018 2018-04-16  Alan Modra  <amodra@gmail.com>
2019
2020         * configure.ac: Remove tahoe support.
2021         * configure: Regenerate.
2022
2023 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
2024
2025         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2026         umwait.
2027         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2028         64-bit mode.
2029         * i386-tbl.h: Regenerated.
2030
2031 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2032
2033         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2034         PREFIX_MOD_1_0FAE_REG_6.
2035         (va_mode): New.
2036         (OP_E_register): Use va_mode.
2037         * i386-dis-evex.h (prefix_table):
2038         New instructions (see prefixes above).
2039         * i386-gen.c (cpu_flag_init): Add WAITPKG.
2040         (cpu_flags): Likewise.
2041         * i386-opc.h (enum): Likewise.
2042         (i386_cpu_flags): Likewise.
2043         * i386-opc.tbl: Add umonitor, umwait, tpause.
2044         * i386-init.h: Regenerate.
2045         * i386-tbl.h: Likewise.
2046
2047 2018-04-11  Alan Modra  <amodra@gmail.com>
2048
2049         * opcodes/i860-dis.c: Delete.
2050         * opcodes/i960-dis.c: Delete.
2051         * Makefile.am: Remove i860 and i960 support.
2052         * configure.ac: Likewise.
2053         * disassemble.c: Likewise.
2054         * disassemble.h: Likewise.
2055         * Makefile.in: Regenerate.
2056         * configure: Regenerate.
2057         * po/POTFILES.in: Regenerate.
2058
2059 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
2060
2061         PR binutils/23025
2062         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2063         to 0.
2064         (print_insn): Clear vex instead of vex.evex.
2065
2066 2018-04-04  Nick Clifton  <nickc@redhat.com>
2067
2068         * po/es.po: Updated Spanish translation.
2069
2070 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2071
2072         * i386-gen.c (opcode_modifiers): Delete VecESize.
2073         * i386-opc.h (VecESize): Delete.
2074         (struct i386_opcode_modifier): Delete vecesize.
2075         * i386-opc.tbl: Drop VecESize.
2076         * i386-tlb.h: Re-generate.
2077
2078 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2079
2080         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2081         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2082         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2083         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2084         * i386-tlb.h: Re-generate.
2085
2086 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2087
2088         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2089         Fold AVX512 forms
2090         * i386-tlb.h: Re-generate.
2091
2092 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2093
2094         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2095         (vex_len_table): Drop Y for vcvt*2si.
2096         (putop): Replace plain 'Y' handling by abort().
2097
2098 2018-03-28  Nick Clifton  <nickc@redhat.com>
2099
2100         PR 22988
2101         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2102         instructions with only a base address register.
2103         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2104         handle AARHC64_OPND_SVE_ADDR_R.
2105         (aarch64_print_operand): Likewise.
2106         * aarch64-asm-2.c: Regenerate.
2107         * aarch64_dis-2.c: Regenerate.
2108         * aarch64-opc-2.c: Regenerate.
2109
2110 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2111
2112         * i386-opc.tbl: Drop VecESize from register only insn forms and
2113         memory forms not allowing broadcast.
2114         * i386-tlb.h: Re-generate.
2115
2116 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2117
2118         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2119         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2120         sha256*): Drop Disp<N>.
2121
2122 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2123
2124         * i386-dis.c (EbndS, bnd_swap_mode): New.
2125         (prefix_table): Use EbndS.
2126         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2127         * i386-opc.tbl (bndmov): Move misplaced Load.
2128         * i386-tlb.h: Re-generate.
2129
2130 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2131
2132         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2133         templates allowing memory operands and folded ones for register
2134         only flavors.
2135         * i386-tlb.h: Re-generate.
2136
2137 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2138
2139         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2140         256-bit templates. Drop redundant leftover Disp<N>.
2141         * i386-tlb.h: Re-generate.
2142
2143 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2144
2145         * riscv-opc.c (riscv_insn_types): New.
2146
2147 2018-03-13  Nick Clifton  <nickc@redhat.com>
2148
2149         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2150
2151 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2152
2153         * i386-opc.tbl: Add Optimize to clr.
2154         * i386-tbl.h: Regenerated.
2155
2156 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2157
2158         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2159         * i386-opc.h (OldGcc): Removed.
2160         (i386_opcode_modifier): Remove oldgcc.
2161         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2162         instructions for old (<= 2.8.1) versions of gcc.
2163         * i386-tbl.h: Regenerated.
2164
2165 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2166
2167         * i386-opc.h (EVEXDYN): New.
2168         * i386-opc.tbl: Fold various AVX512VL templates.
2169         * i386-tlb.h: Re-generate.
2170
2171 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2172
2173         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2174         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2175         vpexpandd, vpexpandq): Fold AFX512VF templates.
2176         * i386-tlb.h: Re-generate.
2177
2178 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2179
2180         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2181         Fold 128- and 256-bit VEX-encoded templates.
2182         * i386-tlb.h: Re-generate.
2183
2184 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2185
2186         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2187         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2188         vpexpandd, vpexpandq): Fold AVX512F templates.
2189         * i386-tlb.h: Re-generate.
2190
2191 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2192
2193         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2194         64-bit templates. Drop Disp<N>.
2195         * i386-tlb.h: Re-generate.
2196
2197 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2198
2199         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2200         and 256-bit templates.
2201         * i386-tlb.h: Re-generate.
2202
2203 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2204
2205         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2206         * i386-tlb.h: Re-generate.
2207
2208 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2209
2210         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2211         Drop NoAVX.
2212         * i386-tlb.h: Re-generate.
2213
2214 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2215
2216         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2217         * i386-tlb.h: Re-generate.
2218
2219 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2220
2221         * i386-gen.c (opcode_modifiers): Delete FloatD.
2222         * i386-opc.h (FloatD): Delete.
2223         (struct i386_opcode_modifier): Delete floatd.
2224         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2225         FloatD by D.
2226         * i386-tlb.h: Re-generate.
2227
2228 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2229
2230         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2231
2232 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2233
2234         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2235         * i386-tlb.h: Re-generate.
2236
2237 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2238
2239         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2240         forms.
2241         * i386-tlb.h: Re-generate.
2242
2243 2018-03-07  Alan Modra  <amodra@gmail.com>
2244
2245         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2246         bfd_arch_rs6000.
2247         * disassemble.h (print_insn_rs6000): Delete.
2248         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2249         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2250         (print_insn_rs6000): Delete.
2251
2252 2018-03-03  Alan Modra  <amodra@gmail.com>
2253
2254         * sysdep.h (opcodes_error_handler): Define.
2255         (_bfd_error_handler): Declare.
2256         * Makefile.am: Remove stray #.
2257         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2258         EDIT" comment.
2259         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2260         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2261         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2262         opcodes_error_handler to print errors.  Standardize error messages.
2263         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2264         and include opintl.h.
2265         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2266         * i386-gen.c: Standardize error messages.
2267         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2268         * Makefile.in: Regenerate.
2269         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2270         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2271         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2272         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2273         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2274         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2275         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2276         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2277         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2278         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2279         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2280         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2281         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2282
2283 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2284
2285         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2286         vpsub[bwdq] instructions.
2287         * i386-tbl.h: Regenerated.
2288
2289 2018-03-01  Alan Modra  <amodra@gmail.com>
2290
2291         * configure.ac (ALL_LINGUAS): Sort.
2292         * configure: Regenerate.
2293
2294 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2295
2296         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2297         macro by assignements.
2298
2299 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2300
2301         PR gas/22871
2302         * i386-gen.c (opcode_modifiers): Add Optimize.
2303         * i386-opc.h (Optimize): New enum.
2304         (i386_opcode_modifier): Add optimize.
2305         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2306         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2307         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2308         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2309         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2310         vpxord and vpxorq.
2311         * i386-tbl.h: Regenerated.
2312
2313 2018-02-26  Alan Modra  <amodra@gmail.com>
2314
2315         * crx-dis.c (getregliststring): Allocate a large enough buffer
2316         to silence false positive gcc8 warning.
2317
2318 2018-02-22  Shea Levy <shea@shealevy.com>
2319
2320         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2321
2322 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2323
2324         * i386-opc.tbl: Add {rex},
2325         * i386-tbl.h: Regenerated.
2326
2327 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2328
2329         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2330         (mips16_opcodes): Replace `M' with `m' for "restore".
2331
2332 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2333
2334         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2335
2336 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2337
2338         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2339         variable to `function_index'.
2340
2341 2018-02-13  Nick Clifton  <nickc@redhat.com>
2342
2343         PR 22823
2344         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2345         about truncation of printing.
2346
2347 2018-02-12  Henry Wong <henry@stuffedcow.net>
2348
2349         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2350
2351 2018-02-05  Nick Clifton  <nickc@redhat.com>
2352
2353         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2354
2355 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2356
2357         * i386-dis.c (enum): Add pconfig.
2358         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2359         (cpu_flags): Add CpuPCONFIG.
2360         * i386-opc.h (enum): Add CpuPCONFIG.
2361         (i386_cpu_flags): Add cpupconfig.
2362         * i386-opc.tbl: Add PCONFIG instruction.
2363         * i386-init.h: Regenerate.
2364         * i386-tbl.h: Likewise.
2365
2366 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2367
2368         * i386-dis.c (enum): Add PREFIX_0F09.
2369         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2370         (cpu_flags): Add CpuWBNOINVD.
2371         * i386-opc.h (enum): Add CpuWBNOINVD.
2372         (i386_cpu_flags): Add cpuwbnoinvd.
2373         * i386-opc.tbl: Add WBNOINVD instruction.
2374         * i386-init.h: Regenerate.
2375         * i386-tbl.h: Likewise.
2376
2377 2018-01-17  Jim Wilson  <jimw@sifive.com>
2378
2379         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2380
2381 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2382
2383         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2384         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2385         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2386         (cpu_flags): Add CpuIBT, CpuSHSTK.
2387         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2388         (i386_cpu_flags): Add cpuibt, cpushstk.
2389         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2390         * i386-init.h: Regenerate.
2391         * i386-tbl.h: Likewise.
2392
2393 2018-01-16  Nick Clifton  <nickc@redhat.com>
2394
2395         * po/pt_BR.po: Updated Brazilian Portugese translation.
2396         * po/de.po: Updated German translation.
2397
2398 2018-01-15  Jim Wilson  <jimw@sifive.com>
2399
2400         * riscv-opc.c (match_c_nop): New.
2401         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2402
2403 2018-01-15  Nick Clifton  <nickc@redhat.com>
2404
2405         * po/uk.po: Updated Ukranian translation.
2406
2407 2018-01-13  Nick Clifton  <nickc@redhat.com>
2408
2409         * po/opcodes.pot: Regenerated.
2410
2411 2018-01-13  Nick Clifton  <nickc@redhat.com>
2412
2413         * configure: Regenerate.
2414
2415 2018-01-13  Nick Clifton  <nickc@redhat.com>
2416
2417         2.30 branch created.
2418
2419 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2420
2421         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2422         * i386-tbl.h: Regenerate.
2423
2424 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2425
2426         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2427         * i386-tbl.h: Re-generate.
2428
2429 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2430
2431         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2432         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2433         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2434         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2435         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2436         Disp8MemShift of AVX512VL forms.
2437         * i386-tbl.h: Re-generate.
2438
2439 2018-01-09  Jim Wilson  <jimw@sifive.com>
2440
2441         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2442         then the hi_addr value is zero.
2443
2444 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2445
2446         * arm-dis.c (arm_opcodes): Add csdb.
2447         (thumb32_opcodes): Add csdb.
2448
2449 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2450
2451         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2452         * aarch64-asm-2.c: Regenerate.
2453         * aarch64-dis-2.c: Regenerate.
2454         * aarch64-opc-2.c: Regenerate.
2455
2456 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2457
2458         PR gas/22681
2459         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2460         Remove AVX512 vmovd with 64-bit operands.
2461         * i386-tbl.h: Regenerated.
2462
2463 2018-01-05  Jim Wilson  <jimw@sifive.com>
2464
2465         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2466         jalr.
2467
2468 2018-01-03  Alan Modra  <amodra@gmail.com>
2469
2470         Update year range in copyright notice of all files.
2471
2472 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2473
2474         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2475         and OPERAND_TYPE_REGZMM entries.
2476
2477 For older changes see ChangeLog-2017
2478 \f
2479 Copyright (C) 2018 Free Software Foundation, Inc.
2480
2481 Copying and distribution of this file, with or without modification,
2482 are permitted in any medium without royalty provided the copyright
2483 notice and this notice are preserved.
2484
2485 Local Variables:
2486 mode: change-log
2487 left-margin: 8
2488 fill-column: 74
2489 version-control: never
2490 End: