opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
   4         meaningless.
   5         * i386-tbl.h: Re-generate.
   6
   7 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
  10         meaningless.
  11         * i386-tbl.h: Re-generate.
  12
  13 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
  16         meaningless.
  17         * i386-tbl.h: Re-generate.
  18
  19 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  20
  21         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
  22         * i386-tbl.h: Re-generate.
  23
  24 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  25
  26         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
  27         * i386-tbl.h: Re-generate.
  28
  29 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  30
  31         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
  32         meaningless.
  33         * i386-tbl.h: Re-generate.
  34
  35 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  36
  37         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
  38         meaningless.
  39         * i386-tbl.h: Re-generate.
  40
  41 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
  44         * i386-tbl.h: Re-generate.
  45
  46 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
  49         * i386-tbl.h: Re-generate.
  50
  51 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
  54         * i386-tbl.h: Re-generate.
  55
  56 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
  59         meaningless.
  60         * i386-tbl.h: Re-generate.
  61
  62 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
  65         meaningless.
  66         * i386-tbl.h: Re-generate.
  67
  68 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
  71         meaningless.
  72         * i386-tbl.h: Re-generate.
  73
  74 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
  77         * i386-tbl.h: Re-generate.
  78
  79 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
  82         * i386-tbl.h: Re-generate.
  83
  84 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
  87         * i386-tbl.h: Re-generate.
  88
  89 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
  92         (vpbroadcastw, rdpid): Drop NoRex64.
  93         * i386-tbl.h: Re-generate.
  94
  95 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
  98         store templates, adding D.
  99         * i386-tbl.h: Re-generate.
 100
 101 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 104         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 105         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 106         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 107         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 108         Fold load and store templates where possible, adding D. Drop
 109         IgnoreSize where it was pointlessly present. Drop redundant
 110         *word.
 111         * i386-tbl.h: Re-generate.
 112
 113 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 116         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 117         (intel_operand_size): Handle v_bndmk_mode.
 118         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 119
 120 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 121
 122         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 123
 124 2018-08-31  Kito Cheng  <kito@andestech.com>
 125
 126         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 127         compressed floating point instructions.
 128
 129 2018-08-30  Kito Cheng  <kito@andestech.com>
 130
 131         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 132         riscv_opcode.xlen_requirement.
 133         * riscv-opc.c (riscv_opcodes): Update for struct change.
 134
 135 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 136
 137         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 138         psr (PWRPSR) instruction.
 139
 140 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 141
 142         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 143
 144 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 145
 146         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 147
 148 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 149
 150         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 151         loongson3a as an alias of gs464 for compatibility.
 152         * mips-opc.c (mips_opcodes): Change Comments.
 153
 154 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 155
 156         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 157         option.
 158         (print_mips_disassembler_options): Document -M loongson-ext.
 159         * mips-opc.c (LEXT2): New macro.
 160         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 161
 162 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 163
 164          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 165          descriptors.
 166          (parse_mips_ase_option): Handle -M loongson-ext option.
 167          (print_mips_disassembler_options): Document -M loongson-ext.
 168          * mips-opc.c (IL3A): Delete.
 169          * mips-opc.c (LEXT): New macro.
 170          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 171          instructions.
 172
 173 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 174
 175         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 176         descriptors.
 177         (parse_mips_ase_option): Handle -M loongson-cam option.
 178         (print_mips_disassembler_options): Document -M loongson-cam.
 179         * mips-opc.c (LCAM): New macro.
 180         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 181         instructions.
 182
 183 2018-08-21  Alan Modra  <amodra@gmail.com>
 184
 185         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 186         (skip_optional_operands): Count optional operands, and update
 187         ppc_optional_operand_value call.
 188         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 189         (extract_vlensi): Likewise.
 190         (extract_fxm): Return default value for missing optional operand.
 191         (extract_ls, extract_raq, extract_tbr): Likewise.
 192         (insert_sxl, extract_sxl): New functions.
 193         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 194         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 195         flag and extra entry.
 196         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 197         extract_sxl.
 198
 199 2018-08-20  Alan Modra  <amodra@gmail.com>
 200
 201         * sh-opc.h (MASK): Simplify.
 202
 203 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 204
 205         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 206         BM_RESERVED0 or BM_RESERVED1
 207         (bm_rel_decode, bm_n_bytes): Ditto.
 208
 209 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 210
 211         * s12z.h: Delete.
 212
 213 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 214
 215         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 216         address with the addr32 prefix and without base nor index
 217         registers.
 218
 219 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 220
 221         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 222         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 223         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 224         (cpu_flags): Add CpuCMOV and CpuFXSR.
 225         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 226         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 227         * i386-init.h: Regenerated.
 228         * i386-tbl.h: Likewise.
 229
 230 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 231
 232         * arc-regs.h: Update auxiliary registers.
 233
 234 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 235
 236         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 237         (RegIP, RegIZ): Define.
 238         * i386-reg.tbl: Adjust comments.
 239         (rip): Use Qword instead of BaseIndex. Use RegIP.
 240         (eip): Use Dword instead of BaseIndex. Use RegIP.
 241         (riz): Add Qword. Use RegIZ.
 242         (eiz): Add Dword. Use RegIZ.
 243         * i386-tbl.h: Re-generate.
 244
 245 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 248         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 249         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 250         * i386-tbl.h: Re-generate.
 251
 252 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-gen.c (operand_types): Remove Mem field.
 255         * i386-opc.h (union i386_operand_type): Remove mem field.
 256         * i386-init.h, i386-tbl.h: Re-generate.
 257
 258 2018-08-01  Alan Modra  <amodra@gmail.com>
 259
 260         * po/POTFILES.in: Regenerate.
 261
 262 2018-07-31  Nick Clifton  <nickc@redhat.com>
 263
 264         * po/sv.po: Updated Swedish translation.
 265
 266 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 269         * i386-init.h, i386-tbl.h: Re-generate.
 270
 271 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 272
 273         * i386-opc.h (ZEROING_MASKING) Rename to ...
 274         (DYNAMIC_MASKING): ... this. Adjust comment.
 275         * i386-opc.tbl (MaskingMorZ): Define.
 276         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 277         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 278         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 279         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 280         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 281         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 282         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 283         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 284         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 285
 286 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 287
 288         * i386-opc.tbl: Use element rather than vector size for AVX512*
 289         scatter/gather insns.
 290         * i386-tbl.h: Re-generate.
 291
 292 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 295         (cpu_flags): Drop CpuVREX.
 296         * i386-opc.h (CpuVREX): Delete.
 297         (union i386_cpu_flags): Remove cpuvrex.
 298         * i386-init.h, i386-tbl.h: Re-generate.
 299
 300 2018-07-30  Jim Wilson  <jimw@sifive.com>
 301
 302         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 303         fields.
 304         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 305
 306 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 307
 308         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 309         * Makefile.in: Regenerated.
 310         * configure.ac: Add C-SKY.
 311         * configure: Regenerated.
 312         * csky-dis.c: New file.
 313         * csky-opc.h: New file.
 314         * disassemble.c (ARCH_csky): Define.
 315         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 316         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 317
 318 2018-07-27  Alan Modra  <amodra@gmail.com>
 319
 320         * ppc-opc.c (insert_sprbat): Correct function parameter and
 321         return type.
 322         (extract_sprbat): Likewise, variable too.
 323
 324 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 325             Alan Modra  <amodra@gmail.com>
 326
 327         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 328         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 329         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 330         support disjointed BAT.
 331         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 332         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 333         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 334
 335 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 336             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 337
 338         * i386-gen.c (adjust_broadcast_modifier): New function.
 339         (process_i386_opcode_modifier): Add an argument for operands.
 340         Adjust the Broadcast value based on operands.
 341         (output_i386_opcode): Pass operand_types to
 342         process_i386_opcode_modifier.
 343         (process_i386_opcodes): Pass NULL as operands to
 344         process_i386_opcode_modifier.
 345         * i386-opc.h (BYTE_BROADCAST): New.
 346         (WORD_BROADCAST): Likewise.
 347         (DWORD_BROADCAST): Likewise.
 348         (QWORD_BROADCAST): Likewise.
 349         (i386_opcode_modifier): Expand broadcast to 3 bits.
 350         * i386-tbl.h: Regenerated.
 351
 352 2018-07-24  Alan Modra  <amodra@gmail.com>
 353
 354         PR 23430
 355         * or1k-desc.h: Regenerate.
 356
 357 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 360         vcvtusi2ss, and vcvtusi2sd.
 361         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 362         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 363         * i386-tbl.h: Re-generate.
 364
 365 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 366
 367         * arc-opc.c (extract_w6): Fix extending the sign.
 368
 369 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 370
 371         * arc-tbl.h (vewt): Allow it for ARC EM family.
 372
 373 2018-07-23  Alan Modra  <amodra@gmail.com>
 374
 375         PR 23419
 376         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 377         opcode variants for mtspr/mfspr encodings.
 378
 379 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 380             Maciej W. Rozycki  <macro@mips.com>
 381
 382         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 383         loongson3a descriptors.
 384         (parse_mips_ase_option): Handle -M loongson-mmi option.
 385         (print_mips_disassembler_options): Document -M loongson-mmi.
 386         * mips-opc.c (LMMI): New macro.
 387         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 388         instructions.
 389
 390 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 393         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 394         IgnoreSize and [XYZ]MMword where applicable.
 395         * i386-tbl.h: Re-generate.
 396
 397 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 400         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 401         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 402         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 403         * i386-tbl.h: Re-generate.
 404
 405 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 408         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 409         VPCLMULQDQ templates into their respective AVX512VL counterparts
 410         where possible, using Disp8ShiftVL and CheckRegSize instead of
 411         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 412         * i386-tbl.h: Re-generate.
 413
 414 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 417         AVX512VL counterparts where possible, using Disp8ShiftVL and
 418         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 419         IgnoreSize) as appropriate.
 420         * i386-tbl.h: Re-generate.
 421
 422 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 423
 424         * i386-opc.tbl: Fold AVX512BW templates into their respective
 425         AVX512VL counterparts where possible, using Disp8ShiftVL and
 426         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 427         IgnoreSize) as appropriate.
 428         * i386-tbl.h: Re-generate.
 429
 430 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-opc.tbl: Fold AVX512CD templates into their respective
 433         AVX512VL counterparts where possible, using Disp8ShiftVL and
 434         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 435         IgnoreSize) as appropriate.
 436         * i386-tbl.h: Re-generate.
 437
 438 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 439
 440         * i386-opc.h (DISP8_SHIFT_VL): New.
 441         * i386-opc.tbl (Disp8ShiftVL):  Define.
 442         (various): Fold AVX512VL templates into their respective
 443         AVX512F counterparts where possible, using Disp8ShiftVL and
 444         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 445         IgnoreSize) as appropriate.
 446         * i386-tbl.h: Re-generate.
 447
 448 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 449
 450         * Makefile.am: Change dependencies and rule for
 451         $(srcdir)/i386-init.h.
 452         * Makefile.in: Re-generate.
 453         * i386-gen.c (process_i386_opcodes): New local variable
 454         "marker". Drop opening of input file. Recognize marker and line
 455         number directives.
 456         * i386-opc.tbl (OPCODE_I386_H): Define.
 457         (i386-opc.h): Include it.
 458         (None): Undefine.
 459
 460 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 461
 462         PR gas/23418
 463         * i386-opc.h (Byte): Update comments.
 464         (Word): Likewise.
 465         (Dword): Likewise.
 466         (Fword): Likewise.
 467         (Qword): Likewise.
 468         (Tbyte): Likewise.
 469         (Xmmword): Likewise.
 470         (Ymmword): Likewise.
 471         (Zmmword): Likewise.
 472         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 473         vcvttps2uqq.
 474         * i386-tbl.h: Regenerated.
 475
 476 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 477
 478         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 479         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 480         * aarch64-asm-2.c: Regenerate.
 481         * aarch64-dis-2.c: Regenerate.
 482         * aarch64-opc-2.c: Regenerate.
 483
 484 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 485
 486         PR binutils/23192
 487         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 488         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 489         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 490         sqdmulh, sqrdmulh): Use Em16.
 491
 492 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 493
 494         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 495         csdb together with them.
 496         (thumb32_opcodes): Likewise.
 497
 498 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 501         requiring 32-bit registers as operands 2 and 3. Improve
 502         comments.
 503         (mwait, mwaitx): Fold templates. Improve comments.
 504         OPERAND_TYPE_INOUTPORTREG.
 505         * i386-tbl.h: Re-generate.
 506
 507 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 508
 509         * i386-gen.c (operand_type_init): Remove
 510         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 511         OPERAND_TYPE_INOUTPORTREG.
 512         * i386-init.h: Re-generate.
 513
 514 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 515
 516         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 517         (wrssq, wrussq): Add Qword.
 518         * i386-tbl.h: Re-generate.
 519
 520 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 521
 522         * i386-opc.h: Rename OTMax to OTNum.
 523         (OTNumOfUints): Adjust calculation.
 524         (OTUnused): Directly alias to OTNum.
 525
 526 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 527
 528         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 529         `reg_xys'.
 530         (lea_reg_xys): Likewise.
 531         (print_insn_loop_primitive): Rename `reg' local variable to
 532         `reg_dxy'.
 533
 534 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 535
 536         PR binutils/23242
 537         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 538
 539 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 540
 541         PR binutils/23369
 542         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 543         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 544
 545 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 546
 547         PR tdep/8282
 548         * mips-dis.c (mips_option_arg_t): New enumeration.
 549         (mips_options): New variable.
 550         (disassembler_options_mips): New function.
 551         (print_mips_disassembler_options): Reimplement in terms of
 552         `disassembler_options_mips'.
 553         * arm-dis.c (disassembler_options_arm): Adapt to using the
 554         `disasm_options_and_args_t' structure.
 555         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 556         * s390-dis.c (disassembler_options_s390): Likewise.
 557
 558 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 559
 560         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 561         expected result.
 562         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 563         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 564         * testsuite/ld-arm/tls-longplt.d: Likewise.
 565
 566 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 567
 568         PR binutils/23192
 569         * aarch64-asm-2.c: Regenerate.
 570         * aarch64-dis-2.c: Likewise.
 571         * aarch64-opc-2.c: Likewise.
 572         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 573         * aarch64-opc.c (operand_general_constraint_met_p,
 574         aarch64_print_operand): Likewise.
 575         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 576         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 577         fmlal2, fmlsl2.
 578         (AARCH64_OPERANDS): Add Em2.
 579
 580 2018-06-26  Nick Clifton  <nickc@redhat.com>
 581
 582         * po/uk.po: Updated Ukranian translation.
 583         * po/de.po: Updated German translation.
 584         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 585
 586 2018-06-26  Nick Clifton  <nickc@redhat.com>
 587
 588         * nfp-dis.c: Fix spelling mistake.
 589
 590 2018-06-24  Nick Clifton  <nickc@redhat.com>
 591
 592         * configure: Regenerate.
 593         * po/opcodes.pot: Regenerate.
 594
 595 2018-06-24  Nick Clifton  <nickc@redhat.com>
 596
 597         2.31 branch created.
 598
 599 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 600
 601         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 602         * aarch64-asm-2.c: Regenerate.
 603         * aarch64-dis-2.c: Likewise.
 604
 605 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 606
 607         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 608         `-M ginv' option description.
 609
 610 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 611
 612         PR gas/23305
 613         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 614         la and lla.
 615
 616 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 617
 618         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 619         * configure.ac: Remove AC_PREREQ.
 620         * Makefile.in: Re-generate.
 621         * aclocal.m4: Re-generate.
 622         * configure: Re-generate.
 623
 624 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 625
 626         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 627         mips64r6 descriptors.
 628         (parse_mips_ase_option): Handle -Mginv option.
 629         (print_mips_disassembler_options): Document -Mginv.
 630         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 631         (GINV): New macro.
 632         (mips_opcodes): Define ginvi and ginvt.
 633
 634 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 635             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 636
 637         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 638         * mips-opc.c (CRC, CRC64): New macros.
 639         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 640         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 641         crc32cd for CRC64.
 642
 643 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 644
 645         PR 20319
 646         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 647         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 648
 649 2018-06-06  Alan Modra  <amodra@gmail.com>
 650
 651         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 652         setjmp.  Move init for some other vars later too.
 653
 654 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 655
 656         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 657         (dis_private): Add new fields for property section tracking.
 658         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 659         (xtensa_instruction_fits): New functions.
 660         (fetch_data): Bump minimal fetch size to 4.
 661         (print_insn_xtensa): Make struct dis_private static.
 662         Load and prepare property table on section change.
 663         Don't disassemble literals. Don't disassemble instructions that
 664         cross property table boundaries.
 665
 666 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 667
 668         * configure: Regenerated.
 669
 670 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 673         * i386-tbl.h: Re-generate.
 674
 675 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 676
 677         * i386-opc.tbl (sldt, str): Add NoRex64.
 678         * i386-tbl.h: Re-generate.
 679
 680 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-opc.tbl (invpcid): Add Oword.
 683         * i386-tbl.h: Re-generate.
 684
 685 2018-06-01  Alan Modra  <amodra@gmail.com>
 686
 687         * sysdep.h (_bfd_error_handler): Don't declare.
 688         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 689         * rl78-decode.opc: Likewise.
 690         * msp430-decode.c: Regenerate.
 691         * rl78-decode.c: Regenerate.
 692
 693 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 694
 695         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 696         * i386-init.h : Regenerated.
 697
 698 2018-05-25  Alan Modra  <amodra@gmail.com>
 699
 700         * Makefile.in: Regenerate.
 701         * po/POTFILES.in: Regenerate.
 702
 703 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 704
 705         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 706         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 707         (insert_bab, extract_bab, insert_btab, extract_btab,
 708         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 709         (BAT, BBA VBA RBS XB6S): Delete macros.
 710         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 711         (BB, BD, RBX, XC6): Update for new macros.
 712         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 713         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 714         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 715         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 716
 717 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 718
 719         * Makefile.am: Add support for s12z architecture.
 720         * configure.ac: Likewise.
 721         * disassemble.c: Likewise.
 722         * disassemble.h: Likewise.
 723         * Makefile.in: Regenerate.
 724         * configure: Regenerate.
 725         * s12z-dis.c: New file.
 726         * s12z.h: New file.
 727
 728 2018-05-18  Alan Modra  <amodra@gmail.com>
 729
 730         * nfp-dis.c: Don't #include libbfd.h.
 731         (init_nfp3200_priv): Use bfd_get_section_contents.
 732         (nit_nfp6000_mecsr_sec): Likewise.
 733
 734 2018-05-17  Nick Clifton  <nickc@redhat.com>
 735
 736         * po/zh_CN.po: Updated simplified Chinese translation.
 737
 738 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 739
 740         PR binutils/23109
 741         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 742         * aarch64-dis-2.c: Regenerate.
 743
 744 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 745
 746         PR binutils/21446
 747         * aarch64-asm.c (opintl.h): Include.
 748         (aarch64_ins_sysreg): Enforce read/write constraints.
 749         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 750         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 751         (F_REG_READ, F_REG_WRITE): New.
 752         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 753         AARCH64_OPND_SYSREG.
 754         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 755         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 756         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 757         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 758         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 759         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 760         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 761         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 762         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 763         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 764         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 765         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 766         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 767         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 768         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 769         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 770         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 771
 772 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 773
 774         PR binutils/21446
 775         * aarch64-dis.c (no_notes: New.
 776         (parse_aarch64_dis_option): Support notes.
 777         (aarch64_decode_insn, print_operands): Likewise.
 778         (print_aarch64_disassembler_options): Document notes.
 779         * aarch64-opc.c (aarch64_print_operand): Support notes.
 780
 781 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 782
 783         PR binutils/21446
 784         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 785         and take error struct.
 786         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 787         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 788         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 789         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 790         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 791         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 792         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 793         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 794         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 795         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 796         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 797         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 798         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 799         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 800         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 801         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 802         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 803         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 804         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 805         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 806         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 807         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 808         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 809         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 810         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 811         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 812         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 813         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 814         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 815         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 816         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 817         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 818         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 819         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 820         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 821         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 822         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 823         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 824         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 825         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 826         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 827         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 828         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 829         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 830         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 831         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 832         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 833         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 834         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 835         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 836         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 837         (determine_disassembling_preference, aarch64_decode_insn,
 838         print_insn_aarch64_word, print_insn_data): Take errors struct.
 839         (print_insn_aarch64): Use errors.
 840         * aarch64-asm-2.c: Regenerate.
 841         * aarch64-dis-2.c: Regenerate.
 842         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 843         boolean in aarch64_insert_operan.
 844         (print_operand_extractor): Likewise.
 845         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 846
 847 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 848
 849         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 850
 851 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 852
 853         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 854
 855 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 856
 857         * cr16-opc.c (cr16_instruction): Comment typo fix.
 858         * hppa-dis.c (print_insn_hppa): Likewise.
 859
 860 2018-05-08  Jim Wilson  <jimw@sifive.com>
 861
 862         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 863         (match_c_slli64, match_srxi_as_c_srxi): New.
 864         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 865         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 866         <c.slli, c.srli, c.srai>: Use match_s_slli.
 867         <c.slli64, c.srli64, c.srai64>: New.
 868
 869 2018-05-08  Alan Modra  <amodra@gmail.com>
 870
 871         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 872         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 873         partition opcode space for index lookup.
 874
 875 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 876
 877         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 878         <insn_length>: ...with this.  Update usage.
 879         Remove duplicate call to *info->memory_error_func.
 880
 881 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 882             H.J. Lu  <hongjiu.lu@intel.com>
 883
 884         * i386-dis.c (Gva): New.
 885         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 886         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 887         (prefix_table): New instructions (see prefix above).
 888         (mod_table): New instructions (see prefix above).
 889         (OP_G): Handle va_mode.
 890         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 891         CPU_MOVDIR64B_FLAGS.
 892         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 893         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 894         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 895         * i386-opc.tbl: Add movidir{i,64b}.
 896         * i386-init.h: Regenerated.
 897         * i386-tbl.h: Likewise.
 898
 899 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 900
 901         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 902         AddrPrefixOpReg.
 903         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 904         (AddrPrefixOpReg): This.
 905         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 906         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 907
 908 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 909
 910         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 911         (vle_num_opcodes): Likewise.
 912         (spe2_num_opcodes): Likewise.
 913         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 914         initialization loop.
 915         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 916         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 917         only once.
 918
 919 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 920
 921         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 922
 923 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 924
 925         Makefile.am: Added nfp-dis.c.
 926         configure.ac: Added bfd_nfp_arch.
 927         disassemble.h: Added print_insn_nfp prototype.
 928         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 929         nfp-dis.c: New, for NFP support.
 930         po/POTFILES.in: Added nfp-dis.c to the list.
 931         Makefile.in: Regenerate.
 932         configure: Regenerate.
 933
 934 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 937         templates into their base ones.
 938         * i386-tlb.h: Re-generate.
 939
 940 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 941
 942         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 943         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 944         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 945         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 946         * i386-init.h: Re-generate.
 947
 948 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 949
 950         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 951         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 952         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 953         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 954         comment.
 955         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 956         and CpuRegMask.
 957         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 958         CpuRegMask: Delete.
 959         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 960         cpuregzmm, and cpuregmask.
 961         * i386-init.h: Re-generate.
 962         * i386-tbl.h: Re-generate.
 963
 964 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 965
 966         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 967         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 968         * i386-init.h: Re-generate.
 969
 970 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-gen.c (VexImmExt): Delete.
 973         * i386-opc.h (VexImmExt, veximmext): Delete.
 974         * i386-opc.tbl: Drop all VexImmExt uses.
 975         * i386-tlb.h: Re-generate.
 976
 977 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 978
 979         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 980         register-only forms.
 981         * i386-tlb.h: Re-generate.
 982
 983 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 984
 985         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 986
 987 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 988
 989         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 990         PREFIX_0F1C.
 991         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 992         (cpu_flags): Add CpuCLDEMOTE.
 993         * i386-init.h: Regenerate.
 994         * i386-opc.h (enum): Add CpuCLDEMOTE,
 995         (i386_cpu_flags): Add cpucldemote.
 996         * i386-opc.tbl: Add cldemote.
 997         * i386-tbl.h: Regenerate.
 998
 999 2018-04-16  Alan Modra  <amodra@gmail.com>
1000
1001         * Makefile.am: Remove sh5 and sh64 support.
1002         * configure.ac: Likewise.
1003         * disassemble.c: Likewise.
1004         * disassemble.h: Likewise.
1005         * sh-dis.c: Likewise.
1006         * sh64-dis.c: Delete.
1007         * sh64-opc.c: Delete.
1008         * sh64-opc.h: Delete.
1009         * Makefile.in: Regenerate.
1010         * configure: Regenerate.
1011         * po/POTFILES.in: Regenerate.
1012
1013 2018-04-16  Alan Modra  <amodra@gmail.com>
1014
1015         * Makefile.am: Remove w65 support.
1016         * configure.ac: Likewise.
1017         * disassemble.c: Likewise.
1018         * disassemble.h: Likewise.
1019         * w65-dis.c: Delete.
1020         * w65-opc.h: Delete.
1021         * Makefile.in: Regenerate.
1022         * configure: Regenerate.
1023         * po/POTFILES.in: Regenerate.
1024
1025 2018-04-16  Alan Modra  <amodra@gmail.com>
1026
1027         * configure.ac: Remove we32k support.
1028         * configure: Regenerate.
1029
1030 2018-04-16  Alan Modra  <amodra@gmail.com>
1031
1032         * Makefile.am: Remove m88k support.
1033         * configure.ac: Likewise.
1034         * disassemble.c: Likewise.
1035         * disassemble.h: Likewise.
1036         * m88k-dis.c: Delete.
1037         * Makefile.in: Regenerate.
1038         * configure: Regenerate.
1039         * po/POTFILES.in: Regenerate.
1040
1041 2018-04-16  Alan Modra  <amodra@gmail.com>
1042
1043         * Makefile.am: Remove i370 support.
1044         * configure.ac: Likewise.
1045         * disassemble.c: Likewise.
1046         * disassemble.h: Likewise.
1047         * i370-dis.c: Delete.
1048         * i370-opc.c: Delete.
1049         * Makefile.in: Regenerate.
1050         * configure: Regenerate.
1051         * po/POTFILES.in: Regenerate.
1052
1053 2018-04-16  Alan Modra  <amodra@gmail.com>
1054
1055         * Makefile.am: Remove h8500 support.
1056         * configure.ac: Likewise.
1057         * disassemble.c: Likewise.
1058         * disassemble.h: Likewise.
1059         * h8500-dis.c: Delete.
1060         * h8500-opc.h: Delete.
1061         * Makefile.in: Regenerate.
1062         * configure: Regenerate.
1063         * po/POTFILES.in: Regenerate.
1064
1065 2018-04-16  Alan Modra  <amodra@gmail.com>
1066
1067         * configure.ac: Remove tahoe support.
1068         * configure: Regenerate.
1069
1070 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1071
1072         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1073         umwait.
1074         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1075         64-bit mode.
1076         * i386-tbl.h: Regenerated.
1077
1078 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1079
1080         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1081         PREFIX_MOD_1_0FAE_REG_6.
1082         (va_mode): New.
1083         (OP_E_register): Use va_mode.
1084         * i386-dis-evex.h (prefix_table):
1085         New instructions (see prefixes above).
1086         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1087         (cpu_flags): Likewise.
1088         * i386-opc.h (enum): Likewise.
1089         (i386_cpu_flags): Likewise.
1090         * i386-opc.tbl: Add umonitor, umwait, tpause.
1091         * i386-init.h: Regenerate.
1092         * i386-tbl.h: Likewise.
1093
1094 2018-04-11  Alan Modra  <amodra@gmail.com>
1095
1096         * opcodes/i860-dis.c: Delete.
1097         * opcodes/i960-dis.c: Delete.
1098         * Makefile.am: Remove i860 and i960 support.
1099         * configure.ac: Likewise.
1100         * disassemble.c: Likewise.
1101         * disassemble.h: Likewise.
1102         * Makefile.in: Regenerate.
1103         * configure: Regenerate.
1104         * po/POTFILES.in: Regenerate.
1105
1106 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1107
1108         PR binutils/23025
1109         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1110         to 0.
1111         (print_insn): Clear vex instead of vex.evex.
1112
1113 2018-04-04  Nick Clifton  <nickc@redhat.com>
1114
1115         * po/es.po: Updated Spanish translation.
1116
1117 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1118
1119         * i386-gen.c (opcode_modifiers): Delete VecESize.
1120         * i386-opc.h (VecESize): Delete.
1121         (struct i386_opcode_modifier): Delete vecesize.
1122         * i386-opc.tbl: Drop VecESize.
1123         * i386-tlb.h: Re-generate.
1124
1125 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1126
1127         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1128         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1129         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1130         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1131         * i386-tlb.h: Re-generate.
1132
1133 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1134
1135         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1136         Fold AVX512 forms
1137         * i386-tlb.h: Re-generate.
1138
1139 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1140
1141         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1142         (vex_len_table): Drop Y for vcvt*2si.
1143         (putop): Replace plain 'Y' handling by abort().
1144
1145 2018-03-28  Nick Clifton  <nickc@redhat.com>
1146
1147         PR 22988
1148         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1149         instructions with only a base address register.
1150         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1151         handle AARHC64_OPND_SVE_ADDR_R.
1152         (aarch64_print_operand): Likewise.
1153         * aarch64-asm-2.c: Regenerate.
1154         * aarch64_dis-2.c: Regenerate.
1155         * aarch64-opc-2.c: Regenerate.
1156
1157 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1158
1159         * i386-opc.tbl: Drop VecESize from register only insn forms and
1160         memory forms not allowing broadcast.
1161         * i386-tlb.h: Re-generate.
1162
1163 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1164
1165         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1166         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1167         sha256*): Drop Disp<N>.
1168
1169 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1170
1171         * i386-dis.c (EbndS, bnd_swap_mode): New.
1172         (prefix_table): Use EbndS.
1173         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1174         * i386-opc.tbl (bndmov): Move misplaced Load.
1175         * i386-tlb.h: Re-generate.
1176
1177 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1178
1179         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1180         templates allowing memory operands and folded ones for register
1181         only flavors.
1182         * i386-tlb.h: Re-generate.
1183
1184 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1185
1186         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1187         256-bit templates. Drop redundant leftover Disp<N>.
1188         * i386-tlb.h: Re-generate.
1189
1190 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1191
1192         * riscv-opc.c (riscv_insn_types): New.
1193
1194 2018-03-13  Nick Clifton  <nickc@redhat.com>
1195
1196         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1197
1198 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1199
1200         * i386-opc.tbl: Add Optimize to clr.
1201         * i386-tbl.h: Regenerated.
1202
1203 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1204
1205         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1206         * i386-opc.h (OldGcc): Removed.
1207         (i386_opcode_modifier): Remove oldgcc.
1208         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1209         instructions for old (<= 2.8.1) versions of gcc.
1210         * i386-tbl.h: Regenerated.
1211
1212 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1213
1214         * i386-opc.h (EVEXDYN): New.
1215         * i386-opc.tbl: Fold various AVX512VL templates.
1216         * i386-tlb.h: Re-generate.
1217
1218 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1219
1220         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1221         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1222         vpexpandd, vpexpandq): Fold AFX512VF templates.
1223         * i386-tlb.h: Re-generate.
1224
1225 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1226
1227         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1228         Fold 128- and 256-bit VEX-encoded templates.
1229         * i386-tlb.h: Re-generate.
1230
1231 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1232
1233         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1234         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1235         vpexpandd, vpexpandq): Fold AVX512F templates.
1236         * i386-tlb.h: Re-generate.
1237
1238 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1239
1240         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1241         64-bit templates. Drop Disp<N>.
1242         * i386-tlb.h: Re-generate.
1243
1244 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1245
1246         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1247         and 256-bit templates.
1248         * i386-tlb.h: Re-generate.
1249
1250 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1251
1252         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1253         * i386-tlb.h: Re-generate.
1254
1255 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1256
1257         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1258         Drop NoAVX.
1259         * i386-tlb.h: Re-generate.
1260
1261 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1262
1263         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1264         * i386-tlb.h: Re-generate.
1265
1266 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1267
1268         * i386-gen.c (opcode_modifiers): Delete FloatD.
1269         * i386-opc.h (FloatD): Delete.
1270         (struct i386_opcode_modifier): Delete floatd.
1271         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1272         FloatD by D.
1273         * i386-tlb.h: Re-generate.
1274
1275 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1276
1277         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1278
1279 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1280
1281         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1282         * i386-tlb.h: Re-generate.
1283
1284 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1285
1286         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1287         forms.
1288         * i386-tlb.h: Re-generate.
1289
1290 2018-03-07  Alan Modra  <amodra@gmail.com>
1291
1292         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1293         bfd_arch_rs6000.
1294         * disassemble.h (print_insn_rs6000): Delete.
1295         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1296         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1297         (print_insn_rs6000): Delete.
1298
1299 2018-03-03  Alan Modra  <amodra@gmail.com>
1300
1301         * sysdep.h (opcodes_error_handler): Define.
1302         (_bfd_error_handler): Declare.
1303         * Makefile.am: Remove stray #.
1304         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1305         EDIT" comment.
1306         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1307         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1308         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1309         opcodes_error_handler to print errors.  Standardize error messages.
1310         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1311         and include opintl.h.
1312         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1313         * i386-gen.c: Standardize error messages.
1314         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1315         * Makefile.in: Regenerate.
1316         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1317         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1318         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1319         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1320         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1321         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1322         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1323         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1324         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1325         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1326         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1327         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1328         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1329
1330 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1331
1332         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1333         vpsub[bwdq] instructions.
1334         * i386-tbl.h: Regenerated.
1335
1336 2018-03-01  Alan Modra  <amodra@gmail.com>
1337
1338         * configure.ac (ALL_LINGUAS): Sort.
1339         * configure: Regenerate.
1340
1341 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1342
1343         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1344         macro by assignements.
1345
1346 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1347
1348         PR gas/22871
1349         * i386-gen.c (opcode_modifiers): Add Optimize.
1350         * i386-opc.h (Optimize): New enum.
1351         (i386_opcode_modifier): Add optimize.
1352         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1353         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1354         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1355         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1356         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1357         vpxord and vpxorq.
1358         * i386-tbl.h: Regenerated.
1359
1360 2018-02-26  Alan Modra  <amodra@gmail.com>
1361
1362         * crx-dis.c (getregliststring): Allocate a large enough buffer
1363         to silence false positive gcc8 warning.
1364
1365 2018-02-22  Shea Levy <shea@shealevy.com>
1366
1367         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1368
1369 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1370
1371         * i386-opc.tbl: Add {rex},
1372         * i386-tbl.h: Regenerated.
1373
1374 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1375
1376         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1377         (mips16_opcodes): Replace `M' with `m' for "restore".
1378
1379 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1380
1381         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1382
1383 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1384
1385         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1386         variable to `function_index'.
1387
1388 2018-02-13  Nick Clifton  <nickc@redhat.com>
1389
1390         PR 22823
1391         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1392         about truncation of printing.
1393
1394 2018-02-12  Henry Wong <henry@stuffedcow.net>
1395
1396         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1397
1398 2018-02-05  Nick Clifton  <nickc@redhat.com>
1399
1400         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1401
1402 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1403
1404         * i386-dis.c (enum): Add pconfig.
1405         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1406         (cpu_flags): Add CpuPCONFIG.
1407         * i386-opc.h (enum): Add CpuPCONFIG.
1408         (i386_cpu_flags): Add cpupconfig.
1409         * i386-opc.tbl: Add PCONFIG instruction.
1410         * i386-init.h: Regenerate.
1411         * i386-tbl.h: Likewise.
1412
1413 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1414
1415         * i386-dis.c (enum): Add PREFIX_0F09.
1416         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1417         (cpu_flags): Add CpuWBNOINVD.
1418         * i386-opc.h (enum): Add CpuWBNOINVD.
1419         (i386_cpu_flags): Add cpuwbnoinvd.
1420         * i386-opc.tbl: Add WBNOINVD instruction.
1421         * i386-init.h: Regenerate.
1422         * i386-tbl.h: Likewise.
1423
1424 2018-01-17  Jim Wilson  <jimw@sifive.com>
1425
1426         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1427
1428 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1429
1430         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1431         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1432         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1433         (cpu_flags): Add CpuIBT, CpuSHSTK.
1434         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1435         (i386_cpu_flags): Add cpuibt, cpushstk.
1436         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1437         * i386-init.h: Regenerate.
1438         * i386-tbl.h: Likewise.
1439
1440 2018-01-16  Nick Clifton  <nickc@redhat.com>
1441
1442         * po/pt_BR.po: Updated Brazilian Portugese translation.
1443         * po/de.po: Updated German translation.
1444
1445 2018-01-15  Jim Wilson  <jimw@sifive.com>
1446
1447         * riscv-opc.c (match_c_nop): New.
1448         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1449
1450 2018-01-15  Nick Clifton  <nickc@redhat.com>
1451
1452         * po/uk.po: Updated Ukranian translation.
1453
1454 2018-01-13  Nick Clifton  <nickc@redhat.com>
1455
1456         * po/opcodes.pot: Regenerated.
1457
1458 2018-01-13  Nick Clifton  <nickc@redhat.com>
1459
1460         * configure: Regenerate.
1461
1462 2018-01-13  Nick Clifton  <nickc@redhat.com>
1463
1464         2.30 branch created.
1465
1466 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1467
1468         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1469         * i386-tbl.h: Regenerate.
1470
1471 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1472
1473         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1474         * i386-tbl.h: Re-generate.
1475
1476 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1477
1478         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1479         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1480         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1481         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1482         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1483         Disp8MemShift of AVX512VL forms.
1484         * i386-tbl.h: Re-generate.
1485
1486 2018-01-09  Jim Wilson  <jimw@sifive.com>
1487
1488         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1489         then the hi_addr value is zero.
1490
1491 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1492
1493         * arm-dis.c (arm_opcodes): Add csdb.
1494         (thumb32_opcodes): Add csdb.
1495
1496 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1497
1498         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1499         * aarch64-asm-2.c: Regenerate.
1500         * aarch64-dis-2.c: Regenerate.
1501         * aarch64-opc-2.c: Regenerate.
1502
1503 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1504
1505         PR gas/22681
1506         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1507         Remove AVX512 vmovd with 64-bit operands.
1508         * i386-tbl.h: Regenerated.
1509
1510 2018-01-05  Jim Wilson  <jimw@sifive.com>
1511
1512         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1513         jalr.
1514
1515 2018-01-03  Alan Modra  <amodra@gmail.com>
1516
1517         Update year range in copyright notice of all files.
1518
1519 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1520
1521         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1522         and OPERAND_TYPE_REGZMM entries.
1523
1524 For older changes see ChangeLog-2017
1525 \f
1526 Copyright (C) 2018 Free Software Foundation, Inc.
1527
1528 Copying and distribution of this file, with or without modification,
1529 are permitted in any medium without royalty provided the copyright
1530 notice and this notice are preserved.
1531
1532 Local Variables:
1533 mode: change-log
1534 left-margin: 8
1535 fill-column: 74
1536 version-control: never
1537 End: