opcodes/ChangeLog

   1 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (rm_table): Add enclv.
   4         * i386-opc.tbl: Add enclv.
   5         * i386-tbl.h: Regenerated.
   6
   7 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
   8
   9         * arm-dis.c (arm_opcodes): Add sb.
  10         (thumb32_opcodes): Likewise.
  11
  12 2018-10-05  Richard Henderson  <rth@twiddle.net>
  13             Stafford Horne  <shorne@gmail.com>
  14
  15         * or1k-desc.c: Regenerate.
  16         * or1k-desc.h: Regenerate.
  17         * or1k-opc.c: Regenerate.
  18         * or1k-opc.h: Regenerate.
  19         * or1k-opinst.c: Regenerate.
  20
  21 2018-10-05  Richard Henderson  <rth@twiddle.net>
  22
  23         * or1k-asm.c: Regenerated.
  24         * or1k-desc.c: Regenerated.
  25         * or1k-desc.h: Regenerated.
  26         * or1k-dis.c: Regenerated.
  27         * or1k-ibld.c: Regenerated.
  28         * or1k-opc.c: Regenerated.
  29         * or1k-opc.h: Regenerated.
  30         * or1k-opinst.c: Regenerated.
  31
  32 2018-10-05  Richard Henderson  <rth@twiddle.net>
  33
  34         * or1k-asm.c: Regenerate.
  35
  36 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  37
  38         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
  39         * aarch64-dis.c (print_operands): Refactor to take notes.
  40         (print_verifier_notes): New.
  41         (print_aarch64_insn): Apply constraint verifier.
  42         (print_insn_aarch64_word): Update call to print_aarch64_insn.
  43         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
  44
  45 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  46
  47         * aarch64-opc.c (init_insn_block): New.
  48         (verify_constraints, aarch64_is_destructive_by_operands): New.
  49         * aarch64-opc.h (verify_constraints): New.
  50
  51 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  52
  53         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
  54         * aarch64-opc.c (verify_ldpsw): Update arguments.
  55
  56 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  57
  58         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
  59         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
  60
  61 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  62
  63         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
  64         * aarch64-dis.c (insn_sequence): New.
  65
  66 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  67
  68         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
  69         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
  70         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
  71         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
  72         constraints.
  73         (_SVE_INSNC): New.
  74         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
  75         constraints.
  76         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
  77         F_SCAN flags.
  78         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
  79         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
  80         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
  81         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
  82         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
  83         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
  84         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
  85
  86 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
  87
  88         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
  89
  90 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
  91
  92         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
  93         are used when extracting signed fields and converting them to
  94         potentially 64-bit types.
  95
  96 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
  97
  98         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
  99         * Makefile.in: Re-generate.
 100         * aclocal.m4: Re-generate.
 101         * configure: Re-generate.
 102         * configure.ac: Remove check for -Wno-missing-field-initializers.
 103         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 104         (csky_v2_opcodes): Likewise.
 105
 106 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 107
 108         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 109
 110 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 111
 112         * nds32-asm.c (operand_fields): Remove the unused fields.
 113         (nds32_opcodes): Remove the unused instructions.
 114         * nds32-dis.c (nds32_ex9_info): Removed.
 115         (nds32_parse_opcode): Updated.
 116         (print_insn_nds32): Likewise.
 117         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 118         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 119         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 120         build_opcode_hash_table): New functions.
 121         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 122         nds32_opcode_table): New.
 123         (hw_ktabs): Declare it to a pointer rather than an array.
 124         (build_hash_table): Removed.
 125         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 126         SYN_ROPT and upadte HW_GPR and HW_INT.
 127         * nds32-dis.c (keywords): Remove const.
 128         (match_field): New function.
 129         (nds32_parse_opcode): Updated.
 130         * disassemble.c (disassemble_init_for_target):
 131         Add disassemble_init_nds32.
 132         * nds32-dis.c (eum map_type): New.
 133         (nds32_private_data): Likewise.
 134         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 135         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 136         (print_insn_nds32): Updated.
 137         * nds32-asm.c (parse_aext_reg): Add new parameter.
 138         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 139         are allowed to use.
 140         All callers changed.
 141         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 142         (operand_fields): Add new fields.
 143         (nds32_opcodes): Add new instructions.
 144         (keyword_aridxi_mx): New keyword.
 145         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 146         and NASM_ATTR_ZOL.
 147         (ALU2_1, ALU2_2, ALU2_3): New macros.
 148         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 149
 150 2018-09-17  Kito Cheng  <kito@andestech.com>
 151
 152         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 153
 154 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         PR gas/23670
 157         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 158         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 159         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 160         (EVEX_LEN_0F7E_P_1): Likewise.
 161         (EVEX_LEN_0F7E_P_2): Likewise.
 162         (EVEX_LEN_0FD6_P_2): Likewise.
 163         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 164         (EVEX_LEN_TABLE): Likewise.
 165         (EVEX_LEN_0F6E_P_2): New enum.
 166         (EVEX_LEN_0F7E_P_1): Likewise.
 167         (EVEX_LEN_0F7E_P_2): Likewise.
 168         (EVEX_LEN_0FD6_P_2): Likewise.
 169         (evex_len_table): New.
 170         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 171         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 172         * i386-tbl.h: Regenerated.
 173
 174 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 175
 176         PR gas/23665
 177         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 178         VEX_LEN_0F7E_P_2 entries.
 179         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 180         * i386-tbl.h: Regenerated.
 181
 182 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 183
 184         * i386-dis.c (VZERO_Fixup): Removed.
 185         (VZERO): Likewise.
 186         (VEX_LEN_0F10_P_1): Likewise.
 187         (VEX_LEN_0F10_P_3): Likewise.
 188         (VEX_LEN_0F11_P_1): Likewise.
 189         (VEX_LEN_0F11_P_3): Likewise.
 190         (VEX_LEN_0F2E_P_0): Likewise.
 191         (VEX_LEN_0F2E_P_2): Likewise.
 192         (VEX_LEN_0F2F_P_0): Likewise.
 193         (VEX_LEN_0F2F_P_2): Likewise.
 194         (VEX_LEN_0F51_P_1): Likewise.
 195         (VEX_LEN_0F51_P_3): Likewise.
 196         (VEX_LEN_0F52_P_1): Likewise.
 197         (VEX_LEN_0F53_P_1): Likewise.
 198         (VEX_LEN_0F58_P_1): Likewise.
 199         (VEX_LEN_0F58_P_3): Likewise.
 200         (VEX_LEN_0F59_P_1): Likewise.
 201         (VEX_LEN_0F59_P_3): Likewise.
 202         (VEX_LEN_0F5A_P_1): Likewise.
 203         (VEX_LEN_0F5A_P_3): Likewise.
 204         (VEX_LEN_0F5C_P_1): Likewise.
 205         (VEX_LEN_0F5C_P_3): Likewise.
 206         (VEX_LEN_0F5D_P_1): Likewise.
 207         (VEX_LEN_0F5D_P_3): Likewise.
 208         (VEX_LEN_0F5E_P_1): Likewise.
 209         (VEX_LEN_0F5E_P_3): Likewise.
 210         (VEX_LEN_0F5F_P_1): Likewise.
 211         (VEX_LEN_0F5F_P_3): Likewise.
 212         (VEX_LEN_0FC2_P_1): Likewise.
 213         (VEX_LEN_0FC2_P_3): Likewise.
 214         (VEX_LEN_0F3A0A_P_2): Likewise.
 215         (VEX_LEN_0F3A0B_P_2): Likewise.
 216         (VEX_W_0F10_P_0): Likewise.
 217         (VEX_W_0F10_P_1): Likewise.
 218         (VEX_W_0F10_P_2): Likewise.
 219         (VEX_W_0F10_P_3): Likewise.
 220         (VEX_W_0F11_P_0): Likewise.
 221         (VEX_W_0F11_P_1): Likewise.
 222         (VEX_W_0F11_P_2): Likewise.
 223         (VEX_W_0F11_P_3): Likewise.
 224         (VEX_W_0F12_P_0_M_0): Likewise.
 225         (VEX_W_0F12_P_0_M_1): Likewise.
 226         (VEX_W_0F12_P_1): Likewise.
 227         (VEX_W_0F12_P_2): Likewise.
 228         (VEX_W_0F12_P_3): Likewise.
 229         (VEX_W_0F13_M_0): Likewise.
 230         (VEX_W_0F14): Likewise.
 231         (VEX_W_0F15): Likewise.
 232         (VEX_W_0F16_P_0_M_0): Likewise.
 233         (VEX_W_0F16_P_0_M_1): Likewise.
 234         (VEX_W_0F16_P_1): Likewise.
 235         (VEX_W_0F16_P_2): Likewise.
 236         (VEX_W_0F17_M_0): Likewise.
 237         (VEX_W_0F28): Likewise.
 238         (VEX_W_0F29): Likewise.
 239         (VEX_W_0F2B_M_0): Likewise.
 240         (VEX_W_0F2E_P_0): Likewise.
 241         (VEX_W_0F2E_P_2): Likewise.
 242         (VEX_W_0F2F_P_0): Likewise.
 243         (VEX_W_0F2F_P_2): Likewise.
 244         (VEX_W_0F50_M_0): Likewise.
 245         (VEX_W_0F51_P_0): Likewise.
 246         (VEX_W_0F51_P_1): Likewise.
 247         (VEX_W_0F51_P_2): Likewise.
 248         (VEX_W_0F51_P_3): Likewise.
 249         (VEX_W_0F52_P_0): Likewise.
 250         (VEX_W_0F52_P_1): Likewise.
 251         (VEX_W_0F53_P_0): Likewise.
 252         (VEX_W_0F53_P_1): Likewise.
 253         (VEX_W_0F58_P_0): Likewise.
 254         (VEX_W_0F58_P_1): Likewise.
 255         (VEX_W_0F58_P_2): Likewise.
 256         (VEX_W_0F58_P_3): Likewise.
 257         (VEX_W_0F59_P_0): Likewise.
 258         (VEX_W_0F59_P_1): Likewise.
 259         (VEX_W_0F59_P_2): Likewise.
 260         (VEX_W_0F59_P_3): Likewise.
 261         (VEX_W_0F5A_P_0): Likewise.
 262         (VEX_W_0F5A_P_1): Likewise.
 263         (VEX_W_0F5A_P_3): Likewise.
 264         (VEX_W_0F5B_P_0): Likewise.
 265         (VEX_W_0F5B_P_1): Likewise.
 266         (VEX_W_0F5B_P_2): Likewise.
 267         (VEX_W_0F5C_P_0): Likewise.
 268         (VEX_W_0F5C_P_1): Likewise.
 269         (VEX_W_0F5C_P_2): Likewise.
 270         (VEX_W_0F5C_P_3): Likewise.
 271         (VEX_W_0F5D_P_0): Likewise.
 272         (VEX_W_0F5D_P_1): Likewise.
 273         (VEX_W_0F5D_P_2): Likewise.
 274         (VEX_W_0F5D_P_3): Likewise.
 275         (VEX_W_0F5E_P_0): Likewise.
 276         (VEX_W_0F5E_P_1): Likewise.
 277         (VEX_W_0F5E_P_2): Likewise.
 278         (VEX_W_0F5E_P_3): Likewise.
 279         (VEX_W_0F5F_P_0): Likewise.
 280         (VEX_W_0F5F_P_1): Likewise.
 281         (VEX_W_0F5F_P_2): Likewise.
 282         (VEX_W_0F5F_P_3): Likewise.
 283         (VEX_W_0F60_P_2): Likewise.
 284         (VEX_W_0F61_P_2): Likewise.
 285         (VEX_W_0F62_P_2): Likewise.
 286         (VEX_W_0F63_P_2): Likewise.
 287         (VEX_W_0F64_P_2): Likewise.
 288         (VEX_W_0F65_P_2): Likewise.
 289         (VEX_W_0F66_P_2): Likewise.
 290         (VEX_W_0F67_P_2): Likewise.
 291         (VEX_W_0F68_P_2): Likewise.
 292         (VEX_W_0F69_P_2): Likewise.
 293         (VEX_W_0F6A_P_2): Likewise.
 294         (VEX_W_0F6B_P_2): Likewise.
 295         (VEX_W_0F6C_P_2): Likewise.
 296         (VEX_W_0F6D_P_2): Likewise.
 297         (VEX_W_0F6F_P_1): Likewise.
 298         (VEX_W_0F6F_P_2): Likewise.
 299         (VEX_W_0F70_P_1): Likewise.
 300         (VEX_W_0F70_P_2): Likewise.
 301         (VEX_W_0F70_P_3): Likewise.
 302         (VEX_W_0F71_R_2_P_2): Likewise.
 303         (VEX_W_0F71_R_4_P_2): Likewise.
 304         (VEX_W_0F71_R_6_P_2): Likewise.
 305         (VEX_W_0F72_R_2_P_2): Likewise.
 306         (VEX_W_0F72_R_4_P_2): Likewise.
 307         (VEX_W_0F72_R_6_P_2): Likewise.
 308         (VEX_W_0F73_R_2_P_2): Likewise.
 309         (VEX_W_0F73_R_3_P_2): Likewise.
 310         (VEX_W_0F73_R_6_P_2): Likewise.
 311         (VEX_W_0F73_R_7_P_2): Likewise.
 312         (VEX_W_0F74_P_2): Likewise.
 313         (VEX_W_0F75_P_2): Likewise.
 314         (VEX_W_0F76_P_2): Likewise.
 315         (VEX_W_0F77_P_0): Likewise.
 316         (VEX_W_0F7C_P_2): Likewise.
 317         (VEX_W_0F7C_P_3): Likewise.
 318         (VEX_W_0F7D_P_2): Likewise.
 319         (VEX_W_0F7D_P_3): Likewise.
 320         (VEX_W_0F7E_P_1): Likewise.
 321         (VEX_W_0F7F_P_1): Likewise.
 322         (VEX_W_0F7F_P_2): Likewise.
 323         (VEX_W_0FAE_R_2_M_0): Likewise.
 324         (VEX_W_0FAE_R_3_M_0): Likewise.
 325         (VEX_W_0FC2_P_0): Likewise.
 326         (VEX_W_0FC2_P_1): Likewise.
 327         (VEX_W_0FC2_P_2): Likewise.
 328         (VEX_W_0FC2_P_3): Likewise.
 329         (VEX_W_0FD0_P_2): Likewise.
 330         (VEX_W_0FD0_P_3): Likewise.
 331         (VEX_W_0FD1_P_2): Likewise.
 332         (VEX_W_0FD2_P_2): Likewise.
 333         (VEX_W_0FD3_P_2): Likewise.
 334         (VEX_W_0FD4_P_2): Likewise.
 335         (VEX_W_0FD5_P_2): Likewise.
 336         (VEX_W_0FD6_P_2): Likewise.
 337         (VEX_W_0FD7_P_2_M_1): Likewise.
 338         (VEX_W_0FD8_P_2): Likewise.
 339         (VEX_W_0FD9_P_2): Likewise.
 340         (VEX_W_0FDA_P_2): Likewise.
 341         (VEX_W_0FDB_P_2): Likewise.
 342         (VEX_W_0FDC_P_2): Likewise.
 343         (VEX_W_0FDD_P_2): Likewise.
 344         (VEX_W_0FDE_P_2): Likewise.
 345         (VEX_W_0FDF_P_2): Likewise.
 346         (VEX_W_0FE0_P_2): Likewise.
 347         (VEX_W_0FE1_P_2): Likewise.
 348         (VEX_W_0FE2_P_2): Likewise.
 349         (VEX_W_0FE3_P_2): Likewise.
 350         (VEX_W_0FE4_P_2): Likewise.
 351         (VEX_W_0FE5_P_2): Likewise.
 352         (VEX_W_0FE6_P_1): Likewise.
 353         (VEX_W_0FE6_P_2): Likewise.
 354         (VEX_W_0FE6_P_3): Likewise.
 355         (VEX_W_0FE7_P_2_M_0): Likewise.
 356         (VEX_W_0FE8_P_2): Likewise.
 357         (VEX_W_0FE9_P_2): Likewise.
 358         (VEX_W_0FEA_P_2): Likewise.
 359         (VEX_W_0FEB_P_2): Likewise.
 360         (VEX_W_0FEC_P_2): Likewise.
 361         (VEX_W_0FED_P_2): Likewise.
 362         (VEX_W_0FEE_P_2): Likewise.
 363         (VEX_W_0FEF_P_2): Likewise.
 364         (VEX_W_0FF0_P_3_M_0): Likewise.
 365         (VEX_W_0FF1_P_2): Likewise.
 366         (VEX_W_0FF2_P_2): Likewise.
 367         (VEX_W_0FF3_P_2): Likewise.
 368         (VEX_W_0FF4_P_2): Likewise.
 369         (VEX_W_0FF5_P_2): Likewise.
 370         (VEX_W_0FF6_P_2): Likewise.
 371         (VEX_W_0FF7_P_2): Likewise.
 372         (VEX_W_0FF8_P_2): Likewise.
 373         (VEX_W_0FF9_P_2): Likewise.
 374         (VEX_W_0FFA_P_2): Likewise.
 375         (VEX_W_0FFB_P_2): Likewise.
 376         (VEX_W_0FFC_P_2): Likewise.
 377         (VEX_W_0FFD_P_2): Likewise.
 378         (VEX_W_0FFE_P_2): Likewise.
 379         (VEX_W_0F3800_P_2): Likewise.
 380         (VEX_W_0F3801_P_2): Likewise.
 381         (VEX_W_0F3802_P_2): Likewise.
 382         (VEX_W_0F3803_P_2): Likewise.
 383         (VEX_W_0F3804_P_2): Likewise.
 384         (VEX_W_0F3805_P_2): Likewise.
 385         (VEX_W_0F3806_P_2): Likewise.
 386         (VEX_W_0F3807_P_2): Likewise.
 387         (VEX_W_0F3808_P_2): Likewise.
 388         (VEX_W_0F3809_P_2): Likewise.
 389         (VEX_W_0F380A_P_2): Likewise.
 390         (VEX_W_0F380B_P_2): Likewise.
 391         (VEX_W_0F3817_P_2): Likewise.
 392         (VEX_W_0F381C_P_2): Likewise.
 393         (VEX_W_0F381D_P_2): Likewise.
 394         (VEX_W_0F381E_P_2): Likewise.
 395         (VEX_W_0F3820_P_2): Likewise.
 396         (VEX_W_0F3821_P_2): Likewise.
 397         (VEX_W_0F3822_P_2): Likewise.
 398         (VEX_W_0F3823_P_2): Likewise.
 399         (VEX_W_0F3824_P_2): Likewise.
 400         (VEX_W_0F3825_P_2): Likewise.
 401         (VEX_W_0F3828_P_2): Likewise.
 402         (VEX_W_0F3829_P_2): Likewise.
 403         (VEX_W_0F382A_P_2_M_0): Likewise.
 404         (VEX_W_0F382B_P_2): Likewise.
 405         (VEX_W_0F3830_P_2): Likewise.
 406         (VEX_W_0F3831_P_2): Likewise.
 407         (VEX_W_0F3832_P_2): Likewise.
 408         (VEX_W_0F3833_P_2): Likewise.
 409         (VEX_W_0F3834_P_2): Likewise.
 410         (VEX_W_0F3835_P_2): Likewise.
 411         (VEX_W_0F3837_P_2): Likewise.
 412         (VEX_W_0F3838_P_2): Likewise.
 413         (VEX_W_0F3839_P_2): Likewise.
 414         (VEX_W_0F383A_P_2): Likewise.
 415         (VEX_W_0F383B_P_2): Likewise.
 416         (VEX_W_0F383C_P_2): Likewise.
 417         (VEX_W_0F383D_P_2): Likewise.
 418         (VEX_W_0F383E_P_2): Likewise.
 419         (VEX_W_0F383F_P_2): Likewise.
 420         (VEX_W_0F3840_P_2): Likewise.
 421         (VEX_W_0F3841_P_2): Likewise.
 422         (VEX_W_0F38DB_P_2): Likewise.
 423         (VEX_W_0F3A08_P_2): Likewise.
 424         (VEX_W_0F3A09_P_2): Likewise.
 425         (VEX_W_0F3A0A_P_2): Likewise.
 426         (VEX_W_0F3A0B_P_2): Likewise.
 427         (VEX_W_0F3A0C_P_2): Likewise.
 428         (VEX_W_0F3A0D_P_2): Likewise.
 429         (VEX_W_0F3A0E_P_2): Likewise.
 430         (VEX_W_0F3A0F_P_2): Likewise.
 431         (VEX_W_0F3A21_P_2): Likewise.
 432         (VEX_W_0F3A40_P_2): Likewise.
 433         (VEX_W_0F3A41_P_2): Likewise.
 434         (VEX_W_0F3A42_P_2): Likewise.
 435         (VEX_W_0F3A62_P_2): Likewise.
 436         (VEX_W_0F3A63_P_2): Likewise.
 437         (VEX_W_0F3ADF_P_2): Likewise.
 438         (VEX_LEN_0F77_P_0): New.
 439         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 440         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 441         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 442         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 443         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 444         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 445         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 446         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 447         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 448         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 449         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 450         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 451         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 452         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 453         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 454         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 455         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 456         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 457         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 458         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 459         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 460         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 461         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 462         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 463         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 464         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 465         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 466         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 467         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 468         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 469         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 470         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 471         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 472         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 473         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 474         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 475         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 476         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 477         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 478         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 479         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 480         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 481         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 482         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 483         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 484         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 485         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 486         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 487         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 488         (vex_table): Update VEX 0F28 and 0F29 entries.
 489         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 490         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 491         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 492         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 493         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 494         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 495         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 496         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 497         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 498         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 499         VEX_LEN_0F3A0B_P_2 entries.
 500         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 501         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 502         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 503         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 504         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 505         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 506         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 507         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 508         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 509         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 510         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 511         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 512         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 513         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 514         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 515         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 516         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 517         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 518         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 519         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 520         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 521         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 522         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 523         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 524         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 525         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 526         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 527         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 528         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 529         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 530         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 531         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 532         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 533         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 534         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 535         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 536         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 537         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 538         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 539         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 540         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 541         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 542         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 543         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 544         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 545         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 546         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 547         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 548         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 549         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 550         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 551         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 552         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 553         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 554         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 555         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 556         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 557         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 558         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 559         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 560         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 561         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 562         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 563         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 564         VEX_W_0F3ADF_P_2 entries.
 565         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 566         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 567         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 568
 569 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 570
 571         * i386-opc.tbl (VexWIG): New.
 572         Replace VexW=3 with VexWIG.
 573
 574 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 575
 576         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 577         * i386-tbl.h: Regenerated.
 578
 579 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 580
 581         PR gas/23665
 582         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 583         VEX_LEN_0FD6_P_2 entries.
 584         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 585         * i386-tbl.h: Regenerated.
 586
 587 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 588
 589         PR gas/23642
 590         * i386-opc.h (VEXWIG): New.
 591         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 592         * i386-tbl.h: Regenerated.
 593
 594 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         PR binutils/23655
 597         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 598         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 599         * i386-dis.c (EXxEVexR64): New.
 600         (evex_rounding_64_mode): Likewise.
 601         (OP_Rounding): Handle evex_rounding_64_mode.
 602
 603 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 604
 605         PR binutils/23655
 606         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 607         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 608         * i386-dis.c (Edqa): New.
 609         (dqa_mode): Likewise.
 610         (intel_operand_size): Handle dqa_mode as m_mode.
 611         (OP_E_register): Handle dqa_mode as dq_mode.
 612         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 613
 614 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 615
 616         * i386-dis.c (OP_E_memory): Reformat.
 617
 618 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 619
 620         * i386-opc.tbl (crc32): Fold byte and word forms.
 621         * i386-tbl.h: Re-generate.
 622
 623 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 626         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 627         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 628         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 629         * i386-tbl.h: Regenerated.
 630
 631 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 632
 633         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 634         meaningless.
 635         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 636         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 637         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 638         * i386-tbl.h: Re-generate.
 639
 640 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 643         AVX512_4VNNIW insns.
 644         * i386-tbl.h: Re-generate.
 645
 646 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 649         meaningless.
 650         * i386-tbl.h: Re-generate.
 651
 652 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 655         meaningless.
 656         * i386-tbl.h: Re-generate.
 657
 658 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 659
 660         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 661         meaningless.
 662         * i386-tbl.h: Re-generate.
 663
 664 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 665
 666         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 667         meaningless.
 668         * i386-tbl.h: Re-generate.
 669
 670 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 673         meaningless.
 674         * i386-tbl.h: Re-generate.
 675
 676 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 677
 678         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 679         * i386-tbl.h: Re-generate.
 680
 681 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 684         * i386-tbl.h: Re-generate.
 685
 686 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 687
 688         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 689         meaningless.
 690         * i386-tbl.h: Re-generate.
 691
 692 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 695         meaningless.
 696         * i386-tbl.h: Re-generate.
 697
 698 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 699
 700         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 701         * i386-tbl.h: Re-generate.
 702
 703 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 704
 705         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 706         * i386-tbl.h: Re-generate.
 707
 708 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 709
 710         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 711         * i386-tbl.h: Re-generate.
 712
 713 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 714
 715         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 716         meaningless.
 717         * i386-tbl.h: Re-generate.
 718
 719 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 720
 721         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 722         meaningless.
 723         * i386-tbl.h: Re-generate.
 724
 725 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 728         meaningless.
 729         * i386-tbl.h: Re-generate.
 730
 731 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 732
 733         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 734         * i386-tbl.h: Re-generate.
 735
 736 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 739         * i386-tbl.h: Re-generate.
 740
 741 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 742
 743         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 744         * i386-tbl.h: Re-generate.
 745
 746 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 749         (vpbroadcastw, rdpid): Drop NoRex64.
 750         * i386-tbl.h: Re-generate.
 751
 752 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 753
 754         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 755         store templates, adding D.
 756         * i386-tbl.h: Re-generate.
 757
 758 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 761         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 762         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 763         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 764         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 765         Fold load and store templates where possible, adding D. Drop
 766         IgnoreSize where it was pointlessly present. Drop redundant
 767         *word.
 768         * i386-tbl.h: Re-generate.
 769
 770 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 773         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 774         (intel_operand_size): Handle v_bndmk_mode.
 775         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 776
 777 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 778
 779         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 780
 781 2018-08-31  Kito Cheng  <kito@andestech.com>
 782
 783         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 784         compressed floating point instructions.
 785
 786 2018-08-30  Kito Cheng  <kito@andestech.com>
 787
 788         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 789         riscv_opcode.xlen_requirement.
 790         * riscv-opc.c (riscv_opcodes): Update for struct change.
 791
 792 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 793
 794         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 795         psr (PWRPSR) instruction.
 796
 797 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 798
 799         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 800
 801 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 802
 803         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 804
 805 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 806
 807         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 808         loongson3a as an alias of gs464 for compatibility.
 809         * mips-opc.c (mips_opcodes): Change Comments.
 810
 811 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 812
 813         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 814         option.
 815         (print_mips_disassembler_options): Document -M loongson-ext.
 816         * mips-opc.c (LEXT2): New macro.
 817         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 818
 819 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 820
 821          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 822          descriptors.
 823          (parse_mips_ase_option): Handle -M loongson-ext option.
 824          (print_mips_disassembler_options): Document -M loongson-ext.
 825          * mips-opc.c (IL3A): Delete.
 826          * mips-opc.c (LEXT): New macro.
 827          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 828          instructions.
 829
 830 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 831
 832         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 833         descriptors.
 834         (parse_mips_ase_option): Handle -M loongson-cam option.
 835         (print_mips_disassembler_options): Document -M loongson-cam.
 836         * mips-opc.c (LCAM): New macro.
 837         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 838         instructions.
 839
 840 2018-08-21  Alan Modra  <amodra@gmail.com>
 841
 842         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 843         (skip_optional_operands): Count optional operands, and update
 844         ppc_optional_operand_value call.
 845         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 846         (extract_vlensi): Likewise.
 847         (extract_fxm): Return default value for missing optional operand.
 848         (extract_ls, extract_raq, extract_tbr): Likewise.
 849         (insert_sxl, extract_sxl): New functions.
 850         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 851         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 852         flag and extra entry.
 853         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 854         extract_sxl.
 855
 856 2018-08-20  Alan Modra  <amodra@gmail.com>
 857
 858         * sh-opc.h (MASK): Simplify.
 859
 860 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 861
 862         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 863         BM_RESERVED0 or BM_RESERVED1
 864         (bm_rel_decode, bm_n_bytes): Ditto.
 865
 866 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 867
 868         * s12z.h: Delete.
 869
 870 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 873         address with the addr32 prefix and without base nor index
 874         registers.
 875
 876 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 877
 878         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 879         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 880         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 881         (cpu_flags): Add CpuCMOV and CpuFXSR.
 882         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 883         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 884         * i386-init.h: Regenerated.
 885         * i386-tbl.h: Likewise.
 886
 887 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 888
 889         * arc-regs.h: Update auxiliary registers.
 890
 891 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 892
 893         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 894         (RegIP, RegIZ): Define.
 895         * i386-reg.tbl: Adjust comments.
 896         (rip): Use Qword instead of BaseIndex. Use RegIP.
 897         (eip): Use Dword instead of BaseIndex. Use RegIP.
 898         (riz): Add Qword. Use RegIZ.
 899         (eiz): Add Dword. Use RegIZ.
 900         * i386-tbl.h: Re-generate.
 901
 902 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 903
 904         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 905         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 906         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 907         * i386-tbl.h: Re-generate.
 908
 909 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 910
 911         * i386-gen.c (operand_types): Remove Mem field.
 912         * i386-opc.h (union i386_operand_type): Remove mem field.
 913         * i386-init.h, i386-tbl.h: Re-generate.
 914
 915 2018-08-01  Alan Modra  <amodra@gmail.com>
 916
 917         * po/POTFILES.in: Regenerate.
 918
 919 2018-07-31  Nick Clifton  <nickc@redhat.com>
 920
 921         * po/sv.po: Updated Swedish translation.
 922
 923 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 924
 925         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 926         * i386-init.h, i386-tbl.h: Re-generate.
 927
 928 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-opc.h (ZEROING_MASKING) Rename to ...
 931         (DYNAMIC_MASKING): ... this. Adjust comment.
 932         * i386-opc.tbl (MaskingMorZ): Define.
 933         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 934         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 935         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 936         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 937         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 938         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 939         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 940         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 941         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 942
 943 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 944
 945         * i386-opc.tbl: Use element rather than vector size for AVX512*
 946         scatter/gather insns.
 947         * i386-tbl.h: Re-generate.
 948
 949 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 950
 951         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 952         (cpu_flags): Drop CpuVREX.
 953         * i386-opc.h (CpuVREX): Delete.
 954         (union i386_cpu_flags): Remove cpuvrex.
 955         * i386-init.h, i386-tbl.h: Re-generate.
 956
 957 2018-07-30  Jim Wilson  <jimw@sifive.com>
 958
 959         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 960         fields.
 961         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 962
 963 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 964
 965         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 966         * Makefile.in: Regenerated.
 967         * configure.ac: Add C-SKY.
 968         * configure: Regenerated.
 969         * csky-dis.c: New file.
 970         * csky-opc.h: New file.
 971         * disassemble.c (ARCH_csky): Define.
 972         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 973         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 974
 975 2018-07-27  Alan Modra  <amodra@gmail.com>
 976
 977         * ppc-opc.c (insert_sprbat): Correct function parameter and
 978         return type.
 979         (extract_sprbat): Likewise, variable too.
 980
 981 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 982             Alan Modra  <amodra@gmail.com>
 983
 984         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 985         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 986         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 987         support disjointed BAT.
 988         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 989         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 990         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 991
 992 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 993             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 994
 995         * i386-gen.c (adjust_broadcast_modifier): New function.
 996         (process_i386_opcode_modifier): Add an argument for operands.
 997         Adjust the Broadcast value based on operands.
 998         (output_i386_opcode): Pass operand_types to
 999         process_i386_opcode_modifier.
1000         (process_i386_opcodes): Pass NULL as operands to
1001         process_i386_opcode_modifier.
1002         * i386-opc.h (BYTE_BROADCAST): New.
1003         (WORD_BROADCAST): Likewise.
1004         (DWORD_BROADCAST): Likewise.
1005         (QWORD_BROADCAST): Likewise.
1006         (i386_opcode_modifier): Expand broadcast to 3 bits.
1007         * i386-tbl.h: Regenerated.
1008
1009 2018-07-24  Alan Modra  <amodra@gmail.com>
1010
1011         PR 23430
1012         * or1k-desc.h: Regenerate.
1013
1014 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1017         vcvtusi2ss, and vcvtusi2sd.
1018         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1019         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1020         * i386-tbl.h: Re-generate.
1021
1022 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1023
1024         * arc-opc.c (extract_w6): Fix extending the sign.
1025
1026 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1027
1028         * arc-tbl.h (vewt): Allow it for ARC EM family.
1029
1030 2018-07-23  Alan Modra  <amodra@gmail.com>
1031
1032         PR 23419
1033         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1034         opcode variants for mtspr/mfspr encodings.
1035
1036 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1037             Maciej W. Rozycki  <macro@mips.com>
1038
1039         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1040         loongson3a descriptors.
1041         (parse_mips_ase_option): Handle -M loongson-mmi option.
1042         (print_mips_disassembler_options): Document -M loongson-mmi.
1043         * mips-opc.c (LMMI): New macro.
1044         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1045         instructions.
1046
1047 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1048
1049         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1050         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1051         IgnoreSize and [XYZ]MMword where applicable.
1052         * i386-tbl.h: Re-generate.
1053
1054 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1057         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1058         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1059         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1060         * i386-tbl.h: Re-generate.
1061
1062 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1063
1064         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1065         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1066         VPCLMULQDQ templates into their respective AVX512VL counterparts
1067         where possible, using Disp8ShiftVL and CheckRegSize instead of
1068         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1069         * i386-tbl.h: Re-generate.
1070
1071 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1072
1073         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1074         AVX512VL counterparts where possible, using Disp8ShiftVL and
1075         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1076         IgnoreSize) as appropriate.
1077         * i386-tbl.h: Re-generate.
1078
1079 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1080
1081         * i386-opc.tbl: Fold AVX512BW templates into their respective
1082         AVX512VL counterparts where possible, using Disp8ShiftVL and
1083         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1084         IgnoreSize) as appropriate.
1085         * i386-tbl.h: Re-generate.
1086
1087 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1088
1089         * i386-opc.tbl: Fold AVX512CD templates into their respective
1090         AVX512VL counterparts where possible, using Disp8ShiftVL and
1091         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1092         IgnoreSize) as appropriate.
1093         * i386-tbl.h: Re-generate.
1094
1095 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1096
1097         * i386-opc.h (DISP8_SHIFT_VL): New.
1098         * i386-opc.tbl (Disp8ShiftVL):  Define.
1099         (various): Fold AVX512VL templates into their respective
1100         AVX512F counterparts where possible, using Disp8ShiftVL and
1101         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1102         IgnoreSize) as appropriate.
1103         * i386-tbl.h: Re-generate.
1104
1105 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1106
1107         * Makefile.am: Change dependencies and rule for
1108         $(srcdir)/i386-init.h.
1109         * Makefile.in: Re-generate.
1110         * i386-gen.c (process_i386_opcodes): New local variable
1111         "marker". Drop opening of input file. Recognize marker and line
1112         number directives.
1113         * i386-opc.tbl (OPCODE_I386_H): Define.
1114         (i386-opc.h): Include it.
1115         (None): Undefine.
1116
1117 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1118
1119         PR gas/23418
1120         * i386-opc.h (Byte): Update comments.
1121         (Word): Likewise.
1122         (Dword): Likewise.
1123         (Fword): Likewise.
1124         (Qword): Likewise.
1125         (Tbyte): Likewise.
1126         (Xmmword): Likewise.
1127         (Ymmword): Likewise.
1128         (Zmmword): Likewise.
1129         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1130         vcvttps2uqq.
1131         * i386-tbl.h: Regenerated.
1132
1133 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1134
1135         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1136         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1137         * aarch64-asm-2.c: Regenerate.
1138         * aarch64-dis-2.c: Regenerate.
1139         * aarch64-opc-2.c: Regenerate.
1140
1141 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1142
1143         PR binutils/23192
1144         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1145         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1146         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1147         sqdmulh, sqrdmulh): Use Em16.
1148
1149 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1150
1151         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1152         csdb together with them.
1153         (thumb32_opcodes): Likewise.
1154
1155 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1156
1157         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1158         requiring 32-bit registers as operands 2 and 3. Improve
1159         comments.
1160         (mwait, mwaitx): Fold templates. Improve comments.
1161         OPERAND_TYPE_INOUTPORTREG.
1162         * i386-tbl.h: Re-generate.
1163
1164 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1165
1166         * i386-gen.c (operand_type_init): Remove
1167         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1168         OPERAND_TYPE_INOUTPORTREG.
1169         * i386-init.h: Re-generate.
1170
1171 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1172
1173         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1174         (wrssq, wrussq): Add Qword.
1175         * i386-tbl.h: Re-generate.
1176
1177 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1178
1179         * i386-opc.h: Rename OTMax to OTNum.
1180         (OTNumOfUints): Adjust calculation.
1181         (OTUnused): Directly alias to OTNum.
1182
1183 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1184
1185         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1186         `reg_xys'.
1187         (lea_reg_xys): Likewise.
1188         (print_insn_loop_primitive): Rename `reg' local variable to
1189         `reg_dxy'.
1190
1191 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1192
1193         PR binutils/23242
1194         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1195
1196 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1197
1198         PR binutils/23369
1199         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1200         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1201
1202 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1203
1204         PR tdep/8282
1205         * mips-dis.c (mips_option_arg_t): New enumeration.
1206         (mips_options): New variable.
1207         (disassembler_options_mips): New function.
1208         (print_mips_disassembler_options): Reimplement in terms of
1209         `disassembler_options_mips'.
1210         * arm-dis.c (disassembler_options_arm): Adapt to using the
1211         `disasm_options_and_args_t' structure.
1212         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1213         * s390-dis.c (disassembler_options_s390): Likewise.
1214
1215 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1216
1217         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1218         expected result.
1219         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1220         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1221         * testsuite/ld-arm/tls-longplt.d: Likewise.
1222
1223 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1224
1225         PR binutils/23192
1226         * aarch64-asm-2.c: Regenerate.
1227         * aarch64-dis-2.c: Likewise.
1228         * aarch64-opc-2.c: Likewise.
1229         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1230         * aarch64-opc.c (operand_general_constraint_met_p,
1231         aarch64_print_operand): Likewise.
1232         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1233         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1234         fmlal2, fmlsl2.
1235         (AARCH64_OPERANDS): Add Em2.
1236
1237 2018-06-26  Nick Clifton  <nickc@redhat.com>
1238
1239         * po/uk.po: Updated Ukranian translation.
1240         * po/de.po: Updated German translation.
1241         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1242
1243 2018-06-26  Nick Clifton  <nickc@redhat.com>
1244
1245         * nfp-dis.c: Fix spelling mistake.
1246
1247 2018-06-24  Nick Clifton  <nickc@redhat.com>
1248
1249         * configure: Regenerate.
1250         * po/opcodes.pot: Regenerate.
1251
1252 2018-06-24  Nick Clifton  <nickc@redhat.com>
1253
1254         2.31 branch created.
1255
1256 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1257
1258         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1259         * aarch64-asm-2.c: Regenerate.
1260         * aarch64-dis-2.c: Likewise.
1261
1262 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1263
1264         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1265         `-M ginv' option description.
1266
1267 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1268
1269         PR gas/23305
1270         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1271         la and lla.
1272
1273 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1274
1275         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1276         * configure.ac: Remove AC_PREREQ.
1277         * Makefile.in: Re-generate.
1278         * aclocal.m4: Re-generate.
1279         * configure: Re-generate.
1280
1281 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1282
1283         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1284         mips64r6 descriptors.
1285         (parse_mips_ase_option): Handle -Mginv option.
1286         (print_mips_disassembler_options): Document -Mginv.
1287         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1288         (GINV): New macro.
1289         (mips_opcodes): Define ginvi and ginvt.
1290
1291 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1292             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1293
1294         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1295         * mips-opc.c (CRC, CRC64): New macros.
1296         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1297         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1298         crc32cd for CRC64.
1299
1300 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1301
1302         PR 20319
1303         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1304         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1305
1306 2018-06-06  Alan Modra  <amodra@gmail.com>
1307
1308         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1309         setjmp.  Move init for some other vars later too.
1310
1311 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1312
1313         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1314         (dis_private): Add new fields for property section tracking.
1315         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1316         (xtensa_instruction_fits): New functions.
1317         (fetch_data): Bump minimal fetch size to 4.
1318         (print_insn_xtensa): Make struct dis_private static.
1319         Load and prepare property table on section change.
1320         Don't disassemble literals. Don't disassemble instructions that
1321         cross property table boundaries.
1322
1323 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1324
1325         * configure: Regenerated.
1326
1327 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1328
1329         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1330         * i386-tbl.h: Re-generate.
1331
1332 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1333
1334         * i386-opc.tbl (sldt, str): Add NoRex64.
1335         * i386-tbl.h: Re-generate.
1336
1337 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1338
1339         * i386-opc.tbl (invpcid): Add Oword.
1340         * i386-tbl.h: Re-generate.
1341
1342 2018-06-01  Alan Modra  <amodra@gmail.com>
1343
1344         * sysdep.h (_bfd_error_handler): Don't declare.
1345         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1346         * rl78-decode.opc: Likewise.
1347         * msp430-decode.c: Regenerate.
1348         * rl78-decode.c: Regenerate.
1349
1350 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1351
1352         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1353         * i386-init.h : Regenerated.
1354
1355 2018-05-25  Alan Modra  <amodra@gmail.com>
1356
1357         * Makefile.in: Regenerate.
1358         * po/POTFILES.in: Regenerate.
1359
1360 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1361
1362         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1363         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1364         (insert_bab, extract_bab, insert_btab, extract_btab,
1365         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1366         (BAT, BBA VBA RBS XB6S): Delete macros.
1367         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1368         (BB, BD, RBX, XC6): Update for new macros.
1369         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1370         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1371         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1372         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1373
1374 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1375
1376         * Makefile.am: Add support for s12z architecture.
1377         * configure.ac: Likewise.
1378         * disassemble.c: Likewise.
1379         * disassemble.h: Likewise.
1380         * Makefile.in: Regenerate.
1381         * configure: Regenerate.
1382         * s12z-dis.c: New file.
1383         * s12z.h: New file.
1384
1385 2018-05-18  Alan Modra  <amodra@gmail.com>
1386
1387         * nfp-dis.c: Don't #include libbfd.h.
1388         (init_nfp3200_priv): Use bfd_get_section_contents.
1389         (nit_nfp6000_mecsr_sec): Likewise.
1390
1391 2018-05-17  Nick Clifton  <nickc@redhat.com>
1392
1393         * po/zh_CN.po: Updated simplified Chinese translation.
1394
1395 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1396
1397         PR binutils/23109
1398         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1399         * aarch64-dis-2.c: Regenerate.
1400
1401 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1402
1403         PR binutils/21446
1404         * aarch64-asm.c (opintl.h): Include.
1405         (aarch64_ins_sysreg): Enforce read/write constraints.
1406         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1407         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1408         (F_REG_READ, F_REG_WRITE): New.
1409         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1410         AARCH64_OPND_SYSREG.
1411         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1412         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1413         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1414         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1415         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1416         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1417         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1418         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1419         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1420         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1421         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1422         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1423         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1424         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1425         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1426         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1427         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1428
1429 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1430
1431         PR binutils/21446
1432         * aarch64-dis.c (no_notes: New.
1433         (parse_aarch64_dis_option): Support notes.
1434         (aarch64_decode_insn, print_operands): Likewise.
1435         (print_aarch64_disassembler_options): Document notes.
1436         * aarch64-opc.c (aarch64_print_operand): Support notes.
1437
1438 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1439
1440         PR binutils/21446
1441         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1442         and take error struct.
1443         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1444         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1445         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1446         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1447         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1448         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1449         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1450         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1451         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1452         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1453         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1454         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1455         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1456         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1457         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1458         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1459         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1460         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1461         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1462         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1463         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1464         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1465         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1466         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1467         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1468         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1469         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1470         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1471         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1472         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1473         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1474         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1475         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1476         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1477         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1478         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1479         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1480         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1481         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1482         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1483         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1484         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1485         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1486         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1487         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1488         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1489         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1490         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1491         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1492         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1493         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1494         (determine_disassembling_preference, aarch64_decode_insn,
1495         print_insn_aarch64_word, print_insn_data): Take errors struct.
1496         (print_insn_aarch64): Use errors.
1497         * aarch64-asm-2.c: Regenerate.
1498         * aarch64-dis-2.c: Regenerate.
1499         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1500         boolean in aarch64_insert_operan.
1501         (print_operand_extractor): Likewise.
1502         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1503
1504 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1505
1506         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1507
1508 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1509
1510         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1511
1512 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1513
1514         * cr16-opc.c (cr16_instruction): Comment typo fix.
1515         * hppa-dis.c (print_insn_hppa): Likewise.
1516
1517 2018-05-08  Jim Wilson  <jimw@sifive.com>
1518
1519         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1520         (match_c_slli64, match_srxi_as_c_srxi): New.
1521         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1522         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1523         <c.slli, c.srli, c.srai>: Use match_s_slli.
1524         <c.slli64, c.srli64, c.srai64>: New.
1525
1526 2018-05-08  Alan Modra  <amodra@gmail.com>
1527
1528         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1529         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1530         partition opcode space for index lookup.
1531
1532 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1533
1534         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1535         <insn_length>: ...with this.  Update usage.
1536         Remove duplicate call to *info->memory_error_func.
1537
1538 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1539             H.J. Lu  <hongjiu.lu@intel.com>
1540
1541         * i386-dis.c (Gva): New.
1542         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1543         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1544         (prefix_table): New instructions (see prefix above).
1545         (mod_table): New instructions (see prefix above).
1546         (OP_G): Handle va_mode.
1547         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1548         CPU_MOVDIR64B_FLAGS.
1549         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1550         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1551         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1552         * i386-opc.tbl: Add movidir{i,64b}.
1553         * i386-init.h: Regenerated.
1554         * i386-tbl.h: Likewise.
1555
1556 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1557
1558         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1559         AddrPrefixOpReg.
1560         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1561         (AddrPrefixOpReg): This.
1562         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1563         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1564
1565 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1566
1567         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1568         (vle_num_opcodes): Likewise.
1569         (spe2_num_opcodes): Likewise.
1570         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1571         initialization loop.
1572         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1573         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1574         only once.
1575
1576 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1577
1578         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1579
1580 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1581
1582         Makefile.am: Added nfp-dis.c.
1583         configure.ac: Added bfd_nfp_arch.
1584         disassemble.h: Added print_insn_nfp prototype.
1585         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1586         nfp-dis.c: New, for NFP support.
1587         po/POTFILES.in: Added nfp-dis.c to the list.
1588         Makefile.in: Regenerate.
1589         configure: Regenerate.
1590
1591 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1592
1593         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1594         templates into their base ones.
1595         * i386-tlb.h: Re-generate.
1596
1597 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1598
1599         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1600         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1601         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1602         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1603         * i386-init.h: Re-generate.
1604
1605 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1606
1607         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1608         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1609         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1610         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1611         comment.
1612         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1613         and CpuRegMask.
1614         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1615         CpuRegMask: Delete.
1616         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1617         cpuregzmm, and cpuregmask.
1618         * i386-init.h: Re-generate.
1619         * i386-tbl.h: Re-generate.
1620
1621 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1622
1623         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1624         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1625         * i386-init.h: Re-generate.
1626
1627 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1628
1629         * i386-gen.c (VexImmExt): Delete.
1630         * i386-opc.h (VexImmExt, veximmext): Delete.
1631         * i386-opc.tbl: Drop all VexImmExt uses.
1632         * i386-tlb.h: Re-generate.
1633
1634 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1635
1636         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1637         register-only forms.
1638         * i386-tlb.h: Re-generate.
1639
1640 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1641
1642         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1643
1644 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1645
1646         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1647         PREFIX_0F1C.
1648         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1649         (cpu_flags): Add CpuCLDEMOTE.
1650         * i386-init.h: Regenerate.
1651         * i386-opc.h (enum): Add CpuCLDEMOTE,
1652         (i386_cpu_flags): Add cpucldemote.
1653         * i386-opc.tbl: Add cldemote.
1654         * i386-tbl.h: Regenerate.
1655
1656 2018-04-16  Alan Modra  <amodra@gmail.com>
1657
1658         * Makefile.am: Remove sh5 and sh64 support.
1659         * configure.ac: Likewise.
1660         * disassemble.c: Likewise.
1661         * disassemble.h: Likewise.
1662         * sh-dis.c: Likewise.
1663         * sh64-dis.c: Delete.
1664         * sh64-opc.c: Delete.
1665         * sh64-opc.h: Delete.
1666         * Makefile.in: Regenerate.
1667         * configure: Regenerate.
1668         * po/POTFILES.in: Regenerate.
1669
1670 2018-04-16  Alan Modra  <amodra@gmail.com>
1671
1672         * Makefile.am: Remove w65 support.
1673         * configure.ac: Likewise.
1674         * disassemble.c: Likewise.
1675         * disassemble.h: Likewise.
1676         * w65-dis.c: Delete.
1677         * w65-opc.h: Delete.
1678         * Makefile.in: Regenerate.
1679         * configure: Regenerate.
1680         * po/POTFILES.in: Regenerate.
1681
1682 2018-04-16  Alan Modra  <amodra@gmail.com>
1683
1684         * configure.ac: Remove we32k support.
1685         * configure: Regenerate.
1686
1687 2018-04-16  Alan Modra  <amodra@gmail.com>
1688
1689         * Makefile.am: Remove m88k support.
1690         * configure.ac: Likewise.
1691         * disassemble.c: Likewise.
1692         * disassemble.h: Likewise.
1693         * m88k-dis.c: Delete.
1694         * Makefile.in: Regenerate.
1695         * configure: Regenerate.
1696         * po/POTFILES.in: Regenerate.
1697
1698 2018-04-16  Alan Modra  <amodra@gmail.com>
1699
1700         * Makefile.am: Remove i370 support.
1701         * configure.ac: Likewise.
1702         * disassemble.c: Likewise.
1703         * disassemble.h: Likewise.
1704         * i370-dis.c: Delete.
1705         * i370-opc.c: Delete.
1706         * Makefile.in: Regenerate.
1707         * configure: Regenerate.
1708         * po/POTFILES.in: Regenerate.
1709
1710 2018-04-16  Alan Modra  <amodra@gmail.com>
1711
1712         * Makefile.am: Remove h8500 support.
1713         * configure.ac: Likewise.
1714         * disassemble.c: Likewise.
1715         * disassemble.h: Likewise.
1716         * h8500-dis.c: Delete.
1717         * h8500-opc.h: Delete.
1718         * Makefile.in: Regenerate.
1719         * configure: Regenerate.
1720         * po/POTFILES.in: Regenerate.
1721
1722 2018-04-16  Alan Modra  <amodra@gmail.com>
1723
1724         * configure.ac: Remove tahoe support.
1725         * configure: Regenerate.
1726
1727 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1728
1729         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1730         umwait.
1731         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1732         64-bit mode.
1733         * i386-tbl.h: Regenerated.
1734
1735 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1736
1737         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1738         PREFIX_MOD_1_0FAE_REG_6.
1739         (va_mode): New.
1740         (OP_E_register): Use va_mode.
1741         * i386-dis-evex.h (prefix_table):
1742         New instructions (see prefixes above).
1743         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1744         (cpu_flags): Likewise.
1745         * i386-opc.h (enum): Likewise.
1746         (i386_cpu_flags): Likewise.
1747         * i386-opc.tbl: Add umonitor, umwait, tpause.
1748         * i386-init.h: Regenerate.
1749         * i386-tbl.h: Likewise.
1750
1751 2018-04-11  Alan Modra  <amodra@gmail.com>
1752
1753         * opcodes/i860-dis.c: Delete.
1754         * opcodes/i960-dis.c: Delete.
1755         * Makefile.am: Remove i860 and i960 support.
1756         * configure.ac: Likewise.
1757         * disassemble.c: Likewise.
1758         * disassemble.h: Likewise.
1759         * Makefile.in: Regenerate.
1760         * configure: Regenerate.
1761         * po/POTFILES.in: Regenerate.
1762
1763 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1764
1765         PR binutils/23025
1766         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1767         to 0.
1768         (print_insn): Clear vex instead of vex.evex.
1769
1770 2018-04-04  Nick Clifton  <nickc@redhat.com>
1771
1772         * po/es.po: Updated Spanish translation.
1773
1774 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1775
1776         * i386-gen.c (opcode_modifiers): Delete VecESize.
1777         * i386-opc.h (VecESize): Delete.
1778         (struct i386_opcode_modifier): Delete vecesize.
1779         * i386-opc.tbl: Drop VecESize.
1780         * i386-tlb.h: Re-generate.
1781
1782 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1783
1784         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1785         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1786         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1787         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1788         * i386-tlb.h: Re-generate.
1789
1790 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1791
1792         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1793         Fold AVX512 forms
1794         * i386-tlb.h: Re-generate.
1795
1796 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1797
1798         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1799         (vex_len_table): Drop Y for vcvt*2si.
1800         (putop): Replace plain 'Y' handling by abort().
1801
1802 2018-03-28  Nick Clifton  <nickc@redhat.com>
1803
1804         PR 22988
1805         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1806         instructions with only a base address register.
1807         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1808         handle AARHC64_OPND_SVE_ADDR_R.
1809         (aarch64_print_operand): Likewise.
1810         * aarch64-asm-2.c: Regenerate.
1811         * aarch64_dis-2.c: Regenerate.
1812         * aarch64-opc-2.c: Regenerate.
1813
1814 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1815
1816         * i386-opc.tbl: Drop VecESize from register only insn forms and
1817         memory forms not allowing broadcast.
1818         * i386-tlb.h: Re-generate.
1819
1820 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1821
1822         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1823         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1824         sha256*): Drop Disp<N>.
1825
1826 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1827
1828         * i386-dis.c (EbndS, bnd_swap_mode): New.
1829         (prefix_table): Use EbndS.
1830         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1831         * i386-opc.tbl (bndmov): Move misplaced Load.
1832         * i386-tlb.h: Re-generate.
1833
1834 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1835
1836         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1837         templates allowing memory operands and folded ones for register
1838         only flavors.
1839         * i386-tlb.h: Re-generate.
1840
1841 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1842
1843         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1844         256-bit templates. Drop redundant leftover Disp<N>.
1845         * i386-tlb.h: Re-generate.
1846
1847 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1848
1849         * riscv-opc.c (riscv_insn_types): New.
1850
1851 2018-03-13  Nick Clifton  <nickc@redhat.com>
1852
1853         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1854
1855 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1856
1857         * i386-opc.tbl: Add Optimize to clr.
1858         * i386-tbl.h: Regenerated.
1859
1860 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1861
1862         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1863         * i386-opc.h (OldGcc): Removed.
1864         (i386_opcode_modifier): Remove oldgcc.
1865         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1866         instructions for old (<= 2.8.1) versions of gcc.
1867         * i386-tbl.h: Regenerated.
1868
1869 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1870
1871         * i386-opc.h (EVEXDYN): New.
1872         * i386-opc.tbl: Fold various AVX512VL templates.
1873         * i386-tlb.h: Re-generate.
1874
1875 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1876
1877         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1878         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1879         vpexpandd, vpexpandq): Fold AFX512VF templates.
1880         * i386-tlb.h: Re-generate.
1881
1882 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1883
1884         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1885         Fold 128- and 256-bit VEX-encoded templates.
1886         * i386-tlb.h: Re-generate.
1887
1888 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1889
1890         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1891         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1892         vpexpandd, vpexpandq): Fold AVX512F templates.
1893         * i386-tlb.h: Re-generate.
1894
1895 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1896
1897         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1898         64-bit templates. Drop Disp<N>.
1899         * i386-tlb.h: Re-generate.
1900
1901 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1902
1903         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1904         and 256-bit templates.
1905         * i386-tlb.h: Re-generate.
1906
1907 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1908
1909         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1910         * i386-tlb.h: Re-generate.
1911
1912 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1913
1914         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1915         Drop NoAVX.
1916         * i386-tlb.h: Re-generate.
1917
1918 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1919
1920         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1921         * i386-tlb.h: Re-generate.
1922
1923 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1924
1925         * i386-gen.c (opcode_modifiers): Delete FloatD.
1926         * i386-opc.h (FloatD): Delete.
1927         (struct i386_opcode_modifier): Delete floatd.
1928         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1929         FloatD by D.
1930         * i386-tlb.h: Re-generate.
1931
1932 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1933
1934         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1935
1936 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1937
1938         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1939         * i386-tlb.h: Re-generate.
1940
1941 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1942
1943         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1944         forms.
1945         * i386-tlb.h: Re-generate.
1946
1947 2018-03-07  Alan Modra  <amodra@gmail.com>
1948
1949         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1950         bfd_arch_rs6000.
1951         * disassemble.h (print_insn_rs6000): Delete.
1952         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1953         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1954         (print_insn_rs6000): Delete.
1955
1956 2018-03-03  Alan Modra  <amodra@gmail.com>
1957
1958         * sysdep.h (opcodes_error_handler): Define.
1959         (_bfd_error_handler): Declare.
1960         * Makefile.am: Remove stray #.
1961         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1962         EDIT" comment.
1963         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1964         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1965         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1966         opcodes_error_handler to print errors.  Standardize error messages.
1967         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1968         and include opintl.h.
1969         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1970         * i386-gen.c: Standardize error messages.
1971         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1972         * Makefile.in: Regenerate.
1973         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1974         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1975         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1976         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1977         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1978         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1979         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1980         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1981         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1982         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1983         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1984         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1985         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1986
1987 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1988
1989         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1990         vpsub[bwdq] instructions.
1991         * i386-tbl.h: Regenerated.
1992
1993 2018-03-01  Alan Modra  <amodra@gmail.com>
1994
1995         * configure.ac (ALL_LINGUAS): Sort.
1996         * configure: Regenerate.
1997
1998 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1999
2000         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2001         macro by assignements.
2002
2003 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2004
2005         PR gas/22871
2006         * i386-gen.c (opcode_modifiers): Add Optimize.
2007         * i386-opc.h (Optimize): New enum.
2008         (i386_opcode_modifier): Add optimize.
2009         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2010         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2011         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2012         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2013         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2014         vpxord and vpxorq.
2015         * i386-tbl.h: Regenerated.
2016
2017 2018-02-26  Alan Modra  <amodra@gmail.com>
2018
2019         * crx-dis.c (getregliststring): Allocate a large enough buffer
2020         to silence false positive gcc8 warning.
2021
2022 2018-02-22  Shea Levy <shea@shealevy.com>
2023
2024         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2025
2026 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2027
2028         * i386-opc.tbl: Add {rex},
2029         * i386-tbl.h: Regenerated.
2030
2031 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2032
2033         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2034         (mips16_opcodes): Replace `M' with `m' for "restore".
2035
2036 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2037
2038         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2039
2040 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2041
2042         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2043         variable to `function_index'.
2044
2045 2018-02-13  Nick Clifton  <nickc@redhat.com>
2046
2047         PR 22823
2048         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2049         about truncation of printing.
2050
2051 2018-02-12  Henry Wong <henry@stuffedcow.net>
2052
2053         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2054
2055 2018-02-05  Nick Clifton  <nickc@redhat.com>
2056
2057         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2058
2059 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2060
2061         * i386-dis.c (enum): Add pconfig.
2062         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2063         (cpu_flags): Add CpuPCONFIG.
2064         * i386-opc.h (enum): Add CpuPCONFIG.
2065         (i386_cpu_flags): Add cpupconfig.
2066         * i386-opc.tbl: Add PCONFIG instruction.
2067         * i386-init.h: Regenerate.
2068         * i386-tbl.h: Likewise.
2069
2070 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2071
2072         * i386-dis.c (enum): Add PREFIX_0F09.
2073         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2074         (cpu_flags): Add CpuWBNOINVD.
2075         * i386-opc.h (enum): Add CpuWBNOINVD.
2076         (i386_cpu_flags): Add cpuwbnoinvd.
2077         * i386-opc.tbl: Add WBNOINVD instruction.
2078         * i386-init.h: Regenerate.
2079         * i386-tbl.h: Likewise.
2080
2081 2018-01-17  Jim Wilson  <jimw@sifive.com>
2082
2083         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2084
2085 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2086
2087         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2088         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2089         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2090         (cpu_flags): Add CpuIBT, CpuSHSTK.
2091         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2092         (i386_cpu_flags): Add cpuibt, cpushstk.
2093         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2094         * i386-init.h: Regenerate.
2095         * i386-tbl.h: Likewise.
2096
2097 2018-01-16  Nick Clifton  <nickc@redhat.com>
2098
2099         * po/pt_BR.po: Updated Brazilian Portugese translation.
2100         * po/de.po: Updated German translation.
2101
2102 2018-01-15  Jim Wilson  <jimw@sifive.com>
2103
2104         * riscv-opc.c (match_c_nop): New.
2105         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2106
2107 2018-01-15  Nick Clifton  <nickc@redhat.com>
2108
2109         * po/uk.po: Updated Ukranian translation.
2110
2111 2018-01-13  Nick Clifton  <nickc@redhat.com>
2112
2113         * po/opcodes.pot: Regenerated.
2114
2115 2018-01-13  Nick Clifton  <nickc@redhat.com>
2116
2117         * configure: Regenerate.
2118
2119 2018-01-13  Nick Clifton  <nickc@redhat.com>
2120
2121         2.30 branch created.
2122
2123 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2124
2125         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2126         * i386-tbl.h: Regenerate.
2127
2128 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2129
2130         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2131         * i386-tbl.h: Re-generate.
2132
2133 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2134
2135         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2136         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2137         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2138         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2139         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2140         Disp8MemShift of AVX512VL forms.
2141         * i386-tbl.h: Re-generate.
2142
2143 2018-01-09  Jim Wilson  <jimw@sifive.com>
2144
2145         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2146         then the hi_addr value is zero.
2147
2148 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2149
2150         * arm-dis.c (arm_opcodes): Add csdb.
2151         (thumb32_opcodes): Add csdb.
2152
2153 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2154
2155         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2156         * aarch64-asm-2.c: Regenerate.
2157         * aarch64-dis-2.c: Regenerate.
2158         * aarch64-opc-2.c: Regenerate.
2159
2160 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2161
2162         PR gas/22681
2163         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2164         Remove AVX512 vmovd with 64-bit operands.
2165         * i386-tbl.h: Regenerated.
2166
2167 2018-01-05  Jim Wilson  <jimw@sifive.com>
2168
2169         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2170         jalr.
2171
2172 2018-01-03  Alan Modra  <amodra@gmail.com>
2173
2174         Update year range in copyright notice of all files.
2175
2176 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2177
2178         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2179         and OPERAND_TYPE_REGZMM entries.
2180
2181 For older changes see ChangeLog-2017
2182 \f
2183 Copyright (C) 2018 Free Software Foundation, Inc.
2184
2185 Copying and distribution of this file, with or without modification,
2186 are permitted in any medium without royalty provided the copyright
2187 notice and this notice are preserved.
2188
2189 Local Variables:
2190 mode: change-log
2191 left-margin: 8
2192 fill-column: 74
2193 version-control: never
2194 End: