opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
   4         rather than "should be" or "expected to be" in error messages.
   5
   6 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   7
   8         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
   9         (print_mnemonic_name): ...here.
  10         (print_comment): New function.
  11         (print_aarch64_insn): Call it.
  12         * aarch64-opc.c (aarch64_conds): Add SVE names.
  13         (aarch64_print_operand): Print alternative condition names in
  14         a comment.
  15
  16 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  17
  18         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
  19         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
  20         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
  21         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
  22         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
  23         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
  24         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
  25         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
  26         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
  27         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
  28         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
  29         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
  30         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
  31         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
  32         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
  33         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
  34         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
  35         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
  36         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
  37         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
  38         (OP_SVE_XWU, OP_SVE_XXU): New macros.
  39         (aarch64_feature_sve): New variable.
  40         (SVE): New macro.
  41         (_SVE_INSN): Likewise.
  42         (aarch64_opcode_table): Add SVE instructions.
  43         * aarch64-opc.h (extract_fields): Declare.
  44         * aarch64-opc-2.c: Regenerate.
  45         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
  46         * aarch64-asm-2.c: Regenerate.
  47         * aarch64-dis.c (extract_fields): Make global.
  48         (do_misc_decoding): Handle the new SVE aarch64_ops.
  49         * aarch64-dis-2.c: Regenerate.
  50
  51 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  52
  53         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
  54         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
  55         aarch64_field_kinds.
  56         * aarch64-opc.c (fields): Add corresponding entries.
  57         * aarch64-asm.c (aarch64_get_variant): New function.
  58         (aarch64_encode_variant_using_iclass): Likewise.
  59         (aarch64_opcode_encode): Call it.
  60         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
  61         (aarch64_opcode_decode): Call it.
  62
  63 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  64
  65         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
  66         and FP register operands.
  67         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
  68         (FLD_SVE_Vn): New aarch64_field_kinds.
  69         * aarch64-opc.c (fields): Add corresponding entries.
  70         (aarch64_print_operand): Handle the new SVE core and FP register
  71         operands.
  72         * aarch64-opc-2.c: Regenerate.
  73         * aarch64-asm-2.c: Likewise.
  74         * aarch64-dis-2.c: Likewise.
  75
  76 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  77
  78         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
  79         immediate operands.
  80         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
  81         * aarch64-opc.c (fields): Add corresponding entry.
  82         (operand_general_constraint_met_p): Handle the new SVE FP immediate
  83         operands.
  84         (aarch64_print_operand): Likewise.
  85         * aarch64-opc-2.c: Regenerate.
  86         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
  87         (ins_sve_float_zero_one): New inserters.
  88         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
  89         (aarch64_ins_sve_float_half_two): Likewise.
  90         (aarch64_ins_sve_float_zero_one): Likewise.
  91         * aarch64-asm-2.c: Regenerate.
  92         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
  93         (ext_sve_float_zero_one): New extractors.
  94         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
  95         (aarch64_ext_sve_float_half_two): Likewise.
  96         (aarch64_ext_sve_float_zero_one): Likewise.
  97         * aarch64-dis-2.c: Regenerate.
  98
  99 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 100
 101         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 102         integer immediate operands.
 103         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 104         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 105         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 106         * aarch64-opc.c (fields): Add corresponding entries.
 107         (operand_general_constraint_met_p): Handle the new SVE integer
 108         immediate operands.
 109         (aarch64_print_operand): Likewise.
 110         (aarch64_sve_dupm_mov_immediate_p): New function.
 111         * aarch64-opc-2.c: Regenerate.
 112         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 113         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 114         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 115         (aarch64_ins_limm): ...here.
 116         (aarch64_ins_inv_limm): New function.
 117         (aarch64_ins_sve_aimm): Likewise.
 118         (aarch64_ins_sve_asimm): Likewise.
 119         (aarch64_ins_sve_limm_mov): Likewise.
 120         (aarch64_ins_sve_shlimm): Likewise.
 121         (aarch64_ins_sve_shrimm): Likewise.
 122         * aarch64-asm-2.c: Regenerate.
 123         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 124         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 125         * aarch64-dis.c (decode_limm): New function, split out from...
 126         (aarch64_ext_limm): ...here.
 127         (aarch64_ext_inv_limm): New function.
 128         (decode_sve_aimm): Likewise.
 129         (aarch64_ext_sve_aimm): Likewise.
 130         (aarch64_ext_sve_asimm): Likewise.
 131         (aarch64_ext_sve_limm_mov): Likewise.
 132         (aarch64_top_bit): Likewise.
 133         (aarch64_ext_sve_shlimm): Likewise.
 134         (aarch64_ext_sve_shrimm): Likewise.
 135         * aarch64-dis-2.c: Regenerate.
 136
 137 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 138
 139         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 140         operands.
 141         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 142         the AARCH64_MOD_MUL_VL entry.
 143         (value_aligned_p): Cope with non-power-of-two alignments.
 144         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 145         (print_immediate_offset_address): Likewise.
 146         (aarch64_print_operand): Likewise.
 147         * aarch64-opc-2.c: Regenerate.
 148         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 149         (ins_sve_addr_ri_s9xvl): New inserters.
 150         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 151         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 152         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 153         * aarch64-asm-2.c: Regenerate.
 154         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 155         (ext_sve_addr_ri_s9xvl): New extractors.
 156         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 157         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 158         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 159         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 160         * aarch64-dis-2.c: Regenerate.
 161
 162 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 163
 164         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 165         address operands.
 166         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 167         (FLD_SVE_xs_22): New aarch64_field_kinds.
 168         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 169         (get_operand_specific_data): New function.
 170         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 171         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 172         (operand_general_constraint_met_p): Handle the new SVE address
 173         operands.
 174         (sve_reg): New array.
 175         (get_addr_sve_reg_name): New function.
 176         (aarch64_print_operand): Handle the new SVE address operands.
 177         * aarch64-opc-2.c: Regenerate.
 178         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 179         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 180         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 181         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 182         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 183         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 184         (aarch64_ins_sve_addr_zi_u5): Likewise.
 185         (aarch64_ins_sve_addr_zz): Likewise.
 186         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 187         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 188         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 189         * aarch64-asm-2.c: Regenerate.
 190         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 191         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 192         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 193         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 194         (aarch64_ext_sve_addr_ri_u6): Likewise.
 195         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 196         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 197         (aarch64_ext_sve_addr_zi_u5): Likewise.
 198         (aarch64_ext_sve_addr_zz): Likewise.
 199         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 200         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 201         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 202         * aarch64-dis-2.c: Regenerate.
 203
 204 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 205
 206         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 207         AARCH64_OPND_SVE_PATTERN_SCALED.
 208         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 209         * aarch64-opc.c (fields): Add a corresponding entry.
 210         (set_multiplier_out_of_range_error): New function.
 211         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 212         (operand_general_constraint_met_p): Handle
 213         AARCH64_OPND_SVE_PATTERN_SCALED.
 214         (print_register_offset_address): Use PRIi64 to print the
 215         shift amount.
 216         (aarch64_print_operand): Likewise.  Handle
 217         AARCH64_OPND_SVE_PATTERN_SCALED.
 218         * aarch64-opc-2.c: Regenerate.
 219         * aarch64-asm.h (ins_sve_scale): New inserter.
 220         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 221         * aarch64-asm-2.c: Regenerate.
 222         * aarch64-dis.h (ext_sve_scale): New inserter.
 223         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 224         * aarch64-dis-2.c: Regenerate.
 225
 226 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 227
 228         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 229         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 230         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 231         (FLD_SVE_prfop): Likewise.
 232         * aarch64-opc.c: Include libiberty.h.
 233         (aarch64_sve_pattern_array): New variable.
 234         (aarch64_sve_prfop_array): Likewise.
 235         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 236         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 237         AARCH64_OPND_SVE_PRFOP.
 238         * aarch64-asm-2.c: Regenerate.
 239         * aarch64-dis-2.c: Likewise.
 240         * aarch64-opc-2.c: Likewise.
 241
 242 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 243
 244         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 245         AARCH64_OPND_QLF_P_[ZM].
 246         (aarch64_print_operand): Print /z and /m where appropriate.
 247
 248 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 249
 250         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 251         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 252         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 253         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 254         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 255         * aarch64-opc.c (fields): Add corresponding entries here.
 256         (operand_general_constraint_met_p): Check that SVE register lists
 257         have the correct length.  Check the ranges of SVE index registers.
 258         Check for cases where p8-p15 are used in 3-bit predicate fields.
 259         (aarch64_print_operand): Handle the new SVE operands.
 260         * aarch64-opc-2.c: Regenerate.
 261         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 262         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 263         (aarch64_ins_sve_reglist): Likewise.
 264         * aarch64-asm-2.c: Regenerate.
 265         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 266         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 267         (aarch64_ext_sve_reglist): Likewise.
 268         * aarch64-dis-2.c: Regenerate.
 269
 270 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 271
 272         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 273         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 274         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 275         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 276         tied operands.
 277
 278 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 279
 280         * aarch64-opc.c (get_offset_int_reg_name): New function.
 281         (print_immediate_offset_address): Likewise.
 282         (print_register_offset_address): Take the base and offset
 283         registers as parameters.
 284         (aarch64_print_operand): Update caller accordingly.  Use
 285         print_immediate_offset_address.
 286
 287 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 288
 289         * aarch64-opc.c (BANK): New macro.
 290         (R32, R64): Take a register number as argument
 291         (int_reg): Use BANK.
 292
 293 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 294
 295         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 296         (aarch64_print_operand): Update accordingly.
 297
 298 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 299
 300         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 301         for FPIMM.
 302         * aarch64-asm.h (ins_fpimm): New inserter.
 303         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 304         * aarch64-asm-2.c: Regenerate.
 305         * aarch64-dis.h (ext_fpimm): New extractor.
 306         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 307         (aarch64_ext_fpimm): New function.
 308         * aarch64-dis-2.c: Regenerate.
 309
 310 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 311
 312         * aarch64-asm.c: Include libiberty.h.
 313         (insert_fields): New function.
 314         (aarch64_ins_imm): Use it.
 315         * aarch64-dis.c (extract_fields): New function.
 316         (aarch64_ext_imm): Use it.
 317
 318 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 319
 320         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 321         with an esize parameter.
 322         (operand_general_constraint_met_p): Update accordingly.
 323         Fix misindented code.
 324         * aarch64-asm.c (aarch64_ins_limm): Update call to
 325         aarch64_logical_immediate_p.
 326
 327 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 328
 329         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 330
 331 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 332
 333         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 334
 335 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 336
 337         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 338
 339 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 340
 341         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 342         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 343         xor3>: Delete mnemonics.
 344         <cp_abort>: Rename mnemonic from ...
 345         <cpabort>: ...to this.
 346         <setb>: Change to a X form instruction.
 347         <sync>: Change to 1 operand form.
 348         <copy>: Delete mnemonic.
 349         <copy_first>: Rename mnemonic from ...
 350         <copy>: ...to this.
 351         <paste, paste.>: Delete mnemonics.
 352         <paste_last>: Rename mnemonic from ...
 353         <paste.>: ...to this.
 354
 355 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 356
 357         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 358
 359 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 360
 361         * s390-mkopc.c (main): Support alternate arch strings.
 362
 363 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 364
 365         * s390-opc.txt: Fix kmctr instruction type.
 366
 367 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 368
 369         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 370         * i386-init.h: Regenerated.
 371
 372 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 373
 374         * opcodes/arc-dis.c (print_insn_arc): Changed.
 375
 376 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 377
 378         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 379         camellia_fl.
 380
 381 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 382
 383         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 384         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 385         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 386
 387 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 388
 389         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 390         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 391         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 392         PREFIX_MOD_3_0FAE_REG_4.
 393         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 394         PREFIX_MOD_3_0FAE_REG_4.
 395         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 396         (cpu_flags): Add CpuPTWRITE.
 397         * i386-opc.h (CpuPTWRITE): New.
 398         (i386_cpu_flags): Add cpuptwrite.
 399         * i386-opc.tbl: Add ptwrite instruction.
 400         * i386-init.h: Regenerated.
 401         * i386-tbl.h: Likewise.
 402
 403 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 404
 405         * arc-dis.h: Wrap around in extern "C".
 406
 407 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 408
 409         * aarch64-tbl.h (V8_2_INSN): New macro.
 410         (aarch64_opcode_table): Use it.
 411
 412 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 413
 414         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 415         CORE_INSN, __FP_INSN and SIMD_INSN.
 416
 417 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 418
 419         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 420         (aarch64_opcode_table): Update uses accordingly.
 421
 422 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 423         Kwok Cheung Yeung  <kcy@codesourcery.com>
 424
 425         opcodes/
 426         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 427         'e_cmplwi' to 'e_cmpli' instead.
 428         (OPVUPRT, OPVUPRT_MASK): Define.
 429         (powerpc_opcodes): Add E200Z4 insns.
 430         (vle_opcodes): Add context save/restore insns.
 431
 432 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 433
 434         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 435         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 436         "j".
 437
 438 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 439
 440         * arc-nps400-tbl.h: Change block comments to GNU format.
 441         * arc-dis.c: Add new globals addrtypenames,
 442         addrtypenames_max, and addtypeunknown.
 443         (get_addrtype): New function.
 444         (print_insn_arc): Print colons and address types when
 445         required.
 446         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 447         define insert and extract functions for all address types.
 448         (arc_operands): Add operands for colon and all address
 449         types.
 450         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 451         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 452         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 453         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 454         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 455         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 456
 457 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 458
 459         * configure: Regenerated.
 460
 461 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 462
 463         * arc-dis.c (skipclass): New structure.
 464         (decodelist): New variable.
 465         (is_compatible_p): New function.
 466         (new_element): Likewise.
 467         (skip_class_p): Likewise.
 468         (find_format_from_table): Use skip_class_p function.
 469         (find_format): Decode first the extension instructions.
 470         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 471         e_flags.
 472         (parse_option): New function.
 473         (parse_disassembler_options): Likewise.
 474         (print_arc_disassembler_options): Likewise.
 475         (print_insn_arc): Use parse_disassembler_options function.  Proper
 476         select ARCv2 cpu variant.
 477         * disassemble.c (disassembler_usage): Add ARC disassembler
 478         options.
 479
 480 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 481
 482         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 483         annotation from the "nal" entry and reorder it beyond "bltzal".
 484
 485 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 486
 487         * sparc-opc.c (ldtxa): New macro.
 488         (sparc_opcodes): Use the macro defined above to add entries for
 489         the LDTXA instructions.
 490         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 491         instruction.
 492
 493 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 494
 495         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 496         and "jmpc".
 497
 498 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 501         (movzb): Adjust to cover all permitted suffixes.
 502         (movzw): New.
 503         * i386-tbl.h: Re-generate.
 504
 505 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 508         (lgdt): Remove Tbyte from non-64-bit variant.
 509         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 510         xsaves64, xsavec64): Remove Disp16.
 511         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 512         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 513         64-bit variants.
 514         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 515         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 516         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 517         64-bit variants.
 518         * i386-tbl.h: Re-generate.
 519
 520 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 521
 522         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 523         * i386-tbl.h: Re-generate.
 524
 525 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 526
 527         * arm-dis.c (print_insn): Fix typo in comment.
 528
 529 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 530
 531         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 532         range of ldst_elemlist operands.
 533         (print_register_list): Use PRIi64 to print the index.
 534         (aarch64_print_operand): Likewise.
 535
 536 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 537
 538         * mcore-opc.h: Remove sentinal.
 539         * mcore-dis.c (print_insn_mcore): Adjust.
 540
 541 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 542
 543         * arc-opc.c: Correct description of availability of NPS400
 544         features.
 545
 546 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 547
 548         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 549         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 550         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 551         xor3>: New mnemonics.
 552         <setb>: Change to a VX form instruction.
 553         (insert_sh6): Add support for rldixor.
 554         (extract_sh6): Likewise.
 555
 556 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 557
 558         * arc-ext.h: Wrap in extern C.
 559
 560 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 561
 562         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 563         Use same method for determining instruction length on ARC700 and
 564         NPS-400.
 565         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 566         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 567         with the NPS400 subclass.
 568         * arc-opc.c: Likewise.
 569
 570 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 571
 572         * sparc-opc.c (rdasr): New macro.
 573         (wrasr): Likewise.
 574         (rdpr): Likewise.
 575         (wrpr): Likewise.
 576         (rdhpr): Likewise.
 577         (wrhpr): Likewise.
 578         (sparc_opcodes): Use the macros above to fix and expand the
 579         definition of read/write instructions from/to
 580         asr/privileged/hyperprivileged instructions.
 581         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 582         %hva_mask_nz.  Prefer softint_set and softint_clear over
 583         set_softint and clear_softint.
 584         (print_insn_sparc): Support %ver in Rd.
 585
 586 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 587
 588         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 589         architecture according to the hardware capabilities they require.
 590
 591 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 592
 593         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 594         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 595         bfd_mach_sparc_v9{c,d,e,v,m}.
 596         * sparc-opc.c (MASK_V9C): Define.
 597         (MASK_V9D): Likewise.
 598         (MASK_V9E): Likewise.
 599         (MASK_V9V): Likewise.
 600         (MASK_V9M): Likewise.
 601         (v6): Add MASK_V9{C,D,E,V,M}.
 602         (v6notlet): Likewise.
 603         (v7): Likewise.
 604         (v8): Likewise.
 605         (v9): Likewise.
 606         (v9andleon): Likewise.
 607         (v9a): Likewise.
 608         (v9b): Likewise.
 609         (v9c): Define.
 610         (v9d): Likewise.
 611         (v9e): Likewise.
 612         (v9v): Likewise.
 613         (v9m): Likewise.
 614         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 615
 616 2016-06-15  Nick Clifton  <nickc@redhat.com>
 617
 618         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 619         constants to match expected behaviour.
 620         (nds32_parse_opcode): Likewise.  Also for whitespace.
 621
 622 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 623
 624         * arc-opc.c (extract_rhv1): Extract value from insn.
 625
 626 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 627
 628         * arc-nps400-tbl.h: Add ldbit instruction.
 629         * arc-opc.c: Add flag classes required for ldbit.
 630
 631 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 632
 633         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 634         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 635         support the above instructions.
 636
 637 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 638
 639         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 640         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 641         csma, cbba, zncv, and hofs.
 642         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 643         support the above instructions.
 644
 645 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 646
 647         * arc-nps400-tbl.h: Add andab and orab instructions.
 648
 649 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 650
 651         * arc-nps400-tbl.h: Add addl-like instructions.
 652
 653 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 654
 655         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 656
 657 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 658
 659         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 660         instructions.
 661
 662 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 663
 664         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 665         variable.
 666         (init_disasm): Handle new command line option "insnlength".
 667         (print_s390_disassembler_options): Mention new option in help
 668         output.
 669         (print_insn_s390): Use the encoded insn length when dumping
 670         unknown instructions.
 671
 672 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 673
 674         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 675          to the address and set as symbol address for LDS/ STS immediate operands.
 676
 677 2016-06-07  Alan Modra  <amodra@gmail.com>
 678
 679         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 680         cpu for "vle" to e500.
 681         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 682         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 683         (PPCNONE): Delete, substitute throughout.
 684         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 685         except for major opcode 4 and 31.
 686         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 687
 688 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 689
 690         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 691         ARM_EXT_RAS in relevant entries.
 692
 693 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 694
 695         PR binutils/20196
 696         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 697         opcodes for E6500.
 698
 699 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 700
 701         PR binutis/18386
 702         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 703         (indir_v_mode): New.
 704         Add comments for '&'.
 705         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 706         (putop): Handle '&'.
 707         (intel_operand_size): Handle indir_v_mode.
 708         (OP_E_register): Likewise.
 709         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 710         64-bit indirect call/jmp for AMD64.
 711         * i386-tbl.h: Regenerated
 712
 713 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 714
 715         * arc-dis.c (struct arc_operand_iterator): New structure.
 716         (find_format_from_table): All the old content from find_format,
 717         with some minor adjustments, and parameter renaming.
 718         (find_format_long_instructions): New function.
 719         (find_format): Rewritten.
 720         (arc_insn_length): Add LSB parameter.
 721         (extract_operand_value): New function.
 722         (operand_iterator_next): New function.
 723         (print_insn_arc): Use new functions to find opcode, and iterator
 724         over operands.
 725         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 726         (extract_nps_3bit_dst_short): New function.
 727         (insert_nps_3bit_src2_short): New function.
 728         (extract_nps_3bit_src2_short): New function.
 729         (insert_nps_bitop1_size): New function.
 730         (extract_nps_bitop1_size): New function.
 731         (insert_nps_bitop2_size): New function.
 732         (extract_nps_bitop2_size): New function.
 733         (insert_nps_bitop_mod4_msb): New function.
 734         (extract_nps_bitop_mod4_msb): New function.
 735         (insert_nps_bitop_mod4_lsb): New function.
 736         (extract_nps_bitop_mod4_lsb): New function.
 737         (insert_nps_bitop_dst_pos3_pos4): New function.
 738         (extract_nps_bitop_dst_pos3_pos4): New function.
 739         (insert_nps_bitop_ins_ext): New function.
 740         (extract_nps_bitop_ins_ext): New function.
 741         (arc_operands): Add new operands.
 742         (arc_long_opcodes): New global array.
 743         (arc_num_long_opcodes): New global.
 744         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 745
 746 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 747
 748         * nds32-asm.h: Add extern "C".
 749         * sh-opc.h: Likewise.
 750
 751 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 752
 753         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 754         0,b,limm to the rflt instruction.
 755
 756 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 757
 758         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 759         constant.
 760
 761 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 762
 763         PR gas/20145
 764         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 765         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 766         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 767         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 768         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 769         * i386-init.h: Regenerated.
 770
 771 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 772
 773         PR gas/20145
 774         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 775         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 776         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 777         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 778         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 779         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 780         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 781         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 782         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 783         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 784         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 785         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 786         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 787         CpuRegMask for AVX512.
 788         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 789         and CpuRegMask.
 790         (set_bitfield_from_cpu_flag_init): New function.
 791         (set_bitfield): Remove const on f.  Call
 792         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 793         * i386-opc.h (CpuRegMMX): New.
 794         (CpuRegXMM): Likewise.
 795         (CpuRegYMM): Likewise.
 796         (CpuRegZMM): Likewise.
 797         (CpuRegMask): Likewise.
 798         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 799         and cpuregmask.
 800         * i386-init.h: Regenerated.
 801         * i386-tbl.h: Likewise.
 802
 803 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 804
 805         PR gas/20154
 806         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 807         (opcode_modifiers): Add AMD64 and Intel64.
 808         (main): Properly verify CpuMax.
 809         * i386-opc.h (CpuAMD64): Removed.
 810         (CpuIntel64): Likewise.
 811         (CpuMax): Set to CpuNo64.
 812         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 813         (AMD64): New.
 814         (Intel64): Likewise.
 815         (i386_opcode_modifier): Add amd64 and intel64.
 816         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 817         on call and jmp.
 818         * i386-init.h: Regenerated.
 819         * i386-tbl.h: Likewise.
 820
 821 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 822
 823         PR gas/20154
 824         * i386-gen.c (main): Fail if CpuMax is incorrect.
 825         * i386-opc.h (CpuMax): Set to CpuIntel64.
 826         * i386-tbl.h: Regenerated.
 827
 828 2016-05-27  Nick Clifton  <nickc@redhat.com>
 829
 830         PR target/20150
 831         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 832         (msp430dis_opcode_unsigned): New function.
 833         (msp430dis_opcode_signed): New function.
 834         (msp430_singleoperand): Use the new opcode reading functions.
 835         Only disassenmble bytes if they were successfully read.
 836         (msp430_doubleoperand): Likewise.
 837         (msp430_branchinstr): Likewise.
 838         (msp430x_callx_instr): Likewise.
 839         (print_insn_msp430): Check that it is safe to read bytes before
 840         attempting disassembly.  Use the new opcode reading functions.
 841
 842 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 843
 844         * ppc-opc.c (CY): New define.  Document it.
 845         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 846
 847 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 848
 849         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 850         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 851         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 852         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 853         CPU_ANY_AVX_FLAGS.
 854         * i386-init.h: Regenerated.
 855
 856 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 857
 858         PR gas/20141
 859         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 860         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 861         * i386-init.h: Regenerated.
 862
 863 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 866         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 867         * i386-init.h: Regenerated.
 868
 869 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 870
 871         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 872         information.
 873         (print_insn_arc): Set insn_type information.
 874         * arc-opc.c (C_CC): Add F_CLASS_COND.
 875         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 876         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 877         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 878         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 879         (brne, brne_s, jeq_s, jne_s): Likewise.
 880
 881 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 882
 883         * arc-tbl.h (neg): New instruction variant.
 884
 885 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 886
 887         * arc-dis.c (find_format, find_format, get_auxreg)
 888         (print_insn_arc): Changed.
 889         * arc-ext.h (INSERT_XOP): Likewise.
 890
 891 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 892
 893         * tic54x-dis.c (sprint_mmr): Adjust.
 894         * tic54x-opc.c: Likewise.
 895
 896 2016-05-19  Alan Modra  <amodra@gmail.com>
 897
 898         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 899
 900 2016-05-19  Alan Modra  <amodra@gmail.com>
 901
 902         * ppc-opc.c: Formatting.
 903         (NSISIGNOPT): Define.
 904         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 905
 906 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 907
 908         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 909         replacing references to `micromips_ase' throughout.
 910         (_print_insn_mips): Don't use file-level microMIPS annotation to
 911         determine the disassembly mode with the symbol table.
 912
 913 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 914
 915         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 916
 917 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 918
 919         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 920         mips64r6.
 921         * mips-opc.c (D34): New macro.
 922         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 923
 924 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 925
 926         * i386-dis.c (prefix_table): Add RDPID instruction.
 927         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 928         (cpu_flags): Add RDPID bitfield.
 929         * i386-opc.h (enum): Add RDPID element.
 930         (i386_cpu_flags): Add RDPID field.
 931         * i386-opc.tbl: Add RDPID instruction.
 932         * i386-init.h: Regenerate.
 933         * i386-tbl.h: Regenerate.
 934
 935 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 936
 937         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 938         branch type of a symbol.
 939         (print_insn): Likewise.
 940
 941 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 942
 943         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 944         Mainline Security Extensions instructions.
 945         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 946         Extensions instructions.
 947         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 948         instructions.
 949         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 950         special registers.
 951
 952 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 953
 954         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 955
 956 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 957
 958         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 959         (arcExtMap_genOpcode): Likewise.
 960         * arc-opc.c (arg_32bit_rc): Define new variable.
 961         (arg_32bit_u6): Likewise.
 962         (arg_32bit_limm): Likewise.
 963
 964 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 965
 966         * aarch64-gen.c (VERIFIER): Define.
 967         * aarch64-opc.c (VERIFIER): Define.
 968         (verify_ldpsw): Use static linkage.
 969         * aarch64-opc.h (verify_ldpsw): Remove.
 970         * aarch64-tbl.h: Use VERIFIER for verifiers.
 971
 972 2016-04-28  Nick Clifton  <nickc@redhat.com>
 973
 974         PR target/19722
 975         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 976         * aarch64-opc.c (verify_ldpsw): New function.
 977         * aarch64-opc.h (verify_ldpsw): New prototype.
 978         * aarch64-tbl.h: Add initialiser for verifier field.
 979         (LDPSW): Set verifier to verify_ldpsw.
 980
 981 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 982
 983         PR binutils/19983
 984         PR binutils/19984
 985         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 986         smaller than address size.
 987
 988 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 989
 990         * alpha-dis.c: Regenerate.
 991         * crx-dis.c: Likewise.
 992         * disassemble.c: Likewise.
 993         * epiphany-opc.c: Likewise.
 994         * fr30-opc.c: Likewise.
 995         * frv-opc.c: Likewise.
 996         * ip2k-opc.c: Likewise.
 997         * iq2000-opc.c: Likewise.
 998         * lm32-opc.c: Likewise.
 999         * lm32-opinst.c: Likewise.
1000         * m32c-opc.c: Likewise.
1001         * m32r-opc.c: Likewise.
1002         * m32r-opinst.c: Likewise.
1003         * mep-opc.c: Likewise.
1004         * mt-opc.c: Likewise.
1005         * or1k-opc.c: Likewise.
1006         * or1k-opinst.c: Likewise.
1007         * tic80-opc.c: Likewise.
1008         * xc16x-opc.c: Likewise.
1009         * xstormy16-opc.c: Likewise.
1010
1011 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1012
1013         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1014         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1015         calcsd, and calcxd instructions.
1016         * arc-opc.c (insert_nps_bitop_size): Delete.
1017         (extract_nps_bitop_size): Delete.
1018         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1019         (extract_nps_qcmp_m3): Define.
1020         (extract_nps_qcmp_m2): Define.
1021         (extract_nps_qcmp_m1): Define.
1022         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1023         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1024         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1025         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1026         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1027         NPS_QCMP_M3.
1028
1029 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1030
1031         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1032
1033 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1034
1035         * Makefile.in: Regenerated with automake 1.11.6.
1036         * aclocal.m4: Likewise.
1037
1038 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1039
1040         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1041         instructions.
1042         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1043         (extract_nps_cmem_uimm16): New function.
1044         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1045
1046 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1047
1048         * arc-dis.c (arc_insn_length): New function.
1049         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1050         (find_format): Change insnLen parameter to unsigned.
1051
1052 2016-04-13  Nick Clifton  <nickc@redhat.com>
1053
1054         PR target/19937
1055         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1056         the LD.B and LD.BU instructions.
1057
1058 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1059
1060         * arc-dis.c (find_format): Check for extension flags.
1061         (print_flags): New function.
1062         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1063         .extAuxRegister.
1064         * arc-ext.c (arcExtMap_coreRegName): Use
1065         LAST_EXTENSION_CORE_REGISTER.
1066         (arcExtMap_coreReadWrite): Likewise.
1067         (dump_ARC_extmap): Update printing.
1068         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1069         (arc_aux_regs): Add cpu field.
1070         * arc-regs.h: Add cpu field, lower case name aux registers.
1071
1072 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1073
1074         * arc-tbl.h: Add rtsc, sleep with no arguments.
1075
1076 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1077
1078         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1079         Initialize.
1080         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1081         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1082         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1083         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1084         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1085         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1086         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1087         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1088         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1089         (arc_opcode arc_opcodes): Null terminate the array.
1090         (arc_num_opcodes): Remove.
1091         * arc-ext.h (INSERT_XOP): Define.
1092         (extInstruction_t): Likewise.
1093         (arcExtMap_instName): Delete.
1094         (arcExtMap_insn): New function.
1095         (arcExtMap_genOpcode): Likewise.
1096         * arc-ext.c (ExtInstruction): Remove.
1097         (create_map): Zero initialize instruction fields.
1098         (arcExtMap_instName): Remove.
1099         (arcExtMap_insn): New function.
1100         (dump_ARC_extmap): More info while debuging.
1101         (arcExtMap_genOpcode): New function.
1102         * arc-dis.c (find_format): New function.
1103         (print_insn_arc): Use find_format.
1104         (arc_get_disassembler): Enable dump_ARC_extmap only when
1105         debugging.
1106
1107 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1108
1109         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1110         instruction bits out.
1111
1112 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1113
1114         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1115         * arc-opc.c (arc_flag_operands): Add new flags.
1116         (arc_flag_classes): Add new classes.
1117
1118 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1119
1120         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1121
1122 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1123
1124         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1125         encode1, rflt, crc16, and crc32 instructions.
1126         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1127         (arc_flag_classes): Add C_NPS_R.
1128         (insert_nps_bitop_size_2b): New function.
1129         (extract_nps_bitop_size_2b): Likewise.
1130         (insert_nps_bitop_uimm8): Likewise.
1131         (extract_nps_bitop_uimm8): Likewise.
1132         (arc_operands): Add new operand entries.
1133
1134 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1135
1136         * arc-regs.h: Add a new subclass field.  Add double assist
1137         accumulator register values.
1138         * arc-tbl.h: Use DPA subclass to mark the double assist
1139         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1140         * arc-opc.c (RSP): Define instead of SP.
1141         (arc_aux_regs): Add the subclass field.
1142
1143 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1144
1145         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1146
1147 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1148
1149         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1150         NPS_R_SRC1.
1151
1152 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1153
1154         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1155         issues.  No functional changes.
1156
1157 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1158
1159         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1160         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1161         (RTT): Remove duplicate.
1162         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1163         (PCT_CONFIG*): Remove.
1164         (D1L, D1H, D2H, D2L): Define.
1165
1166 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1167
1168         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1169
1170 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1171
1172         * arc-tbl.h (invld07): Remove.
1173         * arc-ext-tbl.h: New file.
1174         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1175         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1176
1177 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1178
1179         Fix -Wstack-usage warnings.
1180         * aarch64-dis.c (print_operands): Substitute size.
1181         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1182
1183 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1184
1185         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1186         to get a proper diagnostic when an invalid ASR register is used.
1187
1188 2016-03-22  Nick Clifton  <nickc@redhat.com>
1189
1190         * configure: Regenerate.
1191
1192 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1193
1194         * arc-nps400-tbl.h: New file.
1195         * arc-opc.c: Add top level comment.
1196         (insert_nps_3bit_dst): New function.
1197         (extract_nps_3bit_dst): New function.
1198         (insert_nps_3bit_src2): New function.
1199         (extract_nps_3bit_src2): New function.
1200         (insert_nps_bitop_size): New function.
1201         (extract_nps_bitop_size): New function.
1202         (arc_flag_operands): Add nps400 entries.
1203         (arc_flag_classes): Add nps400 entries.
1204         (arc_operands): Add nps400 entries.
1205         (arc_opcodes): Add nps400 include.
1206
1207 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1208
1209         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1210         the new class enum values.
1211
1212 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1213
1214         * arc-dis.c (print_insn_arc): Handle nps400.
1215
1216 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1217
1218         * arc-opc.c (BASE): Delete.
1219
1220 2016-03-18  Nick Clifton  <nickc@redhat.com>
1221
1222         PR target/19721
1223         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1224         of MOV insn that aliases an ORR insn.
1225
1226 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1227
1228         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1229
1230 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1231
1232         * mcore-opc.h: Add const qualifiers.
1233         * microblaze-opc.h (struct op_code_struct): Likewise.
1234         * sh-opc.h: Likewise.
1235         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1236         (tic4x_print_op): Likewise.
1237
1238 2016-03-02  Alan Modra  <amodra@gmail.com>
1239
1240         * or1k-desc.h: Regenerate.
1241         * fr30-ibld.c: Regenerate.
1242         * rl78-decode.c: Regenerate.
1243
1244 2016-03-01  Nick Clifton  <nickc@redhat.com>
1245
1246         PR target/19747
1247         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1248
1249 2016-02-24  Renlin Li  <renlin.li@arm.com>
1250
1251         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1252         (print_insn_coprocessor): Support fp16 instructions.
1253
1254 2016-02-24  Renlin Li  <renlin.li@arm.com>
1255
1256         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1257         vminnm, vrint(mpna).
1258
1259 2016-02-24  Renlin Li  <renlin.li@arm.com>
1260
1261         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1262         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1263
1264 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1265
1266         * i386-dis.c (print_insn): Parenthesize expression to prevent
1267         truncated addresses.
1268         (OP_J): Likewise.
1269
1270 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1271             Janek van Oirschot  <jvanoirs@synopsys.com>
1272
1273         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1274         variable.
1275
1276 2016-02-04  Nick Clifton  <nickc@redhat.com>
1277
1278         PR target/19561
1279         * msp430-dis.c (print_insn_msp430): Add a special case for
1280         decoding an RRC instruction with the ZC bit set in the extension
1281         word.
1282
1283 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1284
1285         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1286         * epiphany-ibld.c: Regenerate.
1287         * fr30-ibld.c: Regenerate.
1288         * frv-ibld.c: Regenerate.
1289         * ip2k-ibld.c: Regenerate.
1290         * iq2000-ibld.c: Regenerate.
1291         * lm32-ibld.c: Regenerate.
1292         * m32c-ibld.c: Regenerate.
1293         * m32r-ibld.c: Regenerate.
1294         * mep-ibld.c: Regenerate.
1295         * mt-ibld.c: Regenerate.
1296         * or1k-ibld.c: Regenerate.
1297         * xc16x-ibld.c: Regenerate.
1298         * xstormy16-ibld.c: Regenerate.
1299
1300 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1301
1302         * epiphany-dis.c: Regenerated from latest cpu files.
1303
1304 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1305
1306         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1307         test bit.
1308
1309 2016-01-25  Renlin Li  <renlin.li@arm.com>
1310
1311         * arm-dis.c (mapping_symbol_for_insn): New function.
1312         (find_ifthen_state): Call mapping_symbol_for_insn().
1313
1314 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1315
1316         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1317         of MSR UAO immediate operand.
1318
1319 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1320
1321         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1322         instruction support.
1323
1324 2016-01-17  Alan Modra  <amodra@gmail.com>
1325
1326         * configure: Regenerate.
1327
1328 2016-01-14  Nick Clifton  <nickc@redhat.com>
1329
1330         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1331         instructions that can support stack pointer operations.
1332         * rl78-decode.c: Regenerate.
1333         * rl78-dis.c: Fix display of stack pointer in MOVW based
1334         instructions.
1335
1336 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1337
1338         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1339         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1340         erxtatus_el1 and erxaddr_el1.
1341
1342 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1343
1344         * arm-dis.c (arm_opcodes): Add "esb".
1345         (thumb_opcodes): Likewise.
1346
1347 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1348
1349         * ppc-opc.c <xscmpnedp>: Delete.
1350         <xvcmpnedp>: Likewise.
1351         <xvcmpnedp.>: Likewise.
1352         <xvcmpnesp>: Likewise.
1353         <xvcmpnesp.>: Likewise.
1354
1355 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1356
1357         PR gas/13050
1358         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1359         addition to ISA_A.
1360
1361 2016-01-01  Alan Modra  <amodra@gmail.com>
1362
1363         Update year range in copyright notice of all files.
1364
1365 For older changes see ChangeLog-2015
1366 \f
1367 Copyright (C) 2016 Free Software Foundation, Inc.
1368
1369 Copying and distribution of this file, with or without modification,
1370 are permitted in any medium without royalty provided the copyright
1371 notice and this notice are preserved.
1372
1373 Local Variables:
1374 mode: change-log
1375 left-margin: 8
1376 fill-column: 74
1377 version-control: never
1378 End: