opcodes/ChangeLog

   1 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-opc.c (aarch64_sys_regs): New entries for
   4         rndr and rndrrs.
   5         (aarch64_sys_reg_supported_p): New check for above.
   6
   7 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
   8
   9         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
  10         (aarch64_sys_ins_reg_supported_p): New check for above.
  11
  12 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  13
  14         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
  15         AARCH64_OPND_SYSREG_SR.
  16         * aarch64-opc.c (aarch64_print_operand): Likewise.
  17         (aarch64_sys_regs_sr): Define table.
  18         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
  19         AARCH64_FEATURE_PREDRES.
  20         * aarch64-tbl.h (aarch64_feature_predres): New.
  21         (PREDRES, PREDRES_INSN): New.
  22         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
  23         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
  24         * aarch64-asm-2.c: Regenerate.
  25         * aarch64-dis-2.c: Regenerate.
  26         * aarch64-opc-2.c: Regenerate.
  27
  28 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  29
  30         * aarch64-tbl.h (aarch64_feature_sb): New.
  31         (SB, SB_INSN): New.
  32         (aarch64_opcode_table): Add entry for sb.
  33         * aarch64-asm-2.c: Regenerate.
  34         * aarch64-dis-2.c: Regenerate.
  35         * aarch64-opc-2.c: Regenerate.
  36
  37 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  38
  39         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
  40         (aarch64_feature_frintts): New.
  41         (FLAGMANIP, FRINTTS): New.
  42         (aarch64_opcode_table): Add entries for xaflag, axflag
  43         and frint[32,64][x,z] instructions.
  44         * aarch64-asm-2.c: Regenerate.
  45         * aarch64-dis-2.c: Regenerate.
  46         * aarch64-opc-2.c: Regenerate.
  47
  48 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  49
  50         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
  51         (ARMV8_5, V8_5_INSN): New.
  52
  53 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
  54
  55         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
  56
  57 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
  58
  59         * i386-dis.c (rm_table): Add enclv.
  60         * i386-opc.tbl: Add enclv.
  61         * i386-tbl.h: Regenerated.
  62
  63 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
  64
  65         * arm-dis.c (arm_opcodes): Add sb.
  66         (thumb32_opcodes): Likewise.
  67
  68 2018-10-05  Richard Henderson  <rth@twiddle.net>
  69             Stafford Horne  <shorne@gmail.com>
  70
  71         * or1k-desc.c: Regenerate.
  72         * or1k-desc.h: Regenerate.
  73         * or1k-opc.c: Regenerate.
  74         * or1k-opc.h: Regenerate.
  75         * or1k-opinst.c: Regenerate.
  76
  77 2018-10-05  Richard Henderson  <rth@twiddle.net>
  78
  79         * or1k-asm.c: Regenerated.
  80         * or1k-desc.c: Regenerated.
  81         * or1k-desc.h: Regenerated.
  82         * or1k-dis.c: Regenerated.
  83         * or1k-ibld.c: Regenerated.
  84         * or1k-opc.c: Regenerated.
  85         * or1k-opc.h: Regenerated.
  86         * or1k-opinst.c: Regenerated.
  87
  88 2018-10-05  Richard Henderson  <rth@twiddle.net>
  89
  90         * or1k-asm.c: Regenerate.
  91
  92 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  93
  94         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
  95         * aarch64-dis.c (print_operands): Refactor to take notes.
  96         (print_verifier_notes): New.
  97         (print_aarch64_insn): Apply constraint verifier.
  98         (print_insn_aarch64_word): Update call to print_aarch64_insn.
  99         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 100
 101 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 102
 103         * aarch64-opc.c (init_insn_block): New.
 104         (verify_constraints, aarch64_is_destructive_by_operands): New.
 105         * aarch64-opc.h (verify_constraints): New.
 106
 107 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 108
 109         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 110         * aarch64-opc.c (verify_ldpsw): Update arguments.
 111
 112 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 113
 114         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 115         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 116
 117 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 118
 119         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 120         * aarch64-dis.c (insn_sequence): New.
 121
 122 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 123
 124         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 125         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 126         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 127         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 128         constraints.
 129         (_SVE_INSNC): New.
 130         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 131         constraints.
 132         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 133         F_SCAN flags.
 134         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 135         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 136         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 137         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 138         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 139         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 140         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 141
 142 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 143
 144         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 145
 146 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 147
 148         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 149         are used when extracting signed fields and converting them to
 150         potentially 64-bit types.
 151
 152 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 153
 154         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 155         * Makefile.in: Re-generate.
 156         * aclocal.m4: Re-generate.
 157         * configure: Re-generate.
 158         * configure.ac: Remove check for -Wno-missing-field-initializers.
 159         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 160         (csky_v2_opcodes): Likewise.
 161
 162 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 163
 164         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 165
 166 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 167
 168         * nds32-asm.c (operand_fields): Remove the unused fields.
 169         (nds32_opcodes): Remove the unused instructions.
 170         * nds32-dis.c (nds32_ex9_info): Removed.
 171         (nds32_parse_opcode): Updated.
 172         (print_insn_nds32): Likewise.
 173         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 174         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 175         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 176         build_opcode_hash_table): New functions.
 177         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 178         nds32_opcode_table): New.
 179         (hw_ktabs): Declare it to a pointer rather than an array.
 180         (build_hash_table): Removed.
 181         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 182         SYN_ROPT and upadte HW_GPR and HW_INT.
 183         * nds32-dis.c (keywords): Remove const.
 184         (match_field): New function.
 185         (nds32_parse_opcode): Updated.
 186         * disassemble.c (disassemble_init_for_target):
 187         Add disassemble_init_nds32.
 188         * nds32-dis.c (eum map_type): New.
 189         (nds32_private_data): Likewise.
 190         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 191         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 192         (print_insn_nds32): Updated.
 193         * nds32-asm.c (parse_aext_reg): Add new parameter.
 194         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 195         are allowed to use.
 196         All callers changed.
 197         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 198         (operand_fields): Add new fields.
 199         (nds32_opcodes): Add new instructions.
 200         (keyword_aridxi_mx): New keyword.
 201         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 202         and NASM_ATTR_ZOL.
 203         (ALU2_1, ALU2_2, ALU2_3): New macros.
 204         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 205
 206 2018-09-17  Kito Cheng  <kito@andestech.com>
 207
 208         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 209
 210 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         PR gas/23670
 213         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 214         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 215         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 216         (EVEX_LEN_0F7E_P_1): Likewise.
 217         (EVEX_LEN_0F7E_P_2): Likewise.
 218         (EVEX_LEN_0FD6_P_2): Likewise.
 219         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 220         (EVEX_LEN_TABLE): Likewise.
 221         (EVEX_LEN_0F6E_P_2): New enum.
 222         (EVEX_LEN_0F7E_P_1): Likewise.
 223         (EVEX_LEN_0F7E_P_2): Likewise.
 224         (EVEX_LEN_0FD6_P_2): Likewise.
 225         (evex_len_table): New.
 226         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 227         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 228         * i386-tbl.h: Regenerated.
 229
 230 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         PR gas/23665
 233         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 234         VEX_LEN_0F7E_P_2 entries.
 235         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 236         * i386-tbl.h: Regenerated.
 237
 238 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 239
 240         * i386-dis.c (VZERO_Fixup): Removed.
 241         (VZERO): Likewise.
 242         (VEX_LEN_0F10_P_1): Likewise.
 243         (VEX_LEN_0F10_P_3): Likewise.
 244         (VEX_LEN_0F11_P_1): Likewise.
 245         (VEX_LEN_0F11_P_3): Likewise.
 246         (VEX_LEN_0F2E_P_0): Likewise.
 247         (VEX_LEN_0F2E_P_2): Likewise.
 248         (VEX_LEN_0F2F_P_0): Likewise.
 249         (VEX_LEN_0F2F_P_2): Likewise.
 250         (VEX_LEN_0F51_P_1): Likewise.
 251         (VEX_LEN_0F51_P_3): Likewise.
 252         (VEX_LEN_0F52_P_1): Likewise.
 253         (VEX_LEN_0F53_P_1): Likewise.
 254         (VEX_LEN_0F58_P_1): Likewise.
 255         (VEX_LEN_0F58_P_3): Likewise.
 256         (VEX_LEN_0F59_P_1): Likewise.
 257         (VEX_LEN_0F59_P_3): Likewise.
 258         (VEX_LEN_0F5A_P_1): Likewise.
 259         (VEX_LEN_0F5A_P_3): Likewise.
 260         (VEX_LEN_0F5C_P_1): Likewise.
 261         (VEX_LEN_0F5C_P_3): Likewise.
 262         (VEX_LEN_0F5D_P_1): Likewise.
 263         (VEX_LEN_0F5D_P_3): Likewise.
 264         (VEX_LEN_0F5E_P_1): Likewise.
 265         (VEX_LEN_0F5E_P_3): Likewise.
 266         (VEX_LEN_0F5F_P_1): Likewise.
 267         (VEX_LEN_0F5F_P_3): Likewise.
 268         (VEX_LEN_0FC2_P_1): Likewise.
 269         (VEX_LEN_0FC2_P_3): Likewise.
 270         (VEX_LEN_0F3A0A_P_2): Likewise.
 271         (VEX_LEN_0F3A0B_P_2): Likewise.
 272         (VEX_W_0F10_P_0): Likewise.
 273         (VEX_W_0F10_P_1): Likewise.
 274         (VEX_W_0F10_P_2): Likewise.
 275         (VEX_W_0F10_P_3): Likewise.
 276         (VEX_W_0F11_P_0): Likewise.
 277         (VEX_W_0F11_P_1): Likewise.
 278         (VEX_W_0F11_P_2): Likewise.
 279         (VEX_W_0F11_P_3): Likewise.
 280         (VEX_W_0F12_P_0_M_0): Likewise.
 281         (VEX_W_0F12_P_0_M_1): Likewise.
 282         (VEX_W_0F12_P_1): Likewise.
 283         (VEX_W_0F12_P_2): Likewise.
 284         (VEX_W_0F12_P_3): Likewise.
 285         (VEX_W_0F13_M_0): Likewise.
 286         (VEX_W_0F14): Likewise.
 287         (VEX_W_0F15): Likewise.
 288         (VEX_W_0F16_P_0_M_0): Likewise.
 289         (VEX_W_0F16_P_0_M_1): Likewise.
 290         (VEX_W_0F16_P_1): Likewise.
 291         (VEX_W_0F16_P_2): Likewise.
 292         (VEX_W_0F17_M_0): Likewise.
 293         (VEX_W_0F28): Likewise.
 294         (VEX_W_0F29): Likewise.
 295         (VEX_W_0F2B_M_0): Likewise.
 296         (VEX_W_0F2E_P_0): Likewise.
 297         (VEX_W_0F2E_P_2): Likewise.
 298         (VEX_W_0F2F_P_0): Likewise.
 299         (VEX_W_0F2F_P_2): Likewise.
 300         (VEX_W_0F50_M_0): Likewise.
 301         (VEX_W_0F51_P_0): Likewise.
 302         (VEX_W_0F51_P_1): Likewise.
 303         (VEX_W_0F51_P_2): Likewise.
 304         (VEX_W_0F51_P_3): Likewise.
 305         (VEX_W_0F52_P_0): Likewise.
 306         (VEX_W_0F52_P_1): Likewise.
 307         (VEX_W_0F53_P_0): Likewise.
 308         (VEX_W_0F53_P_1): Likewise.
 309         (VEX_W_0F58_P_0): Likewise.
 310         (VEX_W_0F58_P_1): Likewise.
 311         (VEX_W_0F58_P_2): Likewise.
 312         (VEX_W_0F58_P_3): Likewise.
 313         (VEX_W_0F59_P_0): Likewise.
 314         (VEX_W_0F59_P_1): Likewise.
 315         (VEX_W_0F59_P_2): Likewise.
 316         (VEX_W_0F59_P_3): Likewise.
 317         (VEX_W_0F5A_P_0): Likewise.
 318         (VEX_W_0F5A_P_1): Likewise.
 319         (VEX_W_0F5A_P_3): Likewise.
 320         (VEX_W_0F5B_P_0): Likewise.
 321         (VEX_W_0F5B_P_1): Likewise.
 322         (VEX_W_0F5B_P_2): Likewise.
 323         (VEX_W_0F5C_P_0): Likewise.
 324         (VEX_W_0F5C_P_1): Likewise.
 325         (VEX_W_0F5C_P_2): Likewise.
 326         (VEX_W_0F5C_P_3): Likewise.
 327         (VEX_W_0F5D_P_0): Likewise.
 328         (VEX_W_0F5D_P_1): Likewise.
 329         (VEX_W_0F5D_P_2): Likewise.
 330         (VEX_W_0F5D_P_3): Likewise.
 331         (VEX_W_0F5E_P_0): Likewise.
 332         (VEX_W_0F5E_P_1): Likewise.
 333         (VEX_W_0F5E_P_2): Likewise.
 334         (VEX_W_0F5E_P_3): Likewise.
 335         (VEX_W_0F5F_P_0): Likewise.
 336         (VEX_W_0F5F_P_1): Likewise.
 337         (VEX_W_0F5F_P_2): Likewise.
 338         (VEX_W_0F5F_P_3): Likewise.
 339         (VEX_W_0F60_P_2): Likewise.
 340         (VEX_W_0F61_P_2): Likewise.
 341         (VEX_W_0F62_P_2): Likewise.
 342         (VEX_W_0F63_P_2): Likewise.
 343         (VEX_W_0F64_P_2): Likewise.
 344         (VEX_W_0F65_P_2): Likewise.
 345         (VEX_W_0F66_P_2): Likewise.
 346         (VEX_W_0F67_P_2): Likewise.
 347         (VEX_W_0F68_P_2): Likewise.
 348         (VEX_W_0F69_P_2): Likewise.
 349         (VEX_W_0F6A_P_2): Likewise.
 350         (VEX_W_0F6B_P_2): Likewise.
 351         (VEX_W_0F6C_P_2): Likewise.
 352         (VEX_W_0F6D_P_2): Likewise.
 353         (VEX_W_0F6F_P_1): Likewise.
 354         (VEX_W_0F6F_P_2): Likewise.
 355         (VEX_W_0F70_P_1): Likewise.
 356         (VEX_W_0F70_P_2): Likewise.
 357         (VEX_W_0F70_P_3): Likewise.
 358         (VEX_W_0F71_R_2_P_2): Likewise.
 359         (VEX_W_0F71_R_4_P_2): Likewise.
 360         (VEX_W_0F71_R_6_P_2): Likewise.
 361         (VEX_W_0F72_R_2_P_2): Likewise.
 362         (VEX_W_0F72_R_4_P_2): Likewise.
 363         (VEX_W_0F72_R_6_P_2): Likewise.
 364         (VEX_W_0F73_R_2_P_2): Likewise.
 365         (VEX_W_0F73_R_3_P_2): Likewise.
 366         (VEX_W_0F73_R_6_P_2): Likewise.
 367         (VEX_W_0F73_R_7_P_2): Likewise.
 368         (VEX_W_0F74_P_2): Likewise.
 369         (VEX_W_0F75_P_2): Likewise.
 370         (VEX_W_0F76_P_2): Likewise.
 371         (VEX_W_0F77_P_0): Likewise.
 372         (VEX_W_0F7C_P_2): Likewise.
 373         (VEX_W_0F7C_P_3): Likewise.
 374         (VEX_W_0F7D_P_2): Likewise.
 375         (VEX_W_0F7D_P_3): Likewise.
 376         (VEX_W_0F7E_P_1): Likewise.
 377         (VEX_W_0F7F_P_1): Likewise.
 378         (VEX_W_0F7F_P_2): Likewise.
 379         (VEX_W_0FAE_R_2_M_0): Likewise.
 380         (VEX_W_0FAE_R_3_M_0): Likewise.
 381         (VEX_W_0FC2_P_0): Likewise.
 382         (VEX_W_0FC2_P_1): Likewise.
 383         (VEX_W_0FC2_P_2): Likewise.
 384         (VEX_W_0FC2_P_3): Likewise.
 385         (VEX_W_0FD0_P_2): Likewise.
 386         (VEX_W_0FD0_P_3): Likewise.
 387         (VEX_W_0FD1_P_2): Likewise.
 388         (VEX_W_0FD2_P_2): Likewise.
 389         (VEX_W_0FD3_P_2): Likewise.
 390         (VEX_W_0FD4_P_2): Likewise.
 391         (VEX_W_0FD5_P_2): Likewise.
 392         (VEX_W_0FD6_P_2): Likewise.
 393         (VEX_W_0FD7_P_2_M_1): Likewise.
 394         (VEX_W_0FD8_P_2): Likewise.
 395         (VEX_W_0FD9_P_2): Likewise.
 396         (VEX_W_0FDA_P_2): Likewise.
 397         (VEX_W_0FDB_P_2): Likewise.
 398         (VEX_W_0FDC_P_2): Likewise.
 399         (VEX_W_0FDD_P_2): Likewise.
 400         (VEX_W_0FDE_P_2): Likewise.
 401         (VEX_W_0FDF_P_2): Likewise.
 402         (VEX_W_0FE0_P_2): Likewise.
 403         (VEX_W_0FE1_P_2): Likewise.
 404         (VEX_W_0FE2_P_2): Likewise.
 405         (VEX_W_0FE3_P_2): Likewise.
 406         (VEX_W_0FE4_P_2): Likewise.
 407         (VEX_W_0FE5_P_2): Likewise.
 408         (VEX_W_0FE6_P_1): Likewise.
 409         (VEX_W_0FE6_P_2): Likewise.
 410         (VEX_W_0FE6_P_3): Likewise.
 411         (VEX_W_0FE7_P_2_M_0): Likewise.
 412         (VEX_W_0FE8_P_2): Likewise.
 413         (VEX_W_0FE9_P_2): Likewise.
 414         (VEX_W_0FEA_P_2): Likewise.
 415         (VEX_W_0FEB_P_2): Likewise.
 416         (VEX_W_0FEC_P_2): Likewise.
 417         (VEX_W_0FED_P_2): Likewise.
 418         (VEX_W_0FEE_P_2): Likewise.
 419         (VEX_W_0FEF_P_2): Likewise.
 420         (VEX_W_0FF0_P_3_M_0): Likewise.
 421         (VEX_W_0FF1_P_2): Likewise.
 422         (VEX_W_0FF2_P_2): Likewise.
 423         (VEX_W_0FF3_P_2): Likewise.
 424         (VEX_W_0FF4_P_2): Likewise.
 425         (VEX_W_0FF5_P_2): Likewise.
 426         (VEX_W_0FF6_P_2): Likewise.
 427         (VEX_W_0FF7_P_2): Likewise.
 428         (VEX_W_0FF8_P_2): Likewise.
 429         (VEX_W_0FF9_P_2): Likewise.
 430         (VEX_W_0FFA_P_2): Likewise.
 431         (VEX_W_0FFB_P_2): Likewise.
 432         (VEX_W_0FFC_P_2): Likewise.
 433         (VEX_W_0FFD_P_2): Likewise.
 434         (VEX_W_0FFE_P_2): Likewise.
 435         (VEX_W_0F3800_P_2): Likewise.
 436         (VEX_W_0F3801_P_2): Likewise.
 437         (VEX_W_0F3802_P_2): Likewise.
 438         (VEX_W_0F3803_P_2): Likewise.
 439         (VEX_W_0F3804_P_2): Likewise.
 440         (VEX_W_0F3805_P_2): Likewise.
 441         (VEX_W_0F3806_P_2): Likewise.
 442         (VEX_W_0F3807_P_2): Likewise.
 443         (VEX_W_0F3808_P_2): Likewise.
 444         (VEX_W_0F3809_P_2): Likewise.
 445         (VEX_W_0F380A_P_2): Likewise.
 446         (VEX_W_0F380B_P_2): Likewise.
 447         (VEX_W_0F3817_P_2): Likewise.
 448         (VEX_W_0F381C_P_2): Likewise.
 449         (VEX_W_0F381D_P_2): Likewise.
 450         (VEX_W_0F381E_P_2): Likewise.
 451         (VEX_W_0F3820_P_2): Likewise.
 452         (VEX_W_0F3821_P_2): Likewise.
 453         (VEX_W_0F3822_P_2): Likewise.
 454         (VEX_W_0F3823_P_2): Likewise.
 455         (VEX_W_0F3824_P_2): Likewise.
 456         (VEX_W_0F3825_P_2): Likewise.
 457         (VEX_W_0F3828_P_2): Likewise.
 458         (VEX_W_0F3829_P_2): Likewise.
 459         (VEX_W_0F382A_P_2_M_0): Likewise.
 460         (VEX_W_0F382B_P_2): Likewise.
 461         (VEX_W_0F3830_P_2): Likewise.
 462         (VEX_W_0F3831_P_2): Likewise.
 463         (VEX_W_0F3832_P_2): Likewise.
 464         (VEX_W_0F3833_P_2): Likewise.
 465         (VEX_W_0F3834_P_2): Likewise.
 466         (VEX_W_0F3835_P_2): Likewise.
 467         (VEX_W_0F3837_P_2): Likewise.
 468         (VEX_W_0F3838_P_2): Likewise.
 469         (VEX_W_0F3839_P_2): Likewise.
 470         (VEX_W_0F383A_P_2): Likewise.
 471         (VEX_W_0F383B_P_2): Likewise.
 472         (VEX_W_0F383C_P_2): Likewise.
 473         (VEX_W_0F383D_P_2): Likewise.
 474         (VEX_W_0F383E_P_2): Likewise.
 475         (VEX_W_0F383F_P_2): Likewise.
 476         (VEX_W_0F3840_P_2): Likewise.
 477         (VEX_W_0F3841_P_2): Likewise.
 478         (VEX_W_0F38DB_P_2): Likewise.
 479         (VEX_W_0F3A08_P_2): Likewise.
 480         (VEX_W_0F3A09_P_2): Likewise.
 481         (VEX_W_0F3A0A_P_2): Likewise.
 482         (VEX_W_0F3A0B_P_2): Likewise.
 483         (VEX_W_0F3A0C_P_2): Likewise.
 484         (VEX_W_0F3A0D_P_2): Likewise.
 485         (VEX_W_0F3A0E_P_2): Likewise.
 486         (VEX_W_0F3A0F_P_2): Likewise.
 487         (VEX_W_0F3A21_P_2): Likewise.
 488         (VEX_W_0F3A40_P_2): Likewise.
 489         (VEX_W_0F3A41_P_2): Likewise.
 490         (VEX_W_0F3A42_P_2): Likewise.
 491         (VEX_W_0F3A62_P_2): Likewise.
 492         (VEX_W_0F3A63_P_2): Likewise.
 493         (VEX_W_0F3ADF_P_2): Likewise.
 494         (VEX_LEN_0F77_P_0): New.
 495         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 496         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 497         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 498         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 499         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 500         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 501         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 502         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 503         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 504         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 505         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 506         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 507         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 508         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 509         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 510         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 511         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 512         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 513         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 514         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 515         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 516         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 517         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 518         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 519         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 520         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 521         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 522         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 523         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 524         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 525         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 526         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 527         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 528         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 529         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 530         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 531         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 532         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 533         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 534         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 535         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 536         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 537         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 538         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 539         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 540         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 541         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 542         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 543         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 544         (vex_table): Update VEX 0F28 and 0F29 entries.
 545         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 546         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 547         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 548         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 549         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 550         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 551         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 552         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 553         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 554         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 555         VEX_LEN_0F3A0B_P_2 entries.
 556         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 557         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 558         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 559         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 560         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 561         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 562         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 563         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 564         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 565         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 566         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 567         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 568         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 569         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 570         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 571         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 572         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 573         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 574         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 575         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 576         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 577         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 578         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 579         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 580         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 581         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 582         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 583         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 584         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 585         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 586         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 587         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 588         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 589         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 590         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 591         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 592         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 593         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 594         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 595         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 596         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 597         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 598         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 599         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 600         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 601         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 602         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 603         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 604         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 605         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 606         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 607         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 608         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 609         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 610         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 611         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 612         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 613         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 614         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 615         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 616         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 617         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 618         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 619         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 620         VEX_W_0F3ADF_P_2 entries.
 621         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 622         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 623         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 624
 625 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 626
 627         * i386-opc.tbl (VexWIG): New.
 628         Replace VexW=3 with VexWIG.
 629
 630 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 631
 632         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 633         * i386-tbl.h: Regenerated.
 634
 635 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 636
 637         PR gas/23665
 638         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 639         VEX_LEN_0FD6_P_2 entries.
 640         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 641         * i386-tbl.h: Regenerated.
 642
 643 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         PR gas/23642
 646         * i386-opc.h (VEXWIG): New.
 647         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 648         * i386-tbl.h: Regenerated.
 649
 650 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 651
 652         PR binutils/23655
 653         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 654         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 655         * i386-dis.c (EXxEVexR64): New.
 656         (evex_rounding_64_mode): Likewise.
 657         (OP_Rounding): Handle evex_rounding_64_mode.
 658
 659 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 660
 661         PR binutils/23655
 662         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 663         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 664         * i386-dis.c (Edqa): New.
 665         (dqa_mode): Likewise.
 666         (intel_operand_size): Handle dqa_mode as m_mode.
 667         (OP_E_register): Handle dqa_mode as dq_mode.
 668         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 669
 670 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 671
 672         * i386-dis.c (OP_E_memory): Reformat.
 673
 674 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 675
 676         * i386-opc.tbl (crc32): Fold byte and word forms.
 677         * i386-tbl.h: Re-generate.
 678
 679 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 682         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 683         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 684         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 685         * i386-tbl.h: Regenerated.
 686
 687 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 688
 689         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 690         meaningless.
 691         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 692         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 693         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 694         * i386-tbl.h: Re-generate.
 695
 696 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 699         AVX512_4VNNIW insns.
 700         * i386-tbl.h: Re-generate.
 701
 702 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 703
 704         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 705         meaningless.
 706         * i386-tbl.h: Re-generate.
 707
 708 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 709
 710         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 711         meaningless.
 712         * i386-tbl.h: Re-generate.
 713
 714 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 715
 716         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 717         meaningless.
 718         * i386-tbl.h: Re-generate.
 719
 720 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 721
 722         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 723         meaningless.
 724         * i386-tbl.h: Re-generate.
 725
 726 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 729         meaningless.
 730         * i386-tbl.h: Re-generate.
 731
 732 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 733
 734         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 735         * i386-tbl.h: Re-generate.
 736
 737 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 738
 739         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 740         * i386-tbl.h: Re-generate.
 741
 742 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 745         meaningless.
 746         * i386-tbl.h: Re-generate.
 747
 748 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 751         meaningless.
 752         * i386-tbl.h: Re-generate.
 753
 754 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 757         * i386-tbl.h: Re-generate.
 758
 759 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 760
 761         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 762         * i386-tbl.h: Re-generate.
 763
 764 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 765
 766         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 767         * i386-tbl.h: Re-generate.
 768
 769 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 772         meaningless.
 773         * i386-tbl.h: Re-generate.
 774
 775 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 776
 777         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 778         meaningless.
 779         * i386-tbl.h: Re-generate.
 780
 781 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 782
 783         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 784         meaningless.
 785         * i386-tbl.h: Re-generate.
 786
 787 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 790         * i386-tbl.h: Re-generate.
 791
 792 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 793
 794         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 795         * i386-tbl.h: Re-generate.
 796
 797 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 798
 799         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 800         * i386-tbl.h: Re-generate.
 801
 802 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 805         (vpbroadcastw, rdpid): Drop NoRex64.
 806         * i386-tbl.h: Re-generate.
 807
 808 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 809
 810         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 811         store templates, adding D.
 812         * i386-tbl.h: Re-generate.
 813
 814 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 817         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 818         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 819         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 820         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 821         Fold load and store templates where possible, adding D. Drop
 822         IgnoreSize where it was pointlessly present. Drop redundant
 823         *word.
 824         * i386-tbl.h: Re-generate.
 825
 826 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 829         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 830         (intel_operand_size): Handle v_bndmk_mode.
 831         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 832
 833 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 834
 835         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 836
 837 2018-08-31  Kito Cheng  <kito@andestech.com>
 838
 839         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 840         compressed floating point instructions.
 841
 842 2018-08-30  Kito Cheng  <kito@andestech.com>
 843
 844         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 845         riscv_opcode.xlen_requirement.
 846         * riscv-opc.c (riscv_opcodes): Update for struct change.
 847
 848 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 849
 850         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 851         psr (PWRPSR) instruction.
 852
 853 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 854
 855         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 856
 857 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 858
 859         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 860
 861 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 862
 863         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 864         loongson3a as an alias of gs464 for compatibility.
 865         * mips-opc.c (mips_opcodes): Change Comments.
 866
 867 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 868
 869         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 870         option.
 871         (print_mips_disassembler_options): Document -M loongson-ext.
 872         * mips-opc.c (LEXT2): New macro.
 873         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 874
 875 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 876
 877          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 878          descriptors.
 879          (parse_mips_ase_option): Handle -M loongson-ext option.
 880          (print_mips_disassembler_options): Document -M loongson-ext.
 881          * mips-opc.c (IL3A): Delete.
 882          * mips-opc.c (LEXT): New macro.
 883          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 884          instructions.
 885
 886 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 887
 888         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 889         descriptors.
 890         (parse_mips_ase_option): Handle -M loongson-cam option.
 891         (print_mips_disassembler_options): Document -M loongson-cam.
 892         * mips-opc.c (LCAM): New macro.
 893         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 894         instructions.
 895
 896 2018-08-21  Alan Modra  <amodra@gmail.com>
 897
 898         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 899         (skip_optional_operands): Count optional operands, and update
 900         ppc_optional_operand_value call.
 901         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 902         (extract_vlensi): Likewise.
 903         (extract_fxm): Return default value for missing optional operand.
 904         (extract_ls, extract_raq, extract_tbr): Likewise.
 905         (insert_sxl, extract_sxl): New functions.
 906         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 907         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 908         flag and extra entry.
 909         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 910         extract_sxl.
 911
 912 2018-08-20  Alan Modra  <amodra@gmail.com>
 913
 914         * sh-opc.h (MASK): Simplify.
 915
 916 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 917
 918         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 919         BM_RESERVED0 or BM_RESERVED1
 920         (bm_rel_decode, bm_n_bytes): Ditto.
 921
 922 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 923
 924         * s12z.h: Delete.
 925
 926 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 927
 928         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 929         address with the addr32 prefix and without base nor index
 930         registers.
 931
 932 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 933
 934         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 935         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 936         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 937         (cpu_flags): Add CpuCMOV and CpuFXSR.
 938         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 939         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 940         * i386-init.h: Regenerated.
 941         * i386-tbl.h: Likewise.
 942
 943 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 944
 945         * arc-regs.h: Update auxiliary registers.
 946
 947 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 948
 949         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 950         (RegIP, RegIZ): Define.
 951         * i386-reg.tbl: Adjust comments.
 952         (rip): Use Qword instead of BaseIndex. Use RegIP.
 953         (eip): Use Dword instead of BaseIndex. Use RegIP.
 954         (riz): Add Qword. Use RegIZ.
 955         (eiz): Add Dword. Use RegIZ.
 956         * i386-tbl.h: Re-generate.
 957
 958 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 959
 960         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 961         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 962         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 963         * i386-tbl.h: Re-generate.
 964
 965 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-gen.c (operand_types): Remove Mem field.
 968         * i386-opc.h (union i386_operand_type): Remove mem field.
 969         * i386-init.h, i386-tbl.h: Re-generate.
 970
 971 2018-08-01  Alan Modra  <amodra@gmail.com>
 972
 973         * po/POTFILES.in: Regenerate.
 974
 975 2018-07-31  Nick Clifton  <nickc@redhat.com>
 976
 977         * po/sv.po: Updated Swedish translation.
 978
 979 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 980
 981         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 982         * i386-init.h, i386-tbl.h: Re-generate.
 983
 984 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 985
 986         * i386-opc.h (ZEROING_MASKING) Rename to ...
 987         (DYNAMIC_MASKING): ... this. Adjust comment.
 988         * i386-opc.tbl (MaskingMorZ): Define.
 989         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 990         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 991         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 992         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 993         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 994         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 995         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 996         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 997         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 998
 999 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-opc.tbl: Use element rather than vector size for AVX512*
1002         scatter/gather insns.
1003         * i386-tbl.h: Re-generate.
1004
1005 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1006
1007         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1008         (cpu_flags): Drop CpuVREX.
1009         * i386-opc.h (CpuVREX): Delete.
1010         (union i386_cpu_flags): Remove cpuvrex.
1011         * i386-init.h, i386-tbl.h: Re-generate.
1012
1013 2018-07-30  Jim Wilson  <jimw@sifive.com>
1014
1015         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1016         fields.
1017         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1018
1019 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1020
1021         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1022         * Makefile.in: Regenerated.
1023         * configure.ac: Add C-SKY.
1024         * configure: Regenerated.
1025         * csky-dis.c: New file.
1026         * csky-opc.h: New file.
1027         * disassemble.c (ARCH_csky): Define.
1028         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1029         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1030
1031 2018-07-27  Alan Modra  <amodra@gmail.com>
1032
1033         * ppc-opc.c (insert_sprbat): Correct function parameter and
1034         return type.
1035         (extract_sprbat): Likewise, variable too.
1036
1037 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1038             Alan Modra  <amodra@gmail.com>
1039
1040         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1041         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1042         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1043         support disjointed BAT.
1044         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1045         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1046         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1047
1048 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1049             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1050
1051         * i386-gen.c (adjust_broadcast_modifier): New function.
1052         (process_i386_opcode_modifier): Add an argument for operands.
1053         Adjust the Broadcast value based on operands.
1054         (output_i386_opcode): Pass operand_types to
1055         process_i386_opcode_modifier.
1056         (process_i386_opcodes): Pass NULL as operands to
1057         process_i386_opcode_modifier.
1058         * i386-opc.h (BYTE_BROADCAST): New.
1059         (WORD_BROADCAST): Likewise.
1060         (DWORD_BROADCAST): Likewise.
1061         (QWORD_BROADCAST): Likewise.
1062         (i386_opcode_modifier): Expand broadcast to 3 bits.
1063         * i386-tbl.h: Regenerated.
1064
1065 2018-07-24  Alan Modra  <amodra@gmail.com>
1066
1067         PR 23430
1068         * or1k-desc.h: Regenerate.
1069
1070 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1071
1072         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1073         vcvtusi2ss, and vcvtusi2sd.
1074         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1075         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1076         * i386-tbl.h: Re-generate.
1077
1078 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1079
1080         * arc-opc.c (extract_w6): Fix extending the sign.
1081
1082 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1083
1084         * arc-tbl.h (vewt): Allow it for ARC EM family.
1085
1086 2018-07-23  Alan Modra  <amodra@gmail.com>
1087
1088         PR 23419
1089         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1090         opcode variants for mtspr/mfspr encodings.
1091
1092 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1093             Maciej W. Rozycki  <macro@mips.com>
1094
1095         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1096         loongson3a descriptors.
1097         (parse_mips_ase_option): Handle -M loongson-mmi option.
1098         (print_mips_disassembler_options): Document -M loongson-mmi.
1099         * mips-opc.c (LMMI): New macro.
1100         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1101         instructions.
1102
1103 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1104
1105         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1106         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1107         IgnoreSize and [XYZ]MMword where applicable.
1108         * i386-tbl.h: Re-generate.
1109
1110 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1111
1112         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1113         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1114         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1115         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1116         * i386-tbl.h: Re-generate.
1117
1118 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1119
1120         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1121         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1122         VPCLMULQDQ templates into their respective AVX512VL counterparts
1123         where possible, using Disp8ShiftVL and CheckRegSize instead of
1124         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1125         * i386-tbl.h: Re-generate.
1126
1127 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1130         AVX512VL counterparts where possible, using Disp8ShiftVL and
1131         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1132         IgnoreSize) as appropriate.
1133         * i386-tbl.h: Re-generate.
1134
1135 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1136
1137         * i386-opc.tbl: Fold AVX512BW templates into their respective
1138         AVX512VL counterparts where possible, using Disp8ShiftVL and
1139         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1140         IgnoreSize) as appropriate.
1141         * i386-tbl.h: Re-generate.
1142
1143 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1144
1145         * i386-opc.tbl: Fold AVX512CD templates into their respective
1146         AVX512VL counterparts where possible, using Disp8ShiftVL and
1147         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1148         IgnoreSize) as appropriate.
1149         * i386-tbl.h: Re-generate.
1150
1151 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-opc.h (DISP8_SHIFT_VL): New.
1154         * i386-opc.tbl (Disp8ShiftVL):  Define.
1155         (various): Fold AVX512VL templates into their respective
1156         AVX512F counterparts where possible, using Disp8ShiftVL and
1157         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1158         IgnoreSize) as appropriate.
1159         * i386-tbl.h: Re-generate.
1160
1161 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1162
1163         * Makefile.am: Change dependencies and rule for
1164         $(srcdir)/i386-init.h.
1165         * Makefile.in: Re-generate.
1166         * i386-gen.c (process_i386_opcodes): New local variable
1167         "marker". Drop opening of input file. Recognize marker and line
1168         number directives.
1169         * i386-opc.tbl (OPCODE_I386_H): Define.
1170         (i386-opc.h): Include it.
1171         (None): Undefine.
1172
1173 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1174
1175         PR gas/23418
1176         * i386-opc.h (Byte): Update comments.
1177         (Word): Likewise.
1178         (Dword): Likewise.
1179         (Fword): Likewise.
1180         (Qword): Likewise.
1181         (Tbyte): Likewise.
1182         (Xmmword): Likewise.
1183         (Ymmword): Likewise.
1184         (Zmmword): Likewise.
1185         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1186         vcvttps2uqq.
1187         * i386-tbl.h: Regenerated.
1188
1189 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1190
1191         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1192         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1193         * aarch64-asm-2.c: Regenerate.
1194         * aarch64-dis-2.c: Regenerate.
1195         * aarch64-opc-2.c: Regenerate.
1196
1197 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1198
1199         PR binutils/23192
1200         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1201         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1202         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1203         sqdmulh, sqrdmulh): Use Em16.
1204
1205 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1206
1207         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1208         csdb together with them.
1209         (thumb32_opcodes): Likewise.
1210
1211 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1212
1213         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1214         requiring 32-bit registers as operands 2 and 3. Improve
1215         comments.
1216         (mwait, mwaitx): Fold templates. Improve comments.
1217         OPERAND_TYPE_INOUTPORTREG.
1218         * i386-tbl.h: Re-generate.
1219
1220 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1221
1222         * i386-gen.c (operand_type_init): Remove
1223         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1224         OPERAND_TYPE_INOUTPORTREG.
1225         * i386-init.h: Re-generate.
1226
1227 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1228
1229         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1230         (wrssq, wrussq): Add Qword.
1231         * i386-tbl.h: Re-generate.
1232
1233 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1234
1235         * i386-opc.h: Rename OTMax to OTNum.
1236         (OTNumOfUints): Adjust calculation.
1237         (OTUnused): Directly alias to OTNum.
1238
1239 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1240
1241         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1242         `reg_xys'.
1243         (lea_reg_xys): Likewise.
1244         (print_insn_loop_primitive): Rename `reg' local variable to
1245         `reg_dxy'.
1246
1247 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1248
1249         PR binutils/23242
1250         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1251
1252 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1253
1254         PR binutils/23369
1255         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1256         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1257
1258 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1259
1260         PR tdep/8282
1261         * mips-dis.c (mips_option_arg_t): New enumeration.
1262         (mips_options): New variable.
1263         (disassembler_options_mips): New function.
1264         (print_mips_disassembler_options): Reimplement in terms of
1265         `disassembler_options_mips'.
1266         * arm-dis.c (disassembler_options_arm): Adapt to using the
1267         `disasm_options_and_args_t' structure.
1268         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1269         * s390-dis.c (disassembler_options_s390): Likewise.
1270
1271 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1272
1273         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1274         expected result.
1275         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1276         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1277         * testsuite/ld-arm/tls-longplt.d: Likewise.
1278
1279 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1280
1281         PR binutils/23192
1282         * aarch64-asm-2.c: Regenerate.
1283         * aarch64-dis-2.c: Likewise.
1284         * aarch64-opc-2.c: Likewise.
1285         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1286         * aarch64-opc.c (operand_general_constraint_met_p,
1287         aarch64_print_operand): Likewise.
1288         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1289         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1290         fmlal2, fmlsl2.
1291         (AARCH64_OPERANDS): Add Em2.
1292
1293 2018-06-26  Nick Clifton  <nickc@redhat.com>
1294
1295         * po/uk.po: Updated Ukranian translation.
1296         * po/de.po: Updated German translation.
1297         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1298
1299 2018-06-26  Nick Clifton  <nickc@redhat.com>
1300
1301         * nfp-dis.c: Fix spelling mistake.
1302
1303 2018-06-24  Nick Clifton  <nickc@redhat.com>
1304
1305         * configure: Regenerate.
1306         * po/opcodes.pot: Regenerate.
1307
1308 2018-06-24  Nick Clifton  <nickc@redhat.com>
1309
1310         2.31 branch created.
1311
1312 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1313
1314         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1315         * aarch64-asm-2.c: Regenerate.
1316         * aarch64-dis-2.c: Likewise.
1317
1318 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1319
1320         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1321         `-M ginv' option description.
1322
1323 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1324
1325         PR gas/23305
1326         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1327         la and lla.
1328
1329 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1330
1331         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1332         * configure.ac: Remove AC_PREREQ.
1333         * Makefile.in: Re-generate.
1334         * aclocal.m4: Re-generate.
1335         * configure: Re-generate.
1336
1337 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1338
1339         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1340         mips64r6 descriptors.
1341         (parse_mips_ase_option): Handle -Mginv option.
1342         (print_mips_disassembler_options): Document -Mginv.
1343         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1344         (GINV): New macro.
1345         (mips_opcodes): Define ginvi and ginvt.
1346
1347 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1348             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1349
1350         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1351         * mips-opc.c (CRC, CRC64): New macros.
1352         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1353         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1354         crc32cd for CRC64.
1355
1356 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1357
1358         PR 20319
1359         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1360         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1361
1362 2018-06-06  Alan Modra  <amodra@gmail.com>
1363
1364         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1365         setjmp.  Move init for some other vars later too.
1366
1367 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1368
1369         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1370         (dis_private): Add new fields for property section tracking.
1371         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1372         (xtensa_instruction_fits): New functions.
1373         (fetch_data): Bump minimal fetch size to 4.
1374         (print_insn_xtensa): Make struct dis_private static.
1375         Load and prepare property table on section change.
1376         Don't disassemble literals. Don't disassemble instructions that
1377         cross property table boundaries.
1378
1379 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1380
1381         * configure: Regenerated.
1382
1383 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1384
1385         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1386         * i386-tbl.h: Re-generate.
1387
1388 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1389
1390         * i386-opc.tbl (sldt, str): Add NoRex64.
1391         * i386-tbl.h: Re-generate.
1392
1393 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1394
1395         * i386-opc.tbl (invpcid): Add Oword.
1396         * i386-tbl.h: Re-generate.
1397
1398 2018-06-01  Alan Modra  <amodra@gmail.com>
1399
1400         * sysdep.h (_bfd_error_handler): Don't declare.
1401         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1402         * rl78-decode.opc: Likewise.
1403         * msp430-decode.c: Regenerate.
1404         * rl78-decode.c: Regenerate.
1405
1406 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1407
1408         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1409         * i386-init.h : Regenerated.
1410
1411 2018-05-25  Alan Modra  <amodra@gmail.com>
1412
1413         * Makefile.in: Regenerate.
1414         * po/POTFILES.in: Regenerate.
1415
1416 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1417
1418         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1419         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1420         (insert_bab, extract_bab, insert_btab, extract_btab,
1421         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1422         (BAT, BBA VBA RBS XB6S): Delete macros.
1423         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1424         (BB, BD, RBX, XC6): Update for new macros.
1425         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1426         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1427         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1428         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1429
1430 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1431
1432         * Makefile.am: Add support for s12z architecture.
1433         * configure.ac: Likewise.
1434         * disassemble.c: Likewise.
1435         * disassemble.h: Likewise.
1436         * Makefile.in: Regenerate.
1437         * configure: Regenerate.
1438         * s12z-dis.c: New file.
1439         * s12z.h: New file.
1440
1441 2018-05-18  Alan Modra  <amodra@gmail.com>
1442
1443         * nfp-dis.c: Don't #include libbfd.h.
1444         (init_nfp3200_priv): Use bfd_get_section_contents.
1445         (nit_nfp6000_mecsr_sec): Likewise.
1446
1447 2018-05-17  Nick Clifton  <nickc@redhat.com>
1448
1449         * po/zh_CN.po: Updated simplified Chinese translation.
1450
1451 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1452
1453         PR binutils/23109
1454         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1455         * aarch64-dis-2.c: Regenerate.
1456
1457 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1458
1459         PR binutils/21446
1460         * aarch64-asm.c (opintl.h): Include.
1461         (aarch64_ins_sysreg): Enforce read/write constraints.
1462         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1463         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1464         (F_REG_READ, F_REG_WRITE): New.
1465         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1466         AARCH64_OPND_SYSREG.
1467         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1468         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1469         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1470         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1471         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1472         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1473         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1474         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1475         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1476         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1477         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1478         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1479         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1480         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1481         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1482         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1483         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1484
1485 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1486
1487         PR binutils/21446
1488         * aarch64-dis.c (no_notes: New.
1489         (parse_aarch64_dis_option): Support notes.
1490         (aarch64_decode_insn, print_operands): Likewise.
1491         (print_aarch64_disassembler_options): Document notes.
1492         * aarch64-opc.c (aarch64_print_operand): Support notes.
1493
1494 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1495
1496         PR binutils/21446
1497         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1498         and take error struct.
1499         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1500         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1501         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1502         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1503         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1504         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1505         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1506         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1507         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1508         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1509         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1510         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1511         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1512         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1513         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1514         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1515         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1516         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1517         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1518         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1519         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1520         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1521         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1522         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1523         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1524         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1525         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1526         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1527         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1528         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1529         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1530         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1531         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1532         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1533         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1534         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1535         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1536         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1537         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1538         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1539         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1540         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1541         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1542         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1543         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1544         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1545         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1546         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1547         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1548         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1549         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1550         (determine_disassembling_preference, aarch64_decode_insn,
1551         print_insn_aarch64_word, print_insn_data): Take errors struct.
1552         (print_insn_aarch64): Use errors.
1553         * aarch64-asm-2.c: Regenerate.
1554         * aarch64-dis-2.c: Regenerate.
1555         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1556         boolean in aarch64_insert_operan.
1557         (print_operand_extractor): Likewise.
1558         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1559
1560 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1561
1562         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1563
1564 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1565
1566         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1567
1568 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1569
1570         * cr16-opc.c (cr16_instruction): Comment typo fix.
1571         * hppa-dis.c (print_insn_hppa): Likewise.
1572
1573 2018-05-08  Jim Wilson  <jimw@sifive.com>
1574
1575         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1576         (match_c_slli64, match_srxi_as_c_srxi): New.
1577         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1578         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1579         <c.slli, c.srli, c.srai>: Use match_s_slli.
1580         <c.slli64, c.srli64, c.srai64>: New.
1581
1582 2018-05-08  Alan Modra  <amodra@gmail.com>
1583
1584         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1585         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1586         partition opcode space for index lookup.
1587
1588 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1589
1590         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1591         <insn_length>: ...with this.  Update usage.
1592         Remove duplicate call to *info->memory_error_func.
1593
1594 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1595             H.J. Lu  <hongjiu.lu@intel.com>
1596
1597         * i386-dis.c (Gva): New.
1598         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1599         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1600         (prefix_table): New instructions (see prefix above).
1601         (mod_table): New instructions (see prefix above).
1602         (OP_G): Handle va_mode.
1603         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1604         CPU_MOVDIR64B_FLAGS.
1605         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1606         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1607         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1608         * i386-opc.tbl: Add movidir{i,64b}.
1609         * i386-init.h: Regenerated.
1610         * i386-tbl.h: Likewise.
1611
1612 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1613
1614         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1615         AddrPrefixOpReg.
1616         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1617         (AddrPrefixOpReg): This.
1618         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1619         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1620
1621 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1622
1623         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1624         (vle_num_opcodes): Likewise.
1625         (spe2_num_opcodes): Likewise.
1626         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1627         initialization loop.
1628         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1629         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1630         only once.
1631
1632 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1633
1634         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1635
1636 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1637
1638         Makefile.am: Added nfp-dis.c.
1639         configure.ac: Added bfd_nfp_arch.
1640         disassemble.h: Added print_insn_nfp prototype.
1641         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1642         nfp-dis.c: New, for NFP support.
1643         po/POTFILES.in: Added nfp-dis.c to the list.
1644         Makefile.in: Regenerate.
1645         configure: Regenerate.
1646
1647 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1648
1649         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1650         templates into their base ones.
1651         * i386-tlb.h: Re-generate.
1652
1653 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1654
1655         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1656         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1657         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1658         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1659         * i386-init.h: Re-generate.
1660
1661 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1662
1663         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1664         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1665         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1666         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1667         comment.
1668         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1669         and CpuRegMask.
1670         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1671         CpuRegMask: Delete.
1672         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1673         cpuregzmm, and cpuregmask.
1674         * i386-init.h: Re-generate.
1675         * i386-tbl.h: Re-generate.
1676
1677 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1678
1679         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1680         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1681         * i386-init.h: Re-generate.
1682
1683 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1684
1685         * i386-gen.c (VexImmExt): Delete.
1686         * i386-opc.h (VexImmExt, veximmext): Delete.
1687         * i386-opc.tbl: Drop all VexImmExt uses.
1688         * i386-tlb.h: Re-generate.
1689
1690 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1691
1692         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1693         register-only forms.
1694         * i386-tlb.h: Re-generate.
1695
1696 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1697
1698         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1699
1700 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1701
1702         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1703         PREFIX_0F1C.
1704         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1705         (cpu_flags): Add CpuCLDEMOTE.
1706         * i386-init.h: Regenerate.
1707         * i386-opc.h (enum): Add CpuCLDEMOTE,
1708         (i386_cpu_flags): Add cpucldemote.
1709         * i386-opc.tbl: Add cldemote.
1710         * i386-tbl.h: Regenerate.
1711
1712 2018-04-16  Alan Modra  <amodra@gmail.com>
1713
1714         * Makefile.am: Remove sh5 and sh64 support.
1715         * configure.ac: Likewise.
1716         * disassemble.c: Likewise.
1717         * disassemble.h: Likewise.
1718         * sh-dis.c: Likewise.
1719         * sh64-dis.c: Delete.
1720         * sh64-opc.c: Delete.
1721         * sh64-opc.h: Delete.
1722         * Makefile.in: Regenerate.
1723         * configure: Regenerate.
1724         * po/POTFILES.in: Regenerate.
1725
1726 2018-04-16  Alan Modra  <amodra@gmail.com>
1727
1728         * Makefile.am: Remove w65 support.
1729         * configure.ac: Likewise.
1730         * disassemble.c: Likewise.
1731         * disassemble.h: Likewise.
1732         * w65-dis.c: Delete.
1733         * w65-opc.h: Delete.
1734         * Makefile.in: Regenerate.
1735         * configure: Regenerate.
1736         * po/POTFILES.in: Regenerate.
1737
1738 2018-04-16  Alan Modra  <amodra@gmail.com>
1739
1740         * configure.ac: Remove we32k support.
1741         * configure: Regenerate.
1742
1743 2018-04-16  Alan Modra  <amodra@gmail.com>
1744
1745         * Makefile.am: Remove m88k support.
1746         * configure.ac: Likewise.
1747         * disassemble.c: Likewise.
1748         * disassemble.h: Likewise.
1749         * m88k-dis.c: Delete.
1750         * Makefile.in: Regenerate.
1751         * configure: Regenerate.
1752         * po/POTFILES.in: Regenerate.
1753
1754 2018-04-16  Alan Modra  <amodra@gmail.com>
1755
1756         * Makefile.am: Remove i370 support.
1757         * configure.ac: Likewise.
1758         * disassemble.c: Likewise.
1759         * disassemble.h: Likewise.
1760         * i370-dis.c: Delete.
1761         * i370-opc.c: Delete.
1762         * Makefile.in: Regenerate.
1763         * configure: Regenerate.
1764         * po/POTFILES.in: Regenerate.
1765
1766 2018-04-16  Alan Modra  <amodra@gmail.com>
1767
1768         * Makefile.am: Remove h8500 support.
1769         * configure.ac: Likewise.
1770         * disassemble.c: Likewise.
1771         * disassemble.h: Likewise.
1772         * h8500-dis.c: Delete.
1773         * h8500-opc.h: Delete.
1774         * Makefile.in: Regenerate.
1775         * configure: Regenerate.
1776         * po/POTFILES.in: Regenerate.
1777
1778 2018-04-16  Alan Modra  <amodra@gmail.com>
1779
1780         * configure.ac: Remove tahoe support.
1781         * configure: Regenerate.
1782
1783 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1784
1785         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1786         umwait.
1787         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1788         64-bit mode.
1789         * i386-tbl.h: Regenerated.
1790
1791 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1792
1793         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1794         PREFIX_MOD_1_0FAE_REG_6.
1795         (va_mode): New.
1796         (OP_E_register): Use va_mode.
1797         * i386-dis-evex.h (prefix_table):
1798         New instructions (see prefixes above).
1799         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1800         (cpu_flags): Likewise.
1801         * i386-opc.h (enum): Likewise.
1802         (i386_cpu_flags): Likewise.
1803         * i386-opc.tbl: Add umonitor, umwait, tpause.
1804         * i386-init.h: Regenerate.
1805         * i386-tbl.h: Likewise.
1806
1807 2018-04-11  Alan Modra  <amodra@gmail.com>
1808
1809         * opcodes/i860-dis.c: Delete.
1810         * opcodes/i960-dis.c: Delete.
1811         * Makefile.am: Remove i860 and i960 support.
1812         * configure.ac: Likewise.
1813         * disassemble.c: Likewise.
1814         * disassemble.h: Likewise.
1815         * Makefile.in: Regenerate.
1816         * configure: Regenerate.
1817         * po/POTFILES.in: Regenerate.
1818
1819 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1820
1821         PR binutils/23025
1822         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1823         to 0.
1824         (print_insn): Clear vex instead of vex.evex.
1825
1826 2018-04-04  Nick Clifton  <nickc@redhat.com>
1827
1828         * po/es.po: Updated Spanish translation.
1829
1830 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1831
1832         * i386-gen.c (opcode_modifiers): Delete VecESize.
1833         * i386-opc.h (VecESize): Delete.
1834         (struct i386_opcode_modifier): Delete vecesize.
1835         * i386-opc.tbl: Drop VecESize.
1836         * i386-tlb.h: Re-generate.
1837
1838 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1839
1840         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1841         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1842         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1843         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1844         * i386-tlb.h: Re-generate.
1845
1846 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1847
1848         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1849         Fold AVX512 forms
1850         * i386-tlb.h: Re-generate.
1851
1852 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1853
1854         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1855         (vex_len_table): Drop Y for vcvt*2si.
1856         (putop): Replace plain 'Y' handling by abort().
1857
1858 2018-03-28  Nick Clifton  <nickc@redhat.com>
1859
1860         PR 22988
1861         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1862         instructions with only a base address register.
1863         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1864         handle AARHC64_OPND_SVE_ADDR_R.
1865         (aarch64_print_operand): Likewise.
1866         * aarch64-asm-2.c: Regenerate.
1867         * aarch64_dis-2.c: Regenerate.
1868         * aarch64-opc-2.c: Regenerate.
1869
1870 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1871
1872         * i386-opc.tbl: Drop VecESize from register only insn forms and
1873         memory forms not allowing broadcast.
1874         * i386-tlb.h: Re-generate.
1875
1876 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1877
1878         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1879         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1880         sha256*): Drop Disp<N>.
1881
1882 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1883
1884         * i386-dis.c (EbndS, bnd_swap_mode): New.
1885         (prefix_table): Use EbndS.
1886         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1887         * i386-opc.tbl (bndmov): Move misplaced Load.
1888         * i386-tlb.h: Re-generate.
1889
1890 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1891
1892         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1893         templates allowing memory operands and folded ones for register
1894         only flavors.
1895         * i386-tlb.h: Re-generate.
1896
1897 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1898
1899         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1900         256-bit templates. Drop redundant leftover Disp<N>.
1901         * i386-tlb.h: Re-generate.
1902
1903 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1904
1905         * riscv-opc.c (riscv_insn_types): New.
1906
1907 2018-03-13  Nick Clifton  <nickc@redhat.com>
1908
1909         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1910
1911 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1912
1913         * i386-opc.tbl: Add Optimize to clr.
1914         * i386-tbl.h: Regenerated.
1915
1916 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1917
1918         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1919         * i386-opc.h (OldGcc): Removed.
1920         (i386_opcode_modifier): Remove oldgcc.
1921         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1922         instructions for old (<= 2.8.1) versions of gcc.
1923         * i386-tbl.h: Regenerated.
1924
1925 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1926
1927         * i386-opc.h (EVEXDYN): New.
1928         * i386-opc.tbl: Fold various AVX512VL templates.
1929         * i386-tlb.h: Re-generate.
1930
1931 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1932
1933         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1934         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1935         vpexpandd, vpexpandq): Fold AFX512VF templates.
1936         * i386-tlb.h: Re-generate.
1937
1938 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1939
1940         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1941         Fold 128- and 256-bit VEX-encoded templates.
1942         * i386-tlb.h: Re-generate.
1943
1944 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1945
1946         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1947         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1948         vpexpandd, vpexpandq): Fold AVX512F templates.
1949         * i386-tlb.h: Re-generate.
1950
1951 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1952
1953         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1954         64-bit templates. Drop Disp<N>.
1955         * i386-tlb.h: Re-generate.
1956
1957 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1958
1959         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1960         and 256-bit templates.
1961         * i386-tlb.h: Re-generate.
1962
1963 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1964
1965         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1966         * i386-tlb.h: Re-generate.
1967
1968 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1969
1970         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1971         Drop NoAVX.
1972         * i386-tlb.h: Re-generate.
1973
1974 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1975
1976         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1977         * i386-tlb.h: Re-generate.
1978
1979 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1980
1981         * i386-gen.c (opcode_modifiers): Delete FloatD.
1982         * i386-opc.h (FloatD): Delete.
1983         (struct i386_opcode_modifier): Delete floatd.
1984         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1985         FloatD by D.
1986         * i386-tlb.h: Re-generate.
1987
1988 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1989
1990         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1991
1992 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1993
1994         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1995         * i386-tlb.h: Re-generate.
1996
1997 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1998
1999         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2000         forms.
2001         * i386-tlb.h: Re-generate.
2002
2003 2018-03-07  Alan Modra  <amodra@gmail.com>
2004
2005         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2006         bfd_arch_rs6000.
2007         * disassemble.h (print_insn_rs6000): Delete.
2008         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2009         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2010         (print_insn_rs6000): Delete.
2011
2012 2018-03-03  Alan Modra  <amodra@gmail.com>
2013
2014         * sysdep.h (opcodes_error_handler): Define.
2015         (_bfd_error_handler): Declare.
2016         * Makefile.am: Remove stray #.
2017         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2018         EDIT" comment.
2019         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2020         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2021         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2022         opcodes_error_handler to print errors.  Standardize error messages.
2023         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2024         and include opintl.h.
2025         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2026         * i386-gen.c: Standardize error messages.
2027         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2028         * Makefile.in: Regenerate.
2029         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2030         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2031         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2032         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2033         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2034         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2035         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2036         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2037         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2038         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2039         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2040         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2041         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2042
2043 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2044
2045         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2046         vpsub[bwdq] instructions.
2047         * i386-tbl.h: Regenerated.
2048
2049 2018-03-01  Alan Modra  <amodra@gmail.com>
2050
2051         * configure.ac (ALL_LINGUAS): Sort.
2052         * configure: Regenerate.
2053
2054 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2055
2056         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2057         macro by assignements.
2058
2059 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2060
2061         PR gas/22871
2062         * i386-gen.c (opcode_modifiers): Add Optimize.
2063         * i386-opc.h (Optimize): New enum.
2064         (i386_opcode_modifier): Add optimize.
2065         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2066         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2067         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2068         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2069         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2070         vpxord and vpxorq.
2071         * i386-tbl.h: Regenerated.
2072
2073 2018-02-26  Alan Modra  <amodra@gmail.com>
2074
2075         * crx-dis.c (getregliststring): Allocate a large enough buffer
2076         to silence false positive gcc8 warning.
2077
2078 2018-02-22  Shea Levy <shea@shealevy.com>
2079
2080         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2081
2082 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2083
2084         * i386-opc.tbl: Add {rex},
2085         * i386-tbl.h: Regenerated.
2086
2087 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2088
2089         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2090         (mips16_opcodes): Replace `M' with `m' for "restore".
2091
2092 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2093
2094         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2095
2096 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2097
2098         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2099         variable to `function_index'.
2100
2101 2018-02-13  Nick Clifton  <nickc@redhat.com>
2102
2103         PR 22823
2104         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2105         about truncation of printing.
2106
2107 2018-02-12  Henry Wong <henry@stuffedcow.net>
2108
2109         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2110
2111 2018-02-05  Nick Clifton  <nickc@redhat.com>
2112
2113         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2114
2115 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2116
2117         * i386-dis.c (enum): Add pconfig.
2118         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2119         (cpu_flags): Add CpuPCONFIG.
2120         * i386-opc.h (enum): Add CpuPCONFIG.
2121         (i386_cpu_flags): Add cpupconfig.
2122         * i386-opc.tbl: Add PCONFIG instruction.
2123         * i386-init.h: Regenerate.
2124         * i386-tbl.h: Likewise.
2125
2126 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2127
2128         * i386-dis.c (enum): Add PREFIX_0F09.
2129         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2130         (cpu_flags): Add CpuWBNOINVD.
2131         * i386-opc.h (enum): Add CpuWBNOINVD.
2132         (i386_cpu_flags): Add cpuwbnoinvd.
2133         * i386-opc.tbl: Add WBNOINVD instruction.
2134         * i386-init.h: Regenerate.
2135         * i386-tbl.h: Likewise.
2136
2137 2018-01-17  Jim Wilson  <jimw@sifive.com>
2138
2139         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2140
2141 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2142
2143         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2144         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2145         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2146         (cpu_flags): Add CpuIBT, CpuSHSTK.
2147         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2148         (i386_cpu_flags): Add cpuibt, cpushstk.
2149         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2150         * i386-init.h: Regenerate.
2151         * i386-tbl.h: Likewise.
2152
2153 2018-01-16  Nick Clifton  <nickc@redhat.com>
2154
2155         * po/pt_BR.po: Updated Brazilian Portugese translation.
2156         * po/de.po: Updated German translation.
2157
2158 2018-01-15  Jim Wilson  <jimw@sifive.com>
2159
2160         * riscv-opc.c (match_c_nop): New.
2161         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2162
2163 2018-01-15  Nick Clifton  <nickc@redhat.com>
2164
2165         * po/uk.po: Updated Ukranian translation.
2166
2167 2018-01-13  Nick Clifton  <nickc@redhat.com>
2168
2169         * po/opcodes.pot: Regenerated.
2170
2171 2018-01-13  Nick Clifton  <nickc@redhat.com>
2172
2173         * configure: Regenerate.
2174
2175 2018-01-13  Nick Clifton  <nickc@redhat.com>
2176
2177         2.30 branch created.
2178
2179 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2180
2181         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2182         * i386-tbl.h: Regenerate.
2183
2184 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2185
2186         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2187         * i386-tbl.h: Re-generate.
2188
2189 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2190
2191         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2192         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2193         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2194         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2195         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2196         Disp8MemShift of AVX512VL forms.
2197         * i386-tbl.h: Re-generate.
2198
2199 2018-01-09  Jim Wilson  <jimw@sifive.com>
2200
2201         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2202         then the hi_addr value is zero.
2203
2204 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2205
2206         * arm-dis.c (arm_opcodes): Add csdb.
2207         (thumb32_opcodes): Add csdb.
2208
2209 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2210
2211         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2212         * aarch64-asm-2.c: Regenerate.
2213         * aarch64-dis-2.c: Regenerate.
2214         * aarch64-opc-2.c: Regenerate.
2215
2216 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2217
2218         PR gas/22681
2219         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2220         Remove AVX512 vmovd with 64-bit operands.
2221         * i386-tbl.h: Regenerated.
2222
2223 2018-01-05  Jim Wilson  <jimw@sifive.com>
2224
2225         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2226         jalr.
2227
2228 2018-01-03  Alan Modra  <amodra@gmail.com>
2229
2230         Update year range in copyright notice of all files.
2231
2232 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2233
2234         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2235         and OPERAND_TYPE_REGZMM entries.
2236
2237 For older changes see ChangeLog-2017
2238 \f
2239 Copyright (C) 2018 Free Software Foundation, Inc.
2240
2241 Copying and distribution of this file, with or without modification,
2242 are permitted in any medium without royalty provided the copyright
2243 notice and this notice are preserved.
2244
2245 Local Variables:
2246 mode: change-log
2247 left-margin: 8
2248 fill-column: 74
2249 version-control: never
2250 End: