opcodes/ChangeLog

   1 2018-11-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
   4         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
   5         EVEX_W_0F3A22_P_2): Delete.
   6         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
   7         entries up one level in the hierarchy.
   8         (OP_E_memory): Handle dq_mode when determining Disp8 shift
   9         value.
  10         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
  11         entries up one level in the hierarchy.
  12         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
  13         VexWIG for AVX flavors.
  14         * i386-tbl.h: Re-generate.
  15
  16 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
  19         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
  20         vcvtusi2ss, kmovd): Drop VexW=1.
  21         * i386-tbl.h: Re-generate.
  22
  23 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
  26         EVex512, EVexLIG, EVexDYN): New.
  27         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
  28         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
  29         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
  30         of EVex=4 (aka EVexLIG).
  31         * i386-tbl.h: Re-generate.
  32
  33 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
  36         (vpmaxub): Re-order attributes on AVX512BW flavor.
  37         * i386-tbl.h: Re-generate.
  38
  39 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
  42         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
  43         Vex=1 on AVX / AVX2 flavors.
  44         (vpmaxub): Re-order attributes on AVX512BW flavor.
  45         * i386-tbl.h: Re-generate.
  46
  47 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-opc.tbl (VexW0, VexW1): New.
  50         (vphadd*, vphsub*): Use VexW0 on XOP variants.
  51         * i386-tbl.h: Re-generate.
  52
  53 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
  54
  55         * s12z-dis.c (decode_possible_symbol): Add fallback case.
  56         (rel_15_7): Likewise.
  57
  58 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
  59
  60         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
  61         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
  62         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
  63
  64 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
  65
  66         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
  67         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
  68
  69 2018-10-10  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
  72         Size64. Add Size.
  73         * i386-opc.h (Size16, Size32, Size64): Delete.
  74         (Size): New.
  75         (SIZE16, SIZE32, SIZE64): Define.
  76         (struct i386_opcode_modifier): Drop size16, size32, and size64.
  77         Add size.
  78         * i386-opc.tbl (Size16, Size32, Size64): Define.
  79         * i386-tbl.h: Re-generate.
  80
  81 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  82
  83         * aarch64-opc.c (operand_general_constraint_met_p): Add
  84         SSBS in the check for one-bit immediate.
  85         (aarch64_sys_regs): New entry for SSBS.
  86         (aarch64_sys_reg_supported_p): New check for above.
  87         (aarch64_pstatefields): New entry for SSBS.
  88         (aarch64_pstatefield_supported_p): New check for above.
  89
  90 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  91
  92         * aarch64-opc.c (aarch64_sys_regs): New entries for
  93         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
  94         (aarch64_sys_reg_supported_p): New checks for above.
  95
  96 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  97
  98         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
  99         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 100         with the hint immediate.
 101         * aarch64-opc.c (aarch64_hint_options): New entries for
 102         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 103         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 104         while checking for HINT_OPD_F_NOPRINT flag.
 105         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 106         extract value.
 107         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 108         (aarch64_opcode_table): Add entry for BTI.
 109         (AARCH64_OPERANDS): Add new description for BTI targets.
 110         * aarch64-asm-2.c: Regenerate.
 111         * aarch64-dis-2.c: Regenerate.
 112         * aarch64-opc-2.c: Regenerate.
 113
 114 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 115
 116         * aarch64-opc.c (aarch64_sys_regs): New entries for
 117         rndr and rndrrs.
 118         (aarch64_sys_reg_supported_p): New check for above.
 119
 120 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 121
 122         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 123         (aarch64_sys_ins_reg_supported_p): New check for above.
 124
 125 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 126
 127         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 128         AARCH64_OPND_SYSREG_SR.
 129         * aarch64-opc.c (aarch64_print_operand): Likewise.
 130         (aarch64_sys_regs_sr): Define table.
 131         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 132         AARCH64_FEATURE_PREDRES.
 133         * aarch64-tbl.h (aarch64_feature_predres): New.
 134         (PREDRES, PREDRES_INSN): New.
 135         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 136         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 137         * aarch64-asm-2.c: Regenerate.
 138         * aarch64-dis-2.c: Regenerate.
 139         * aarch64-opc-2.c: Regenerate.
 140
 141 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 142
 143         * aarch64-tbl.h (aarch64_feature_sb): New.
 144         (SB, SB_INSN): New.
 145         (aarch64_opcode_table): Add entry for sb.
 146         * aarch64-asm-2.c: Regenerate.
 147         * aarch64-dis-2.c: Regenerate.
 148         * aarch64-opc-2.c: Regenerate.
 149
 150 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 151
 152         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 153         (aarch64_feature_frintts): New.
 154         (FLAGMANIP, FRINTTS): New.
 155         (aarch64_opcode_table): Add entries for xaflag, axflag
 156         and frint[32,64][x,z] instructions.
 157         * aarch64-asm-2.c: Regenerate.
 158         * aarch64-dis-2.c: Regenerate.
 159         * aarch64-opc-2.c: Regenerate.
 160
 161 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 162
 163         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 164         (ARMV8_5, V8_5_INSN): New.
 165
 166 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 167
 168         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 169
 170 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 171
 172         * i386-dis.c (rm_table): Add enclv.
 173         * i386-opc.tbl: Add enclv.
 174         * i386-tbl.h: Regenerated.
 175
 176 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 177
 178         * arm-dis.c (arm_opcodes): Add sb.
 179         (thumb32_opcodes): Likewise.
 180
 181 2018-10-05  Richard Henderson  <rth@twiddle.net>
 182             Stafford Horne  <shorne@gmail.com>
 183
 184         * or1k-desc.c: Regenerate.
 185         * or1k-desc.h: Regenerate.
 186         * or1k-opc.c: Regenerate.
 187         * or1k-opc.h: Regenerate.
 188         * or1k-opinst.c: Regenerate.
 189
 190 2018-10-05  Richard Henderson  <rth@twiddle.net>
 191
 192         * or1k-asm.c: Regenerated.
 193         * or1k-desc.c: Regenerated.
 194         * or1k-desc.h: Regenerated.
 195         * or1k-dis.c: Regenerated.
 196         * or1k-ibld.c: Regenerated.
 197         * or1k-opc.c: Regenerated.
 198         * or1k-opc.h: Regenerated.
 199         * or1k-opinst.c: Regenerated.
 200
 201 2018-10-05  Richard Henderson  <rth@twiddle.net>
 202
 203         * or1k-asm.c: Regenerate.
 204
 205 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 206
 207         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 208         * aarch64-dis.c (print_operands): Refactor to take notes.
 209         (print_verifier_notes): New.
 210         (print_aarch64_insn): Apply constraint verifier.
 211         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 212         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 213
 214 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 215
 216         * aarch64-opc.c (init_insn_block): New.
 217         (verify_constraints, aarch64_is_destructive_by_operands): New.
 218         * aarch64-opc.h (verify_constraints): New.
 219
 220 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 221
 222         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 223         * aarch64-opc.c (verify_ldpsw): Update arguments.
 224
 225 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 226
 227         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 228         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 229
 230 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 231
 232         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 233         * aarch64-dis.c (insn_sequence): New.
 234
 235 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 236
 237         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 238         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 239         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 240         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 241         constraints.
 242         (_SVE_INSNC): New.
 243         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 244         constraints.
 245         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 246         F_SCAN flags.
 247         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 248         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 249         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 250         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 251         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 252         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 253         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 254
 255 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 256
 257         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 258
 259 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 260
 261         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 262         are used when extracting signed fields and converting them to
 263         potentially 64-bit types.
 264
 265 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 266
 267         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 268         * Makefile.in: Re-generate.
 269         * aclocal.m4: Re-generate.
 270         * configure: Re-generate.
 271         * configure.ac: Remove check for -Wno-missing-field-initializers.
 272         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 273         (csky_v2_opcodes): Likewise.
 274
 275 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 276
 277         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 278
 279 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 280
 281         * nds32-asm.c (operand_fields): Remove the unused fields.
 282         (nds32_opcodes): Remove the unused instructions.
 283         * nds32-dis.c (nds32_ex9_info): Removed.
 284         (nds32_parse_opcode): Updated.
 285         (print_insn_nds32): Likewise.
 286         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 287         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 288         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 289         build_opcode_hash_table): New functions.
 290         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 291         nds32_opcode_table): New.
 292         (hw_ktabs): Declare it to a pointer rather than an array.
 293         (build_hash_table): Removed.
 294         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 295         SYN_ROPT and upadte HW_GPR and HW_INT.
 296         * nds32-dis.c (keywords): Remove const.
 297         (match_field): New function.
 298         (nds32_parse_opcode): Updated.
 299         * disassemble.c (disassemble_init_for_target):
 300         Add disassemble_init_nds32.
 301         * nds32-dis.c (eum map_type): New.
 302         (nds32_private_data): Likewise.
 303         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 304         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 305         (print_insn_nds32): Updated.
 306         * nds32-asm.c (parse_aext_reg): Add new parameter.
 307         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 308         are allowed to use.
 309         All callers changed.
 310         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 311         (operand_fields): Add new fields.
 312         (nds32_opcodes): Add new instructions.
 313         (keyword_aridxi_mx): New keyword.
 314         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 315         and NASM_ATTR_ZOL.
 316         (ALU2_1, ALU2_2, ALU2_3): New macros.
 317         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 318
 319 2018-09-17  Kito Cheng  <kito@andestech.com>
 320
 321         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 322
 323 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 324
 325         PR gas/23670
 326         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 327         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 328         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 329         (EVEX_LEN_0F7E_P_1): Likewise.
 330         (EVEX_LEN_0F7E_P_2): Likewise.
 331         (EVEX_LEN_0FD6_P_2): Likewise.
 332         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 333         (EVEX_LEN_TABLE): Likewise.
 334         (EVEX_LEN_0F6E_P_2): New enum.
 335         (EVEX_LEN_0F7E_P_1): Likewise.
 336         (EVEX_LEN_0F7E_P_2): Likewise.
 337         (EVEX_LEN_0FD6_P_2): Likewise.
 338         (evex_len_table): New.
 339         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 340         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 341         * i386-tbl.h: Regenerated.
 342
 343 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 344
 345         PR gas/23665
 346         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 347         VEX_LEN_0F7E_P_2 entries.
 348         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 349         * i386-tbl.h: Regenerated.
 350
 351 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 352
 353         * i386-dis.c (VZERO_Fixup): Removed.
 354         (VZERO): Likewise.
 355         (VEX_LEN_0F10_P_1): Likewise.
 356         (VEX_LEN_0F10_P_3): Likewise.
 357         (VEX_LEN_0F11_P_1): Likewise.
 358         (VEX_LEN_0F11_P_3): Likewise.
 359         (VEX_LEN_0F2E_P_0): Likewise.
 360         (VEX_LEN_0F2E_P_2): Likewise.
 361         (VEX_LEN_0F2F_P_0): Likewise.
 362         (VEX_LEN_0F2F_P_2): Likewise.
 363         (VEX_LEN_0F51_P_1): Likewise.
 364         (VEX_LEN_0F51_P_3): Likewise.
 365         (VEX_LEN_0F52_P_1): Likewise.
 366         (VEX_LEN_0F53_P_1): Likewise.
 367         (VEX_LEN_0F58_P_1): Likewise.
 368         (VEX_LEN_0F58_P_3): Likewise.
 369         (VEX_LEN_0F59_P_1): Likewise.
 370         (VEX_LEN_0F59_P_3): Likewise.
 371         (VEX_LEN_0F5A_P_1): Likewise.
 372         (VEX_LEN_0F5A_P_3): Likewise.
 373         (VEX_LEN_0F5C_P_1): Likewise.
 374         (VEX_LEN_0F5C_P_3): Likewise.
 375         (VEX_LEN_0F5D_P_1): Likewise.
 376         (VEX_LEN_0F5D_P_3): Likewise.
 377         (VEX_LEN_0F5E_P_1): Likewise.
 378         (VEX_LEN_0F5E_P_3): Likewise.
 379         (VEX_LEN_0F5F_P_1): Likewise.
 380         (VEX_LEN_0F5F_P_3): Likewise.
 381         (VEX_LEN_0FC2_P_1): Likewise.
 382         (VEX_LEN_0FC2_P_3): Likewise.
 383         (VEX_LEN_0F3A0A_P_2): Likewise.
 384         (VEX_LEN_0F3A0B_P_2): Likewise.
 385         (VEX_W_0F10_P_0): Likewise.
 386         (VEX_W_0F10_P_1): Likewise.
 387         (VEX_W_0F10_P_2): Likewise.
 388         (VEX_W_0F10_P_3): Likewise.
 389         (VEX_W_0F11_P_0): Likewise.
 390         (VEX_W_0F11_P_1): Likewise.
 391         (VEX_W_0F11_P_2): Likewise.
 392         (VEX_W_0F11_P_3): Likewise.
 393         (VEX_W_0F12_P_0_M_0): Likewise.
 394         (VEX_W_0F12_P_0_M_1): Likewise.
 395         (VEX_W_0F12_P_1): Likewise.
 396         (VEX_W_0F12_P_2): Likewise.
 397         (VEX_W_0F12_P_3): Likewise.
 398         (VEX_W_0F13_M_0): Likewise.
 399         (VEX_W_0F14): Likewise.
 400         (VEX_W_0F15): Likewise.
 401         (VEX_W_0F16_P_0_M_0): Likewise.
 402         (VEX_W_0F16_P_0_M_1): Likewise.
 403         (VEX_W_0F16_P_1): Likewise.
 404         (VEX_W_0F16_P_2): Likewise.
 405         (VEX_W_0F17_M_0): Likewise.
 406         (VEX_W_0F28): Likewise.
 407         (VEX_W_0F29): Likewise.
 408         (VEX_W_0F2B_M_0): Likewise.
 409         (VEX_W_0F2E_P_0): Likewise.
 410         (VEX_W_0F2E_P_2): Likewise.
 411         (VEX_W_0F2F_P_0): Likewise.
 412         (VEX_W_0F2F_P_2): Likewise.
 413         (VEX_W_0F50_M_0): Likewise.
 414         (VEX_W_0F51_P_0): Likewise.
 415         (VEX_W_0F51_P_1): Likewise.
 416         (VEX_W_0F51_P_2): Likewise.
 417         (VEX_W_0F51_P_3): Likewise.
 418         (VEX_W_0F52_P_0): Likewise.
 419         (VEX_W_0F52_P_1): Likewise.
 420         (VEX_W_0F53_P_0): Likewise.
 421         (VEX_W_0F53_P_1): Likewise.
 422         (VEX_W_0F58_P_0): Likewise.
 423         (VEX_W_0F58_P_1): Likewise.
 424         (VEX_W_0F58_P_2): Likewise.
 425         (VEX_W_0F58_P_3): Likewise.
 426         (VEX_W_0F59_P_0): Likewise.
 427         (VEX_W_0F59_P_1): Likewise.
 428         (VEX_W_0F59_P_2): Likewise.
 429         (VEX_W_0F59_P_3): Likewise.
 430         (VEX_W_0F5A_P_0): Likewise.
 431         (VEX_W_0F5A_P_1): Likewise.
 432         (VEX_W_0F5A_P_3): Likewise.
 433         (VEX_W_0F5B_P_0): Likewise.
 434         (VEX_W_0F5B_P_1): Likewise.
 435         (VEX_W_0F5B_P_2): Likewise.
 436         (VEX_W_0F5C_P_0): Likewise.
 437         (VEX_W_0F5C_P_1): Likewise.
 438         (VEX_W_0F5C_P_2): Likewise.
 439         (VEX_W_0F5C_P_3): Likewise.
 440         (VEX_W_0F5D_P_0): Likewise.
 441         (VEX_W_0F5D_P_1): Likewise.
 442         (VEX_W_0F5D_P_2): Likewise.
 443         (VEX_W_0F5D_P_3): Likewise.
 444         (VEX_W_0F5E_P_0): Likewise.
 445         (VEX_W_0F5E_P_1): Likewise.
 446         (VEX_W_0F5E_P_2): Likewise.
 447         (VEX_W_0F5E_P_3): Likewise.
 448         (VEX_W_0F5F_P_0): Likewise.
 449         (VEX_W_0F5F_P_1): Likewise.
 450         (VEX_W_0F5F_P_2): Likewise.
 451         (VEX_W_0F5F_P_3): Likewise.
 452         (VEX_W_0F60_P_2): Likewise.
 453         (VEX_W_0F61_P_2): Likewise.
 454         (VEX_W_0F62_P_2): Likewise.
 455         (VEX_W_0F63_P_2): Likewise.
 456         (VEX_W_0F64_P_2): Likewise.
 457         (VEX_W_0F65_P_2): Likewise.
 458         (VEX_W_0F66_P_2): Likewise.
 459         (VEX_W_0F67_P_2): Likewise.
 460         (VEX_W_0F68_P_2): Likewise.
 461         (VEX_W_0F69_P_2): Likewise.
 462         (VEX_W_0F6A_P_2): Likewise.
 463         (VEX_W_0F6B_P_2): Likewise.
 464         (VEX_W_0F6C_P_2): Likewise.
 465         (VEX_W_0F6D_P_2): Likewise.
 466         (VEX_W_0F6F_P_1): Likewise.
 467         (VEX_W_0F6F_P_2): Likewise.
 468         (VEX_W_0F70_P_1): Likewise.
 469         (VEX_W_0F70_P_2): Likewise.
 470         (VEX_W_0F70_P_3): Likewise.
 471         (VEX_W_0F71_R_2_P_2): Likewise.
 472         (VEX_W_0F71_R_4_P_2): Likewise.
 473         (VEX_W_0F71_R_6_P_2): Likewise.
 474         (VEX_W_0F72_R_2_P_2): Likewise.
 475         (VEX_W_0F72_R_4_P_2): Likewise.
 476         (VEX_W_0F72_R_6_P_2): Likewise.
 477         (VEX_W_0F73_R_2_P_2): Likewise.
 478         (VEX_W_0F73_R_3_P_2): Likewise.
 479         (VEX_W_0F73_R_6_P_2): Likewise.
 480         (VEX_W_0F73_R_7_P_2): Likewise.
 481         (VEX_W_0F74_P_2): Likewise.
 482         (VEX_W_0F75_P_2): Likewise.
 483         (VEX_W_0F76_P_2): Likewise.
 484         (VEX_W_0F77_P_0): Likewise.
 485         (VEX_W_0F7C_P_2): Likewise.
 486         (VEX_W_0F7C_P_3): Likewise.
 487         (VEX_W_0F7D_P_2): Likewise.
 488         (VEX_W_0F7D_P_3): Likewise.
 489         (VEX_W_0F7E_P_1): Likewise.
 490         (VEX_W_0F7F_P_1): Likewise.
 491         (VEX_W_0F7F_P_2): Likewise.
 492         (VEX_W_0FAE_R_2_M_0): Likewise.
 493         (VEX_W_0FAE_R_3_M_0): Likewise.
 494         (VEX_W_0FC2_P_0): Likewise.
 495         (VEX_W_0FC2_P_1): Likewise.
 496         (VEX_W_0FC2_P_2): Likewise.
 497         (VEX_W_0FC2_P_3): Likewise.
 498         (VEX_W_0FD0_P_2): Likewise.
 499         (VEX_W_0FD0_P_3): Likewise.
 500         (VEX_W_0FD1_P_2): Likewise.
 501         (VEX_W_0FD2_P_2): Likewise.
 502         (VEX_W_0FD3_P_2): Likewise.
 503         (VEX_W_0FD4_P_2): Likewise.
 504         (VEX_W_0FD5_P_2): Likewise.
 505         (VEX_W_0FD6_P_2): Likewise.
 506         (VEX_W_0FD7_P_2_M_1): Likewise.
 507         (VEX_W_0FD8_P_2): Likewise.
 508         (VEX_W_0FD9_P_2): Likewise.
 509         (VEX_W_0FDA_P_2): Likewise.
 510         (VEX_W_0FDB_P_2): Likewise.
 511         (VEX_W_0FDC_P_2): Likewise.
 512         (VEX_W_0FDD_P_2): Likewise.
 513         (VEX_W_0FDE_P_2): Likewise.
 514         (VEX_W_0FDF_P_2): Likewise.
 515         (VEX_W_0FE0_P_2): Likewise.
 516         (VEX_W_0FE1_P_2): Likewise.
 517         (VEX_W_0FE2_P_2): Likewise.
 518         (VEX_W_0FE3_P_2): Likewise.
 519         (VEX_W_0FE4_P_2): Likewise.
 520         (VEX_W_0FE5_P_2): Likewise.
 521         (VEX_W_0FE6_P_1): Likewise.
 522         (VEX_W_0FE6_P_2): Likewise.
 523         (VEX_W_0FE6_P_3): Likewise.
 524         (VEX_W_0FE7_P_2_M_0): Likewise.
 525         (VEX_W_0FE8_P_2): Likewise.
 526         (VEX_W_0FE9_P_2): Likewise.
 527         (VEX_W_0FEA_P_2): Likewise.
 528         (VEX_W_0FEB_P_2): Likewise.
 529         (VEX_W_0FEC_P_2): Likewise.
 530         (VEX_W_0FED_P_2): Likewise.
 531         (VEX_W_0FEE_P_2): Likewise.
 532         (VEX_W_0FEF_P_2): Likewise.
 533         (VEX_W_0FF0_P_3_M_0): Likewise.
 534         (VEX_W_0FF1_P_2): Likewise.
 535         (VEX_W_0FF2_P_2): Likewise.
 536         (VEX_W_0FF3_P_2): Likewise.
 537         (VEX_W_0FF4_P_2): Likewise.
 538         (VEX_W_0FF5_P_2): Likewise.
 539         (VEX_W_0FF6_P_2): Likewise.
 540         (VEX_W_0FF7_P_2): Likewise.
 541         (VEX_W_0FF8_P_2): Likewise.
 542         (VEX_W_0FF9_P_2): Likewise.
 543         (VEX_W_0FFA_P_2): Likewise.
 544         (VEX_W_0FFB_P_2): Likewise.
 545         (VEX_W_0FFC_P_2): Likewise.
 546         (VEX_W_0FFD_P_2): Likewise.
 547         (VEX_W_0FFE_P_2): Likewise.
 548         (VEX_W_0F3800_P_2): Likewise.
 549         (VEX_W_0F3801_P_2): Likewise.
 550         (VEX_W_0F3802_P_2): Likewise.
 551         (VEX_W_0F3803_P_2): Likewise.
 552         (VEX_W_0F3804_P_2): Likewise.
 553         (VEX_W_0F3805_P_2): Likewise.
 554         (VEX_W_0F3806_P_2): Likewise.
 555         (VEX_W_0F3807_P_2): Likewise.
 556         (VEX_W_0F3808_P_2): Likewise.
 557         (VEX_W_0F3809_P_2): Likewise.
 558         (VEX_W_0F380A_P_2): Likewise.
 559         (VEX_W_0F380B_P_2): Likewise.
 560         (VEX_W_0F3817_P_2): Likewise.
 561         (VEX_W_0F381C_P_2): Likewise.
 562         (VEX_W_0F381D_P_2): Likewise.
 563         (VEX_W_0F381E_P_2): Likewise.
 564         (VEX_W_0F3820_P_2): Likewise.
 565         (VEX_W_0F3821_P_2): Likewise.
 566         (VEX_W_0F3822_P_2): Likewise.
 567         (VEX_W_0F3823_P_2): Likewise.
 568         (VEX_W_0F3824_P_2): Likewise.
 569         (VEX_W_0F3825_P_2): Likewise.
 570         (VEX_W_0F3828_P_2): Likewise.
 571         (VEX_W_0F3829_P_2): Likewise.
 572         (VEX_W_0F382A_P_2_M_0): Likewise.
 573         (VEX_W_0F382B_P_2): Likewise.
 574         (VEX_W_0F3830_P_2): Likewise.
 575         (VEX_W_0F3831_P_2): Likewise.
 576         (VEX_W_0F3832_P_2): Likewise.
 577         (VEX_W_0F3833_P_2): Likewise.
 578         (VEX_W_0F3834_P_2): Likewise.
 579         (VEX_W_0F3835_P_2): Likewise.
 580         (VEX_W_0F3837_P_2): Likewise.
 581         (VEX_W_0F3838_P_2): Likewise.
 582         (VEX_W_0F3839_P_2): Likewise.
 583         (VEX_W_0F383A_P_2): Likewise.
 584         (VEX_W_0F383B_P_2): Likewise.
 585         (VEX_W_0F383C_P_2): Likewise.
 586         (VEX_W_0F383D_P_2): Likewise.
 587         (VEX_W_0F383E_P_2): Likewise.
 588         (VEX_W_0F383F_P_2): Likewise.
 589         (VEX_W_0F3840_P_2): Likewise.
 590         (VEX_W_0F3841_P_2): Likewise.
 591         (VEX_W_0F38DB_P_2): Likewise.
 592         (VEX_W_0F3A08_P_2): Likewise.
 593         (VEX_W_0F3A09_P_2): Likewise.
 594         (VEX_W_0F3A0A_P_2): Likewise.
 595         (VEX_W_0F3A0B_P_2): Likewise.
 596         (VEX_W_0F3A0C_P_2): Likewise.
 597         (VEX_W_0F3A0D_P_2): Likewise.
 598         (VEX_W_0F3A0E_P_2): Likewise.
 599         (VEX_W_0F3A0F_P_2): Likewise.
 600         (VEX_W_0F3A21_P_2): Likewise.
 601         (VEX_W_0F3A40_P_2): Likewise.
 602         (VEX_W_0F3A41_P_2): Likewise.
 603         (VEX_W_0F3A42_P_2): Likewise.
 604         (VEX_W_0F3A62_P_2): Likewise.
 605         (VEX_W_0F3A63_P_2): Likewise.
 606         (VEX_W_0F3ADF_P_2): Likewise.
 607         (VEX_LEN_0F77_P_0): New.
 608         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 609         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 610         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 611         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 612         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 613         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 614         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 615         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 616         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 617         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 618         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 619         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 620         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 621         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 622         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 623         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 624         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 625         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 626         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 627         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 628         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 629         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 630         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 631         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 632         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 633         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 634         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 635         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 636         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 637         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 638         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 639         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 640         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 641         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 642         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 643         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 644         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 645         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 646         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 647         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 648         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 649         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 650         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 651         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 652         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 653         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 654         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 655         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 656         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 657         (vex_table): Update VEX 0F28 and 0F29 entries.
 658         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 659         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 660         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 661         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 662         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 663         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 664         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 665         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 666         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 667         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 668         VEX_LEN_0F3A0B_P_2 entries.
 669         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 670         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 671         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 672         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 673         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 674         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 675         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 676         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 677         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 678         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 679         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 680         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 681         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 682         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 683         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 684         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 685         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 686         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 687         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 688         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 689         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 690         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 691         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 692         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 693         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 694         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 695         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 696         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 697         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 698         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 699         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 700         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 701         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 702         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 703         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 704         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 705         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 706         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 707         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 708         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 709         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 710         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 711         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 712         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 713         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 714         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 715         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 716         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 717         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 718         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 719         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 720         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 721         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 722         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 723         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 724         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 725         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 726         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 727         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 728         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 729         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 730         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 731         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 732         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 733         VEX_W_0F3ADF_P_2 entries.
 734         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 735         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 736         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 737
 738 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 739
 740         * i386-opc.tbl (VexWIG): New.
 741         Replace VexW=3 with VexWIG.
 742
 743 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 744
 745         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 746         * i386-tbl.h: Regenerated.
 747
 748 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 749
 750         PR gas/23665
 751         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 752         VEX_LEN_0FD6_P_2 entries.
 753         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 754         * i386-tbl.h: Regenerated.
 755
 756 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 757
 758         PR gas/23642
 759         * i386-opc.h (VEXWIG): New.
 760         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 761         * i386-tbl.h: Regenerated.
 762
 763 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 764
 765         PR binutils/23655
 766         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 767         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 768         * i386-dis.c (EXxEVexR64): New.
 769         (evex_rounding_64_mode): Likewise.
 770         (OP_Rounding): Handle evex_rounding_64_mode.
 771
 772 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 773
 774         PR binutils/23655
 775         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 776         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 777         * i386-dis.c (Edqa): New.
 778         (dqa_mode): Likewise.
 779         (intel_operand_size): Handle dqa_mode as m_mode.
 780         (OP_E_register): Handle dqa_mode as dq_mode.
 781         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 782
 783 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 784
 785         * i386-dis.c (OP_E_memory): Reformat.
 786
 787 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-opc.tbl (crc32): Fold byte and word forms.
 790         * i386-tbl.h: Re-generate.
 791
 792 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 793
 794         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 795         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 796         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 797         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 798         * i386-tbl.h: Regenerated.
 799
 800 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 801
 802         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 803         meaningless.
 804         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 805         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 806         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 807         * i386-tbl.h: Re-generate.
 808
 809 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 812         AVX512_4VNNIW insns.
 813         * i386-tbl.h: Re-generate.
 814
 815 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 816
 817         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 818         meaningless.
 819         * i386-tbl.h: Re-generate.
 820
 821 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 822
 823         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 824         meaningless.
 825         * i386-tbl.h: Re-generate.
 826
 827 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 828
 829         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 830         meaningless.
 831         * i386-tbl.h: Re-generate.
 832
 833 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 834
 835         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 836         meaningless.
 837         * i386-tbl.h: Re-generate.
 838
 839 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 840
 841         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 842         meaningless.
 843         * i386-tbl.h: Re-generate.
 844
 845 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 846
 847         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 848         * i386-tbl.h: Re-generate.
 849
 850 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 853         * i386-tbl.h: Re-generate.
 854
 855 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 856
 857         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 858         meaningless.
 859         * i386-tbl.h: Re-generate.
 860
 861 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 864         meaningless.
 865         * i386-tbl.h: Re-generate.
 866
 867 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 870         * i386-tbl.h: Re-generate.
 871
 872 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 875         * i386-tbl.h: Re-generate.
 876
 877 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 878
 879         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 880         * i386-tbl.h: Re-generate.
 881
 882 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 885         meaningless.
 886         * i386-tbl.h: Re-generate.
 887
 888 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 889
 890         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 891         meaningless.
 892         * i386-tbl.h: Re-generate.
 893
 894 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 895
 896         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 897         meaningless.
 898         * i386-tbl.h: Re-generate.
 899
 900 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 901
 902         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 903         * i386-tbl.h: Re-generate.
 904
 905 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 906
 907         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 908         * i386-tbl.h: Re-generate.
 909
 910 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 911
 912         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 913         * i386-tbl.h: Re-generate.
 914
 915 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 916
 917         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 918         (vpbroadcastw, rdpid): Drop NoRex64.
 919         * i386-tbl.h: Re-generate.
 920
 921 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 924         store templates, adding D.
 925         * i386-tbl.h: Re-generate.
 926
 927 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 928
 929         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 930         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 931         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 932         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 933         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 934         Fold load and store templates where possible, adding D. Drop
 935         IgnoreSize where it was pointlessly present. Drop redundant
 936         *word.
 937         * i386-tbl.h: Re-generate.
 938
 939 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 940
 941         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 942         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 943         (intel_operand_size): Handle v_bndmk_mode.
 944         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 945
 946 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 947
 948         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 949
 950 2018-08-31  Kito Cheng  <kito@andestech.com>
 951
 952         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 953         compressed floating point instructions.
 954
 955 2018-08-30  Kito Cheng  <kito@andestech.com>
 956
 957         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 958         riscv_opcode.xlen_requirement.
 959         * riscv-opc.c (riscv_opcodes): Update for struct change.
 960
 961 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 962
 963         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 964         psr (PWRPSR) instruction.
 965
 966 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 967
 968         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 969
 970 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 971
 972         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 973
 974 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 975
 976         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 977         loongson3a as an alias of gs464 for compatibility.
 978         * mips-opc.c (mips_opcodes): Change Comments.
 979
 980 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 981
 982         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 983         option.
 984         (print_mips_disassembler_options): Document -M loongson-ext.
 985         * mips-opc.c (LEXT2): New macro.
 986         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 987
 988 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 989
 990          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 991          descriptors.
 992          (parse_mips_ase_option): Handle -M loongson-ext option.
 993          (print_mips_disassembler_options): Document -M loongson-ext.
 994          * mips-opc.c (IL3A): Delete.
 995          * mips-opc.c (LEXT): New macro.
 996          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 997          instructions.
 998
 999 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1000
1001         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1002         descriptors.
1003         (parse_mips_ase_option): Handle -M loongson-cam option.
1004         (print_mips_disassembler_options): Document -M loongson-cam.
1005         * mips-opc.c (LCAM): New macro.
1006         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1007         instructions.
1008
1009 2018-08-21  Alan Modra  <amodra@gmail.com>
1010
1011         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1012         (skip_optional_operands): Count optional operands, and update
1013         ppc_optional_operand_value call.
1014         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1015         (extract_vlensi): Likewise.
1016         (extract_fxm): Return default value for missing optional operand.
1017         (extract_ls, extract_raq, extract_tbr): Likewise.
1018         (insert_sxl, extract_sxl): New functions.
1019         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1020         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1021         flag and extra entry.
1022         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1023         extract_sxl.
1024
1025 2018-08-20  Alan Modra  <amodra@gmail.com>
1026
1027         * sh-opc.h (MASK): Simplify.
1028
1029 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1030
1031         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1032         BM_RESERVED0 or BM_RESERVED1
1033         (bm_rel_decode, bm_n_bytes): Ditto.
1034
1035 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1036
1037         * s12z.h: Delete.
1038
1039 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1040
1041         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1042         address with the addr32 prefix and without base nor index
1043         registers.
1044
1045 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1046
1047         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1048         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1049         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1050         (cpu_flags): Add CpuCMOV and CpuFXSR.
1051         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1052         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1053         * i386-init.h: Regenerated.
1054         * i386-tbl.h: Likewise.
1055
1056 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1057
1058         * arc-regs.h: Update auxiliary registers.
1059
1060 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1061
1062         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1063         (RegIP, RegIZ): Define.
1064         * i386-reg.tbl: Adjust comments.
1065         (rip): Use Qword instead of BaseIndex. Use RegIP.
1066         (eip): Use Dword instead of BaseIndex. Use RegIP.
1067         (riz): Add Qword. Use RegIZ.
1068         (eiz): Add Dword. Use RegIZ.
1069         * i386-tbl.h: Re-generate.
1070
1071 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1072
1073         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1074         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1075         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1076         * i386-tbl.h: Re-generate.
1077
1078 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1079
1080         * i386-gen.c (operand_types): Remove Mem field.
1081         * i386-opc.h (union i386_operand_type): Remove mem field.
1082         * i386-init.h, i386-tbl.h: Re-generate.
1083
1084 2018-08-01  Alan Modra  <amodra@gmail.com>
1085
1086         * po/POTFILES.in: Regenerate.
1087
1088 2018-07-31  Nick Clifton  <nickc@redhat.com>
1089
1090         * po/sv.po: Updated Swedish translation.
1091
1092 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1093
1094         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1095         * i386-init.h, i386-tbl.h: Re-generate.
1096
1097 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1098
1099         * i386-opc.h (ZEROING_MASKING) Rename to ...
1100         (DYNAMIC_MASKING): ... this. Adjust comment.
1101         * i386-opc.tbl (MaskingMorZ): Define.
1102         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1103         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1104         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1105         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1106         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1107         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1108         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1109         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1110         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1111
1112 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1113
1114         * i386-opc.tbl: Use element rather than vector size for AVX512*
1115         scatter/gather insns.
1116         * i386-tbl.h: Re-generate.
1117
1118 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1119
1120         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1121         (cpu_flags): Drop CpuVREX.
1122         * i386-opc.h (CpuVREX): Delete.
1123         (union i386_cpu_flags): Remove cpuvrex.
1124         * i386-init.h, i386-tbl.h: Re-generate.
1125
1126 2018-07-30  Jim Wilson  <jimw@sifive.com>
1127
1128         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1129         fields.
1130         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1131
1132 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1133
1134         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1135         * Makefile.in: Regenerated.
1136         * configure.ac: Add C-SKY.
1137         * configure: Regenerated.
1138         * csky-dis.c: New file.
1139         * csky-opc.h: New file.
1140         * disassemble.c (ARCH_csky): Define.
1141         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1142         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1143
1144 2018-07-27  Alan Modra  <amodra@gmail.com>
1145
1146         * ppc-opc.c (insert_sprbat): Correct function parameter and
1147         return type.
1148         (extract_sprbat): Likewise, variable too.
1149
1150 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1151             Alan Modra  <amodra@gmail.com>
1152
1153         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1154         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1155         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1156         support disjointed BAT.
1157         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1158         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1159         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1160
1161 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1162             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1163
1164         * i386-gen.c (adjust_broadcast_modifier): New function.
1165         (process_i386_opcode_modifier): Add an argument for operands.
1166         Adjust the Broadcast value based on operands.
1167         (output_i386_opcode): Pass operand_types to
1168         process_i386_opcode_modifier.
1169         (process_i386_opcodes): Pass NULL as operands to
1170         process_i386_opcode_modifier.
1171         * i386-opc.h (BYTE_BROADCAST): New.
1172         (WORD_BROADCAST): Likewise.
1173         (DWORD_BROADCAST): Likewise.
1174         (QWORD_BROADCAST): Likewise.
1175         (i386_opcode_modifier): Expand broadcast to 3 bits.
1176         * i386-tbl.h: Regenerated.
1177
1178 2018-07-24  Alan Modra  <amodra@gmail.com>
1179
1180         PR 23430
1181         * or1k-desc.h: Regenerate.
1182
1183 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1186         vcvtusi2ss, and vcvtusi2sd.
1187         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1188         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1189         * i386-tbl.h: Re-generate.
1190
1191 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1192
1193         * arc-opc.c (extract_w6): Fix extending the sign.
1194
1195 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1196
1197         * arc-tbl.h (vewt): Allow it for ARC EM family.
1198
1199 2018-07-23  Alan Modra  <amodra@gmail.com>
1200
1201         PR 23419
1202         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1203         opcode variants for mtspr/mfspr encodings.
1204
1205 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1206             Maciej W. Rozycki  <macro@mips.com>
1207
1208         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1209         loongson3a descriptors.
1210         (parse_mips_ase_option): Handle -M loongson-mmi option.
1211         (print_mips_disassembler_options): Document -M loongson-mmi.
1212         * mips-opc.c (LMMI): New macro.
1213         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1214         instructions.
1215
1216 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1217
1218         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1219         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1220         IgnoreSize and [XYZ]MMword where applicable.
1221         * i386-tbl.h: Re-generate.
1222
1223 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1224
1225         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1226         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1227         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1228         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1229         * i386-tbl.h: Re-generate.
1230
1231 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1232
1233         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1234         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1235         VPCLMULQDQ templates into their respective AVX512VL counterparts
1236         where possible, using Disp8ShiftVL and CheckRegSize instead of
1237         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1238         * i386-tbl.h: Re-generate.
1239
1240 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1241
1242         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1243         AVX512VL counterparts where possible, using Disp8ShiftVL and
1244         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1245         IgnoreSize) as appropriate.
1246         * i386-tbl.h: Re-generate.
1247
1248 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1249
1250         * i386-opc.tbl: Fold AVX512BW templates into their respective
1251         AVX512VL counterparts where possible, using Disp8ShiftVL and
1252         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1253         IgnoreSize) as appropriate.
1254         * i386-tbl.h: Re-generate.
1255
1256 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1257
1258         * i386-opc.tbl: Fold AVX512CD templates into their respective
1259         AVX512VL counterparts where possible, using Disp8ShiftVL and
1260         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1261         IgnoreSize) as appropriate.
1262         * i386-tbl.h: Re-generate.
1263
1264 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1265
1266         * i386-opc.h (DISP8_SHIFT_VL): New.
1267         * i386-opc.tbl (Disp8ShiftVL):  Define.
1268         (various): Fold AVX512VL templates into their respective
1269         AVX512F counterparts where possible, using Disp8ShiftVL and
1270         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1271         IgnoreSize) as appropriate.
1272         * i386-tbl.h: Re-generate.
1273
1274 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1275
1276         * Makefile.am: Change dependencies and rule for
1277         $(srcdir)/i386-init.h.
1278         * Makefile.in: Re-generate.
1279         * i386-gen.c (process_i386_opcodes): New local variable
1280         "marker". Drop opening of input file. Recognize marker and line
1281         number directives.
1282         * i386-opc.tbl (OPCODE_I386_H): Define.
1283         (i386-opc.h): Include it.
1284         (None): Undefine.
1285
1286 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1287
1288         PR gas/23418
1289         * i386-opc.h (Byte): Update comments.
1290         (Word): Likewise.
1291         (Dword): Likewise.
1292         (Fword): Likewise.
1293         (Qword): Likewise.
1294         (Tbyte): Likewise.
1295         (Xmmword): Likewise.
1296         (Ymmword): Likewise.
1297         (Zmmword): Likewise.
1298         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1299         vcvttps2uqq.
1300         * i386-tbl.h: Regenerated.
1301
1302 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1303
1304         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1305         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1306         * aarch64-asm-2.c: Regenerate.
1307         * aarch64-dis-2.c: Regenerate.
1308         * aarch64-opc-2.c: Regenerate.
1309
1310 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1311
1312         PR binutils/23192
1313         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1314         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1315         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1316         sqdmulh, sqrdmulh): Use Em16.
1317
1318 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1319
1320         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1321         csdb together with them.
1322         (thumb32_opcodes): Likewise.
1323
1324 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1325
1326         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1327         requiring 32-bit registers as operands 2 and 3. Improve
1328         comments.
1329         (mwait, mwaitx): Fold templates. Improve comments.
1330         OPERAND_TYPE_INOUTPORTREG.
1331         * i386-tbl.h: Re-generate.
1332
1333 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1334
1335         * i386-gen.c (operand_type_init): Remove
1336         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1337         OPERAND_TYPE_INOUTPORTREG.
1338         * i386-init.h: Re-generate.
1339
1340 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1341
1342         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1343         (wrssq, wrussq): Add Qword.
1344         * i386-tbl.h: Re-generate.
1345
1346 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1347
1348         * i386-opc.h: Rename OTMax to OTNum.
1349         (OTNumOfUints): Adjust calculation.
1350         (OTUnused): Directly alias to OTNum.
1351
1352 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1353
1354         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1355         `reg_xys'.
1356         (lea_reg_xys): Likewise.
1357         (print_insn_loop_primitive): Rename `reg' local variable to
1358         `reg_dxy'.
1359
1360 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1361
1362         PR binutils/23242
1363         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1364
1365 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1366
1367         PR binutils/23369
1368         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1369         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1370
1371 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1372
1373         PR tdep/8282
1374         * mips-dis.c (mips_option_arg_t): New enumeration.
1375         (mips_options): New variable.
1376         (disassembler_options_mips): New function.
1377         (print_mips_disassembler_options): Reimplement in terms of
1378         `disassembler_options_mips'.
1379         * arm-dis.c (disassembler_options_arm): Adapt to using the
1380         `disasm_options_and_args_t' structure.
1381         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1382         * s390-dis.c (disassembler_options_s390): Likewise.
1383
1384 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1385
1386         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1387         expected result.
1388         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1389         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1390         * testsuite/ld-arm/tls-longplt.d: Likewise.
1391
1392 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1393
1394         PR binutils/23192
1395         * aarch64-asm-2.c: Regenerate.
1396         * aarch64-dis-2.c: Likewise.
1397         * aarch64-opc-2.c: Likewise.
1398         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1399         * aarch64-opc.c (operand_general_constraint_met_p,
1400         aarch64_print_operand): Likewise.
1401         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1402         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1403         fmlal2, fmlsl2.
1404         (AARCH64_OPERANDS): Add Em2.
1405
1406 2018-06-26  Nick Clifton  <nickc@redhat.com>
1407
1408         * po/uk.po: Updated Ukranian translation.
1409         * po/de.po: Updated German translation.
1410         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1411
1412 2018-06-26  Nick Clifton  <nickc@redhat.com>
1413
1414         * nfp-dis.c: Fix spelling mistake.
1415
1416 2018-06-24  Nick Clifton  <nickc@redhat.com>
1417
1418         * configure: Regenerate.
1419         * po/opcodes.pot: Regenerate.
1420
1421 2018-06-24  Nick Clifton  <nickc@redhat.com>
1422
1423         2.31 branch created.
1424
1425 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1426
1427         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1428         * aarch64-asm-2.c: Regenerate.
1429         * aarch64-dis-2.c: Likewise.
1430
1431 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1432
1433         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1434         `-M ginv' option description.
1435
1436 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1437
1438         PR gas/23305
1439         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1440         la and lla.
1441
1442 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1443
1444         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1445         * configure.ac: Remove AC_PREREQ.
1446         * Makefile.in: Re-generate.
1447         * aclocal.m4: Re-generate.
1448         * configure: Re-generate.
1449
1450 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1451
1452         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1453         mips64r6 descriptors.
1454         (parse_mips_ase_option): Handle -Mginv option.
1455         (print_mips_disassembler_options): Document -Mginv.
1456         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1457         (GINV): New macro.
1458         (mips_opcodes): Define ginvi and ginvt.
1459
1460 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1461             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1462
1463         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1464         * mips-opc.c (CRC, CRC64): New macros.
1465         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1466         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1467         crc32cd for CRC64.
1468
1469 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1470
1471         PR 20319
1472         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1473         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1474
1475 2018-06-06  Alan Modra  <amodra@gmail.com>
1476
1477         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1478         setjmp.  Move init for some other vars later too.
1479
1480 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1481
1482         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1483         (dis_private): Add new fields for property section tracking.
1484         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1485         (xtensa_instruction_fits): New functions.
1486         (fetch_data): Bump minimal fetch size to 4.
1487         (print_insn_xtensa): Make struct dis_private static.
1488         Load and prepare property table on section change.
1489         Don't disassemble literals. Don't disassemble instructions that
1490         cross property table boundaries.
1491
1492 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1493
1494         * configure: Regenerated.
1495
1496 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1497
1498         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1499         * i386-tbl.h: Re-generate.
1500
1501 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1502
1503         * i386-opc.tbl (sldt, str): Add NoRex64.
1504         * i386-tbl.h: Re-generate.
1505
1506 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1507
1508         * i386-opc.tbl (invpcid): Add Oword.
1509         * i386-tbl.h: Re-generate.
1510
1511 2018-06-01  Alan Modra  <amodra@gmail.com>
1512
1513         * sysdep.h (_bfd_error_handler): Don't declare.
1514         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1515         * rl78-decode.opc: Likewise.
1516         * msp430-decode.c: Regenerate.
1517         * rl78-decode.c: Regenerate.
1518
1519 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1520
1521         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1522         * i386-init.h : Regenerated.
1523
1524 2018-05-25  Alan Modra  <amodra@gmail.com>
1525
1526         * Makefile.in: Regenerate.
1527         * po/POTFILES.in: Regenerate.
1528
1529 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1530
1531         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1532         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1533         (insert_bab, extract_bab, insert_btab, extract_btab,
1534         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1535         (BAT, BBA VBA RBS XB6S): Delete macros.
1536         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1537         (BB, BD, RBX, XC6): Update for new macros.
1538         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1539         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1540         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1541         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1542
1543 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1544
1545         * Makefile.am: Add support for s12z architecture.
1546         * configure.ac: Likewise.
1547         * disassemble.c: Likewise.
1548         * disassemble.h: Likewise.
1549         * Makefile.in: Regenerate.
1550         * configure: Regenerate.
1551         * s12z-dis.c: New file.
1552         * s12z.h: New file.
1553
1554 2018-05-18  Alan Modra  <amodra@gmail.com>
1555
1556         * nfp-dis.c: Don't #include libbfd.h.
1557         (init_nfp3200_priv): Use bfd_get_section_contents.
1558         (nit_nfp6000_mecsr_sec): Likewise.
1559
1560 2018-05-17  Nick Clifton  <nickc@redhat.com>
1561
1562         * po/zh_CN.po: Updated simplified Chinese translation.
1563
1564 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1565
1566         PR binutils/23109
1567         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1568         * aarch64-dis-2.c: Regenerate.
1569
1570 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1571
1572         PR binutils/21446
1573         * aarch64-asm.c (opintl.h): Include.
1574         (aarch64_ins_sysreg): Enforce read/write constraints.
1575         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1576         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1577         (F_REG_READ, F_REG_WRITE): New.
1578         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1579         AARCH64_OPND_SYSREG.
1580         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1581         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1582         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1583         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1584         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1585         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1586         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1587         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1588         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1589         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1590         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1591         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1592         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1593         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1594         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1595         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1596         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1597
1598 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1599
1600         PR binutils/21446
1601         * aarch64-dis.c (no_notes: New.
1602         (parse_aarch64_dis_option): Support notes.
1603         (aarch64_decode_insn, print_operands): Likewise.
1604         (print_aarch64_disassembler_options): Document notes.
1605         * aarch64-opc.c (aarch64_print_operand): Support notes.
1606
1607 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1608
1609         PR binutils/21446
1610         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1611         and take error struct.
1612         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1613         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1614         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1615         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1616         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1617         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1618         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1619         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1620         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1621         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1622         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1623         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1624         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1625         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1626         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1627         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1628         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1629         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1630         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1631         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1632         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1633         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1634         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1635         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1636         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1637         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1638         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1639         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1640         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1641         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1642         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1643         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1644         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1645         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1646         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1647         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1648         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1649         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1650         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1651         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1652         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1653         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1654         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1655         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1656         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1657         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1658         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1659         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1660         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1661         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1662         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1663         (determine_disassembling_preference, aarch64_decode_insn,
1664         print_insn_aarch64_word, print_insn_data): Take errors struct.
1665         (print_insn_aarch64): Use errors.
1666         * aarch64-asm-2.c: Regenerate.
1667         * aarch64-dis-2.c: Regenerate.
1668         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1669         boolean in aarch64_insert_operan.
1670         (print_operand_extractor): Likewise.
1671         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1672
1673 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1674
1675         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1676
1677 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1678
1679         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1680
1681 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1682
1683         * cr16-opc.c (cr16_instruction): Comment typo fix.
1684         * hppa-dis.c (print_insn_hppa): Likewise.
1685
1686 2018-05-08  Jim Wilson  <jimw@sifive.com>
1687
1688         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1689         (match_c_slli64, match_srxi_as_c_srxi): New.
1690         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1691         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1692         <c.slli, c.srli, c.srai>: Use match_s_slli.
1693         <c.slli64, c.srli64, c.srai64>: New.
1694
1695 2018-05-08  Alan Modra  <amodra@gmail.com>
1696
1697         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1698         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1699         partition opcode space for index lookup.
1700
1701 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1702
1703         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1704         <insn_length>: ...with this.  Update usage.
1705         Remove duplicate call to *info->memory_error_func.
1706
1707 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1708             H.J. Lu  <hongjiu.lu@intel.com>
1709
1710         * i386-dis.c (Gva): New.
1711         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1712         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1713         (prefix_table): New instructions (see prefix above).
1714         (mod_table): New instructions (see prefix above).
1715         (OP_G): Handle va_mode.
1716         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1717         CPU_MOVDIR64B_FLAGS.
1718         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1719         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1720         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1721         * i386-opc.tbl: Add movidir{i,64b}.
1722         * i386-init.h: Regenerated.
1723         * i386-tbl.h: Likewise.
1724
1725 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1726
1727         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1728         AddrPrefixOpReg.
1729         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1730         (AddrPrefixOpReg): This.
1731         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1732         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1733
1734 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1735
1736         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1737         (vle_num_opcodes): Likewise.
1738         (spe2_num_opcodes): Likewise.
1739         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1740         initialization loop.
1741         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1742         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1743         only once.
1744
1745 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1746
1747         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1748
1749 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1750
1751         Makefile.am: Added nfp-dis.c.
1752         configure.ac: Added bfd_nfp_arch.
1753         disassemble.h: Added print_insn_nfp prototype.
1754         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1755         nfp-dis.c: New, for NFP support.
1756         po/POTFILES.in: Added nfp-dis.c to the list.
1757         Makefile.in: Regenerate.
1758         configure: Regenerate.
1759
1760 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1761
1762         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1763         templates into their base ones.
1764         * i386-tlb.h: Re-generate.
1765
1766 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1767
1768         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1769         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1770         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1771         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1772         * i386-init.h: Re-generate.
1773
1774 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1775
1776         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1777         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1778         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1779         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1780         comment.
1781         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1782         and CpuRegMask.
1783         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1784         CpuRegMask: Delete.
1785         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1786         cpuregzmm, and cpuregmask.
1787         * i386-init.h: Re-generate.
1788         * i386-tbl.h: Re-generate.
1789
1790 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1791
1792         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1793         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1794         * i386-init.h: Re-generate.
1795
1796 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1797
1798         * i386-gen.c (VexImmExt): Delete.
1799         * i386-opc.h (VexImmExt, veximmext): Delete.
1800         * i386-opc.tbl: Drop all VexImmExt uses.
1801         * i386-tlb.h: Re-generate.
1802
1803 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1804
1805         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1806         register-only forms.
1807         * i386-tlb.h: Re-generate.
1808
1809 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1810
1811         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1812
1813 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1814
1815         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1816         PREFIX_0F1C.
1817         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1818         (cpu_flags): Add CpuCLDEMOTE.
1819         * i386-init.h: Regenerate.
1820         * i386-opc.h (enum): Add CpuCLDEMOTE,
1821         (i386_cpu_flags): Add cpucldemote.
1822         * i386-opc.tbl: Add cldemote.
1823         * i386-tbl.h: Regenerate.
1824
1825 2018-04-16  Alan Modra  <amodra@gmail.com>
1826
1827         * Makefile.am: Remove sh5 and sh64 support.
1828         * configure.ac: Likewise.
1829         * disassemble.c: Likewise.
1830         * disassemble.h: Likewise.
1831         * sh-dis.c: Likewise.
1832         * sh64-dis.c: Delete.
1833         * sh64-opc.c: Delete.
1834         * sh64-opc.h: Delete.
1835         * Makefile.in: Regenerate.
1836         * configure: Regenerate.
1837         * po/POTFILES.in: Regenerate.
1838
1839 2018-04-16  Alan Modra  <amodra@gmail.com>
1840
1841         * Makefile.am: Remove w65 support.
1842         * configure.ac: Likewise.
1843         * disassemble.c: Likewise.
1844         * disassemble.h: Likewise.
1845         * w65-dis.c: Delete.
1846         * w65-opc.h: Delete.
1847         * Makefile.in: Regenerate.
1848         * configure: Regenerate.
1849         * po/POTFILES.in: Regenerate.
1850
1851 2018-04-16  Alan Modra  <amodra@gmail.com>
1852
1853         * configure.ac: Remove we32k support.
1854         * configure: Regenerate.
1855
1856 2018-04-16  Alan Modra  <amodra@gmail.com>
1857
1858         * Makefile.am: Remove m88k support.
1859         * configure.ac: Likewise.
1860         * disassemble.c: Likewise.
1861         * disassemble.h: Likewise.
1862         * m88k-dis.c: Delete.
1863         * Makefile.in: Regenerate.
1864         * configure: Regenerate.
1865         * po/POTFILES.in: Regenerate.
1866
1867 2018-04-16  Alan Modra  <amodra@gmail.com>
1868
1869         * Makefile.am: Remove i370 support.
1870         * configure.ac: Likewise.
1871         * disassemble.c: Likewise.
1872         * disassemble.h: Likewise.
1873         * i370-dis.c: Delete.
1874         * i370-opc.c: Delete.
1875         * Makefile.in: Regenerate.
1876         * configure: Regenerate.
1877         * po/POTFILES.in: Regenerate.
1878
1879 2018-04-16  Alan Modra  <amodra@gmail.com>
1880
1881         * Makefile.am: Remove h8500 support.
1882         * configure.ac: Likewise.
1883         * disassemble.c: Likewise.
1884         * disassemble.h: Likewise.
1885         * h8500-dis.c: Delete.
1886         * h8500-opc.h: Delete.
1887         * Makefile.in: Regenerate.
1888         * configure: Regenerate.
1889         * po/POTFILES.in: Regenerate.
1890
1891 2018-04-16  Alan Modra  <amodra@gmail.com>
1892
1893         * configure.ac: Remove tahoe support.
1894         * configure: Regenerate.
1895
1896 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1897
1898         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1899         umwait.
1900         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1901         64-bit mode.
1902         * i386-tbl.h: Regenerated.
1903
1904 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1905
1906         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1907         PREFIX_MOD_1_0FAE_REG_6.
1908         (va_mode): New.
1909         (OP_E_register): Use va_mode.
1910         * i386-dis-evex.h (prefix_table):
1911         New instructions (see prefixes above).
1912         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1913         (cpu_flags): Likewise.
1914         * i386-opc.h (enum): Likewise.
1915         (i386_cpu_flags): Likewise.
1916         * i386-opc.tbl: Add umonitor, umwait, tpause.
1917         * i386-init.h: Regenerate.
1918         * i386-tbl.h: Likewise.
1919
1920 2018-04-11  Alan Modra  <amodra@gmail.com>
1921
1922         * opcodes/i860-dis.c: Delete.
1923         * opcodes/i960-dis.c: Delete.
1924         * Makefile.am: Remove i860 and i960 support.
1925         * configure.ac: Likewise.
1926         * disassemble.c: Likewise.
1927         * disassemble.h: Likewise.
1928         * Makefile.in: Regenerate.
1929         * configure: Regenerate.
1930         * po/POTFILES.in: Regenerate.
1931
1932 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1933
1934         PR binutils/23025
1935         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1936         to 0.
1937         (print_insn): Clear vex instead of vex.evex.
1938
1939 2018-04-04  Nick Clifton  <nickc@redhat.com>
1940
1941         * po/es.po: Updated Spanish translation.
1942
1943 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1944
1945         * i386-gen.c (opcode_modifiers): Delete VecESize.
1946         * i386-opc.h (VecESize): Delete.
1947         (struct i386_opcode_modifier): Delete vecesize.
1948         * i386-opc.tbl: Drop VecESize.
1949         * i386-tlb.h: Re-generate.
1950
1951 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1952
1953         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1954         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1955         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1956         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1957         * i386-tlb.h: Re-generate.
1958
1959 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1960
1961         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1962         Fold AVX512 forms
1963         * i386-tlb.h: Re-generate.
1964
1965 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1966
1967         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1968         (vex_len_table): Drop Y for vcvt*2si.
1969         (putop): Replace plain 'Y' handling by abort().
1970
1971 2018-03-28  Nick Clifton  <nickc@redhat.com>
1972
1973         PR 22988
1974         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1975         instructions with only a base address register.
1976         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1977         handle AARHC64_OPND_SVE_ADDR_R.
1978         (aarch64_print_operand): Likewise.
1979         * aarch64-asm-2.c: Regenerate.
1980         * aarch64_dis-2.c: Regenerate.
1981         * aarch64-opc-2.c: Regenerate.
1982
1983 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1984
1985         * i386-opc.tbl: Drop VecESize from register only insn forms and
1986         memory forms not allowing broadcast.
1987         * i386-tlb.h: Re-generate.
1988
1989 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1990
1991         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1992         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1993         sha256*): Drop Disp<N>.
1994
1995 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1996
1997         * i386-dis.c (EbndS, bnd_swap_mode): New.
1998         (prefix_table): Use EbndS.
1999         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2000         * i386-opc.tbl (bndmov): Move misplaced Load.
2001         * i386-tlb.h: Re-generate.
2002
2003 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2004
2005         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2006         templates allowing memory operands and folded ones for register
2007         only flavors.
2008         * i386-tlb.h: Re-generate.
2009
2010 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2011
2012         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2013         256-bit templates. Drop redundant leftover Disp<N>.
2014         * i386-tlb.h: Re-generate.
2015
2016 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2017
2018         * riscv-opc.c (riscv_insn_types): New.
2019
2020 2018-03-13  Nick Clifton  <nickc@redhat.com>
2021
2022         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2023
2024 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2025
2026         * i386-opc.tbl: Add Optimize to clr.
2027         * i386-tbl.h: Regenerated.
2028
2029 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2030
2031         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2032         * i386-opc.h (OldGcc): Removed.
2033         (i386_opcode_modifier): Remove oldgcc.
2034         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2035         instructions for old (<= 2.8.1) versions of gcc.
2036         * i386-tbl.h: Regenerated.
2037
2038 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2039
2040         * i386-opc.h (EVEXDYN): New.
2041         * i386-opc.tbl: Fold various AVX512VL templates.
2042         * i386-tlb.h: Re-generate.
2043
2044 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2045
2046         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2047         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2048         vpexpandd, vpexpandq): Fold AFX512VF templates.
2049         * i386-tlb.h: Re-generate.
2050
2051 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2052
2053         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2054         Fold 128- and 256-bit VEX-encoded templates.
2055         * i386-tlb.h: Re-generate.
2056
2057 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2058
2059         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2060         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2061         vpexpandd, vpexpandq): Fold AVX512F templates.
2062         * i386-tlb.h: Re-generate.
2063
2064 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2065
2066         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2067         64-bit templates. Drop Disp<N>.
2068         * i386-tlb.h: Re-generate.
2069
2070 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2071
2072         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2073         and 256-bit templates.
2074         * i386-tlb.h: Re-generate.
2075
2076 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2077
2078         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2079         * i386-tlb.h: Re-generate.
2080
2081 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2082
2083         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2084         Drop NoAVX.
2085         * i386-tlb.h: Re-generate.
2086
2087 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2088
2089         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2090         * i386-tlb.h: Re-generate.
2091
2092 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2093
2094         * i386-gen.c (opcode_modifiers): Delete FloatD.
2095         * i386-opc.h (FloatD): Delete.
2096         (struct i386_opcode_modifier): Delete floatd.
2097         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2098         FloatD by D.
2099         * i386-tlb.h: Re-generate.
2100
2101 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2102
2103         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2104
2105 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2106
2107         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2108         * i386-tlb.h: Re-generate.
2109
2110 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2111
2112         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2113         forms.
2114         * i386-tlb.h: Re-generate.
2115
2116 2018-03-07  Alan Modra  <amodra@gmail.com>
2117
2118         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2119         bfd_arch_rs6000.
2120         * disassemble.h (print_insn_rs6000): Delete.
2121         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2122         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2123         (print_insn_rs6000): Delete.
2124
2125 2018-03-03  Alan Modra  <amodra@gmail.com>
2126
2127         * sysdep.h (opcodes_error_handler): Define.
2128         (_bfd_error_handler): Declare.
2129         * Makefile.am: Remove stray #.
2130         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2131         EDIT" comment.
2132         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2133         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2134         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2135         opcodes_error_handler to print errors.  Standardize error messages.
2136         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2137         and include opintl.h.
2138         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2139         * i386-gen.c: Standardize error messages.
2140         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2141         * Makefile.in: Regenerate.
2142         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2143         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2144         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2145         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2146         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2147         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2148         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2149         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2150         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2151         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2152         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2153         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2154         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2155
2156 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2157
2158         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2159         vpsub[bwdq] instructions.
2160         * i386-tbl.h: Regenerated.
2161
2162 2018-03-01  Alan Modra  <amodra@gmail.com>
2163
2164         * configure.ac (ALL_LINGUAS): Sort.
2165         * configure: Regenerate.
2166
2167 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2168
2169         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2170         macro by assignements.
2171
2172 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2173
2174         PR gas/22871
2175         * i386-gen.c (opcode_modifiers): Add Optimize.
2176         * i386-opc.h (Optimize): New enum.
2177         (i386_opcode_modifier): Add optimize.
2178         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2179         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2180         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2181         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2182         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2183         vpxord and vpxorq.
2184         * i386-tbl.h: Regenerated.
2185
2186 2018-02-26  Alan Modra  <amodra@gmail.com>
2187
2188         * crx-dis.c (getregliststring): Allocate a large enough buffer
2189         to silence false positive gcc8 warning.
2190
2191 2018-02-22  Shea Levy <shea@shealevy.com>
2192
2193         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2194
2195 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2196
2197         * i386-opc.tbl: Add {rex},
2198         * i386-tbl.h: Regenerated.
2199
2200 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2201
2202         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2203         (mips16_opcodes): Replace `M' with `m' for "restore".
2204
2205 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2206
2207         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2208
2209 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2210
2211         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2212         variable to `function_index'.
2213
2214 2018-02-13  Nick Clifton  <nickc@redhat.com>
2215
2216         PR 22823
2217         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2218         about truncation of printing.
2219
2220 2018-02-12  Henry Wong <henry@stuffedcow.net>
2221
2222         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2223
2224 2018-02-05  Nick Clifton  <nickc@redhat.com>
2225
2226         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2227
2228 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2229
2230         * i386-dis.c (enum): Add pconfig.
2231         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2232         (cpu_flags): Add CpuPCONFIG.
2233         * i386-opc.h (enum): Add CpuPCONFIG.
2234         (i386_cpu_flags): Add cpupconfig.
2235         * i386-opc.tbl: Add PCONFIG instruction.
2236         * i386-init.h: Regenerate.
2237         * i386-tbl.h: Likewise.
2238
2239 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2240
2241         * i386-dis.c (enum): Add PREFIX_0F09.
2242         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2243         (cpu_flags): Add CpuWBNOINVD.
2244         * i386-opc.h (enum): Add CpuWBNOINVD.
2245         (i386_cpu_flags): Add cpuwbnoinvd.
2246         * i386-opc.tbl: Add WBNOINVD instruction.
2247         * i386-init.h: Regenerate.
2248         * i386-tbl.h: Likewise.
2249
2250 2018-01-17  Jim Wilson  <jimw@sifive.com>
2251
2252         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2253
2254 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2255
2256         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2257         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2258         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2259         (cpu_flags): Add CpuIBT, CpuSHSTK.
2260         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2261         (i386_cpu_flags): Add cpuibt, cpushstk.
2262         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2263         * i386-init.h: Regenerate.
2264         * i386-tbl.h: Likewise.
2265
2266 2018-01-16  Nick Clifton  <nickc@redhat.com>
2267
2268         * po/pt_BR.po: Updated Brazilian Portugese translation.
2269         * po/de.po: Updated German translation.
2270
2271 2018-01-15  Jim Wilson  <jimw@sifive.com>
2272
2273         * riscv-opc.c (match_c_nop): New.
2274         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2275
2276 2018-01-15  Nick Clifton  <nickc@redhat.com>
2277
2278         * po/uk.po: Updated Ukranian translation.
2279
2280 2018-01-13  Nick Clifton  <nickc@redhat.com>
2281
2282         * po/opcodes.pot: Regenerated.
2283
2284 2018-01-13  Nick Clifton  <nickc@redhat.com>
2285
2286         * configure: Regenerate.
2287
2288 2018-01-13  Nick Clifton  <nickc@redhat.com>
2289
2290         2.30 branch created.
2291
2292 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2293
2294         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2295         * i386-tbl.h: Regenerate.
2296
2297 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2298
2299         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2300         * i386-tbl.h: Re-generate.
2301
2302 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2303
2304         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2305         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2306         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2307         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2308         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2309         Disp8MemShift of AVX512VL forms.
2310         * i386-tbl.h: Re-generate.
2311
2312 2018-01-09  Jim Wilson  <jimw@sifive.com>
2313
2314         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2315         then the hi_addr value is zero.
2316
2317 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2318
2319         * arm-dis.c (arm_opcodes): Add csdb.
2320         (thumb32_opcodes): Add csdb.
2321
2322 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2323
2324         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2325         * aarch64-asm-2.c: Regenerate.
2326         * aarch64-dis-2.c: Regenerate.
2327         * aarch64-opc-2.c: Regenerate.
2328
2329 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2330
2331         PR gas/22681
2332         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2333         Remove AVX512 vmovd with 64-bit operands.
2334         * i386-tbl.h: Regenerated.
2335
2336 2018-01-05  Jim Wilson  <jimw@sifive.com>
2337
2338         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2339         jalr.
2340
2341 2018-01-03  Alan Modra  <amodra@gmail.com>
2342
2343         Update year range in copyright notice of all files.
2344
2345 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2346
2347         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2348         and OPERAND_TYPE_REGZMM entries.
2349
2350 For older changes see ChangeLog-2017
2351 \f
2352 Copyright (C) 2018 Free Software Foundation, Inc.
2353
2354 Copying and distribution of this file, with or without modification,
2355 are permitted in any medium without royalty provided the copyright
2356 notice and this notice are preserved.
2357
2358 Local Variables:
2359 mode: change-log
2360 left-margin: 8
2361 fill-column: 74
2362 version-control: never
2363 End: