opcodes/ChangeLog

   1 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
   4         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
   5         (rm_table): Update the RM_0FAE_REG_7 entry.
   6         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
   7         (cpu_flags): Remove CpuPCOMMIT.
   8         * i386-opc.h (CpuPCOMMIT): Removed.
   9         (i386_cpu_flags): Remove cpupcommit.
  10         * i386-opc.tbl: Remove pcommit.
  11         * i386-init.h: Regenerated.
  12         * i386-tbl.h: Likewise.
  13
  14 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
  15
  16         PR binutis/20705
  17         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
  18         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
  19         32-bit mode.  Don't check vex.register_specifier in 32-bit
  20         mode.
  21         (OP_VEX): Check for invalid mask registers.
  22
  23 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
  24
  25         PR binutis/20699
  26         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
  27         sizeflag.
  28
  29 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         PR binutis/20704
  32         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
  33
  34 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
  35
  36         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
  37         local variable to `index_regno'.
  38
  39 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
  40
  41         * arc-tbl.h: Removed any "inv.+" instructions from the table.
  42
  43 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
  44
  45         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
  46         usage on ISA basis.
  47
  48 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
  49
  50         PR target/20666
  51         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
  52
  53 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
  54
  55         PR target/20667
  56         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
  57         available.
  58
  59 2016-10-07  Alan Modra  <amodra@gmail.com>
  60
  61         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
  62
  63 2016-10-06  Alan Modra  <amodra@gmail.com>
  64
  65         * aarch64-opc.c: Spell fall through comments consistently.
  66         * i386-dis.c: Likewise.
  67         * aarch64-dis.c: Add missing fall through comments.
  68         * aarch64-opc.c: Likewise.
  69         * arc-dis.c: Likewise.
  70         * arm-dis.c: Likewise.
  71         * i386-dis.c: Likewise.
  72         * m68k-dis.c: Likewise.
  73         * mep-asm.c: Likewise.
  74         * ns32k-dis.c: Likewise.
  75         * sh-dis.c: Likewise.
  76         * tic4x-dis.c: Likewise.
  77         * tic6x-dis.c: Likewise.
  78         * vax-dis.c: Likewise.
  79
  80 2016-10-06  Alan Modra  <amodra@gmail.com>
  81
  82         * arc-ext.c (create_map): Add missing break.
  83         * msp430-decode.opc (encode_as): Likewise.
  84         * msp430-decode.c: Regenerate.
  85
  86 2016-10-06  Alan Modra  <amodra@gmail.com>
  87
  88         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
  89         * crx-dis.c (print_insn_crx): Likewise.
  90
  91 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  92
  93         PR binutils/20657
  94         * i386-dis.c (putop): Don't assign alt twice.
  95
  96 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
  97
  98         PR target/20553
  99         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 100
 101 2016-09-29  Alan Modra  <amodra@gmail.com>
 102
 103         * ppc-opc.c (L): Make compulsory.
 104         (LOPT): New, optional form of L.
 105         (HTM_R): Define as LOPT.
 106         (L0, L1): Delete.
 107         (L32OPT): New, optional for 32-bit L.
 108         (L2OPT): New, 2-bit L for dcbf.
 109         (SVC_LEC): Update.
 110         (L2): Define.
 111         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 112         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 113         <dcbf>: Use L2OPT.
 114         <tlbiel, tlbie>: Use LOPT.
 115         <wclr, wclrall>: Use L2.
 116
 117 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 118
 119         * Makefile.in: Regenerate.
 120         * configure: Likewise.
 121
 122 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 123
 124         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 125         (EXTINSN2OP): Use EXTINSN2OPF.
 126         (bspeekm, bspop, modapp): New extension instructions.
 127         * arc-opc.c (F_DNZ_ND): Define.
 128         (F_DNZ_D): Likewise.
 129         (F_SIZEB1): Changed.
 130         (C_DNZ_D): Define.
 131         (C_HARD): Changed.
 132         * arc-tbl.h (dbnz): New instruction.
 133         (prealloc): Allow it for ARC EM.
 134         (xbfu): Likewise.
 135
 136 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 137
 138         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 139         after commas in addresses.
 140         (aarch64_print_operand): Likewise.
 141
 142 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 143
 144         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 145         rather than "should be" or "expected to be" in error messages.
 146
 147 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 148
 149         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 150         (print_mnemonic_name): ...here.
 151         (print_comment): New function.
 152         (print_aarch64_insn): Call it.
 153         * aarch64-opc.c (aarch64_conds): Add SVE names.
 154         (aarch64_print_operand): Print alternative condition names in
 155         a comment.
 156
 157 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 158
 159         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 160         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 161         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 162         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 163         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 164         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 165         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 166         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 167         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 168         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 169         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 170         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 171         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 172         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 173         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 174         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 175         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 176         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 177         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 178         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 179         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 180         (aarch64_feature_sve): New variable.
 181         (SVE): New macro.
 182         (_SVE_INSN): Likewise.
 183         (aarch64_opcode_table): Add SVE instructions.
 184         * aarch64-opc.h (extract_fields): Declare.
 185         * aarch64-opc-2.c: Regenerate.
 186         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 187         * aarch64-asm-2.c: Regenerate.
 188         * aarch64-dis.c (extract_fields): Make global.
 189         (do_misc_decoding): Handle the new SVE aarch64_ops.
 190         * aarch64-dis-2.c: Regenerate.
 191
 192 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 193
 194         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 195         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 196         aarch64_field_kinds.
 197         * aarch64-opc.c (fields): Add corresponding entries.
 198         * aarch64-asm.c (aarch64_get_variant): New function.
 199         (aarch64_encode_variant_using_iclass): Likewise.
 200         (aarch64_opcode_encode): Call it.
 201         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 202         (aarch64_opcode_decode): Call it.
 203
 204 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 205
 206         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 207         and FP register operands.
 208         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 209         (FLD_SVE_Vn): New aarch64_field_kinds.
 210         * aarch64-opc.c (fields): Add corresponding entries.
 211         (aarch64_print_operand): Handle the new SVE core and FP register
 212         operands.
 213         * aarch64-opc-2.c: Regenerate.
 214         * aarch64-asm-2.c: Likewise.
 215         * aarch64-dis-2.c: Likewise.
 216
 217 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 218
 219         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 220         immediate operands.
 221         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 222         * aarch64-opc.c (fields): Add corresponding entry.
 223         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 224         operands.
 225         (aarch64_print_operand): Likewise.
 226         * aarch64-opc-2.c: Regenerate.
 227         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 228         (ins_sve_float_zero_one): New inserters.
 229         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 230         (aarch64_ins_sve_float_half_two): Likewise.
 231         (aarch64_ins_sve_float_zero_one): Likewise.
 232         * aarch64-asm-2.c: Regenerate.
 233         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 234         (ext_sve_float_zero_one): New extractors.
 235         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 236         (aarch64_ext_sve_float_half_two): Likewise.
 237         (aarch64_ext_sve_float_zero_one): Likewise.
 238         * aarch64-dis-2.c: Regenerate.
 239
 240 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 241
 242         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 243         integer immediate operands.
 244         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 245         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 246         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 247         * aarch64-opc.c (fields): Add corresponding entries.
 248         (operand_general_constraint_met_p): Handle the new SVE integer
 249         immediate operands.
 250         (aarch64_print_operand): Likewise.
 251         (aarch64_sve_dupm_mov_immediate_p): New function.
 252         * aarch64-opc-2.c: Regenerate.
 253         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 254         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 255         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 256         (aarch64_ins_limm): ...here.
 257         (aarch64_ins_inv_limm): New function.
 258         (aarch64_ins_sve_aimm): Likewise.
 259         (aarch64_ins_sve_asimm): Likewise.
 260         (aarch64_ins_sve_limm_mov): Likewise.
 261         (aarch64_ins_sve_shlimm): Likewise.
 262         (aarch64_ins_sve_shrimm): Likewise.
 263         * aarch64-asm-2.c: Regenerate.
 264         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 265         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 266         * aarch64-dis.c (decode_limm): New function, split out from...
 267         (aarch64_ext_limm): ...here.
 268         (aarch64_ext_inv_limm): New function.
 269         (decode_sve_aimm): Likewise.
 270         (aarch64_ext_sve_aimm): Likewise.
 271         (aarch64_ext_sve_asimm): Likewise.
 272         (aarch64_ext_sve_limm_mov): Likewise.
 273         (aarch64_top_bit): Likewise.
 274         (aarch64_ext_sve_shlimm): Likewise.
 275         (aarch64_ext_sve_shrimm): Likewise.
 276         * aarch64-dis-2.c: Regenerate.
 277
 278 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 279
 280         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 281         operands.
 282         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 283         the AARCH64_MOD_MUL_VL entry.
 284         (value_aligned_p): Cope with non-power-of-two alignments.
 285         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 286         (print_immediate_offset_address): Likewise.
 287         (aarch64_print_operand): Likewise.
 288         * aarch64-opc-2.c: Regenerate.
 289         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 290         (ins_sve_addr_ri_s9xvl): New inserters.
 291         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 292         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 293         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 294         * aarch64-asm-2.c: Regenerate.
 295         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 296         (ext_sve_addr_ri_s9xvl): New extractors.
 297         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 298         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 299         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 300         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 301         * aarch64-dis-2.c: Regenerate.
 302
 303 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 304
 305         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 306         address operands.
 307         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 308         (FLD_SVE_xs_22): New aarch64_field_kinds.
 309         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 310         (get_operand_specific_data): New function.
 311         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 312         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 313         (operand_general_constraint_met_p): Handle the new SVE address
 314         operands.
 315         (sve_reg): New array.
 316         (get_addr_sve_reg_name): New function.
 317         (aarch64_print_operand): Handle the new SVE address operands.
 318         * aarch64-opc-2.c: Regenerate.
 319         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 320         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 321         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 322         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 323         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 324         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 325         (aarch64_ins_sve_addr_zi_u5): Likewise.
 326         (aarch64_ins_sve_addr_zz): Likewise.
 327         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 328         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 329         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 330         * aarch64-asm-2.c: Regenerate.
 331         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 332         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 333         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 334         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 335         (aarch64_ext_sve_addr_ri_u6): Likewise.
 336         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 337         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 338         (aarch64_ext_sve_addr_zi_u5): Likewise.
 339         (aarch64_ext_sve_addr_zz): Likewise.
 340         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 341         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 342         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 343         * aarch64-dis-2.c: Regenerate.
 344
 345 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 346
 347         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 348         AARCH64_OPND_SVE_PATTERN_SCALED.
 349         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 350         * aarch64-opc.c (fields): Add a corresponding entry.
 351         (set_multiplier_out_of_range_error): New function.
 352         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 353         (operand_general_constraint_met_p): Handle
 354         AARCH64_OPND_SVE_PATTERN_SCALED.
 355         (print_register_offset_address): Use PRIi64 to print the
 356         shift amount.
 357         (aarch64_print_operand): Likewise.  Handle
 358         AARCH64_OPND_SVE_PATTERN_SCALED.
 359         * aarch64-opc-2.c: Regenerate.
 360         * aarch64-asm.h (ins_sve_scale): New inserter.
 361         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 362         * aarch64-asm-2.c: Regenerate.
 363         * aarch64-dis.h (ext_sve_scale): New inserter.
 364         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 365         * aarch64-dis-2.c: Regenerate.
 366
 367 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 368
 369         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 370         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 371         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 372         (FLD_SVE_prfop): Likewise.
 373         * aarch64-opc.c: Include libiberty.h.
 374         (aarch64_sve_pattern_array): New variable.
 375         (aarch64_sve_prfop_array): Likewise.
 376         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 377         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 378         AARCH64_OPND_SVE_PRFOP.
 379         * aarch64-asm-2.c: Regenerate.
 380         * aarch64-dis-2.c: Likewise.
 381         * aarch64-opc-2.c: Likewise.
 382
 383 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 384
 385         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 386         AARCH64_OPND_QLF_P_[ZM].
 387         (aarch64_print_operand): Print /z and /m where appropriate.
 388
 389 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 390
 391         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 392         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 393         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 394         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 395         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 396         * aarch64-opc.c (fields): Add corresponding entries here.
 397         (operand_general_constraint_met_p): Check that SVE register lists
 398         have the correct length.  Check the ranges of SVE index registers.
 399         Check for cases where p8-p15 are used in 3-bit predicate fields.
 400         (aarch64_print_operand): Handle the new SVE operands.
 401         * aarch64-opc-2.c: Regenerate.
 402         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 403         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 404         (aarch64_ins_sve_reglist): Likewise.
 405         * aarch64-asm-2.c: Regenerate.
 406         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 407         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 408         (aarch64_ext_sve_reglist): Likewise.
 409         * aarch64-dis-2.c: Regenerate.
 410
 411 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 412
 413         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 414         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 415         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 416         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 417         tied operands.
 418
 419 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 420
 421         * aarch64-opc.c (get_offset_int_reg_name): New function.
 422         (print_immediate_offset_address): Likewise.
 423         (print_register_offset_address): Take the base and offset
 424         registers as parameters.
 425         (aarch64_print_operand): Update caller accordingly.  Use
 426         print_immediate_offset_address.
 427
 428 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 429
 430         * aarch64-opc.c (BANK): New macro.
 431         (R32, R64): Take a register number as argument
 432         (int_reg): Use BANK.
 433
 434 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 435
 436         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 437         (aarch64_print_operand): Update accordingly.
 438
 439 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 440
 441         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 442         for FPIMM.
 443         * aarch64-asm.h (ins_fpimm): New inserter.
 444         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 445         * aarch64-asm-2.c: Regenerate.
 446         * aarch64-dis.h (ext_fpimm): New extractor.
 447         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 448         (aarch64_ext_fpimm): New function.
 449         * aarch64-dis-2.c: Regenerate.
 450
 451 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 452
 453         * aarch64-asm.c: Include libiberty.h.
 454         (insert_fields): New function.
 455         (aarch64_ins_imm): Use it.
 456         * aarch64-dis.c (extract_fields): New function.
 457         (aarch64_ext_imm): Use it.
 458
 459 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 460
 461         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 462         with an esize parameter.
 463         (operand_general_constraint_met_p): Update accordingly.
 464         Fix misindented code.
 465         * aarch64-asm.c (aarch64_ins_limm): Update call to
 466         aarch64_logical_immediate_p.
 467
 468 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 469
 470         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 471
 472 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 473
 474         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 475
 476 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 477
 478         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 479
 480 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 481
 482         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 483         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 484         xor3>: Delete mnemonics.
 485         <cp_abort>: Rename mnemonic from ...
 486         <cpabort>: ...to this.
 487         <setb>: Change to a X form instruction.
 488         <sync>: Change to 1 operand form.
 489         <copy>: Delete mnemonic.
 490         <copy_first>: Rename mnemonic from ...
 491         <copy>: ...to this.
 492         <paste, paste.>: Delete mnemonics.
 493         <paste_last>: Rename mnemonic from ...
 494         <paste.>: ...to this.
 495
 496 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 497
 498         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 499
 500 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 501
 502         * s390-mkopc.c (main): Support alternate arch strings.
 503
 504 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 505
 506         * s390-opc.txt: Fix kmctr instruction type.
 507
 508 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 509
 510         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 511         * i386-init.h: Regenerated.
 512
 513 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 514
 515         * opcodes/arc-dis.c (print_insn_arc): Changed.
 516
 517 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 518
 519         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 520         camellia_fl.
 521
 522 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 523
 524         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 525         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 526         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 527
 528 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 529
 530         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 531         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 532         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 533         PREFIX_MOD_3_0FAE_REG_4.
 534         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 535         PREFIX_MOD_3_0FAE_REG_4.
 536         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 537         (cpu_flags): Add CpuPTWRITE.
 538         * i386-opc.h (CpuPTWRITE): New.
 539         (i386_cpu_flags): Add cpuptwrite.
 540         * i386-opc.tbl: Add ptwrite instruction.
 541         * i386-init.h: Regenerated.
 542         * i386-tbl.h: Likewise.
 543
 544 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 545
 546         * arc-dis.h: Wrap around in extern "C".
 547
 548 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 549
 550         * aarch64-tbl.h (V8_2_INSN): New macro.
 551         (aarch64_opcode_table): Use it.
 552
 553 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 554
 555         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 556         CORE_INSN, __FP_INSN and SIMD_INSN.
 557
 558 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 559
 560         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 561         (aarch64_opcode_table): Update uses accordingly.
 562
 563 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 564         Kwok Cheung Yeung  <kcy@codesourcery.com>
 565
 566         opcodes/
 567         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 568         'e_cmplwi' to 'e_cmpli' instead.
 569         (OPVUPRT, OPVUPRT_MASK): Define.
 570         (powerpc_opcodes): Add E200Z4 insns.
 571         (vle_opcodes): Add context save/restore insns.
 572
 573 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 574
 575         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 576         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 577         "j".
 578
 579 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 580
 581         * arc-nps400-tbl.h: Change block comments to GNU format.
 582         * arc-dis.c: Add new globals addrtypenames,
 583         addrtypenames_max, and addtypeunknown.
 584         (get_addrtype): New function.
 585         (print_insn_arc): Print colons and address types when
 586         required.
 587         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 588         define insert and extract functions for all address types.
 589         (arc_operands): Add operands for colon and all address
 590         types.
 591         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 592         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 593         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 594         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 595         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 596         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 597
 598 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 599
 600         * configure: Regenerated.
 601
 602 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 603
 604         * arc-dis.c (skipclass): New structure.
 605         (decodelist): New variable.
 606         (is_compatible_p): New function.
 607         (new_element): Likewise.
 608         (skip_class_p): Likewise.
 609         (find_format_from_table): Use skip_class_p function.
 610         (find_format): Decode first the extension instructions.
 611         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 612         e_flags.
 613         (parse_option): New function.
 614         (parse_disassembler_options): Likewise.
 615         (print_arc_disassembler_options): Likewise.
 616         (print_insn_arc): Use parse_disassembler_options function.  Proper
 617         select ARCv2 cpu variant.
 618         * disassemble.c (disassembler_usage): Add ARC disassembler
 619         options.
 620
 621 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 622
 623         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 624         annotation from the "nal" entry and reorder it beyond "bltzal".
 625
 626 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 627
 628         * sparc-opc.c (ldtxa): New macro.
 629         (sparc_opcodes): Use the macro defined above to add entries for
 630         the LDTXA instructions.
 631         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 632         instruction.
 633
 634 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 635
 636         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 637         and "jmpc".
 638
 639 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 640
 641         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 642         (movzb): Adjust to cover all permitted suffixes.
 643         (movzw): New.
 644         * i386-tbl.h: Re-generate.
 645
 646 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 649         (lgdt): Remove Tbyte from non-64-bit variant.
 650         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 651         xsaves64, xsavec64): Remove Disp16.
 652         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 653         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 654         64-bit variants.
 655         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 656         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 657         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 658         64-bit variants.
 659         * i386-tbl.h: Re-generate.
 660
 661 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 662
 663         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 664         * i386-tbl.h: Re-generate.
 665
 666 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 667
 668         * arm-dis.c (print_insn): Fix typo in comment.
 669
 670 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 671
 672         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 673         range of ldst_elemlist operands.
 674         (print_register_list): Use PRIi64 to print the index.
 675         (aarch64_print_operand): Likewise.
 676
 677 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 678
 679         * mcore-opc.h: Remove sentinal.
 680         * mcore-dis.c (print_insn_mcore): Adjust.
 681
 682 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 683
 684         * arc-opc.c: Correct description of availability of NPS400
 685         features.
 686
 687 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 688
 689         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 690         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 691         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 692         xor3>: New mnemonics.
 693         <setb>: Change to a VX form instruction.
 694         (insert_sh6): Add support for rldixor.
 695         (extract_sh6): Likewise.
 696
 697 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 698
 699         * arc-ext.h: Wrap in extern C.
 700
 701 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 702
 703         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 704         Use same method for determining instruction length on ARC700 and
 705         NPS-400.
 706         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 707         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 708         with the NPS400 subclass.
 709         * arc-opc.c: Likewise.
 710
 711 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 712
 713         * sparc-opc.c (rdasr): New macro.
 714         (wrasr): Likewise.
 715         (rdpr): Likewise.
 716         (wrpr): Likewise.
 717         (rdhpr): Likewise.
 718         (wrhpr): Likewise.
 719         (sparc_opcodes): Use the macros above to fix and expand the
 720         definition of read/write instructions from/to
 721         asr/privileged/hyperprivileged instructions.
 722         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 723         %hva_mask_nz.  Prefer softint_set and softint_clear over
 724         set_softint and clear_softint.
 725         (print_insn_sparc): Support %ver in Rd.
 726
 727 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 728
 729         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 730         architecture according to the hardware capabilities they require.
 731
 732 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 733
 734         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 735         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 736         bfd_mach_sparc_v9{c,d,e,v,m}.
 737         * sparc-opc.c (MASK_V9C): Define.
 738         (MASK_V9D): Likewise.
 739         (MASK_V9E): Likewise.
 740         (MASK_V9V): Likewise.
 741         (MASK_V9M): Likewise.
 742         (v6): Add MASK_V9{C,D,E,V,M}.
 743         (v6notlet): Likewise.
 744         (v7): Likewise.
 745         (v8): Likewise.
 746         (v9): Likewise.
 747         (v9andleon): Likewise.
 748         (v9a): Likewise.
 749         (v9b): Likewise.
 750         (v9c): Define.
 751         (v9d): Likewise.
 752         (v9e): Likewise.
 753         (v9v): Likewise.
 754         (v9m): Likewise.
 755         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 756
 757 2016-06-15  Nick Clifton  <nickc@redhat.com>
 758
 759         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 760         constants to match expected behaviour.
 761         (nds32_parse_opcode): Likewise.  Also for whitespace.
 762
 763 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 764
 765         * arc-opc.c (extract_rhv1): Extract value from insn.
 766
 767 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 768
 769         * arc-nps400-tbl.h: Add ldbit instruction.
 770         * arc-opc.c: Add flag classes required for ldbit.
 771
 772 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 773
 774         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 775         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 776         support the above instructions.
 777
 778 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 779
 780         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 781         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 782         csma, cbba, zncv, and hofs.
 783         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 784         support the above instructions.
 785
 786 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 787
 788         * arc-nps400-tbl.h: Add andab and orab instructions.
 789
 790 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 791
 792         * arc-nps400-tbl.h: Add addl-like instructions.
 793
 794 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 795
 796         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 797
 798 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 799
 800         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 801         instructions.
 802
 803 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 804
 805         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 806         variable.
 807         (init_disasm): Handle new command line option "insnlength".
 808         (print_s390_disassembler_options): Mention new option in help
 809         output.
 810         (print_insn_s390): Use the encoded insn length when dumping
 811         unknown instructions.
 812
 813 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 814
 815         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 816          to the address and set as symbol address for LDS/ STS immediate operands.
 817
 818 2016-06-07  Alan Modra  <amodra@gmail.com>
 819
 820         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 821         cpu for "vle" to e500.
 822         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 823         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 824         (PPCNONE): Delete, substitute throughout.
 825         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 826         except for major opcode 4 and 31.
 827         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 828
 829 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 830
 831         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 832         ARM_EXT_RAS in relevant entries.
 833
 834 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 835
 836         PR binutils/20196
 837         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 838         opcodes for E6500.
 839
 840 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 841
 842         PR binutis/18386
 843         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 844         (indir_v_mode): New.
 845         Add comments for '&'.
 846         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 847         (putop): Handle '&'.
 848         (intel_operand_size): Handle indir_v_mode.
 849         (OP_E_register): Likewise.
 850         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 851         64-bit indirect call/jmp for AMD64.
 852         * i386-tbl.h: Regenerated
 853
 854 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 855
 856         * arc-dis.c (struct arc_operand_iterator): New structure.
 857         (find_format_from_table): All the old content from find_format,
 858         with some minor adjustments, and parameter renaming.
 859         (find_format_long_instructions): New function.
 860         (find_format): Rewritten.
 861         (arc_insn_length): Add LSB parameter.
 862         (extract_operand_value): New function.
 863         (operand_iterator_next): New function.
 864         (print_insn_arc): Use new functions to find opcode, and iterator
 865         over operands.
 866         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 867         (extract_nps_3bit_dst_short): New function.
 868         (insert_nps_3bit_src2_short): New function.
 869         (extract_nps_3bit_src2_short): New function.
 870         (insert_nps_bitop1_size): New function.
 871         (extract_nps_bitop1_size): New function.
 872         (insert_nps_bitop2_size): New function.
 873         (extract_nps_bitop2_size): New function.
 874         (insert_nps_bitop_mod4_msb): New function.
 875         (extract_nps_bitop_mod4_msb): New function.
 876         (insert_nps_bitop_mod4_lsb): New function.
 877         (extract_nps_bitop_mod4_lsb): New function.
 878         (insert_nps_bitop_dst_pos3_pos4): New function.
 879         (extract_nps_bitop_dst_pos3_pos4): New function.
 880         (insert_nps_bitop_ins_ext): New function.
 881         (extract_nps_bitop_ins_ext): New function.
 882         (arc_operands): Add new operands.
 883         (arc_long_opcodes): New global array.
 884         (arc_num_long_opcodes): New global.
 885         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 886
 887 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 888
 889         * nds32-asm.h: Add extern "C".
 890         * sh-opc.h: Likewise.
 891
 892 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 893
 894         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 895         0,b,limm to the rflt instruction.
 896
 897 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 898
 899         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 900         constant.
 901
 902 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 903
 904         PR gas/20145
 905         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 906         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 907         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 908         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 909         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 910         * i386-init.h: Regenerated.
 911
 912 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 913
 914         PR gas/20145
 915         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 916         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 917         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 918         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 919         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 920         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 921         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 922         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 923         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 924         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 925         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 926         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 927         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 928         CpuRegMask for AVX512.
 929         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 930         and CpuRegMask.
 931         (set_bitfield_from_cpu_flag_init): New function.
 932         (set_bitfield): Remove const on f.  Call
 933         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 934         * i386-opc.h (CpuRegMMX): New.
 935         (CpuRegXMM): Likewise.
 936         (CpuRegYMM): Likewise.
 937         (CpuRegZMM): Likewise.
 938         (CpuRegMask): Likewise.
 939         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 940         and cpuregmask.
 941         * i386-init.h: Regenerated.
 942         * i386-tbl.h: Likewise.
 943
 944 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 945
 946         PR gas/20154
 947         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 948         (opcode_modifiers): Add AMD64 and Intel64.
 949         (main): Properly verify CpuMax.
 950         * i386-opc.h (CpuAMD64): Removed.
 951         (CpuIntel64): Likewise.
 952         (CpuMax): Set to CpuNo64.
 953         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 954         (AMD64): New.
 955         (Intel64): Likewise.
 956         (i386_opcode_modifier): Add amd64 and intel64.
 957         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 958         on call and jmp.
 959         * i386-init.h: Regenerated.
 960         * i386-tbl.h: Likewise.
 961
 962 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 963
 964         PR gas/20154
 965         * i386-gen.c (main): Fail if CpuMax is incorrect.
 966         * i386-opc.h (CpuMax): Set to CpuIntel64.
 967         * i386-tbl.h: Regenerated.
 968
 969 2016-05-27  Nick Clifton  <nickc@redhat.com>
 970
 971         PR target/20150
 972         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 973         (msp430dis_opcode_unsigned): New function.
 974         (msp430dis_opcode_signed): New function.
 975         (msp430_singleoperand): Use the new opcode reading functions.
 976         Only disassenmble bytes if they were successfully read.
 977         (msp430_doubleoperand): Likewise.
 978         (msp430_branchinstr): Likewise.
 979         (msp430x_callx_instr): Likewise.
 980         (print_insn_msp430): Check that it is safe to read bytes before
 981         attempting disassembly.  Use the new opcode reading functions.
 982
 983 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 984
 985         * ppc-opc.c (CY): New define.  Document it.
 986         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 987
 988 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 989
 990         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 991         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 992         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 993         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 994         CPU_ANY_AVX_FLAGS.
 995         * i386-init.h: Regenerated.
 996
 997 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 998
 999         PR gas/20141
1000         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1001         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1002         * i386-init.h: Regenerated.
1003
1004 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1005
1006         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1007         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1008         * i386-init.h: Regenerated.
1009
1010 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1011
1012         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1013         information.
1014         (print_insn_arc): Set insn_type information.
1015         * arc-opc.c (C_CC): Add F_CLASS_COND.
1016         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1017         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1018         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1019         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1020         (brne, brne_s, jeq_s, jne_s): Likewise.
1021
1022 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1023
1024         * arc-tbl.h (neg): New instruction variant.
1025
1026 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1027
1028         * arc-dis.c (find_format, find_format, get_auxreg)
1029         (print_insn_arc): Changed.
1030         * arc-ext.h (INSERT_XOP): Likewise.
1031
1032 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1033
1034         * tic54x-dis.c (sprint_mmr): Adjust.
1035         * tic54x-opc.c: Likewise.
1036
1037 2016-05-19  Alan Modra  <amodra@gmail.com>
1038
1039         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1040
1041 2016-05-19  Alan Modra  <amodra@gmail.com>
1042
1043         * ppc-opc.c: Formatting.
1044         (NSISIGNOPT): Define.
1045         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1046
1047 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1048
1049         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1050         replacing references to `micromips_ase' throughout.
1051         (_print_insn_mips): Don't use file-level microMIPS annotation to
1052         determine the disassembly mode with the symbol table.
1053
1054 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1055
1056         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1057
1058 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1059
1060         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1061         mips64r6.
1062         * mips-opc.c (D34): New macro.
1063         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1064
1065 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1066
1067         * i386-dis.c (prefix_table): Add RDPID instruction.
1068         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1069         (cpu_flags): Add RDPID bitfield.
1070         * i386-opc.h (enum): Add RDPID element.
1071         (i386_cpu_flags): Add RDPID field.
1072         * i386-opc.tbl: Add RDPID instruction.
1073         * i386-init.h: Regenerate.
1074         * i386-tbl.h: Regenerate.
1075
1076 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1077
1078         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1079         branch type of a symbol.
1080         (print_insn): Likewise.
1081
1082 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1083
1084         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1085         Mainline Security Extensions instructions.
1086         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1087         Extensions instructions.
1088         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1089         instructions.
1090         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1091         special registers.
1092
1093 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1094
1095         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1096
1097 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1098
1099         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1100         (arcExtMap_genOpcode): Likewise.
1101         * arc-opc.c (arg_32bit_rc): Define new variable.
1102         (arg_32bit_u6): Likewise.
1103         (arg_32bit_limm): Likewise.
1104
1105 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1106
1107         * aarch64-gen.c (VERIFIER): Define.
1108         * aarch64-opc.c (VERIFIER): Define.
1109         (verify_ldpsw): Use static linkage.
1110         * aarch64-opc.h (verify_ldpsw): Remove.
1111         * aarch64-tbl.h: Use VERIFIER for verifiers.
1112
1113 2016-04-28  Nick Clifton  <nickc@redhat.com>
1114
1115         PR target/19722
1116         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1117         * aarch64-opc.c (verify_ldpsw): New function.
1118         * aarch64-opc.h (verify_ldpsw): New prototype.
1119         * aarch64-tbl.h: Add initialiser for verifier field.
1120         (LDPSW): Set verifier to verify_ldpsw.
1121
1122 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1123
1124         PR binutils/19983
1125         PR binutils/19984
1126         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1127         smaller than address size.
1128
1129 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1130
1131         * alpha-dis.c: Regenerate.
1132         * crx-dis.c: Likewise.
1133         * disassemble.c: Likewise.
1134         * epiphany-opc.c: Likewise.
1135         * fr30-opc.c: Likewise.
1136         * frv-opc.c: Likewise.
1137         * ip2k-opc.c: Likewise.
1138         * iq2000-opc.c: Likewise.
1139         * lm32-opc.c: Likewise.
1140         * lm32-opinst.c: Likewise.
1141         * m32c-opc.c: Likewise.
1142         * m32r-opc.c: Likewise.
1143         * m32r-opinst.c: Likewise.
1144         * mep-opc.c: Likewise.
1145         * mt-opc.c: Likewise.
1146         * or1k-opc.c: Likewise.
1147         * or1k-opinst.c: Likewise.
1148         * tic80-opc.c: Likewise.
1149         * xc16x-opc.c: Likewise.
1150         * xstormy16-opc.c: Likewise.
1151
1152 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1153
1154         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1155         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1156         calcsd, and calcxd instructions.
1157         * arc-opc.c (insert_nps_bitop_size): Delete.
1158         (extract_nps_bitop_size): Delete.
1159         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1160         (extract_nps_qcmp_m3): Define.
1161         (extract_nps_qcmp_m2): Define.
1162         (extract_nps_qcmp_m1): Define.
1163         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1164         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1165         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1166         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1167         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1168         NPS_QCMP_M3.
1169
1170 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1171
1172         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1173
1174 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1175
1176         * Makefile.in: Regenerated with automake 1.11.6.
1177         * aclocal.m4: Likewise.
1178
1179 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1180
1181         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1182         instructions.
1183         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1184         (extract_nps_cmem_uimm16): New function.
1185         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1186
1187 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1188
1189         * arc-dis.c (arc_insn_length): New function.
1190         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1191         (find_format): Change insnLen parameter to unsigned.
1192
1193 2016-04-13  Nick Clifton  <nickc@redhat.com>
1194
1195         PR target/19937
1196         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1197         the LD.B and LD.BU instructions.
1198
1199 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1200
1201         * arc-dis.c (find_format): Check for extension flags.
1202         (print_flags): New function.
1203         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1204         .extAuxRegister.
1205         * arc-ext.c (arcExtMap_coreRegName): Use
1206         LAST_EXTENSION_CORE_REGISTER.
1207         (arcExtMap_coreReadWrite): Likewise.
1208         (dump_ARC_extmap): Update printing.
1209         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1210         (arc_aux_regs): Add cpu field.
1211         * arc-regs.h: Add cpu field, lower case name aux registers.
1212
1213 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1214
1215         * arc-tbl.h: Add rtsc, sleep with no arguments.
1216
1217 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1218
1219         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1220         Initialize.
1221         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1222         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1223         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1224         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1225         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1226         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1227         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1228         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1229         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1230         (arc_opcode arc_opcodes): Null terminate the array.
1231         (arc_num_opcodes): Remove.
1232         * arc-ext.h (INSERT_XOP): Define.
1233         (extInstruction_t): Likewise.
1234         (arcExtMap_instName): Delete.
1235         (arcExtMap_insn): New function.
1236         (arcExtMap_genOpcode): Likewise.
1237         * arc-ext.c (ExtInstruction): Remove.
1238         (create_map): Zero initialize instruction fields.
1239         (arcExtMap_instName): Remove.
1240         (arcExtMap_insn): New function.
1241         (dump_ARC_extmap): More info while debuging.
1242         (arcExtMap_genOpcode): New function.
1243         * arc-dis.c (find_format): New function.
1244         (print_insn_arc): Use find_format.
1245         (arc_get_disassembler): Enable dump_ARC_extmap only when
1246         debugging.
1247
1248 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1249
1250         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1251         instruction bits out.
1252
1253 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1254
1255         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1256         * arc-opc.c (arc_flag_operands): Add new flags.
1257         (arc_flag_classes): Add new classes.
1258
1259 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1260
1261         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1262
1263 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1264
1265         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1266         encode1, rflt, crc16, and crc32 instructions.
1267         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1268         (arc_flag_classes): Add C_NPS_R.
1269         (insert_nps_bitop_size_2b): New function.
1270         (extract_nps_bitop_size_2b): Likewise.
1271         (insert_nps_bitop_uimm8): Likewise.
1272         (extract_nps_bitop_uimm8): Likewise.
1273         (arc_operands): Add new operand entries.
1274
1275 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1276
1277         * arc-regs.h: Add a new subclass field.  Add double assist
1278         accumulator register values.
1279         * arc-tbl.h: Use DPA subclass to mark the double assist
1280         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1281         * arc-opc.c (RSP): Define instead of SP.
1282         (arc_aux_regs): Add the subclass field.
1283
1284 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1285
1286         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1287
1288 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1289
1290         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1291         NPS_R_SRC1.
1292
1293 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1294
1295         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1296         issues.  No functional changes.
1297
1298 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1299
1300         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1301         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1302         (RTT): Remove duplicate.
1303         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1304         (PCT_CONFIG*): Remove.
1305         (D1L, D1H, D2H, D2L): Define.
1306
1307 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1308
1309         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1310
1311 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1312
1313         * arc-tbl.h (invld07): Remove.
1314         * arc-ext-tbl.h: New file.
1315         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1316         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1317
1318 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1319
1320         Fix -Wstack-usage warnings.
1321         * aarch64-dis.c (print_operands): Substitute size.
1322         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1323
1324 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1325
1326         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1327         to get a proper diagnostic when an invalid ASR register is used.
1328
1329 2016-03-22  Nick Clifton  <nickc@redhat.com>
1330
1331         * configure: Regenerate.
1332
1333 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1334
1335         * arc-nps400-tbl.h: New file.
1336         * arc-opc.c: Add top level comment.
1337         (insert_nps_3bit_dst): New function.
1338         (extract_nps_3bit_dst): New function.
1339         (insert_nps_3bit_src2): New function.
1340         (extract_nps_3bit_src2): New function.
1341         (insert_nps_bitop_size): New function.
1342         (extract_nps_bitop_size): New function.
1343         (arc_flag_operands): Add nps400 entries.
1344         (arc_flag_classes): Add nps400 entries.
1345         (arc_operands): Add nps400 entries.
1346         (arc_opcodes): Add nps400 include.
1347
1348 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1349
1350         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1351         the new class enum values.
1352
1353 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1354
1355         * arc-dis.c (print_insn_arc): Handle nps400.
1356
1357 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1358
1359         * arc-opc.c (BASE): Delete.
1360
1361 2016-03-18  Nick Clifton  <nickc@redhat.com>
1362
1363         PR target/19721
1364         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1365         of MOV insn that aliases an ORR insn.
1366
1367 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1368
1369         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1370
1371 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1372
1373         * mcore-opc.h: Add const qualifiers.
1374         * microblaze-opc.h (struct op_code_struct): Likewise.
1375         * sh-opc.h: Likewise.
1376         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1377         (tic4x_print_op): Likewise.
1378
1379 2016-03-02  Alan Modra  <amodra@gmail.com>
1380
1381         * or1k-desc.h: Regenerate.
1382         * fr30-ibld.c: Regenerate.
1383         * rl78-decode.c: Regenerate.
1384
1385 2016-03-01  Nick Clifton  <nickc@redhat.com>
1386
1387         PR target/19747
1388         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1389
1390 2016-02-24  Renlin Li  <renlin.li@arm.com>
1391
1392         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1393         (print_insn_coprocessor): Support fp16 instructions.
1394
1395 2016-02-24  Renlin Li  <renlin.li@arm.com>
1396
1397         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1398         vminnm, vrint(mpna).
1399
1400 2016-02-24  Renlin Li  <renlin.li@arm.com>
1401
1402         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1403         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1404
1405 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1406
1407         * i386-dis.c (print_insn): Parenthesize expression to prevent
1408         truncated addresses.
1409         (OP_J): Likewise.
1410
1411 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1412             Janek van Oirschot  <jvanoirs@synopsys.com>
1413
1414         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1415         variable.
1416
1417 2016-02-04  Nick Clifton  <nickc@redhat.com>
1418
1419         PR target/19561
1420         * msp430-dis.c (print_insn_msp430): Add a special case for
1421         decoding an RRC instruction with the ZC bit set in the extension
1422         word.
1423
1424 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1425
1426         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1427         * epiphany-ibld.c: Regenerate.
1428         * fr30-ibld.c: Regenerate.
1429         * frv-ibld.c: Regenerate.
1430         * ip2k-ibld.c: Regenerate.
1431         * iq2000-ibld.c: Regenerate.
1432         * lm32-ibld.c: Regenerate.
1433         * m32c-ibld.c: Regenerate.
1434         * m32r-ibld.c: Regenerate.
1435         * mep-ibld.c: Regenerate.
1436         * mt-ibld.c: Regenerate.
1437         * or1k-ibld.c: Regenerate.
1438         * xc16x-ibld.c: Regenerate.
1439         * xstormy16-ibld.c: Regenerate.
1440
1441 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1442
1443         * epiphany-dis.c: Regenerated from latest cpu files.
1444
1445 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1446
1447         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1448         test bit.
1449
1450 2016-01-25  Renlin Li  <renlin.li@arm.com>
1451
1452         * arm-dis.c (mapping_symbol_for_insn): New function.
1453         (find_ifthen_state): Call mapping_symbol_for_insn().
1454
1455 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1456
1457         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1458         of MSR UAO immediate operand.
1459
1460 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1461
1462         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1463         instruction support.
1464
1465 2016-01-17  Alan Modra  <amodra@gmail.com>
1466
1467         * configure: Regenerate.
1468
1469 2016-01-14  Nick Clifton  <nickc@redhat.com>
1470
1471         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1472         instructions that can support stack pointer operations.
1473         * rl78-decode.c: Regenerate.
1474         * rl78-dis.c: Fix display of stack pointer in MOVW based
1475         instructions.
1476
1477 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1478
1479         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1480         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1481         erxtatus_el1 and erxaddr_el1.
1482
1483 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1484
1485         * arm-dis.c (arm_opcodes): Add "esb".
1486         (thumb_opcodes): Likewise.
1487
1488 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1489
1490         * ppc-opc.c <xscmpnedp>: Delete.
1491         <xvcmpnedp>: Likewise.
1492         <xvcmpnedp.>: Likewise.
1493         <xvcmpnesp>: Likewise.
1494         <xvcmpnesp.>: Likewise.
1495
1496 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1497
1498         PR gas/13050
1499         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1500         addition to ISA_A.
1501
1502 2016-01-01  Alan Modra  <amodra@gmail.com>
1503
1504         Update year range in copyright notice of all files.
1505
1506 For older changes see ChangeLog-2015
1507 \f
1508 Copyright (C) 2016 Free Software Foundation, Inc.
1509
1510 Copying and distribution of this file, with or without modification,
1511 are permitted in any medium without royalty provided the copyright
1512 notice and this notice are preserved.
1513
1514 Local Variables:
1515 mode: change-log
1516 left-margin: 8
1517 fill-column: 74
1518 version-control: never
1519 End: