opcodes/ChangeLog

   1 2018-11-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (VexW0, VexW1): New.
   4         (vphadd*, vphsub*): Use VexW0 on XOP variants.
   5         * i386-tbl.h: Re-generate.
   6
   7 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
   8
   9         * s12z-dis.c (decode_possible_symbol): Add fallback case.
  10         (rel_15_7): Likewise.
  11
  12 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
  13
  14         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
  15         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
  16         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
  17
  18 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
  19
  20         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
  21         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
  22
  23 2018-10-10  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
  26         Size64. Add Size.
  27         * i386-opc.h (Size16, Size32, Size64): Delete.
  28         (Size): New.
  29         (SIZE16, SIZE32, SIZE64): Define.
  30         (struct i386_opcode_modifier): Drop size16, size32, and size64.
  31         Add size.
  32         * i386-opc.tbl (Size16, Size32, Size64): Define.
  33         * i386-tbl.h: Re-generate.
  34
  35 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  36
  37         * aarch64-opc.c (operand_general_constraint_met_p): Add
  38         SSBS in the check for one-bit immediate.
  39         (aarch64_sys_regs): New entry for SSBS.
  40         (aarch64_sys_reg_supported_p): New check for above.
  41         (aarch64_pstatefields): New entry for SSBS.
  42         (aarch64_pstatefield_supported_p): New check for above.
  43
  44 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  45
  46         * aarch64-opc.c (aarch64_sys_regs): New entries for
  47         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
  48         (aarch64_sys_reg_supported_p): New checks for above.
  49
  50 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  51
  52         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
  53         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
  54         with the hint immediate.
  55         * aarch64-opc.c (aarch64_hint_options): New entries for
  56         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
  57         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
  58         while checking for HINT_OPD_F_NOPRINT flag.
  59         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
  60         extract value.
  61         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
  62         (aarch64_opcode_table): Add entry for BTI.
  63         (AARCH64_OPERANDS): Add new description for BTI targets.
  64         * aarch64-asm-2.c: Regenerate.
  65         * aarch64-dis-2.c: Regenerate.
  66         * aarch64-opc-2.c: Regenerate.
  67
  68 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  69
  70         * aarch64-opc.c (aarch64_sys_regs): New entries for
  71         rndr and rndrrs.
  72         (aarch64_sys_reg_supported_p): New check for above.
  73
  74 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  75
  76         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
  77         (aarch64_sys_ins_reg_supported_p): New check for above.
  78
  79 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  80
  81         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
  82         AARCH64_OPND_SYSREG_SR.
  83         * aarch64-opc.c (aarch64_print_operand): Likewise.
  84         (aarch64_sys_regs_sr): Define table.
  85         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
  86         AARCH64_FEATURE_PREDRES.
  87         * aarch64-tbl.h (aarch64_feature_predres): New.
  88         (PREDRES, PREDRES_INSN): New.
  89         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
  90         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
  91         * aarch64-asm-2.c: Regenerate.
  92         * aarch64-dis-2.c: Regenerate.
  93         * aarch64-opc-2.c: Regenerate.
  94
  95 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  96
  97         * aarch64-tbl.h (aarch64_feature_sb): New.
  98         (SB, SB_INSN): New.
  99         (aarch64_opcode_table): Add entry for sb.
 100         * aarch64-asm-2.c: Regenerate.
 101         * aarch64-dis-2.c: Regenerate.
 102         * aarch64-opc-2.c: Regenerate.
 103
 104 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 105
 106         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 107         (aarch64_feature_frintts): New.
 108         (FLAGMANIP, FRINTTS): New.
 109         (aarch64_opcode_table): Add entries for xaflag, axflag
 110         and frint[32,64][x,z] instructions.
 111         * aarch64-asm-2.c: Regenerate.
 112         * aarch64-dis-2.c: Regenerate.
 113         * aarch64-opc-2.c: Regenerate.
 114
 115 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 116
 117         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 118         (ARMV8_5, V8_5_INSN): New.
 119
 120 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 121
 122         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 123
 124 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 125
 126         * i386-dis.c (rm_table): Add enclv.
 127         * i386-opc.tbl: Add enclv.
 128         * i386-tbl.h: Regenerated.
 129
 130 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 131
 132         * arm-dis.c (arm_opcodes): Add sb.
 133         (thumb32_opcodes): Likewise.
 134
 135 2018-10-05  Richard Henderson  <rth@twiddle.net>
 136             Stafford Horne  <shorne@gmail.com>
 137
 138         * or1k-desc.c: Regenerate.
 139         * or1k-desc.h: Regenerate.
 140         * or1k-opc.c: Regenerate.
 141         * or1k-opc.h: Regenerate.
 142         * or1k-opinst.c: Regenerate.
 143
 144 2018-10-05  Richard Henderson  <rth@twiddle.net>
 145
 146         * or1k-asm.c: Regenerated.
 147         * or1k-desc.c: Regenerated.
 148         * or1k-desc.h: Regenerated.
 149         * or1k-dis.c: Regenerated.
 150         * or1k-ibld.c: Regenerated.
 151         * or1k-opc.c: Regenerated.
 152         * or1k-opc.h: Regenerated.
 153         * or1k-opinst.c: Regenerated.
 154
 155 2018-10-05  Richard Henderson  <rth@twiddle.net>
 156
 157         * or1k-asm.c: Regenerate.
 158
 159 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 160
 161         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 162         * aarch64-dis.c (print_operands): Refactor to take notes.
 163         (print_verifier_notes): New.
 164         (print_aarch64_insn): Apply constraint verifier.
 165         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 166         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 167
 168 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 169
 170         * aarch64-opc.c (init_insn_block): New.
 171         (verify_constraints, aarch64_is_destructive_by_operands): New.
 172         * aarch64-opc.h (verify_constraints): New.
 173
 174 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 175
 176         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 177         * aarch64-opc.c (verify_ldpsw): Update arguments.
 178
 179 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 180
 181         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 182         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 183
 184 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 185
 186         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 187         * aarch64-dis.c (insn_sequence): New.
 188
 189 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 190
 191         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 192         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 193         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 194         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 195         constraints.
 196         (_SVE_INSNC): New.
 197         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 198         constraints.
 199         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 200         F_SCAN flags.
 201         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 202         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 203         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 204         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 205         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 206         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 207         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 208
 209 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 210
 211         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 212
 213 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 214
 215         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 216         are used when extracting signed fields and converting them to
 217         potentially 64-bit types.
 218
 219 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 220
 221         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 222         * Makefile.in: Re-generate.
 223         * aclocal.m4: Re-generate.
 224         * configure: Re-generate.
 225         * configure.ac: Remove check for -Wno-missing-field-initializers.
 226         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 227         (csky_v2_opcodes): Likewise.
 228
 229 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 230
 231         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 232
 233 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 234
 235         * nds32-asm.c (operand_fields): Remove the unused fields.
 236         (nds32_opcodes): Remove the unused instructions.
 237         * nds32-dis.c (nds32_ex9_info): Removed.
 238         (nds32_parse_opcode): Updated.
 239         (print_insn_nds32): Likewise.
 240         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 241         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 242         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 243         build_opcode_hash_table): New functions.
 244         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 245         nds32_opcode_table): New.
 246         (hw_ktabs): Declare it to a pointer rather than an array.
 247         (build_hash_table): Removed.
 248         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 249         SYN_ROPT and upadte HW_GPR and HW_INT.
 250         * nds32-dis.c (keywords): Remove const.
 251         (match_field): New function.
 252         (nds32_parse_opcode): Updated.
 253         * disassemble.c (disassemble_init_for_target):
 254         Add disassemble_init_nds32.
 255         * nds32-dis.c (eum map_type): New.
 256         (nds32_private_data): Likewise.
 257         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 258         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 259         (print_insn_nds32): Updated.
 260         * nds32-asm.c (parse_aext_reg): Add new parameter.
 261         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 262         are allowed to use.
 263         All callers changed.
 264         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 265         (operand_fields): Add new fields.
 266         (nds32_opcodes): Add new instructions.
 267         (keyword_aridxi_mx): New keyword.
 268         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 269         and NASM_ATTR_ZOL.
 270         (ALU2_1, ALU2_2, ALU2_3): New macros.
 271         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 272
 273 2018-09-17  Kito Cheng  <kito@andestech.com>
 274
 275         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 276
 277 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         PR gas/23670
 280         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 281         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 282         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 283         (EVEX_LEN_0F7E_P_1): Likewise.
 284         (EVEX_LEN_0F7E_P_2): Likewise.
 285         (EVEX_LEN_0FD6_P_2): Likewise.
 286         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 287         (EVEX_LEN_TABLE): Likewise.
 288         (EVEX_LEN_0F6E_P_2): New enum.
 289         (EVEX_LEN_0F7E_P_1): Likewise.
 290         (EVEX_LEN_0F7E_P_2): Likewise.
 291         (EVEX_LEN_0FD6_P_2): Likewise.
 292         (evex_len_table): New.
 293         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 294         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 295         * i386-tbl.h: Regenerated.
 296
 297 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 298
 299         PR gas/23665
 300         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 301         VEX_LEN_0F7E_P_2 entries.
 302         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 303         * i386-tbl.h: Regenerated.
 304
 305 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         * i386-dis.c (VZERO_Fixup): Removed.
 308         (VZERO): Likewise.
 309         (VEX_LEN_0F10_P_1): Likewise.
 310         (VEX_LEN_0F10_P_3): Likewise.
 311         (VEX_LEN_0F11_P_1): Likewise.
 312         (VEX_LEN_0F11_P_3): Likewise.
 313         (VEX_LEN_0F2E_P_0): Likewise.
 314         (VEX_LEN_0F2E_P_2): Likewise.
 315         (VEX_LEN_0F2F_P_0): Likewise.
 316         (VEX_LEN_0F2F_P_2): Likewise.
 317         (VEX_LEN_0F51_P_1): Likewise.
 318         (VEX_LEN_0F51_P_3): Likewise.
 319         (VEX_LEN_0F52_P_1): Likewise.
 320         (VEX_LEN_0F53_P_1): Likewise.
 321         (VEX_LEN_0F58_P_1): Likewise.
 322         (VEX_LEN_0F58_P_3): Likewise.
 323         (VEX_LEN_0F59_P_1): Likewise.
 324         (VEX_LEN_0F59_P_3): Likewise.
 325         (VEX_LEN_0F5A_P_1): Likewise.
 326         (VEX_LEN_0F5A_P_3): Likewise.
 327         (VEX_LEN_0F5C_P_1): Likewise.
 328         (VEX_LEN_0F5C_P_3): Likewise.
 329         (VEX_LEN_0F5D_P_1): Likewise.
 330         (VEX_LEN_0F5D_P_3): Likewise.
 331         (VEX_LEN_0F5E_P_1): Likewise.
 332         (VEX_LEN_0F5E_P_3): Likewise.
 333         (VEX_LEN_0F5F_P_1): Likewise.
 334         (VEX_LEN_0F5F_P_3): Likewise.
 335         (VEX_LEN_0FC2_P_1): Likewise.
 336         (VEX_LEN_0FC2_P_3): Likewise.
 337         (VEX_LEN_0F3A0A_P_2): Likewise.
 338         (VEX_LEN_0F3A0B_P_2): Likewise.
 339         (VEX_W_0F10_P_0): Likewise.
 340         (VEX_W_0F10_P_1): Likewise.
 341         (VEX_W_0F10_P_2): Likewise.
 342         (VEX_W_0F10_P_3): Likewise.
 343         (VEX_W_0F11_P_0): Likewise.
 344         (VEX_W_0F11_P_1): Likewise.
 345         (VEX_W_0F11_P_2): Likewise.
 346         (VEX_W_0F11_P_3): Likewise.
 347         (VEX_W_0F12_P_0_M_0): Likewise.
 348         (VEX_W_0F12_P_0_M_1): Likewise.
 349         (VEX_W_0F12_P_1): Likewise.
 350         (VEX_W_0F12_P_2): Likewise.
 351         (VEX_W_0F12_P_3): Likewise.
 352         (VEX_W_0F13_M_0): Likewise.
 353         (VEX_W_0F14): Likewise.
 354         (VEX_W_0F15): Likewise.
 355         (VEX_W_0F16_P_0_M_0): Likewise.
 356         (VEX_W_0F16_P_0_M_1): Likewise.
 357         (VEX_W_0F16_P_1): Likewise.
 358         (VEX_W_0F16_P_2): Likewise.
 359         (VEX_W_0F17_M_0): Likewise.
 360         (VEX_W_0F28): Likewise.
 361         (VEX_W_0F29): Likewise.
 362         (VEX_W_0F2B_M_0): Likewise.
 363         (VEX_W_0F2E_P_0): Likewise.
 364         (VEX_W_0F2E_P_2): Likewise.
 365         (VEX_W_0F2F_P_0): Likewise.
 366         (VEX_W_0F2F_P_2): Likewise.
 367         (VEX_W_0F50_M_0): Likewise.
 368         (VEX_W_0F51_P_0): Likewise.
 369         (VEX_W_0F51_P_1): Likewise.
 370         (VEX_W_0F51_P_2): Likewise.
 371         (VEX_W_0F51_P_3): Likewise.
 372         (VEX_W_0F52_P_0): Likewise.
 373         (VEX_W_0F52_P_1): Likewise.
 374         (VEX_W_0F53_P_0): Likewise.
 375         (VEX_W_0F53_P_1): Likewise.
 376         (VEX_W_0F58_P_0): Likewise.
 377         (VEX_W_0F58_P_1): Likewise.
 378         (VEX_W_0F58_P_2): Likewise.
 379         (VEX_W_0F58_P_3): Likewise.
 380         (VEX_W_0F59_P_0): Likewise.
 381         (VEX_W_0F59_P_1): Likewise.
 382         (VEX_W_0F59_P_2): Likewise.
 383         (VEX_W_0F59_P_3): Likewise.
 384         (VEX_W_0F5A_P_0): Likewise.
 385         (VEX_W_0F5A_P_1): Likewise.
 386         (VEX_W_0F5A_P_3): Likewise.
 387         (VEX_W_0F5B_P_0): Likewise.
 388         (VEX_W_0F5B_P_1): Likewise.
 389         (VEX_W_0F5B_P_2): Likewise.
 390         (VEX_W_0F5C_P_0): Likewise.
 391         (VEX_W_0F5C_P_1): Likewise.
 392         (VEX_W_0F5C_P_2): Likewise.
 393         (VEX_W_0F5C_P_3): Likewise.
 394         (VEX_W_0F5D_P_0): Likewise.
 395         (VEX_W_0F5D_P_1): Likewise.
 396         (VEX_W_0F5D_P_2): Likewise.
 397         (VEX_W_0F5D_P_3): Likewise.
 398         (VEX_W_0F5E_P_0): Likewise.
 399         (VEX_W_0F5E_P_1): Likewise.
 400         (VEX_W_0F5E_P_2): Likewise.
 401         (VEX_W_0F5E_P_3): Likewise.
 402         (VEX_W_0F5F_P_0): Likewise.
 403         (VEX_W_0F5F_P_1): Likewise.
 404         (VEX_W_0F5F_P_2): Likewise.
 405         (VEX_W_0F5F_P_3): Likewise.
 406         (VEX_W_0F60_P_2): Likewise.
 407         (VEX_W_0F61_P_2): Likewise.
 408         (VEX_W_0F62_P_2): Likewise.
 409         (VEX_W_0F63_P_2): Likewise.
 410         (VEX_W_0F64_P_2): Likewise.
 411         (VEX_W_0F65_P_2): Likewise.
 412         (VEX_W_0F66_P_2): Likewise.
 413         (VEX_W_0F67_P_2): Likewise.
 414         (VEX_W_0F68_P_2): Likewise.
 415         (VEX_W_0F69_P_2): Likewise.
 416         (VEX_W_0F6A_P_2): Likewise.
 417         (VEX_W_0F6B_P_2): Likewise.
 418         (VEX_W_0F6C_P_2): Likewise.
 419         (VEX_W_0F6D_P_2): Likewise.
 420         (VEX_W_0F6F_P_1): Likewise.
 421         (VEX_W_0F6F_P_2): Likewise.
 422         (VEX_W_0F70_P_1): Likewise.
 423         (VEX_W_0F70_P_2): Likewise.
 424         (VEX_W_0F70_P_3): Likewise.
 425         (VEX_W_0F71_R_2_P_2): Likewise.
 426         (VEX_W_0F71_R_4_P_2): Likewise.
 427         (VEX_W_0F71_R_6_P_2): Likewise.
 428         (VEX_W_0F72_R_2_P_2): Likewise.
 429         (VEX_W_0F72_R_4_P_2): Likewise.
 430         (VEX_W_0F72_R_6_P_2): Likewise.
 431         (VEX_W_0F73_R_2_P_2): Likewise.
 432         (VEX_W_0F73_R_3_P_2): Likewise.
 433         (VEX_W_0F73_R_6_P_2): Likewise.
 434         (VEX_W_0F73_R_7_P_2): Likewise.
 435         (VEX_W_0F74_P_2): Likewise.
 436         (VEX_W_0F75_P_2): Likewise.
 437         (VEX_W_0F76_P_2): Likewise.
 438         (VEX_W_0F77_P_0): Likewise.
 439         (VEX_W_0F7C_P_2): Likewise.
 440         (VEX_W_0F7C_P_3): Likewise.
 441         (VEX_W_0F7D_P_2): Likewise.
 442         (VEX_W_0F7D_P_3): Likewise.
 443         (VEX_W_0F7E_P_1): Likewise.
 444         (VEX_W_0F7F_P_1): Likewise.
 445         (VEX_W_0F7F_P_2): Likewise.
 446         (VEX_W_0FAE_R_2_M_0): Likewise.
 447         (VEX_W_0FAE_R_3_M_0): Likewise.
 448         (VEX_W_0FC2_P_0): Likewise.
 449         (VEX_W_0FC2_P_1): Likewise.
 450         (VEX_W_0FC2_P_2): Likewise.
 451         (VEX_W_0FC2_P_3): Likewise.
 452         (VEX_W_0FD0_P_2): Likewise.
 453         (VEX_W_0FD0_P_3): Likewise.
 454         (VEX_W_0FD1_P_2): Likewise.
 455         (VEX_W_0FD2_P_2): Likewise.
 456         (VEX_W_0FD3_P_2): Likewise.
 457         (VEX_W_0FD4_P_2): Likewise.
 458         (VEX_W_0FD5_P_2): Likewise.
 459         (VEX_W_0FD6_P_2): Likewise.
 460         (VEX_W_0FD7_P_2_M_1): Likewise.
 461         (VEX_W_0FD8_P_2): Likewise.
 462         (VEX_W_0FD9_P_2): Likewise.
 463         (VEX_W_0FDA_P_2): Likewise.
 464         (VEX_W_0FDB_P_2): Likewise.
 465         (VEX_W_0FDC_P_2): Likewise.
 466         (VEX_W_0FDD_P_2): Likewise.
 467         (VEX_W_0FDE_P_2): Likewise.
 468         (VEX_W_0FDF_P_2): Likewise.
 469         (VEX_W_0FE0_P_2): Likewise.
 470         (VEX_W_0FE1_P_2): Likewise.
 471         (VEX_W_0FE2_P_2): Likewise.
 472         (VEX_W_0FE3_P_2): Likewise.
 473         (VEX_W_0FE4_P_2): Likewise.
 474         (VEX_W_0FE5_P_2): Likewise.
 475         (VEX_W_0FE6_P_1): Likewise.
 476         (VEX_W_0FE6_P_2): Likewise.
 477         (VEX_W_0FE6_P_3): Likewise.
 478         (VEX_W_0FE7_P_2_M_0): Likewise.
 479         (VEX_W_0FE8_P_2): Likewise.
 480         (VEX_W_0FE9_P_2): Likewise.
 481         (VEX_W_0FEA_P_2): Likewise.
 482         (VEX_W_0FEB_P_2): Likewise.
 483         (VEX_W_0FEC_P_2): Likewise.
 484         (VEX_W_0FED_P_2): Likewise.
 485         (VEX_W_0FEE_P_2): Likewise.
 486         (VEX_W_0FEF_P_2): Likewise.
 487         (VEX_W_0FF0_P_3_M_0): Likewise.
 488         (VEX_W_0FF1_P_2): Likewise.
 489         (VEX_W_0FF2_P_2): Likewise.
 490         (VEX_W_0FF3_P_2): Likewise.
 491         (VEX_W_0FF4_P_2): Likewise.
 492         (VEX_W_0FF5_P_2): Likewise.
 493         (VEX_W_0FF6_P_2): Likewise.
 494         (VEX_W_0FF7_P_2): Likewise.
 495         (VEX_W_0FF8_P_2): Likewise.
 496         (VEX_W_0FF9_P_2): Likewise.
 497         (VEX_W_0FFA_P_2): Likewise.
 498         (VEX_W_0FFB_P_2): Likewise.
 499         (VEX_W_0FFC_P_2): Likewise.
 500         (VEX_W_0FFD_P_2): Likewise.
 501         (VEX_W_0FFE_P_2): Likewise.
 502         (VEX_W_0F3800_P_2): Likewise.
 503         (VEX_W_0F3801_P_2): Likewise.
 504         (VEX_W_0F3802_P_2): Likewise.
 505         (VEX_W_0F3803_P_2): Likewise.
 506         (VEX_W_0F3804_P_2): Likewise.
 507         (VEX_W_0F3805_P_2): Likewise.
 508         (VEX_W_0F3806_P_2): Likewise.
 509         (VEX_W_0F3807_P_2): Likewise.
 510         (VEX_W_0F3808_P_2): Likewise.
 511         (VEX_W_0F3809_P_2): Likewise.
 512         (VEX_W_0F380A_P_2): Likewise.
 513         (VEX_W_0F380B_P_2): Likewise.
 514         (VEX_W_0F3817_P_2): Likewise.
 515         (VEX_W_0F381C_P_2): Likewise.
 516         (VEX_W_0F381D_P_2): Likewise.
 517         (VEX_W_0F381E_P_2): Likewise.
 518         (VEX_W_0F3820_P_2): Likewise.
 519         (VEX_W_0F3821_P_2): Likewise.
 520         (VEX_W_0F3822_P_2): Likewise.
 521         (VEX_W_0F3823_P_2): Likewise.
 522         (VEX_W_0F3824_P_2): Likewise.
 523         (VEX_W_0F3825_P_2): Likewise.
 524         (VEX_W_0F3828_P_2): Likewise.
 525         (VEX_W_0F3829_P_2): Likewise.
 526         (VEX_W_0F382A_P_2_M_0): Likewise.
 527         (VEX_W_0F382B_P_2): Likewise.
 528         (VEX_W_0F3830_P_2): Likewise.
 529         (VEX_W_0F3831_P_2): Likewise.
 530         (VEX_W_0F3832_P_2): Likewise.
 531         (VEX_W_0F3833_P_2): Likewise.
 532         (VEX_W_0F3834_P_2): Likewise.
 533         (VEX_W_0F3835_P_2): Likewise.
 534         (VEX_W_0F3837_P_2): Likewise.
 535         (VEX_W_0F3838_P_2): Likewise.
 536         (VEX_W_0F3839_P_2): Likewise.
 537         (VEX_W_0F383A_P_2): Likewise.
 538         (VEX_W_0F383B_P_2): Likewise.
 539         (VEX_W_0F383C_P_2): Likewise.
 540         (VEX_W_0F383D_P_2): Likewise.
 541         (VEX_W_0F383E_P_2): Likewise.
 542         (VEX_W_0F383F_P_2): Likewise.
 543         (VEX_W_0F3840_P_2): Likewise.
 544         (VEX_W_0F3841_P_2): Likewise.
 545         (VEX_W_0F38DB_P_2): Likewise.
 546         (VEX_W_0F3A08_P_2): Likewise.
 547         (VEX_W_0F3A09_P_2): Likewise.
 548         (VEX_W_0F3A0A_P_2): Likewise.
 549         (VEX_W_0F3A0B_P_2): Likewise.
 550         (VEX_W_0F3A0C_P_2): Likewise.
 551         (VEX_W_0F3A0D_P_2): Likewise.
 552         (VEX_W_0F3A0E_P_2): Likewise.
 553         (VEX_W_0F3A0F_P_2): Likewise.
 554         (VEX_W_0F3A21_P_2): Likewise.
 555         (VEX_W_0F3A40_P_2): Likewise.
 556         (VEX_W_0F3A41_P_2): Likewise.
 557         (VEX_W_0F3A42_P_2): Likewise.
 558         (VEX_W_0F3A62_P_2): Likewise.
 559         (VEX_W_0F3A63_P_2): Likewise.
 560         (VEX_W_0F3ADF_P_2): Likewise.
 561         (VEX_LEN_0F77_P_0): New.
 562         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 563         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 564         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 565         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 566         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 567         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 568         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 569         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 570         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 571         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 572         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 573         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 574         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 575         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 576         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 577         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 578         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 579         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 580         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 581         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 582         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 583         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 584         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 585         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 586         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 587         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 588         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 589         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 590         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 591         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 592         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 593         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 594         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 595         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 596         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 597         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 598         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 599         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 600         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 601         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 602         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 603         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 604         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 605         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 606         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 607         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 608         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 609         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 610         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 611         (vex_table): Update VEX 0F28 and 0F29 entries.
 612         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 613         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 614         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 615         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 616         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 617         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 618         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 619         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 620         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 621         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 622         VEX_LEN_0F3A0B_P_2 entries.
 623         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 624         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 625         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 626         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 627         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 628         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 629         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 630         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 631         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 632         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 633         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 634         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 635         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 636         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 637         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 638         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 639         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 640         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 641         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 642         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 643         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 644         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 645         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 646         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 647         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 648         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 649         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 650         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 651         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 652         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 653         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 654         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 655         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 656         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 657         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 658         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 659         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 660         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 661         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 662         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 663         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 664         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 665         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 666         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 667         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 668         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 669         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 670         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 671         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 672         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 673         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 674         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 675         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 676         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 677         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 678         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 679         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 680         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 681         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 682         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 683         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 684         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 685         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 686         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 687         VEX_W_0F3ADF_P_2 entries.
 688         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 689         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 690         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 691
 692 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 693
 694         * i386-opc.tbl (VexWIG): New.
 695         Replace VexW=3 with VexWIG.
 696
 697 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 698
 699         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 700         * i386-tbl.h: Regenerated.
 701
 702 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 703
 704         PR gas/23665
 705         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 706         VEX_LEN_0FD6_P_2 entries.
 707         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 708         * i386-tbl.h: Regenerated.
 709
 710 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 711
 712         PR gas/23642
 713         * i386-opc.h (VEXWIG): New.
 714         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 715         * i386-tbl.h: Regenerated.
 716
 717 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 718
 719         PR binutils/23655
 720         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 721         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 722         * i386-dis.c (EXxEVexR64): New.
 723         (evex_rounding_64_mode): Likewise.
 724         (OP_Rounding): Handle evex_rounding_64_mode.
 725
 726 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 727
 728         PR binutils/23655
 729         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 730         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 731         * i386-dis.c (Edqa): New.
 732         (dqa_mode): Likewise.
 733         (intel_operand_size): Handle dqa_mode as m_mode.
 734         (OP_E_register): Handle dqa_mode as dq_mode.
 735         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 736
 737 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 738
 739         * i386-dis.c (OP_E_memory): Reformat.
 740
 741 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 742
 743         * i386-opc.tbl (crc32): Fold byte and word forms.
 744         * i386-tbl.h: Re-generate.
 745
 746 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 747
 748         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 749         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 750         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 751         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 752         * i386-tbl.h: Regenerated.
 753
 754 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 757         meaningless.
 758         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 759         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 760         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 761         * i386-tbl.h: Re-generate.
 762
 763 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 764
 765         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 766         AVX512_4VNNIW insns.
 767         * i386-tbl.h: Re-generate.
 768
 769 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 772         meaningless.
 773         * i386-tbl.h: Re-generate.
 774
 775 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 776
 777         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 778         meaningless.
 779         * i386-tbl.h: Re-generate.
 780
 781 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 782
 783         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 784         meaningless.
 785         * i386-tbl.h: Re-generate.
 786
 787 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 790         meaningless.
 791         * i386-tbl.h: Re-generate.
 792
 793 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 796         meaningless.
 797         * i386-tbl.h: Re-generate.
 798
 799 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 802         * i386-tbl.h: Re-generate.
 803
 804 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 807         * i386-tbl.h: Re-generate.
 808
 809 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 812         meaningless.
 813         * i386-tbl.h: Re-generate.
 814
 815 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 816
 817         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 818         meaningless.
 819         * i386-tbl.h: Re-generate.
 820
 821 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 822
 823         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 824         * i386-tbl.h: Re-generate.
 825
 826 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 829         * i386-tbl.h: Re-generate.
 830
 831 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 832
 833         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 834         * i386-tbl.h: Re-generate.
 835
 836 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 839         meaningless.
 840         * i386-tbl.h: Re-generate.
 841
 842 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 843
 844         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 845         meaningless.
 846         * i386-tbl.h: Re-generate.
 847
 848 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 851         meaningless.
 852         * i386-tbl.h: Re-generate.
 853
 854 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 857         * i386-tbl.h: Re-generate.
 858
 859 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 860
 861         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 862         * i386-tbl.h: Re-generate.
 863
 864 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 865
 866         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 867         * i386-tbl.h: Re-generate.
 868
 869 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 870
 871         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 872         (vpbroadcastw, rdpid): Drop NoRex64.
 873         * i386-tbl.h: Re-generate.
 874
 875 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 876
 877         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 878         store templates, adding D.
 879         * i386-tbl.h: Re-generate.
 880
 881 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 882
 883         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 884         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 885         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 886         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 887         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 888         Fold load and store templates where possible, adding D. Drop
 889         IgnoreSize where it was pointlessly present. Drop redundant
 890         *word.
 891         * i386-tbl.h: Re-generate.
 892
 893 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 896         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 897         (intel_operand_size): Handle v_bndmk_mode.
 898         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 899
 900 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 901
 902         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 903
 904 2018-08-31  Kito Cheng  <kito@andestech.com>
 905
 906         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 907         compressed floating point instructions.
 908
 909 2018-08-30  Kito Cheng  <kito@andestech.com>
 910
 911         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 912         riscv_opcode.xlen_requirement.
 913         * riscv-opc.c (riscv_opcodes): Update for struct change.
 914
 915 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 916
 917         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 918         psr (PWRPSR) instruction.
 919
 920 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 921
 922         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 923
 924 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 925
 926         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 927
 928 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 929
 930         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 931         loongson3a as an alias of gs464 for compatibility.
 932         * mips-opc.c (mips_opcodes): Change Comments.
 933
 934 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 935
 936         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 937         option.
 938         (print_mips_disassembler_options): Document -M loongson-ext.
 939         * mips-opc.c (LEXT2): New macro.
 940         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 941
 942 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 943
 944          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 945          descriptors.
 946          (parse_mips_ase_option): Handle -M loongson-ext option.
 947          (print_mips_disassembler_options): Document -M loongson-ext.
 948          * mips-opc.c (IL3A): Delete.
 949          * mips-opc.c (LEXT): New macro.
 950          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 951          instructions.
 952
 953 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 954
 955         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 956         descriptors.
 957         (parse_mips_ase_option): Handle -M loongson-cam option.
 958         (print_mips_disassembler_options): Document -M loongson-cam.
 959         * mips-opc.c (LCAM): New macro.
 960         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 961         instructions.
 962
 963 2018-08-21  Alan Modra  <amodra@gmail.com>
 964
 965         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 966         (skip_optional_operands): Count optional operands, and update
 967         ppc_optional_operand_value call.
 968         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 969         (extract_vlensi): Likewise.
 970         (extract_fxm): Return default value for missing optional operand.
 971         (extract_ls, extract_raq, extract_tbr): Likewise.
 972         (insert_sxl, extract_sxl): New functions.
 973         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 974         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 975         flag and extra entry.
 976         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 977         extract_sxl.
 978
 979 2018-08-20  Alan Modra  <amodra@gmail.com>
 980
 981         * sh-opc.h (MASK): Simplify.
 982
 983 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 984
 985         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 986         BM_RESERVED0 or BM_RESERVED1
 987         (bm_rel_decode, bm_n_bytes): Ditto.
 988
 989 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 990
 991         * s12z.h: Delete.
 992
 993 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 994
 995         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 996         address with the addr32 prefix and without base nor index
 997         registers.
 998
 999 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1000
1001         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1002         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1003         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1004         (cpu_flags): Add CpuCMOV and CpuFXSR.
1005         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1006         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1007         * i386-init.h: Regenerated.
1008         * i386-tbl.h: Likewise.
1009
1010 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1011
1012         * arc-regs.h: Update auxiliary registers.
1013
1014 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1017         (RegIP, RegIZ): Define.
1018         * i386-reg.tbl: Adjust comments.
1019         (rip): Use Qword instead of BaseIndex. Use RegIP.
1020         (eip): Use Dword instead of BaseIndex. Use RegIP.
1021         (riz): Add Qword. Use RegIZ.
1022         (eiz): Add Dword. Use RegIZ.
1023         * i386-tbl.h: Re-generate.
1024
1025 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1026
1027         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1028         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1029         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1030         * i386-tbl.h: Re-generate.
1031
1032 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-gen.c (operand_types): Remove Mem field.
1035         * i386-opc.h (union i386_operand_type): Remove mem field.
1036         * i386-init.h, i386-tbl.h: Re-generate.
1037
1038 2018-08-01  Alan Modra  <amodra@gmail.com>
1039
1040         * po/POTFILES.in: Regenerate.
1041
1042 2018-07-31  Nick Clifton  <nickc@redhat.com>
1043
1044         * po/sv.po: Updated Swedish translation.
1045
1046 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1047
1048         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1049         * i386-init.h, i386-tbl.h: Re-generate.
1050
1051 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1052
1053         * i386-opc.h (ZEROING_MASKING) Rename to ...
1054         (DYNAMIC_MASKING): ... this. Adjust comment.
1055         * i386-opc.tbl (MaskingMorZ): Define.
1056         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1057         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1058         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1059         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1060         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1061         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1062         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1063         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1064         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1065
1066 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1067
1068         * i386-opc.tbl: Use element rather than vector size for AVX512*
1069         scatter/gather insns.
1070         * i386-tbl.h: Re-generate.
1071
1072 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1075         (cpu_flags): Drop CpuVREX.
1076         * i386-opc.h (CpuVREX): Delete.
1077         (union i386_cpu_flags): Remove cpuvrex.
1078         * i386-init.h, i386-tbl.h: Re-generate.
1079
1080 2018-07-30  Jim Wilson  <jimw@sifive.com>
1081
1082         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1083         fields.
1084         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1085
1086 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1087
1088         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1089         * Makefile.in: Regenerated.
1090         * configure.ac: Add C-SKY.
1091         * configure: Regenerated.
1092         * csky-dis.c: New file.
1093         * csky-opc.h: New file.
1094         * disassemble.c (ARCH_csky): Define.
1095         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1096         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1097
1098 2018-07-27  Alan Modra  <amodra@gmail.com>
1099
1100         * ppc-opc.c (insert_sprbat): Correct function parameter and
1101         return type.
1102         (extract_sprbat): Likewise, variable too.
1103
1104 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1105             Alan Modra  <amodra@gmail.com>
1106
1107         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1108         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1109         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1110         support disjointed BAT.
1111         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1112         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1113         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1114
1115 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1116             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1117
1118         * i386-gen.c (adjust_broadcast_modifier): New function.
1119         (process_i386_opcode_modifier): Add an argument for operands.
1120         Adjust the Broadcast value based on operands.
1121         (output_i386_opcode): Pass operand_types to
1122         process_i386_opcode_modifier.
1123         (process_i386_opcodes): Pass NULL as operands to
1124         process_i386_opcode_modifier.
1125         * i386-opc.h (BYTE_BROADCAST): New.
1126         (WORD_BROADCAST): Likewise.
1127         (DWORD_BROADCAST): Likewise.
1128         (QWORD_BROADCAST): Likewise.
1129         (i386_opcode_modifier): Expand broadcast to 3 bits.
1130         * i386-tbl.h: Regenerated.
1131
1132 2018-07-24  Alan Modra  <amodra@gmail.com>
1133
1134         PR 23430
1135         * or1k-desc.h: Regenerate.
1136
1137 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1140         vcvtusi2ss, and vcvtusi2sd.
1141         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1142         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1143         * i386-tbl.h: Re-generate.
1144
1145 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1146
1147         * arc-opc.c (extract_w6): Fix extending the sign.
1148
1149 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1150
1151         * arc-tbl.h (vewt): Allow it for ARC EM family.
1152
1153 2018-07-23  Alan Modra  <amodra@gmail.com>
1154
1155         PR 23419
1156         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1157         opcode variants for mtspr/mfspr encodings.
1158
1159 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1160             Maciej W. Rozycki  <macro@mips.com>
1161
1162         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1163         loongson3a descriptors.
1164         (parse_mips_ase_option): Handle -M loongson-mmi option.
1165         (print_mips_disassembler_options): Document -M loongson-mmi.
1166         * mips-opc.c (LMMI): New macro.
1167         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1168         instructions.
1169
1170 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1171
1172         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1173         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1174         IgnoreSize and [XYZ]MMword where applicable.
1175         * i386-tbl.h: Re-generate.
1176
1177 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1178
1179         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1180         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1181         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1182         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1183         * i386-tbl.h: Re-generate.
1184
1185 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1186
1187         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1188         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1189         VPCLMULQDQ templates into their respective AVX512VL counterparts
1190         where possible, using Disp8ShiftVL and CheckRegSize instead of
1191         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1192         * i386-tbl.h: Re-generate.
1193
1194 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1195
1196         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1197         AVX512VL counterparts where possible, using Disp8ShiftVL and
1198         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1199         IgnoreSize) as appropriate.
1200         * i386-tbl.h: Re-generate.
1201
1202 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1203
1204         * i386-opc.tbl: Fold AVX512BW templates into their respective
1205         AVX512VL counterparts where possible, using Disp8ShiftVL and
1206         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1207         IgnoreSize) as appropriate.
1208         * i386-tbl.h: Re-generate.
1209
1210 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1211
1212         * i386-opc.tbl: Fold AVX512CD templates into their respective
1213         AVX512VL counterparts where possible, using Disp8ShiftVL and
1214         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1215         IgnoreSize) as appropriate.
1216         * i386-tbl.h: Re-generate.
1217
1218 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1219
1220         * i386-opc.h (DISP8_SHIFT_VL): New.
1221         * i386-opc.tbl (Disp8ShiftVL):  Define.
1222         (various): Fold AVX512VL templates into their respective
1223         AVX512F counterparts where possible, using Disp8ShiftVL and
1224         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1225         IgnoreSize) as appropriate.
1226         * i386-tbl.h: Re-generate.
1227
1228 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1229
1230         * Makefile.am: Change dependencies and rule for
1231         $(srcdir)/i386-init.h.
1232         * Makefile.in: Re-generate.
1233         * i386-gen.c (process_i386_opcodes): New local variable
1234         "marker". Drop opening of input file. Recognize marker and line
1235         number directives.
1236         * i386-opc.tbl (OPCODE_I386_H): Define.
1237         (i386-opc.h): Include it.
1238         (None): Undefine.
1239
1240 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1241
1242         PR gas/23418
1243         * i386-opc.h (Byte): Update comments.
1244         (Word): Likewise.
1245         (Dword): Likewise.
1246         (Fword): Likewise.
1247         (Qword): Likewise.
1248         (Tbyte): Likewise.
1249         (Xmmword): Likewise.
1250         (Ymmword): Likewise.
1251         (Zmmword): Likewise.
1252         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1253         vcvttps2uqq.
1254         * i386-tbl.h: Regenerated.
1255
1256 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1257
1258         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1259         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1260         * aarch64-asm-2.c: Regenerate.
1261         * aarch64-dis-2.c: Regenerate.
1262         * aarch64-opc-2.c: Regenerate.
1263
1264 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1265
1266         PR binutils/23192
1267         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1268         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1269         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1270         sqdmulh, sqrdmulh): Use Em16.
1271
1272 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1273
1274         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1275         csdb together with them.
1276         (thumb32_opcodes): Likewise.
1277
1278 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1279
1280         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1281         requiring 32-bit registers as operands 2 and 3. Improve
1282         comments.
1283         (mwait, mwaitx): Fold templates. Improve comments.
1284         OPERAND_TYPE_INOUTPORTREG.
1285         * i386-tbl.h: Re-generate.
1286
1287 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1288
1289         * i386-gen.c (operand_type_init): Remove
1290         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1291         OPERAND_TYPE_INOUTPORTREG.
1292         * i386-init.h: Re-generate.
1293
1294 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1295
1296         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1297         (wrssq, wrussq): Add Qword.
1298         * i386-tbl.h: Re-generate.
1299
1300 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1301
1302         * i386-opc.h: Rename OTMax to OTNum.
1303         (OTNumOfUints): Adjust calculation.
1304         (OTUnused): Directly alias to OTNum.
1305
1306 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1307
1308         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1309         `reg_xys'.
1310         (lea_reg_xys): Likewise.
1311         (print_insn_loop_primitive): Rename `reg' local variable to
1312         `reg_dxy'.
1313
1314 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1315
1316         PR binutils/23242
1317         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1318
1319 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1320
1321         PR binutils/23369
1322         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1323         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1324
1325 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1326
1327         PR tdep/8282
1328         * mips-dis.c (mips_option_arg_t): New enumeration.
1329         (mips_options): New variable.
1330         (disassembler_options_mips): New function.
1331         (print_mips_disassembler_options): Reimplement in terms of
1332         `disassembler_options_mips'.
1333         * arm-dis.c (disassembler_options_arm): Adapt to using the
1334         `disasm_options_and_args_t' structure.
1335         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1336         * s390-dis.c (disassembler_options_s390): Likewise.
1337
1338 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1339
1340         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1341         expected result.
1342         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1343         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1344         * testsuite/ld-arm/tls-longplt.d: Likewise.
1345
1346 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1347
1348         PR binutils/23192
1349         * aarch64-asm-2.c: Regenerate.
1350         * aarch64-dis-2.c: Likewise.
1351         * aarch64-opc-2.c: Likewise.
1352         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1353         * aarch64-opc.c (operand_general_constraint_met_p,
1354         aarch64_print_operand): Likewise.
1355         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1356         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1357         fmlal2, fmlsl2.
1358         (AARCH64_OPERANDS): Add Em2.
1359
1360 2018-06-26  Nick Clifton  <nickc@redhat.com>
1361
1362         * po/uk.po: Updated Ukranian translation.
1363         * po/de.po: Updated German translation.
1364         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1365
1366 2018-06-26  Nick Clifton  <nickc@redhat.com>
1367
1368         * nfp-dis.c: Fix spelling mistake.
1369
1370 2018-06-24  Nick Clifton  <nickc@redhat.com>
1371
1372         * configure: Regenerate.
1373         * po/opcodes.pot: Regenerate.
1374
1375 2018-06-24  Nick Clifton  <nickc@redhat.com>
1376
1377         2.31 branch created.
1378
1379 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1380
1381         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1382         * aarch64-asm-2.c: Regenerate.
1383         * aarch64-dis-2.c: Likewise.
1384
1385 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1386
1387         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1388         `-M ginv' option description.
1389
1390 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1391
1392         PR gas/23305
1393         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1394         la and lla.
1395
1396 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1397
1398         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1399         * configure.ac: Remove AC_PREREQ.
1400         * Makefile.in: Re-generate.
1401         * aclocal.m4: Re-generate.
1402         * configure: Re-generate.
1403
1404 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1405
1406         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1407         mips64r6 descriptors.
1408         (parse_mips_ase_option): Handle -Mginv option.
1409         (print_mips_disassembler_options): Document -Mginv.
1410         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1411         (GINV): New macro.
1412         (mips_opcodes): Define ginvi and ginvt.
1413
1414 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1415             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1416
1417         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1418         * mips-opc.c (CRC, CRC64): New macros.
1419         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1420         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1421         crc32cd for CRC64.
1422
1423 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1424
1425         PR 20319
1426         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1427         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1428
1429 2018-06-06  Alan Modra  <amodra@gmail.com>
1430
1431         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1432         setjmp.  Move init for some other vars later too.
1433
1434 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1435
1436         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1437         (dis_private): Add new fields for property section tracking.
1438         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1439         (xtensa_instruction_fits): New functions.
1440         (fetch_data): Bump minimal fetch size to 4.
1441         (print_insn_xtensa): Make struct dis_private static.
1442         Load and prepare property table on section change.
1443         Don't disassemble literals. Don't disassemble instructions that
1444         cross property table boundaries.
1445
1446 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1447
1448         * configure: Regenerated.
1449
1450 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1451
1452         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1453         * i386-tbl.h: Re-generate.
1454
1455 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1456
1457         * i386-opc.tbl (sldt, str): Add NoRex64.
1458         * i386-tbl.h: Re-generate.
1459
1460 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1461
1462         * i386-opc.tbl (invpcid): Add Oword.
1463         * i386-tbl.h: Re-generate.
1464
1465 2018-06-01  Alan Modra  <amodra@gmail.com>
1466
1467         * sysdep.h (_bfd_error_handler): Don't declare.
1468         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1469         * rl78-decode.opc: Likewise.
1470         * msp430-decode.c: Regenerate.
1471         * rl78-decode.c: Regenerate.
1472
1473 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1474
1475         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1476         * i386-init.h : Regenerated.
1477
1478 2018-05-25  Alan Modra  <amodra@gmail.com>
1479
1480         * Makefile.in: Regenerate.
1481         * po/POTFILES.in: Regenerate.
1482
1483 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1484
1485         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1486         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1487         (insert_bab, extract_bab, insert_btab, extract_btab,
1488         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1489         (BAT, BBA VBA RBS XB6S): Delete macros.
1490         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1491         (BB, BD, RBX, XC6): Update for new macros.
1492         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1493         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1494         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1495         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1496
1497 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1498
1499         * Makefile.am: Add support for s12z architecture.
1500         * configure.ac: Likewise.
1501         * disassemble.c: Likewise.
1502         * disassemble.h: Likewise.
1503         * Makefile.in: Regenerate.
1504         * configure: Regenerate.
1505         * s12z-dis.c: New file.
1506         * s12z.h: New file.
1507
1508 2018-05-18  Alan Modra  <amodra@gmail.com>
1509
1510         * nfp-dis.c: Don't #include libbfd.h.
1511         (init_nfp3200_priv): Use bfd_get_section_contents.
1512         (nit_nfp6000_mecsr_sec): Likewise.
1513
1514 2018-05-17  Nick Clifton  <nickc@redhat.com>
1515
1516         * po/zh_CN.po: Updated simplified Chinese translation.
1517
1518 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1519
1520         PR binutils/23109
1521         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1522         * aarch64-dis-2.c: Regenerate.
1523
1524 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1525
1526         PR binutils/21446
1527         * aarch64-asm.c (opintl.h): Include.
1528         (aarch64_ins_sysreg): Enforce read/write constraints.
1529         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1530         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1531         (F_REG_READ, F_REG_WRITE): New.
1532         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1533         AARCH64_OPND_SYSREG.
1534         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1535         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1536         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1537         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1538         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1539         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1540         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1541         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1542         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1543         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1544         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1545         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1546         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1547         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1548         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1549         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1550         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1551
1552 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1553
1554         PR binutils/21446
1555         * aarch64-dis.c (no_notes: New.
1556         (parse_aarch64_dis_option): Support notes.
1557         (aarch64_decode_insn, print_operands): Likewise.
1558         (print_aarch64_disassembler_options): Document notes.
1559         * aarch64-opc.c (aarch64_print_operand): Support notes.
1560
1561 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1562
1563         PR binutils/21446
1564         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1565         and take error struct.
1566         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1567         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1568         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1569         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1570         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1571         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1572         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1573         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1574         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1575         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1576         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1577         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1578         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1579         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1580         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1581         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1582         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1583         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1584         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1585         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1586         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1587         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1588         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1589         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1590         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1591         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1592         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1593         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1594         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1595         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1596         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1597         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1598         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1599         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1600         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1601         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1602         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1603         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1604         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1605         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1606         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1607         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1608         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1609         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1610         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1611         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1612         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1613         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1614         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1615         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1616         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1617         (determine_disassembling_preference, aarch64_decode_insn,
1618         print_insn_aarch64_word, print_insn_data): Take errors struct.
1619         (print_insn_aarch64): Use errors.
1620         * aarch64-asm-2.c: Regenerate.
1621         * aarch64-dis-2.c: Regenerate.
1622         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1623         boolean in aarch64_insert_operan.
1624         (print_operand_extractor): Likewise.
1625         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1626
1627 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1628
1629         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1630
1631 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1632
1633         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1634
1635 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1636
1637         * cr16-opc.c (cr16_instruction): Comment typo fix.
1638         * hppa-dis.c (print_insn_hppa): Likewise.
1639
1640 2018-05-08  Jim Wilson  <jimw@sifive.com>
1641
1642         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1643         (match_c_slli64, match_srxi_as_c_srxi): New.
1644         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1645         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1646         <c.slli, c.srli, c.srai>: Use match_s_slli.
1647         <c.slli64, c.srli64, c.srai64>: New.
1648
1649 2018-05-08  Alan Modra  <amodra@gmail.com>
1650
1651         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1652         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1653         partition opcode space for index lookup.
1654
1655 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1656
1657         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1658         <insn_length>: ...with this.  Update usage.
1659         Remove duplicate call to *info->memory_error_func.
1660
1661 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1662             H.J. Lu  <hongjiu.lu@intel.com>
1663
1664         * i386-dis.c (Gva): New.
1665         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1666         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1667         (prefix_table): New instructions (see prefix above).
1668         (mod_table): New instructions (see prefix above).
1669         (OP_G): Handle va_mode.
1670         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1671         CPU_MOVDIR64B_FLAGS.
1672         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1673         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1674         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1675         * i386-opc.tbl: Add movidir{i,64b}.
1676         * i386-init.h: Regenerated.
1677         * i386-tbl.h: Likewise.
1678
1679 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1680
1681         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1682         AddrPrefixOpReg.
1683         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1684         (AddrPrefixOpReg): This.
1685         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1686         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1687
1688 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1689
1690         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1691         (vle_num_opcodes): Likewise.
1692         (spe2_num_opcodes): Likewise.
1693         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1694         initialization loop.
1695         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1696         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1697         only once.
1698
1699 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1700
1701         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1702
1703 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1704
1705         Makefile.am: Added nfp-dis.c.
1706         configure.ac: Added bfd_nfp_arch.
1707         disassemble.h: Added print_insn_nfp prototype.
1708         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1709         nfp-dis.c: New, for NFP support.
1710         po/POTFILES.in: Added nfp-dis.c to the list.
1711         Makefile.in: Regenerate.
1712         configure: Regenerate.
1713
1714 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1715
1716         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1717         templates into their base ones.
1718         * i386-tlb.h: Re-generate.
1719
1720 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1721
1722         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1723         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1724         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1725         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1726         * i386-init.h: Re-generate.
1727
1728 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1729
1730         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1731         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1732         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1733         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1734         comment.
1735         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1736         and CpuRegMask.
1737         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1738         CpuRegMask: Delete.
1739         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1740         cpuregzmm, and cpuregmask.
1741         * i386-init.h: Re-generate.
1742         * i386-tbl.h: Re-generate.
1743
1744 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1745
1746         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1747         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1748         * i386-init.h: Re-generate.
1749
1750 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1751
1752         * i386-gen.c (VexImmExt): Delete.
1753         * i386-opc.h (VexImmExt, veximmext): Delete.
1754         * i386-opc.tbl: Drop all VexImmExt uses.
1755         * i386-tlb.h: Re-generate.
1756
1757 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1758
1759         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1760         register-only forms.
1761         * i386-tlb.h: Re-generate.
1762
1763 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1764
1765         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1766
1767 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1768
1769         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1770         PREFIX_0F1C.
1771         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1772         (cpu_flags): Add CpuCLDEMOTE.
1773         * i386-init.h: Regenerate.
1774         * i386-opc.h (enum): Add CpuCLDEMOTE,
1775         (i386_cpu_flags): Add cpucldemote.
1776         * i386-opc.tbl: Add cldemote.
1777         * i386-tbl.h: Regenerate.
1778
1779 2018-04-16  Alan Modra  <amodra@gmail.com>
1780
1781         * Makefile.am: Remove sh5 and sh64 support.
1782         * configure.ac: Likewise.
1783         * disassemble.c: Likewise.
1784         * disassemble.h: Likewise.
1785         * sh-dis.c: Likewise.
1786         * sh64-dis.c: Delete.
1787         * sh64-opc.c: Delete.
1788         * sh64-opc.h: Delete.
1789         * Makefile.in: Regenerate.
1790         * configure: Regenerate.
1791         * po/POTFILES.in: Regenerate.
1792
1793 2018-04-16  Alan Modra  <amodra@gmail.com>
1794
1795         * Makefile.am: Remove w65 support.
1796         * configure.ac: Likewise.
1797         * disassemble.c: Likewise.
1798         * disassemble.h: Likewise.
1799         * w65-dis.c: Delete.
1800         * w65-opc.h: Delete.
1801         * Makefile.in: Regenerate.
1802         * configure: Regenerate.
1803         * po/POTFILES.in: Regenerate.
1804
1805 2018-04-16  Alan Modra  <amodra@gmail.com>
1806
1807         * configure.ac: Remove we32k support.
1808         * configure: Regenerate.
1809
1810 2018-04-16  Alan Modra  <amodra@gmail.com>
1811
1812         * Makefile.am: Remove m88k support.
1813         * configure.ac: Likewise.
1814         * disassemble.c: Likewise.
1815         * disassemble.h: Likewise.
1816         * m88k-dis.c: Delete.
1817         * Makefile.in: Regenerate.
1818         * configure: Regenerate.
1819         * po/POTFILES.in: Regenerate.
1820
1821 2018-04-16  Alan Modra  <amodra@gmail.com>
1822
1823         * Makefile.am: Remove i370 support.
1824         * configure.ac: Likewise.
1825         * disassemble.c: Likewise.
1826         * disassemble.h: Likewise.
1827         * i370-dis.c: Delete.
1828         * i370-opc.c: Delete.
1829         * Makefile.in: Regenerate.
1830         * configure: Regenerate.
1831         * po/POTFILES.in: Regenerate.
1832
1833 2018-04-16  Alan Modra  <amodra@gmail.com>
1834
1835         * Makefile.am: Remove h8500 support.
1836         * configure.ac: Likewise.
1837         * disassemble.c: Likewise.
1838         * disassemble.h: Likewise.
1839         * h8500-dis.c: Delete.
1840         * h8500-opc.h: Delete.
1841         * Makefile.in: Regenerate.
1842         * configure: Regenerate.
1843         * po/POTFILES.in: Regenerate.
1844
1845 2018-04-16  Alan Modra  <amodra@gmail.com>
1846
1847         * configure.ac: Remove tahoe support.
1848         * configure: Regenerate.
1849
1850 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1851
1852         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1853         umwait.
1854         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1855         64-bit mode.
1856         * i386-tbl.h: Regenerated.
1857
1858 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1859
1860         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1861         PREFIX_MOD_1_0FAE_REG_6.
1862         (va_mode): New.
1863         (OP_E_register): Use va_mode.
1864         * i386-dis-evex.h (prefix_table):
1865         New instructions (see prefixes above).
1866         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1867         (cpu_flags): Likewise.
1868         * i386-opc.h (enum): Likewise.
1869         (i386_cpu_flags): Likewise.
1870         * i386-opc.tbl: Add umonitor, umwait, tpause.
1871         * i386-init.h: Regenerate.
1872         * i386-tbl.h: Likewise.
1873
1874 2018-04-11  Alan Modra  <amodra@gmail.com>
1875
1876         * opcodes/i860-dis.c: Delete.
1877         * opcodes/i960-dis.c: Delete.
1878         * Makefile.am: Remove i860 and i960 support.
1879         * configure.ac: Likewise.
1880         * disassemble.c: Likewise.
1881         * disassemble.h: Likewise.
1882         * Makefile.in: Regenerate.
1883         * configure: Regenerate.
1884         * po/POTFILES.in: Regenerate.
1885
1886 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1887
1888         PR binutils/23025
1889         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1890         to 0.
1891         (print_insn): Clear vex instead of vex.evex.
1892
1893 2018-04-04  Nick Clifton  <nickc@redhat.com>
1894
1895         * po/es.po: Updated Spanish translation.
1896
1897 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1898
1899         * i386-gen.c (opcode_modifiers): Delete VecESize.
1900         * i386-opc.h (VecESize): Delete.
1901         (struct i386_opcode_modifier): Delete vecesize.
1902         * i386-opc.tbl: Drop VecESize.
1903         * i386-tlb.h: Re-generate.
1904
1905 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1906
1907         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1908         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1909         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1910         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1911         * i386-tlb.h: Re-generate.
1912
1913 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1914
1915         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1916         Fold AVX512 forms
1917         * i386-tlb.h: Re-generate.
1918
1919 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1920
1921         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1922         (vex_len_table): Drop Y for vcvt*2si.
1923         (putop): Replace plain 'Y' handling by abort().
1924
1925 2018-03-28  Nick Clifton  <nickc@redhat.com>
1926
1927         PR 22988
1928         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1929         instructions with only a base address register.
1930         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1931         handle AARHC64_OPND_SVE_ADDR_R.
1932         (aarch64_print_operand): Likewise.
1933         * aarch64-asm-2.c: Regenerate.
1934         * aarch64_dis-2.c: Regenerate.
1935         * aarch64-opc-2.c: Regenerate.
1936
1937 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1938
1939         * i386-opc.tbl: Drop VecESize from register only insn forms and
1940         memory forms not allowing broadcast.
1941         * i386-tlb.h: Re-generate.
1942
1943 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1944
1945         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1946         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1947         sha256*): Drop Disp<N>.
1948
1949 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1950
1951         * i386-dis.c (EbndS, bnd_swap_mode): New.
1952         (prefix_table): Use EbndS.
1953         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1954         * i386-opc.tbl (bndmov): Move misplaced Load.
1955         * i386-tlb.h: Re-generate.
1956
1957 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1958
1959         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1960         templates allowing memory operands and folded ones for register
1961         only flavors.
1962         * i386-tlb.h: Re-generate.
1963
1964 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1965
1966         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1967         256-bit templates. Drop redundant leftover Disp<N>.
1968         * i386-tlb.h: Re-generate.
1969
1970 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1971
1972         * riscv-opc.c (riscv_insn_types): New.
1973
1974 2018-03-13  Nick Clifton  <nickc@redhat.com>
1975
1976         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1977
1978 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1979
1980         * i386-opc.tbl: Add Optimize to clr.
1981         * i386-tbl.h: Regenerated.
1982
1983 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1984
1985         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1986         * i386-opc.h (OldGcc): Removed.
1987         (i386_opcode_modifier): Remove oldgcc.
1988         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1989         instructions for old (<= 2.8.1) versions of gcc.
1990         * i386-tbl.h: Regenerated.
1991
1992 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1993
1994         * i386-opc.h (EVEXDYN): New.
1995         * i386-opc.tbl: Fold various AVX512VL templates.
1996         * i386-tlb.h: Re-generate.
1997
1998 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1999
2000         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2001         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2002         vpexpandd, vpexpandq): Fold AFX512VF templates.
2003         * i386-tlb.h: Re-generate.
2004
2005 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2006
2007         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2008         Fold 128- and 256-bit VEX-encoded templates.
2009         * i386-tlb.h: Re-generate.
2010
2011 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2012
2013         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2014         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2015         vpexpandd, vpexpandq): Fold AVX512F templates.
2016         * i386-tlb.h: Re-generate.
2017
2018 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2019
2020         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2021         64-bit templates. Drop Disp<N>.
2022         * i386-tlb.h: Re-generate.
2023
2024 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2025
2026         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2027         and 256-bit templates.
2028         * i386-tlb.h: Re-generate.
2029
2030 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2031
2032         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2033         * i386-tlb.h: Re-generate.
2034
2035 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2036
2037         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2038         Drop NoAVX.
2039         * i386-tlb.h: Re-generate.
2040
2041 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2042
2043         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2044         * i386-tlb.h: Re-generate.
2045
2046 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2047
2048         * i386-gen.c (opcode_modifiers): Delete FloatD.
2049         * i386-opc.h (FloatD): Delete.
2050         (struct i386_opcode_modifier): Delete floatd.
2051         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2052         FloatD by D.
2053         * i386-tlb.h: Re-generate.
2054
2055 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2056
2057         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2058
2059 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2060
2061         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2062         * i386-tlb.h: Re-generate.
2063
2064 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2065
2066         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2067         forms.
2068         * i386-tlb.h: Re-generate.
2069
2070 2018-03-07  Alan Modra  <amodra@gmail.com>
2071
2072         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2073         bfd_arch_rs6000.
2074         * disassemble.h (print_insn_rs6000): Delete.
2075         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2076         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2077         (print_insn_rs6000): Delete.
2078
2079 2018-03-03  Alan Modra  <amodra@gmail.com>
2080
2081         * sysdep.h (opcodes_error_handler): Define.
2082         (_bfd_error_handler): Declare.
2083         * Makefile.am: Remove stray #.
2084         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2085         EDIT" comment.
2086         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2087         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2088         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2089         opcodes_error_handler to print errors.  Standardize error messages.
2090         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2091         and include opintl.h.
2092         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2093         * i386-gen.c: Standardize error messages.
2094         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2095         * Makefile.in: Regenerate.
2096         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2097         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2098         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2099         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2100         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2101         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2102         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2103         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2104         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2105         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2106         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2107         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2108         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2109
2110 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2111
2112         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2113         vpsub[bwdq] instructions.
2114         * i386-tbl.h: Regenerated.
2115
2116 2018-03-01  Alan Modra  <amodra@gmail.com>
2117
2118         * configure.ac (ALL_LINGUAS): Sort.
2119         * configure: Regenerate.
2120
2121 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2122
2123         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2124         macro by assignements.
2125
2126 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2127
2128         PR gas/22871
2129         * i386-gen.c (opcode_modifiers): Add Optimize.
2130         * i386-opc.h (Optimize): New enum.
2131         (i386_opcode_modifier): Add optimize.
2132         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2133         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2134         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2135         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2136         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2137         vpxord and vpxorq.
2138         * i386-tbl.h: Regenerated.
2139
2140 2018-02-26  Alan Modra  <amodra@gmail.com>
2141
2142         * crx-dis.c (getregliststring): Allocate a large enough buffer
2143         to silence false positive gcc8 warning.
2144
2145 2018-02-22  Shea Levy <shea@shealevy.com>
2146
2147         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2148
2149 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2150
2151         * i386-opc.tbl: Add {rex},
2152         * i386-tbl.h: Regenerated.
2153
2154 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2155
2156         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2157         (mips16_opcodes): Replace `M' with `m' for "restore".
2158
2159 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2160
2161         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2162
2163 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2164
2165         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2166         variable to `function_index'.
2167
2168 2018-02-13  Nick Clifton  <nickc@redhat.com>
2169
2170         PR 22823
2171         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2172         about truncation of printing.
2173
2174 2018-02-12  Henry Wong <henry@stuffedcow.net>
2175
2176         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2177
2178 2018-02-05  Nick Clifton  <nickc@redhat.com>
2179
2180         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2181
2182 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2183
2184         * i386-dis.c (enum): Add pconfig.
2185         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2186         (cpu_flags): Add CpuPCONFIG.
2187         * i386-opc.h (enum): Add CpuPCONFIG.
2188         (i386_cpu_flags): Add cpupconfig.
2189         * i386-opc.tbl: Add PCONFIG instruction.
2190         * i386-init.h: Regenerate.
2191         * i386-tbl.h: Likewise.
2192
2193 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2194
2195         * i386-dis.c (enum): Add PREFIX_0F09.
2196         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2197         (cpu_flags): Add CpuWBNOINVD.
2198         * i386-opc.h (enum): Add CpuWBNOINVD.
2199         (i386_cpu_flags): Add cpuwbnoinvd.
2200         * i386-opc.tbl: Add WBNOINVD instruction.
2201         * i386-init.h: Regenerate.
2202         * i386-tbl.h: Likewise.
2203
2204 2018-01-17  Jim Wilson  <jimw@sifive.com>
2205
2206         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2207
2208 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2209
2210         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2211         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2212         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2213         (cpu_flags): Add CpuIBT, CpuSHSTK.
2214         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2215         (i386_cpu_flags): Add cpuibt, cpushstk.
2216         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2217         * i386-init.h: Regenerate.
2218         * i386-tbl.h: Likewise.
2219
2220 2018-01-16  Nick Clifton  <nickc@redhat.com>
2221
2222         * po/pt_BR.po: Updated Brazilian Portugese translation.
2223         * po/de.po: Updated German translation.
2224
2225 2018-01-15  Jim Wilson  <jimw@sifive.com>
2226
2227         * riscv-opc.c (match_c_nop): New.
2228         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2229
2230 2018-01-15  Nick Clifton  <nickc@redhat.com>
2231
2232         * po/uk.po: Updated Ukranian translation.
2233
2234 2018-01-13  Nick Clifton  <nickc@redhat.com>
2235
2236         * po/opcodes.pot: Regenerated.
2237
2238 2018-01-13  Nick Clifton  <nickc@redhat.com>
2239
2240         * configure: Regenerate.
2241
2242 2018-01-13  Nick Clifton  <nickc@redhat.com>
2243
2244         2.30 branch created.
2245
2246 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2247
2248         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2249         * i386-tbl.h: Regenerate.
2250
2251 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2252
2253         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2254         * i386-tbl.h: Re-generate.
2255
2256 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2257
2258         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2259         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2260         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2261         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2262         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2263         Disp8MemShift of AVX512VL forms.
2264         * i386-tbl.h: Re-generate.
2265
2266 2018-01-09  Jim Wilson  <jimw@sifive.com>
2267
2268         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2269         then the hi_addr value is zero.
2270
2271 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2272
2273         * arm-dis.c (arm_opcodes): Add csdb.
2274         (thumb32_opcodes): Add csdb.
2275
2276 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2277
2278         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2279         * aarch64-asm-2.c: Regenerate.
2280         * aarch64-dis-2.c: Regenerate.
2281         * aarch64-opc-2.c: Regenerate.
2282
2283 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2284
2285         PR gas/22681
2286         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2287         Remove AVX512 vmovd with 64-bit operands.
2288         * i386-tbl.h: Regenerated.
2289
2290 2018-01-05  Jim Wilson  <jimw@sifive.com>
2291
2292         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2293         jalr.
2294
2295 2018-01-03  Alan Modra  <amodra@gmail.com>
2296
2297         Update year range in copyright notice of all files.
2298
2299 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2300
2301         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2302         and OPERAND_TYPE_REGZMM entries.
2303
2304 For older changes see ChangeLog-2017
2305 \f
2306 Copyright (C) 2018 Free Software Foundation, Inc.
2307
2308 Copying and distribution of this file, with or without modification,
2309 are permitted in any medium without royalty provided the copyright
2310 notice and this notice are preserved.
2311
2312 Local Variables:
2313 mode: change-log
2314 left-margin: 8
2315 fill-column: 74
2316 version-control: never
2317 End: