opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
   4         meaningless.
   5         * i386-tbl.h: Re-generate.
   6
   7 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
  10         meaningless.
  11         * i386-tbl.h: Re-generate.
  12
  13 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
  16         * i386-tbl.h: Re-generate.
  17
  18 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  19
  20         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
  21         * i386-tbl.h: Re-generate.
  22
  23 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
  26         * i386-tbl.h: Re-generate.
  27
  28 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
  31         (vpbroadcastw, rdpid): Drop NoRex64.
  32         * i386-tbl.h: Re-generate.
  33
  34 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
  37         store templates, adding D.
  38         * i386-tbl.h: Re-generate.
  39
  40 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
  43         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
  44         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
  45         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
  46         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
  47         Fold load and store templates where possible, adding D. Drop
  48         IgnoreSize where it was pointlessly present. Drop redundant
  49         *word.
  50         * i386-tbl.h: Re-generate.
  51
  52 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  53
  54         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
  55         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
  56         (intel_operand_size): Handle v_bndmk_mode.
  57         (OP_E_memory): Likewise. Produce (bad) when also riprel.
  58
  59 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
  60
  61         * disassemble.c (ARCH_s12z): Define if ARCH_all.
  62
  63 2018-08-31  Kito Cheng  <kito@andestech.com>
  64
  65         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
  66         compressed floating point instructions.
  67
  68 2018-08-30  Kito Cheng  <kito@andestech.com>
  69
  70         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
  71         riscv_opcode.xlen_requirement.
  72         * riscv-opc.c (riscv_opcodes): Update for struct change.
  73
  74 2018-08-29  Martin Aberg  <maberg@gaisler.com>
  75
  76         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
  77         psr (PWRPSR) instruction.
  78
  79 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  80
  81         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
  82
  83 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  84
  85         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
  86
  87 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  88
  89         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
  90         loongson3a as an alias of gs464 for compatibility.
  91         * mips-opc.c (mips_opcodes): Change Comments.
  92
  93 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  94
  95         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
  96         option.
  97         (print_mips_disassembler_options): Document -M loongson-ext.
  98         * mips-opc.c (LEXT2): New macro.
  99         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 100
 101 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 102
 103          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 104          descriptors.
 105          (parse_mips_ase_option): Handle -M loongson-ext option.
 106          (print_mips_disassembler_options): Document -M loongson-ext.
 107          * mips-opc.c (IL3A): Delete.
 108          * mips-opc.c (LEXT): New macro.
 109          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 110          instructions.
 111
 112 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 113
 114         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 115         descriptors.
 116         (parse_mips_ase_option): Handle -M loongson-cam option.
 117         (print_mips_disassembler_options): Document -M loongson-cam.
 118         * mips-opc.c (LCAM): New macro.
 119         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 120         instructions.
 121
 122 2018-08-21  Alan Modra  <amodra@gmail.com>
 123
 124         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 125         (skip_optional_operands): Count optional operands, and update
 126         ppc_optional_operand_value call.
 127         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 128         (extract_vlensi): Likewise.
 129         (extract_fxm): Return default value for missing optional operand.
 130         (extract_ls, extract_raq, extract_tbr): Likewise.
 131         (insert_sxl, extract_sxl): New functions.
 132         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 133         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 134         flag and extra entry.
 135         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 136         extract_sxl.
 137
 138 2018-08-20  Alan Modra  <amodra@gmail.com>
 139
 140         * sh-opc.h (MASK): Simplify.
 141
 142 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 143
 144         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 145         BM_RESERVED0 or BM_RESERVED1
 146         (bm_rel_decode, bm_n_bytes): Ditto.
 147
 148 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 149
 150         * s12z.h: Delete.
 151
 152 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 153
 154         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 155         address with the addr32 prefix and without base nor index
 156         registers.
 157
 158 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 159
 160         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 161         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 162         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 163         (cpu_flags): Add CpuCMOV and CpuFXSR.
 164         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 165         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 166         * i386-init.h: Regenerated.
 167         * i386-tbl.h: Likewise.
 168
 169 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 170
 171         * arc-regs.h: Update auxiliary registers.
 172
 173 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 176         (RegIP, RegIZ): Define.
 177         * i386-reg.tbl: Adjust comments.
 178         (rip): Use Qword instead of BaseIndex. Use RegIP.
 179         (eip): Use Dword instead of BaseIndex. Use RegIP.
 180         (riz): Add Qword. Use RegIZ.
 181         (eiz): Add Dword. Use RegIZ.
 182         * i386-tbl.h: Re-generate.
 183
 184 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 187         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 188         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 189         * i386-tbl.h: Re-generate.
 190
 191 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-gen.c (operand_types): Remove Mem field.
 194         * i386-opc.h (union i386_operand_type): Remove mem field.
 195         * i386-init.h, i386-tbl.h: Re-generate.
 196
 197 2018-08-01  Alan Modra  <amodra@gmail.com>
 198
 199         * po/POTFILES.in: Regenerate.
 200
 201 2018-07-31  Nick Clifton  <nickc@redhat.com>
 202
 203         * po/sv.po: Updated Swedish translation.
 204
 205 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 208         * i386-init.h, i386-tbl.h: Re-generate.
 209
 210 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-opc.h (ZEROING_MASKING) Rename to ...
 213         (DYNAMIC_MASKING): ... this. Adjust comment.
 214         * i386-opc.tbl (MaskingMorZ): Define.
 215         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 216         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 217         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 218         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 219         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 220         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 221         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 222         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 223         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 224
 225 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-opc.tbl: Use element rather than vector size for AVX512*
 228         scatter/gather insns.
 229         * i386-tbl.h: Re-generate.
 230
 231 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 234         (cpu_flags): Drop CpuVREX.
 235         * i386-opc.h (CpuVREX): Delete.
 236         (union i386_cpu_flags): Remove cpuvrex.
 237         * i386-init.h, i386-tbl.h: Re-generate.
 238
 239 2018-07-30  Jim Wilson  <jimw@sifive.com>
 240
 241         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 242         fields.
 243         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 244
 245 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 246
 247         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 248         * Makefile.in: Regenerated.
 249         * configure.ac: Add C-SKY.
 250         * configure: Regenerated.
 251         * csky-dis.c: New file.
 252         * csky-opc.h: New file.
 253         * disassemble.c (ARCH_csky): Define.
 254         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 255         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 256
 257 2018-07-27  Alan Modra  <amodra@gmail.com>
 258
 259         * ppc-opc.c (insert_sprbat): Correct function parameter and
 260         return type.
 261         (extract_sprbat): Likewise, variable too.
 262
 263 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 264             Alan Modra  <amodra@gmail.com>
 265
 266         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 267         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 268         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 269         support disjointed BAT.
 270         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 271         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 272         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 273
 274 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 275             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 276
 277         * i386-gen.c (adjust_broadcast_modifier): New function.
 278         (process_i386_opcode_modifier): Add an argument for operands.
 279         Adjust the Broadcast value based on operands.
 280         (output_i386_opcode): Pass operand_types to
 281         process_i386_opcode_modifier.
 282         (process_i386_opcodes): Pass NULL as operands to
 283         process_i386_opcode_modifier.
 284         * i386-opc.h (BYTE_BROADCAST): New.
 285         (WORD_BROADCAST): Likewise.
 286         (DWORD_BROADCAST): Likewise.
 287         (QWORD_BROADCAST): Likewise.
 288         (i386_opcode_modifier): Expand broadcast to 3 bits.
 289         * i386-tbl.h: Regenerated.
 290
 291 2018-07-24  Alan Modra  <amodra@gmail.com>
 292
 293         PR 23430
 294         * or1k-desc.h: Regenerate.
 295
 296 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 297
 298         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 299         vcvtusi2ss, and vcvtusi2sd.
 300         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 301         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 302         * i386-tbl.h: Re-generate.
 303
 304 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 305
 306         * arc-opc.c (extract_w6): Fix extending the sign.
 307
 308 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 309
 310         * arc-tbl.h (vewt): Allow it for ARC EM family.
 311
 312 2018-07-23  Alan Modra  <amodra@gmail.com>
 313
 314         PR 23419
 315         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 316         opcode variants for mtspr/mfspr encodings.
 317
 318 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 319             Maciej W. Rozycki  <macro@mips.com>
 320
 321         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 322         loongson3a descriptors.
 323         (parse_mips_ase_option): Handle -M loongson-mmi option.
 324         (print_mips_disassembler_options): Document -M loongson-mmi.
 325         * mips-opc.c (LMMI): New macro.
 326         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 327         instructions.
 328
 329 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 332         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 333         IgnoreSize and [XYZ]MMword where applicable.
 334         * i386-tbl.h: Re-generate.
 335
 336 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 339         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 340         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 341         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 342         * i386-tbl.h: Re-generate.
 343
 344 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 345
 346         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 347         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 348         VPCLMULQDQ templates into their respective AVX512VL counterparts
 349         where possible, using Disp8ShiftVL and CheckRegSize instead of
 350         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 351         * i386-tbl.h: Re-generate.
 352
 353 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 354
 355         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 356         AVX512VL counterparts where possible, using Disp8ShiftVL and
 357         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 358         IgnoreSize) as appropriate.
 359         * i386-tbl.h: Re-generate.
 360
 361 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 362
 363         * i386-opc.tbl: Fold AVX512BW templates into their respective
 364         AVX512VL counterparts where possible, using Disp8ShiftVL and
 365         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 366         IgnoreSize) as appropriate.
 367         * i386-tbl.h: Re-generate.
 368
 369 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 370
 371         * i386-opc.tbl: Fold AVX512CD templates into their respective
 372         AVX512VL counterparts where possible, using Disp8ShiftVL and
 373         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 374         IgnoreSize) as appropriate.
 375         * i386-tbl.h: Re-generate.
 376
 377 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 378
 379         * i386-opc.h (DISP8_SHIFT_VL): New.
 380         * i386-opc.tbl (Disp8ShiftVL):  Define.
 381         (various): Fold AVX512VL templates into their respective
 382         AVX512F counterparts where possible, using Disp8ShiftVL and
 383         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 384         IgnoreSize) as appropriate.
 385         * i386-tbl.h: Re-generate.
 386
 387 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 388
 389         * Makefile.am: Change dependencies and rule for
 390         $(srcdir)/i386-init.h.
 391         * Makefile.in: Re-generate.
 392         * i386-gen.c (process_i386_opcodes): New local variable
 393         "marker". Drop opening of input file. Recognize marker and line
 394         number directives.
 395         * i386-opc.tbl (OPCODE_I386_H): Define.
 396         (i386-opc.h): Include it.
 397         (None): Undefine.
 398
 399 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 400
 401         PR gas/23418
 402         * i386-opc.h (Byte): Update comments.
 403         (Word): Likewise.
 404         (Dword): Likewise.
 405         (Fword): Likewise.
 406         (Qword): Likewise.
 407         (Tbyte): Likewise.
 408         (Xmmword): Likewise.
 409         (Ymmword): Likewise.
 410         (Zmmword): Likewise.
 411         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 412         vcvttps2uqq.
 413         * i386-tbl.h: Regenerated.
 414
 415 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 416
 417         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 418         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 419         * aarch64-asm-2.c: Regenerate.
 420         * aarch64-dis-2.c: Regenerate.
 421         * aarch64-opc-2.c: Regenerate.
 422
 423 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 424
 425         PR binutils/23192
 426         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 427         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 428         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 429         sqdmulh, sqrdmulh): Use Em16.
 430
 431 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 432
 433         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 434         csdb together with them.
 435         (thumb32_opcodes): Likewise.
 436
 437 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 438
 439         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 440         requiring 32-bit registers as operands 2 and 3. Improve
 441         comments.
 442         (mwait, mwaitx): Fold templates. Improve comments.
 443         OPERAND_TYPE_INOUTPORTREG.
 444         * i386-tbl.h: Re-generate.
 445
 446 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 447
 448         * i386-gen.c (operand_type_init): Remove
 449         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 450         OPERAND_TYPE_INOUTPORTREG.
 451         * i386-init.h: Re-generate.
 452
 453 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 456         (wrssq, wrussq): Add Qword.
 457         * i386-tbl.h: Re-generate.
 458
 459 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-opc.h: Rename OTMax to OTNum.
 462         (OTNumOfUints): Adjust calculation.
 463         (OTUnused): Directly alias to OTNum.
 464
 465 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 466
 467         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 468         `reg_xys'.
 469         (lea_reg_xys): Likewise.
 470         (print_insn_loop_primitive): Rename `reg' local variable to
 471         `reg_dxy'.
 472
 473 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 474
 475         PR binutils/23242
 476         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 477
 478 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 479
 480         PR binutils/23369
 481         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 482         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 483
 484 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 485
 486         PR tdep/8282
 487         * mips-dis.c (mips_option_arg_t): New enumeration.
 488         (mips_options): New variable.
 489         (disassembler_options_mips): New function.
 490         (print_mips_disassembler_options): Reimplement in terms of
 491         `disassembler_options_mips'.
 492         * arm-dis.c (disassembler_options_arm): Adapt to using the
 493         `disasm_options_and_args_t' structure.
 494         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 495         * s390-dis.c (disassembler_options_s390): Likewise.
 496
 497 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 498
 499         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 500         expected result.
 501         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 502         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 503         * testsuite/ld-arm/tls-longplt.d: Likewise.
 504
 505 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 506
 507         PR binutils/23192
 508         * aarch64-asm-2.c: Regenerate.
 509         * aarch64-dis-2.c: Likewise.
 510         * aarch64-opc-2.c: Likewise.
 511         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 512         * aarch64-opc.c (operand_general_constraint_met_p,
 513         aarch64_print_operand): Likewise.
 514         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 515         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 516         fmlal2, fmlsl2.
 517         (AARCH64_OPERANDS): Add Em2.
 518
 519 2018-06-26  Nick Clifton  <nickc@redhat.com>
 520
 521         * po/uk.po: Updated Ukranian translation.
 522         * po/de.po: Updated German translation.
 523         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 524
 525 2018-06-26  Nick Clifton  <nickc@redhat.com>
 526
 527         * nfp-dis.c: Fix spelling mistake.
 528
 529 2018-06-24  Nick Clifton  <nickc@redhat.com>
 530
 531         * configure: Regenerate.
 532         * po/opcodes.pot: Regenerate.
 533
 534 2018-06-24  Nick Clifton  <nickc@redhat.com>
 535
 536         2.31 branch created.
 537
 538 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 539
 540         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 541         * aarch64-asm-2.c: Regenerate.
 542         * aarch64-dis-2.c: Likewise.
 543
 544 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 545
 546         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 547         `-M ginv' option description.
 548
 549 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 550
 551         PR gas/23305
 552         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 553         la and lla.
 554
 555 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 556
 557         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 558         * configure.ac: Remove AC_PREREQ.
 559         * Makefile.in: Re-generate.
 560         * aclocal.m4: Re-generate.
 561         * configure: Re-generate.
 562
 563 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 564
 565         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 566         mips64r6 descriptors.
 567         (parse_mips_ase_option): Handle -Mginv option.
 568         (print_mips_disassembler_options): Document -Mginv.
 569         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 570         (GINV): New macro.
 571         (mips_opcodes): Define ginvi and ginvt.
 572
 573 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 574             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 575
 576         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 577         * mips-opc.c (CRC, CRC64): New macros.
 578         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 579         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 580         crc32cd for CRC64.
 581
 582 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 583
 584         PR 20319
 585         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 586         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 587
 588 2018-06-06  Alan Modra  <amodra@gmail.com>
 589
 590         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 591         setjmp.  Move init for some other vars later too.
 592
 593 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 594
 595         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 596         (dis_private): Add new fields for property section tracking.
 597         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 598         (xtensa_instruction_fits): New functions.
 599         (fetch_data): Bump minimal fetch size to 4.
 600         (print_insn_xtensa): Make struct dis_private static.
 601         Load and prepare property table on section change.
 602         Don't disassemble literals. Don't disassemble instructions that
 603         cross property table boundaries.
 604
 605 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 606
 607         * configure: Regenerated.
 608
 609 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 612         * i386-tbl.h: Re-generate.
 613
 614 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-opc.tbl (sldt, str): Add NoRex64.
 617         * i386-tbl.h: Re-generate.
 618
 619 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 620
 621         * i386-opc.tbl (invpcid): Add Oword.
 622         * i386-tbl.h: Re-generate.
 623
 624 2018-06-01  Alan Modra  <amodra@gmail.com>
 625
 626         * sysdep.h (_bfd_error_handler): Don't declare.
 627         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 628         * rl78-decode.opc: Likewise.
 629         * msp430-decode.c: Regenerate.
 630         * rl78-decode.c: Regenerate.
 631
 632 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 633
 634         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 635         * i386-init.h : Regenerated.
 636
 637 2018-05-25  Alan Modra  <amodra@gmail.com>
 638
 639         * Makefile.in: Regenerate.
 640         * po/POTFILES.in: Regenerate.
 641
 642 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 643
 644         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 645         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 646         (insert_bab, extract_bab, insert_btab, extract_btab,
 647         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 648         (BAT, BBA VBA RBS XB6S): Delete macros.
 649         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 650         (BB, BD, RBX, XC6): Update for new macros.
 651         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 652         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 653         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 654         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 655
 656 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 657
 658         * Makefile.am: Add support for s12z architecture.
 659         * configure.ac: Likewise.
 660         * disassemble.c: Likewise.
 661         * disassemble.h: Likewise.
 662         * Makefile.in: Regenerate.
 663         * configure: Regenerate.
 664         * s12z-dis.c: New file.
 665         * s12z.h: New file.
 666
 667 2018-05-18  Alan Modra  <amodra@gmail.com>
 668
 669         * nfp-dis.c: Don't #include libbfd.h.
 670         (init_nfp3200_priv): Use bfd_get_section_contents.
 671         (nit_nfp6000_mecsr_sec): Likewise.
 672
 673 2018-05-17  Nick Clifton  <nickc@redhat.com>
 674
 675         * po/zh_CN.po: Updated simplified Chinese translation.
 676
 677 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 678
 679         PR binutils/23109
 680         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 681         * aarch64-dis-2.c: Regenerate.
 682
 683 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 684
 685         PR binutils/21446
 686         * aarch64-asm.c (opintl.h): Include.
 687         (aarch64_ins_sysreg): Enforce read/write constraints.
 688         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 689         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 690         (F_REG_READ, F_REG_WRITE): New.
 691         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 692         AARCH64_OPND_SYSREG.
 693         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 694         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 695         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 696         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 697         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 698         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 699         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 700         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 701         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 702         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 703         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 704         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 705         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 706         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 707         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 708         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 709         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 710
 711 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 712
 713         PR binutils/21446
 714         * aarch64-dis.c (no_notes: New.
 715         (parse_aarch64_dis_option): Support notes.
 716         (aarch64_decode_insn, print_operands): Likewise.
 717         (print_aarch64_disassembler_options): Document notes.
 718         * aarch64-opc.c (aarch64_print_operand): Support notes.
 719
 720 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 721
 722         PR binutils/21446
 723         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 724         and take error struct.
 725         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 726         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 727         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 728         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 729         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 730         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 731         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 732         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 733         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 734         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 735         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 736         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 737         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 738         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 739         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 740         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 741         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 742         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 743         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 744         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 745         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 746         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 747         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 748         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 749         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 750         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 751         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 752         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 753         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 754         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 755         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 756         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 757         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 758         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 759         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 760         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 761         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 762         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 763         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 764         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 765         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 766         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 767         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 768         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 769         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 770         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 771         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 772         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 773         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 774         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 775         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 776         (determine_disassembling_preference, aarch64_decode_insn,
 777         print_insn_aarch64_word, print_insn_data): Take errors struct.
 778         (print_insn_aarch64): Use errors.
 779         * aarch64-asm-2.c: Regenerate.
 780         * aarch64-dis-2.c: Regenerate.
 781         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 782         boolean in aarch64_insert_operan.
 783         (print_operand_extractor): Likewise.
 784         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 785
 786 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 787
 788         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 789
 790 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 791
 792         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 793
 794 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 795
 796         * cr16-opc.c (cr16_instruction): Comment typo fix.
 797         * hppa-dis.c (print_insn_hppa): Likewise.
 798
 799 2018-05-08  Jim Wilson  <jimw@sifive.com>
 800
 801         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 802         (match_c_slli64, match_srxi_as_c_srxi): New.
 803         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 804         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 805         <c.slli, c.srli, c.srai>: Use match_s_slli.
 806         <c.slli64, c.srli64, c.srai64>: New.
 807
 808 2018-05-08  Alan Modra  <amodra@gmail.com>
 809
 810         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 811         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 812         partition opcode space for index lookup.
 813
 814 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 815
 816         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 817         <insn_length>: ...with this.  Update usage.
 818         Remove duplicate call to *info->memory_error_func.
 819
 820 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 821             H.J. Lu  <hongjiu.lu@intel.com>
 822
 823         * i386-dis.c (Gva): New.
 824         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 825         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 826         (prefix_table): New instructions (see prefix above).
 827         (mod_table): New instructions (see prefix above).
 828         (OP_G): Handle va_mode.
 829         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 830         CPU_MOVDIR64B_FLAGS.
 831         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 832         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 833         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 834         * i386-opc.tbl: Add movidir{i,64b}.
 835         * i386-init.h: Regenerated.
 836         * i386-tbl.h: Likewise.
 837
 838 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 839
 840         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 841         AddrPrefixOpReg.
 842         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 843         (AddrPrefixOpReg): This.
 844         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 845         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 846
 847 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 848
 849         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 850         (vle_num_opcodes): Likewise.
 851         (spe2_num_opcodes): Likewise.
 852         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 853         initialization loop.
 854         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 855         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 856         only once.
 857
 858 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 859
 860         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 861
 862 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 863
 864         Makefile.am: Added nfp-dis.c.
 865         configure.ac: Added bfd_nfp_arch.
 866         disassemble.h: Added print_insn_nfp prototype.
 867         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 868         nfp-dis.c: New, for NFP support.
 869         po/POTFILES.in: Added nfp-dis.c to the list.
 870         Makefile.in: Regenerate.
 871         configure: Regenerate.
 872
 873 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 874
 875         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 876         templates into their base ones.
 877         * i386-tlb.h: Re-generate.
 878
 879 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 880
 881         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 882         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 883         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 884         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 885         * i386-init.h: Re-generate.
 886
 887 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 888
 889         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 890         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 891         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 892         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 893         comment.
 894         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 895         and CpuRegMask.
 896         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 897         CpuRegMask: Delete.
 898         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 899         cpuregzmm, and cpuregmask.
 900         * i386-init.h: Re-generate.
 901         * i386-tbl.h: Re-generate.
 902
 903 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 904
 905         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 906         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 907         * i386-init.h: Re-generate.
 908
 909 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 910
 911         * i386-gen.c (VexImmExt): Delete.
 912         * i386-opc.h (VexImmExt, veximmext): Delete.
 913         * i386-opc.tbl: Drop all VexImmExt uses.
 914         * i386-tlb.h: Re-generate.
 915
 916 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 917
 918         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 919         register-only forms.
 920         * i386-tlb.h: Re-generate.
 921
 922 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 923
 924         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 925
 926 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 927
 928         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 929         PREFIX_0F1C.
 930         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 931         (cpu_flags): Add CpuCLDEMOTE.
 932         * i386-init.h: Regenerate.
 933         * i386-opc.h (enum): Add CpuCLDEMOTE,
 934         (i386_cpu_flags): Add cpucldemote.
 935         * i386-opc.tbl: Add cldemote.
 936         * i386-tbl.h: Regenerate.
 937
 938 2018-04-16  Alan Modra  <amodra@gmail.com>
 939
 940         * Makefile.am: Remove sh5 and sh64 support.
 941         * configure.ac: Likewise.
 942         * disassemble.c: Likewise.
 943         * disassemble.h: Likewise.
 944         * sh-dis.c: Likewise.
 945         * sh64-dis.c: Delete.
 946         * sh64-opc.c: Delete.
 947         * sh64-opc.h: Delete.
 948         * Makefile.in: Regenerate.
 949         * configure: Regenerate.
 950         * po/POTFILES.in: Regenerate.
 951
 952 2018-04-16  Alan Modra  <amodra@gmail.com>
 953
 954         * Makefile.am: Remove w65 support.
 955         * configure.ac: Likewise.
 956         * disassemble.c: Likewise.
 957         * disassemble.h: Likewise.
 958         * w65-dis.c: Delete.
 959         * w65-opc.h: Delete.
 960         * Makefile.in: Regenerate.
 961         * configure: Regenerate.
 962         * po/POTFILES.in: Regenerate.
 963
 964 2018-04-16  Alan Modra  <amodra@gmail.com>
 965
 966         * configure.ac: Remove we32k support.
 967         * configure: Regenerate.
 968
 969 2018-04-16  Alan Modra  <amodra@gmail.com>
 970
 971         * Makefile.am: Remove m88k support.
 972         * configure.ac: Likewise.
 973         * disassemble.c: Likewise.
 974         * disassemble.h: Likewise.
 975         * m88k-dis.c: Delete.
 976         * Makefile.in: Regenerate.
 977         * configure: Regenerate.
 978         * po/POTFILES.in: Regenerate.
 979
 980 2018-04-16  Alan Modra  <amodra@gmail.com>
 981
 982         * Makefile.am: Remove i370 support.
 983         * configure.ac: Likewise.
 984         * disassemble.c: Likewise.
 985         * disassemble.h: Likewise.
 986         * i370-dis.c: Delete.
 987         * i370-opc.c: Delete.
 988         * Makefile.in: Regenerate.
 989         * configure: Regenerate.
 990         * po/POTFILES.in: Regenerate.
 991
 992 2018-04-16  Alan Modra  <amodra@gmail.com>
 993
 994         * Makefile.am: Remove h8500 support.
 995         * configure.ac: Likewise.
 996         * disassemble.c: Likewise.
 997         * disassemble.h: Likewise.
 998         * h8500-dis.c: Delete.
 999         * h8500-opc.h: Delete.
1000         * Makefile.in: Regenerate.
1001         * configure: Regenerate.
1002         * po/POTFILES.in: Regenerate.
1003
1004 2018-04-16  Alan Modra  <amodra@gmail.com>
1005
1006         * configure.ac: Remove tahoe support.
1007         * configure: Regenerate.
1008
1009 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1010
1011         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1012         umwait.
1013         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1014         64-bit mode.
1015         * i386-tbl.h: Regenerated.
1016
1017 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1018
1019         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1020         PREFIX_MOD_1_0FAE_REG_6.
1021         (va_mode): New.
1022         (OP_E_register): Use va_mode.
1023         * i386-dis-evex.h (prefix_table):
1024         New instructions (see prefixes above).
1025         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1026         (cpu_flags): Likewise.
1027         * i386-opc.h (enum): Likewise.
1028         (i386_cpu_flags): Likewise.
1029         * i386-opc.tbl: Add umonitor, umwait, tpause.
1030         * i386-init.h: Regenerate.
1031         * i386-tbl.h: Likewise.
1032
1033 2018-04-11  Alan Modra  <amodra@gmail.com>
1034
1035         * opcodes/i860-dis.c: Delete.
1036         * opcodes/i960-dis.c: Delete.
1037         * Makefile.am: Remove i860 and i960 support.
1038         * configure.ac: Likewise.
1039         * disassemble.c: Likewise.
1040         * disassemble.h: Likewise.
1041         * Makefile.in: Regenerate.
1042         * configure: Regenerate.
1043         * po/POTFILES.in: Regenerate.
1044
1045 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1046
1047         PR binutils/23025
1048         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1049         to 0.
1050         (print_insn): Clear vex instead of vex.evex.
1051
1052 2018-04-04  Nick Clifton  <nickc@redhat.com>
1053
1054         * po/es.po: Updated Spanish translation.
1055
1056 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1057
1058         * i386-gen.c (opcode_modifiers): Delete VecESize.
1059         * i386-opc.h (VecESize): Delete.
1060         (struct i386_opcode_modifier): Delete vecesize.
1061         * i386-opc.tbl: Drop VecESize.
1062         * i386-tlb.h: Re-generate.
1063
1064 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1065
1066         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1067         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1068         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1069         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1070         * i386-tlb.h: Re-generate.
1071
1072 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1075         Fold AVX512 forms
1076         * i386-tlb.h: Re-generate.
1077
1078 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1079
1080         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1081         (vex_len_table): Drop Y for vcvt*2si.
1082         (putop): Replace plain 'Y' handling by abort().
1083
1084 2018-03-28  Nick Clifton  <nickc@redhat.com>
1085
1086         PR 22988
1087         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1088         instructions with only a base address register.
1089         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1090         handle AARHC64_OPND_SVE_ADDR_R.
1091         (aarch64_print_operand): Likewise.
1092         * aarch64-asm-2.c: Regenerate.
1093         * aarch64_dis-2.c: Regenerate.
1094         * aarch64-opc-2.c: Regenerate.
1095
1096 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1097
1098         * i386-opc.tbl: Drop VecESize from register only insn forms and
1099         memory forms not allowing broadcast.
1100         * i386-tlb.h: Re-generate.
1101
1102 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1103
1104         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1105         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1106         sha256*): Drop Disp<N>.
1107
1108 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1109
1110         * i386-dis.c (EbndS, bnd_swap_mode): New.
1111         (prefix_table): Use EbndS.
1112         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1113         * i386-opc.tbl (bndmov): Move misplaced Load.
1114         * i386-tlb.h: Re-generate.
1115
1116 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1117
1118         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1119         templates allowing memory operands and folded ones for register
1120         only flavors.
1121         * i386-tlb.h: Re-generate.
1122
1123 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1124
1125         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1126         256-bit templates. Drop redundant leftover Disp<N>.
1127         * i386-tlb.h: Re-generate.
1128
1129 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1130
1131         * riscv-opc.c (riscv_insn_types): New.
1132
1133 2018-03-13  Nick Clifton  <nickc@redhat.com>
1134
1135         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1136
1137 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1138
1139         * i386-opc.tbl: Add Optimize to clr.
1140         * i386-tbl.h: Regenerated.
1141
1142 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1143
1144         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1145         * i386-opc.h (OldGcc): Removed.
1146         (i386_opcode_modifier): Remove oldgcc.
1147         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1148         instructions for old (<= 2.8.1) versions of gcc.
1149         * i386-tbl.h: Regenerated.
1150
1151 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-opc.h (EVEXDYN): New.
1154         * i386-opc.tbl: Fold various AVX512VL templates.
1155         * i386-tlb.h: Re-generate.
1156
1157 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1158
1159         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1160         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1161         vpexpandd, vpexpandq): Fold AFX512VF templates.
1162         * i386-tlb.h: Re-generate.
1163
1164 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1165
1166         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1167         Fold 128- and 256-bit VEX-encoded templates.
1168         * i386-tlb.h: Re-generate.
1169
1170 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1171
1172         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1173         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1174         vpexpandd, vpexpandq): Fold AVX512F templates.
1175         * i386-tlb.h: Re-generate.
1176
1177 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1178
1179         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1180         64-bit templates. Drop Disp<N>.
1181         * i386-tlb.h: Re-generate.
1182
1183 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1186         and 256-bit templates.
1187         * i386-tlb.h: Re-generate.
1188
1189 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1190
1191         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1192         * i386-tlb.h: Re-generate.
1193
1194 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1195
1196         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1197         Drop NoAVX.
1198         * i386-tlb.h: Re-generate.
1199
1200 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1201
1202         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1203         * i386-tlb.h: Re-generate.
1204
1205 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1206
1207         * i386-gen.c (opcode_modifiers): Delete FloatD.
1208         * i386-opc.h (FloatD): Delete.
1209         (struct i386_opcode_modifier): Delete floatd.
1210         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1211         FloatD by D.
1212         * i386-tlb.h: Re-generate.
1213
1214 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1215
1216         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1217
1218 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1219
1220         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1221         * i386-tlb.h: Re-generate.
1222
1223 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1224
1225         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1226         forms.
1227         * i386-tlb.h: Re-generate.
1228
1229 2018-03-07  Alan Modra  <amodra@gmail.com>
1230
1231         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1232         bfd_arch_rs6000.
1233         * disassemble.h (print_insn_rs6000): Delete.
1234         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1235         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1236         (print_insn_rs6000): Delete.
1237
1238 2018-03-03  Alan Modra  <amodra@gmail.com>
1239
1240         * sysdep.h (opcodes_error_handler): Define.
1241         (_bfd_error_handler): Declare.
1242         * Makefile.am: Remove stray #.
1243         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1244         EDIT" comment.
1245         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1246         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1247         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1248         opcodes_error_handler to print errors.  Standardize error messages.
1249         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1250         and include opintl.h.
1251         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1252         * i386-gen.c: Standardize error messages.
1253         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1254         * Makefile.in: Regenerate.
1255         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1256         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1257         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1258         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1259         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1260         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1261         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1262         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1263         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1264         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1265         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1266         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1267         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1268
1269 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1270
1271         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1272         vpsub[bwdq] instructions.
1273         * i386-tbl.h: Regenerated.
1274
1275 2018-03-01  Alan Modra  <amodra@gmail.com>
1276
1277         * configure.ac (ALL_LINGUAS): Sort.
1278         * configure: Regenerate.
1279
1280 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1281
1282         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1283         macro by assignements.
1284
1285 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1286
1287         PR gas/22871
1288         * i386-gen.c (opcode_modifiers): Add Optimize.
1289         * i386-opc.h (Optimize): New enum.
1290         (i386_opcode_modifier): Add optimize.
1291         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1292         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1293         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1294         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1295         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1296         vpxord and vpxorq.
1297         * i386-tbl.h: Regenerated.
1298
1299 2018-02-26  Alan Modra  <amodra@gmail.com>
1300
1301         * crx-dis.c (getregliststring): Allocate a large enough buffer
1302         to silence false positive gcc8 warning.
1303
1304 2018-02-22  Shea Levy <shea@shealevy.com>
1305
1306         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1307
1308 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1309
1310         * i386-opc.tbl: Add {rex},
1311         * i386-tbl.h: Regenerated.
1312
1313 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1314
1315         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1316         (mips16_opcodes): Replace `M' with `m' for "restore".
1317
1318 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1319
1320         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1321
1322 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1323
1324         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1325         variable to `function_index'.
1326
1327 2018-02-13  Nick Clifton  <nickc@redhat.com>
1328
1329         PR 22823
1330         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1331         about truncation of printing.
1332
1333 2018-02-12  Henry Wong <henry@stuffedcow.net>
1334
1335         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1336
1337 2018-02-05  Nick Clifton  <nickc@redhat.com>
1338
1339         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1340
1341 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1342
1343         * i386-dis.c (enum): Add pconfig.
1344         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1345         (cpu_flags): Add CpuPCONFIG.
1346         * i386-opc.h (enum): Add CpuPCONFIG.
1347         (i386_cpu_flags): Add cpupconfig.
1348         * i386-opc.tbl: Add PCONFIG instruction.
1349         * i386-init.h: Regenerate.
1350         * i386-tbl.h: Likewise.
1351
1352 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1353
1354         * i386-dis.c (enum): Add PREFIX_0F09.
1355         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1356         (cpu_flags): Add CpuWBNOINVD.
1357         * i386-opc.h (enum): Add CpuWBNOINVD.
1358         (i386_cpu_flags): Add cpuwbnoinvd.
1359         * i386-opc.tbl: Add WBNOINVD instruction.
1360         * i386-init.h: Regenerate.
1361         * i386-tbl.h: Likewise.
1362
1363 2018-01-17  Jim Wilson  <jimw@sifive.com>
1364
1365         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1366
1367 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1368
1369         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1370         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1371         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1372         (cpu_flags): Add CpuIBT, CpuSHSTK.
1373         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1374         (i386_cpu_flags): Add cpuibt, cpushstk.
1375         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1376         * i386-init.h: Regenerate.
1377         * i386-tbl.h: Likewise.
1378
1379 2018-01-16  Nick Clifton  <nickc@redhat.com>
1380
1381         * po/pt_BR.po: Updated Brazilian Portugese translation.
1382         * po/de.po: Updated German translation.
1383
1384 2018-01-15  Jim Wilson  <jimw@sifive.com>
1385
1386         * riscv-opc.c (match_c_nop): New.
1387         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1388
1389 2018-01-15  Nick Clifton  <nickc@redhat.com>
1390
1391         * po/uk.po: Updated Ukranian translation.
1392
1393 2018-01-13  Nick Clifton  <nickc@redhat.com>
1394
1395         * po/opcodes.pot: Regenerated.
1396
1397 2018-01-13  Nick Clifton  <nickc@redhat.com>
1398
1399         * configure: Regenerate.
1400
1401 2018-01-13  Nick Clifton  <nickc@redhat.com>
1402
1403         2.30 branch created.
1404
1405 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1406
1407         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1408         * i386-tbl.h: Regenerate.
1409
1410 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1411
1412         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1413         * i386-tbl.h: Re-generate.
1414
1415 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1416
1417         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1418         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1419         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1420         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1421         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1422         Disp8MemShift of AVX512VL forms.
1423         * i386-tbl.h: Re-generate.
1424
1425 2018-01-09  Jim Wilson  <jimw@sifive.com>
1426
1427         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1428         then the hi_addr value is zero.
1429
1430 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1431
1432         * arm-dis.c (arm_opcodes): Add csdb.
1433         (thumb32_opcodes): Add csdb.
1434
1435 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1436
1437         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1438         * aarch64-asm-2.c: Regenerate.
1439         * aarch64-dis-2.c: Regenerate.
1440         * aarch64-opc-2.c: Regenerate.
1441
1442 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1443
1444         PR gas/22681
1445         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1446         Remove AVX512 vmovd with 64-bit operands.
1447         * i386-tbl.h: Regenerated.
1448
1449 2018-01-05  Jim Wilson  <jimw@sifive.com>
1450
1451         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1452         jalr.
1453
1454 2018-01-03  Alan Modra  <amodra@gmail.com>
1455
1456         Update year range in copyright notice of all files.
1457
1458 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1459
1460         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1461         and OPERAND_TYPE_REGZMM entries.
1462
1463 For older changes see ChangeLog-2017
1464 \f
1465 Copyright (C) 2018 Free Software Foundation, Inc.
1466
1467 Copying and distribution of this file, with or without modification,
1468 are permitted in any medium without royalty provided the copyright
1469 notice and this notice are preserved.
1470
1471 Local Variables:
1472 mode: change-log
1473 left-margin: 8
1474 fill-column: 74
1475 version-control: never
1476 End: