opcodes/ChangeLog

   1 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
   2
   3         * Makefile.in: Regenerate.
   4         * configure: Likewise.
   5
   6 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
   7
   8         * arc-ext-tbl.h (EXTINSN2OPF): Define.
   9         (EXTINSN2OP): Use EXTINSN2OPF.
  10         (bspeekm, bspop, modapp): New extension instructions.
  11         * arc-opc.c (F_DNZ_ND): Define.
  12         (F_DNZ_D): Likewise.
  13         (F_SIZEB1): Changed.
  14         (C_DNZ_D): Define.
  15         (C_HARD): Changed.
  16         * arc-tbl.h (dbnz): New instruction.
  17         (prealloc): Allow it for ARC EM.
  18         (xbfu): Likewise.
  19
  20 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  21
  22         * aarch64-opc.c (print_immediate_offset_address): Print spaces
  23         after commas in addresses.
  24         (aarch64_print_operand): Likewise.
  25
  26 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  27
  28         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
  29         rather than "should be" or "expected to be" in error messages.
  30
  31 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  32
  33         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
  34         (print_mnemonic_name): ...here.
  35         (print_comment): New function.
  36         (print_aarch64_insn): Call it.
  37         * aarch64-opc.c (aarch64_conds): Add SVE names.
  38         (aarch64_print_operand): Print alternative condition names in
  39         a comment.
  40
  41 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  42
  43         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
  44         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
  45         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
  46         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
  47         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
  48         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
  49         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
  50         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
  51         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
  52         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
  53         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
  54         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
  55         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
  56         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
  57         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
  58         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
  59         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
  60         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
  61         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
  62         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
  63         (OP_SVE_XWU, OP_SVE_XXU): New macros.
  64         (aarch64_feature_sve): New variable.
  65         (SVE): New macro.
  66         (_SVE_INSN): Likewise.
  67         (aarch64_opcode_table): Add SVE instructions.
  68         * aarch64-opc.h (extract_fields): Declare.
  69         * aarch64-opc-2.c: Regenerate.
  70         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
  71         * aarch64-asm-2.c: Regenerate.
  72         * aarch64-dis.c (extract_fields): Make global.
  73         (do_misc_decoding): Handle the new SVE aarch64_ops.
  74         * aarch64-dis-2.c: Regenerate.
  75
  76 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  77
  78         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
  79         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
  80         aarch64_field_kinds.
  81         * aarch64-opc.c (fields): Add corresponding entries.
  82         * aarch64-asm.c (aarch64_get_variant): New function.
  83         (aarch64_encode_variant_using_iclass): Likewise.
  84         (aarch64_opcode_encode): Call it.
  85         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
  86         (aarch64_opcode_decode): Call it.
  87
  88 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  89
  90         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
  91         and FP register operands.
  92         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
  93         (FLD_SVE_Vn): New aarch64_field_kinds.
  94         * aarch64-opc.c (fields): Add corresponding entries.
  95         (aarch64_print_operand): Handle the new SVE core and FP register
  96         operands.
  97         * aarch64-opc-2.c: Regenerate.
  98         * aarch64-asm-2.c: Likewise.
  99         * aarch64-dis-2.c: Likewise.
 100
 101 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 102
 103         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 104         immediate operands.
 105         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 106         * aarch64-opc.c (fields): Add corresponding entry.
 107         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 108         operands.
 109         (aarch64_print_operand): Likewise.
 110         * aarch64-opc-2.c: Regenerate.
 111         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 112         (ins_sve_float_zero_one): New inserters.
 113         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 114         (aarch64_ins_sve_float_half_two): Likewise.
 115         (aarch64_ins_sve_float_zero_one): Likewise.
 116         * aarch64-asm-2.c: Regenerate.
 117         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 118         (ext_sve_float_zero_one): New extractors.
 119         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 120         (aarch64_ext_sve_float_half_two): Likewise.
 121         (aarch64_ext_sve_float_zero_one): Likewise.
 122         * aarch64-dis-2.c: Regenerate.
 123
 124 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 125
 126         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 127         integer immediate operands.
 128         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 129         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 130         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 131         * aarch64-opc.c (fields): Add corresponding entries.
 132         (operand_general_constraint_met_p): Handle the new SVE integer
 133         immediate operands.
 134         (aarch64_print_operand): Likewise.
 135         (aarch64_sve_dupm_mov_immediate_p): New function.
 136         * aarch64-opc-2.c: Regenerate.
 137         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 138         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 139         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 140         (aarch64_ins_limm): ...here.
 141         (aarch64_ins_inv_limm): New function.
 142         (aarch64_ins_sve_aimm): Likewise.
 143         (aarch64_ins_sve_asimm): Likewise.
 144         (aarch64_ins_sve_limm_mov): Likewise.
 145         (aarch64_ins_sve_shlimm): Likewise.
 146         (aarch64_ins_sve_shrimm): Likewise.
 147         * aarch64-asm-2.c: Regenerate.
 148         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 149         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 150         * aarch64-dis.c (decode_limm): New function, split out from...
 151         (aarch64_ext_limm): ...here.
 152         (aarch64_ext_inv_limm): New function.
 153         (decode_sve_aimm): Likewise.
 154         (aarch64_ext_sve_aimm): Likewise.
 155         (aarch64_ext_sve_asimm): Likewise.
 156         (aarch64_ext_sve_limm_mov): Likewise.
 157         (aarch64_top_bit): Likewise.
 158         (aarch64_ext_sve_shlimm): Likewise.
 159         (aarch64_ext_sve_shrimm): Likewise.
 160         * aarch64-dis-2.c: Regenerate.
 161
 162 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 163
 164         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 165         operands.
 166         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 167         the AARCH64_MOD_MUL_VL entry.
 168         (value_aligned_p): Cope with non-power-of-two alignments.
 169         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 170         (print_immediate_offset_address): Likewise.
 171         (aarch64_print_operand): Likewise.
 172         * aarch64-opc-2.c: Regenerate.
 173         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 174         (ins_sve_addr_ri_s9xvl): New inserters.
 175         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 176         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 177         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 178         * aarch64-asm-2.c: Regenerate.
 179         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 180         (ext_sve_addr_ri_s9xvl): New extractors.
 181         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 182         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 183         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 184         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 185         * aarch64-dis-2.c: Regenerate.
 186
 187 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 188
 189         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 190         address operands.
 191         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 192         (FLD_SVE_xs_22): New aarch64_field_kinds.
 193         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 194         (get_operand_specific_data): New function.
 195         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 196         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 197         (operand_general_constraint_met_p): Handle the new SVE address
 198         operands.
 199         (sve_reg): New array.
 200         (get_addr_sve_reg_name): New function.
 201         (aarch64_print_operand): Handle the new SVE address operands.
 202         * aarch64-opc-2.c: Regenerate.
 203         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 204         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 205         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 206         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 207         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 208         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 209         (aarch64_ins_sve_addr_zi_u5): Likewise.
 210         (aarch64_ins_sve_addr_zz): Likewise.
 211         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 212         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 213         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 214         * aarch64-asm-2.c: Regenerate.
 215         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 216         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 217         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 218         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 219         (aarch64_ext_sve_addr_ri_u6): Likewise.
 220         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 221         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 222         (aarch64_ext_sve_addr_zi_u5): Likewise.
 223         (aarch64_ext_sve_addr_zz): Likewise.
 224         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 225         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 226         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 227         * aarch64-dis-2.c: Regenerate.
 228
 229 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 230
 231         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 232         AARCH64_OPND_SVE_PATTERN_SCALED.
 233         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 234         * aarch64-opc.c (fields): Add a corresponding entry.
 235         (set_multiplier_out_of_range_error): New function.
 236         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 237         (operand_general_constraint_met_p): Handle
 238         AARCH64_OPND_SVE_PATTERN_SCALED.
 239         (print_register_offset_address): Use PRIi64 to print the
 240         shift amount.
 241         (aarch64_print_operand): Likewise.  Handle
 242         AARCH64_OPND_SVE_PATTERN_SCALED.
 243         * aarch64-opc-2.c: Regenerate.
 244         * aarch64-asm.h (ins_sve_scale): New inserter.
 245         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 246         * aarch64-asm-2.c: Regenerate.
 247         * aarch64-dis.h (ext_sve_scale): New inserter.
 248         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 249         * aarch64-dis-2.c: Regenerate.
 250
 251 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 252
 253         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 254         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 255         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 256         (FLD_SVE_prfop): Likewise.
 257         * aarch64-opc.c: Include libiberty.h.
 258         (aarch64_sve_pattern_array): New variable.
 259         (aarch64_sve_prfop_array): Likewise.
 260         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 261         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 262         AARCH64_OPND_SVE_PRFOP.
 263         * aarch64-asm-2.c: Regenerate.
 264         * aarch64-dis-2.c: Likewise.
 265         * aarch64-opc-2.c: Likewise.
 266
 267 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 268
 269         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 270         AARCH64_OPND_QLF_P_[ZM].
 271         (aarch64_print_operand): Print /z and /m where appropriate.
 272
 273 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 274
 275         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 276         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 277         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 278         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 279         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 280         * aarch64-opc.c (fields): Add corresponding entries here.
 281         (operand_general_constraint_met_p): Check that SVE register lists
 282         have the correct length.  Check the ranges of SVE index registers.
 283         Check for cases where p8-p15 are used in 3-bit predicate fields.
 284         (aarch64_print_operand): Handle the new SVE operands.
 285         * aarch64-opc-2.c: Regenerate.
 286         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 287         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 288         (aarch64_ins_sve_reglist): Likewise.
 289         * aarch64-asm-2.c: Regenerate.
 290         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 291         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 292         (aarch64_ext_sve_reglist): Likewise.
 293         * aarch64-dis-2.c: Regenerate.
 294
 295 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 296
 297         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 298         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 299         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 300         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 301         tied operands.
 302
 303 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 304
 305         * aarch64-opc.c (get_offset_int_reg_name): New function.
 306         (print_immediate_offset_address): Likewise.
 307         (print_register_offset_address): Take the base and offset
 308         registers as parameters.
 309         (aarch64_print_operand): Update caller accordingly.  Use
 310         print_immediate_offset_address.
 311
 312 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 313
 314         * aarch64-opc.c (BANK): New macro.
 315         (R32, R64): Take a register number as argument
 316         (int_reg): Use BANK.
 317
 318 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 319
 320         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 321         (aarch64_print_operand): Update accordingly.
 322
 323 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 324
 325         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 326         for FPIMM.
 327         * aarch64-asm.h (ins_fpimm): New inserter.
 328         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 329         * aarch64-asm-2.c: Regenerate.
 330         * aarch64-dis.h (ext_fpimm): New extractor.
 331         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 332         (aarch64_ext_fpimm): New function.
 333         * aarch64-dis-2.c: Regenerate.
 334
 335 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 336
 337         * aarch64-asm.c: Include libiberty.h.
 338         (insert_fields): New function.
 339         (aarch64_ins_imm): Use it.
 340         * aarch64-dis.c (extract_fields): New function.
 341         (aarch64_ext_imm): Use it.
 342
 343 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 344
 345         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 346         with an esize parameter.
 347         (operand_general_constraint_met_p): Update accordingly.
 348         Fix misindented code.
 349         * aarch64-asm.c (aarch64_ins_limm): Update call to
 350         aarch64_logical_immediate_p.
 351
 352 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 353
 354         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 355
 356 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 357
 358         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 359
 360 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 361
 362         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 363
 364 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 365
 366         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 367         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 368         xor3>: Delete mnemonics.
 369         <cp_abort>: Rename mnemonic from ...
 370         <cpabort>: ...to this.
 371         <setb>: Change to a X form instruction.
 372         <sync>: Change to 1 operand form.
 373         <copy>: Delete mnemonic.
 374         <copy_first>: Rename mnemonic from ...
 375         <copy>: ...to this.
 376         <paste, paste.>: Delete mnemonics.
 377         <paste_last>: Rename mnemonic from ...
 378         <paste.>: ...to this.
 379
 380 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 381
 382         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 383
 384 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 385
 386         * s390-mkopc.c (main): Support alternate arch strings.
 387
 388 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 389
 390         * s390-opc.txt: Fix kmctr instruction type.
 391
 392 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 393
 394         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 395         * i386-init.h: Regenerated.
 396
 397 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 398
 399         * opcodes/arc-dis.c (print_insn_arc): Changed.
 400
 401 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 402
 403         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 404         camellia_fl.
 405
 406 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 407
 408         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 409         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 410         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 411
 412 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 415         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 416         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 417         PREFIX_MOD_3_0FAE_REG_4.
 418         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 419         PREFIX_MOD_3_0FAE_REG_4.
 420         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 421         (cpu_flags): Add CpuPTWRITE.
 422         * i386-opc.h (CpuPTWRITE): New.
 423         (i386_cpu_flags): Add cpuptwrite.
 424         * i386-opc.tbl: Add ptwrite instruction.
 425         * i386-init.h: Regenerated.
 426         * i386-tbl.h: Likewise.
 427
 428 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 429
 430         * arc-dis.h: Wrap around in extern "C".
 431
 432 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 433
 434         * aarch64-tbl.h (V8_2_INSN): New macro.
 435         (aarch64_opcode_table): Use it.
 436
 437 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 438
 439         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 440         CORE_INSN, __FP_INSN and SIMD_INSN.
 441
 442 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 443
 444         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 445         (aarch64_opcode_table): Update uses accordingly.
 446
 447 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 448         Kwok Cheung Yeung  <kcy@codesourcery.com>
 449
 450         opcodes/
 451         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 452         'e_cmplwi' to 'e_cmpli' instead.
 453         (OPVUPRT, OPVUPRT_MASK): Define.
 454         (powerpc_opcodes): Add E200Z4 insns.
 455         (vle_opcodes): Add context save/restore insns.
 456
 457 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 458
 459         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 460         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 461         "j".
 462
 463 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 464
 465         * arc-nps400-tbl.h: Change block comments to GNU format.
 466         * arc-dis.c: Add new globals addrtypenames,
 467         addrtypenames_max, and addtypeunknown.
 468         (get_addrtype): New function.
 469         (print_insn_arc): Print colons and address types when
 470         required.
 471         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 472         define insert and extract functions for all address types.
 473         (arc_operands): Add operands for colon and all address
 474         types.
 475         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 476         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 477         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 478         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 479         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 480         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 481
 482 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 483
 484         * configure: Regenerated.
 485
 486 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 487
 488         * arc-dis.c (skipclass): New structure.
 489         (decodelist): New variable.
 490         (is_compatible_p): New function.
 491         (new_element): Likewise.
 492         (skip_class_p): Likewise.
 493         (find_format_from_table): Use skip_class_p function.
 494         (find_format): Decode first the extension instructions.
 495         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 496         e_flags.
 497         (parse_option): New function.
 498         (parse_disassembler_options): Likewise.
 499         (print_arc_disassembler_options): Likewise.
 500         (print_insn_arc): Use parse_disassembler_options function.  Proper
 501         select ARCv2 cpu variant.
 502         * disassemble.c (disassembler_usage): Add ARC disassembler
 503         options.
 504
 505 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 506
 507         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 508         annotation from the "nal" entry and reorder it beyond "bltzal".
 509
 510 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 511
 512         * sparc-opc.c (ldtxa): New macro.
 513         (sparc_opcodes): Use the macro defined above to add entries for
 514         the LDTXA instructions.
 515         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 516         instruction.
 517
 518 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 519
 520         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 521         and "jmpc".
 522
 523 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 524
 525         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 526         (movzb): Adjust to cover all permitted suffixes.
 527         (movzw): New.
 528         * i386-tbl.h: Re-generate.
 529
 530 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 533         (lgdt): Remove Tbyte from non-64-bit variant.
 534         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 535         xsaves64, xsavec64): Remove Disp16.
 536         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 537         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 538         64-bit variants.
 539         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 540         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 541         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 542         64-bit variants.
 543         * i386-tbl.h: Re-generate.
 544
 545 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 546
 547         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 548         * i386-tbl.h: Re-generate.
 549
 550 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 551
 552         * arm-dis.c (print_insn): Fix typo in comment.
 553
 554 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 555
 556         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 557         range of ldst_elemlist operands.
 558         (print_register_list): Use PRIi64 to print the index.
 559         (aarch64_print_operand): Likewise.
 560
 561 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 562
 563         * mcore-opc.h: Remove sentinal.
 564         * mcore-dis.c (print_insn_mcore): Adjust.
 565
 566 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 567
 568         * arc-opc.c: Correct description of availability of NPS400
 569         features.
 570
 571 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 572
 573         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 574         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 575         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 576         xor3>: New mnemonics.
 577         <setb>: Change to a VX form instruction.
 578         (insert_sh6): Add support for rldixor.
 579         (extract_sh6): Likewise.
 580
 581 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 582
 583         * arc-ext.h: Wrap in extern C.
 584
 585 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 586
 587         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 588         Use same method for determining instruction length on ARC700 and
 589         NPS-400.
 590         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 591         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 592         with the NPS400 subclass.
 593         * arc-opc.c: Likewise.
 594
 595 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 596
 597         * sparc-opc.c (rdasr): New macro.
 598         (wrasr): Likewise.
 599         (rdpr): Likewise.
 600         (wrpr): Likewise.
 601         (rdhpr): Likewise.
 602         (wrhpr): Likewise.
 603         (sparc_opcodes): Use the macros above to fix and expand the
 604         definition of read/write instructions from/to
 605         asr/privileged/hyperprivileged instructions.
 606         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 607         %hva_mask_nz.  Prefer softint_set and softint_clear over
 608         set_softint and clear_softint.
 609         (print_insn_sparc): Support %ver in Rd.
 610
 611 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 612
 613         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 614         architecture according to the hardware capabilities they require.
 615
 616 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 617
 618         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 619         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 620         bfd_mach_sparc_v9{c,d,e,v,m}.
 621         * sparc-opc.c (MASK_V9C): Define.
 622         (MASK_V9D): Likewise.
 623         (MASK_V9E): Likewise.
 624         (MASK_V9V): Likewise.
 625         (MASK_V9M): Likewise.
 626         (v6): Add MASK_V9{C,D,E,V,M}.
 627         (v6notlet): Likewise.
 628         (v7): Likewise.
 629         (v8): Likewise.
 630         (v9): Likewise.
 631         (v9andleon): Likewise.
 632         (v9a): Likewise.
 633         (v9b): Likewise.
 634         (v9c): Define.
 635         (v9d): Likewise.
 636         (v9e): Likewise.
 637         (v9v): Likewise.
 638         (v9m): Likewise.
 639         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 640
 641 2016-06-15  Nick Clifton  <nickc@redhat.com>
 642
 643         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 644         constants to match expected behaviour.
 645         (nds32_parse_opcode): Likewise.  Also for whitespace.
 646
 647 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 648
 649         * arc-opc.c (extract_rhv1): Extract value from insn.
 650
 651 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 652
 653         * arc-nps400-tbl.h: Add ldbit instruction.
 654         * arc-opc.c: Add flag classes required for ldbit.
 655
 656 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 657
 658         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 659         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 660         support the above instructions.
 661
 662 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 663
 664         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 665         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 666         csma, cbba, zncv, and hofs.
 667         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 668         support the above instructions.
 669
 670 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 671
 672         * arc-nps400-tbl.h: Add andab and orab instructions.
 673
 674 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 675
 676         * arc-nps400-tbl.h: Add addl-like instructions.
 677
 678 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 679
 680         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 681
 682 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 683
 684         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 685         instructions.
 686
 687 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 688
 689         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 690         variable.
 691         (init_disasm): Handle new command line option "insnlength".
 692         (print_s390_disassembler_options): Mention new option in help
 693         output.
 694         (print_insn_s390): Use the encoded insn length when dumping
 695         unknown instructions.
 696
 697 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 698
 699         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 700          to the address and set as symbol address for LDS/ STS immediate operands.
 701
 702 2016-06-07  Alan Modra  <amodra@gmail.com>
 703
 704         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 705         cpu for "vle" to e500.
 706         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 707         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 708         (PPCNONE): Delete, substitute throughout.
 709         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 710         except for major opcode 4 and 31.
 711         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 712
 713 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 714
 715         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 716         ARM_EXT_RAS in relevant entries.
 717
 718 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 719
 720         PR binutils/20196
 721         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 722         opcodes for E6500.
 723
 724 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 725
 726         PR binutis/18386
 727         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 728         (indir_v_mode): New.
 729         Add comments for '&'.
 730         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 731         (putop): Handle '&'.
 732         (intel_operand_size): Handle indir_v_mode.
 733         (OP_E_register): Likewise.
 734         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 735         64-bit indirect call/jmp for AMD64.
 736         * i386-tbl.h: Regenerated
 737
 738 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 739
 740         * arc-dis.c (struct arc_operand_iterator): New structure.
 741         (find_format_from_table): All the old content from find_format,
 742         with some minor adjustments, and parameter renaming.
 743         (find_format_long_instructions): New function.
 744         (find_format): Rewritten.
 745         (arc_insn_length): Add LSB parameter.
 746         (extract_operand_value): New function.
 747         (operand_iterator_next): New function.
 748         (print_insn_arc): Use new functions to find opcode, and iterator
 749         over operands.
 750         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 751         (extract_nps_3bit_dst_short): New function.
 752         (insert_nps_3bit_src2_short): New function.
 753         (extract_nps_3bit_src2_short): New function.
 754         (insert_nps_bitop1_size): New function.
 755         (extract_nps_bitop1_size): New function.
 756         (insert_nps_bitop2_size): New function.
 757         (extract_nps_bitop2_size): New function.
 758         (insert_nps_bitop_mod4_msb): New function.
 759         (extract_nps_bitop_mod4_msb): New function.
 760         (insert_nps_bitop_mod4_lsb): New function.
 761         (extract_nps_bitop_mod4_lsb): New function.
 762         (insert_nps_bitop_dst_pos3_pos4): New function.
 763         (extract_nps_bitop_dst_pos3_pos4): New function.
 764         (insert_nps_bitop_ins_ext): New function.
 765         (extract_nps_bitop_ins_ext): New function.
 766         (arc_operands): Add new operands.
 767         (arc_long_opcodes): New global array.
 768         (arc_num_long_opcodes): New global.
 769         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 770
 771 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 772
 773         * nds32-asm.h: Add extern "C".
 774         * sh-opc.h: Likewise.
 775
 776 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 777
 778         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 779         0,b,limm to the rflt instruction.
 780
 781 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 782
 783         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 784         constant.
 785
 786 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 787
 788         PR gas/20145
 789         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 790         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 791         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 792         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 793         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 794         * i386-init.h: Regenerated.
 795
 796 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 797
 798         PR gas/20145
 799         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 800         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 801         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 802         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 803         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 804         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 805         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 806         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 807         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 808         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 809         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 810         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 811         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 812         CpuRegMask for AVX512.
 813         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 814         and CpuRegMask.
 815         (set_bitfield_from_cpu_flag_init): New function.
 816         (set_bitfield): Remove const on f.  Call
 817         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 818         * i386-opc.h (CpuRegMMX): New.
 819         (CpuRegXMM): Likewise.
 820         (CpuRegYMM): Likewise.
 821         (CpuRegZMM): Likewise.
 822         (CpuRegMask): Likewise.
 823         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 824         and cpuregmask.
 825         * i386-init.h: Regenerated.
 826         * i386-tbl.h: Likewise.
 827
 828 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 829
 830         PR gas/20154
 831         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 832         (opcode_modifiers): Add AMD64 and Intel64.
 833         (main): Properly verify CpuMax.
 834         * i386-opc.h (CpuAMD64): Removed.
 835         (CpuIntel64): Likewise.
 836         (CpuMax): Set to CpuNo64.
 837         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 838         (AMD64): New.
 839         (Intel64): Likewise.
 840         (i386_opcode_modifier): Add amd64 and intel64.
 841         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 842         on call and jmp.
 843         * i386-init.h: Regenerated.
 844         * i386-tbl.h: Likewise.
 845
 846 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 847
 848         PR gas/20154
 849         * i386-gen.c (main): Fail if CpuMax is incorrect.
 850         * i386-opc.h (CpuMax): Set to CpuIntel64.
 851         * i386-tbl.h: Regenerated.
 852
 853 2016-05-27  Nick Clifton  <nickc@redhat.com>
 854
 855         PR target/20150
 856         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 857         (msp430dis_opcode_unsigned): New function.
 858         (msp430dis_opcode_signed): New function.
 859         (msp430_singleoperand): Use the new opcode reading functions.
 860         Only disassenmble bytes if they were successfully read.
 861         (msp430_doubleoperand): Likewise.
 862         (msp430_branchinstr): Likewise.
 863         (msp430x_callx_instr): Likewise.
 864         (print_insn_msp430): Check that it is safe to read bytes before
 865         attempting disassembly.  Use the new opcode reading functions.
 866
 867 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 868
 869         * ppc-opc.c (CY): New define.  Document it.
 870         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 871
 872 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 873
 874         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 875         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 876         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 877         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 878         CPU_ANY_AVX_FLAGS.
 879         * i386-init.h: Regenerated.
 880
 881 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 882
 883         PR gas/20141
 884         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 885         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 886         * i386-init.h: Regenerated.
 887
 888 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 889
 890         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 891         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 892         * i386-init.h: Regenerated.
 893
 894 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 895
 896         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 897         information.
 898         (print_insn_arc): Set insn_type information.
 899         * arc-opc.c (C_CC): Add F_CLASS_COND.
 900         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 901         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 902         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 903         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 904         (brne, brne_s, jeq_s, jne_s): Likewise.
 905
 906 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 907
 908         * arc-tbl.h (neg): New instruction variant.
 909
 910 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 911
 912         * arc-dis.c (find_format, find_format, get_auxreg)
 913         (print_insn_arc): Changed.
 914         * arc-ext.h (INSERT_XOP): Likewise.
 915
 916 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 917
 918         * tic54x-dis.c (sprint_mmr): Adjust.
 919         * tic54x-opc.c: Likewise.
 920
 921 2016-05-19  Alan Modra  <amodra@gmail.com>
 922
 923         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 924
 925 2016-05-19  Alan Modra  <amodra@gmail.com>
 926
 927         * ppc-opc.c: Formatting.
 928         (NSISIGNOPT): Define.
 929         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 930
 931 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 932
 933         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 934         replacing references to `micromips_ase' throughout.
 935         (_print_insn_mips): Don't use file-level microMIPS annotation to
 936         determine the disassembly mode with the symbol table.
 937
 938 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 939
 940         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 941
 942 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 943
 944         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 945         mips64r6.
 946         * mips-opc.c (D34): New macro.
 947         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 948
 949 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 950
 951         * i386-dis.c (prefix_table): Add RDPID instruction.
 952         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 953         (cpu_flags): Add RDPID bitfield.
 954         * i386-opc.h (enum): Add RDPID element.
 955         (i386_cpu_flags): Add RDPID field.
 956         * i386-opc.tbl: Add RDPID instruction.
 957         * i386-init.h: Regenerate.
 958         * i386-tbl.h: Regenerate.
 959
 960 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 961
 962         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 963         branch type of a symbol.
 964         (print_insn): Likewise.
 965
 966 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 967
 968         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 969         Mainline Security Extensions instructions.
 970         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 971         Extensions instructions.
 972         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 973         instructions.
 974         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 975         special registers.
 976
 977 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 978
 979         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 980
 981 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 982
 983         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 984         (arcExtMap_genOpcode): Likewise.
 985         * arc-opc.c (arg_32bit_rc): Define new variable.
 986         (arg_32bit_u6): Likewise.
 987         (arg_32bit_limm): Likewise.
 988
 989 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 990
 991         * aarch64-gen.c (VERIFIER): Define.
 992         * aarch64-opc.c (VERIFIER): Define.
 993         (verify_ldpsw): Use static linkage.
 994         * aarch64-opc.h (verify_ldpsw): Remove.
 995         * aarch64-tbl.h: Use VERIFIER for verifiers.
 996
 997 2016-04-28  Nick Clifton  <nickc@redhat.com>
 998
 999         PR target/19722
1000         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1001         * aarch64-opc.c (verify_ldpsw): New function.
1002         * aarch64-opc.h (verify_ldpsw): New prototype.
1003         * aarch64-tbl.h: Add initialiser for verifier field.
1004         (LDPSW): Set verifier to verify_ldpsw.
1005
1006 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1007
1008         PR binutils/19983
1009         PR binutils/19984
1010         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1011         smaller than address size.
1012
1013 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1014
1015         * alpha-dis.c: Regenerate.
1016         * crx-dis.c: Likewise.
1017         * disassemble.c: Likewise.
1018         * epiphany-opc.c: Likewise.
1019         * fr30-opc.c: Likewise.
1020         * frv-opc.c: Likewise.
1021         * ip2k-opc.c: Likewise.
1022         * iq2000-opc.c: Likewise.
1023         * lm32-opc.c: Likewise.
1024         * lm32-opinst.c: Likewise.
1025         * m32c-opc.c: Likewise.
1026         * m32r-opc.c: Likewise.
1027         * m32r-opinst.c: Likewise.
1028         * mep-opc.c: Likewise.
1029         * mt-opc.c: Likewise.
1030         * or1k-opc.c: Likewise.
1031         * or1k-opinst.c: Likewise.
1032         * tic80-opc.c: Likewise.
1033         * xc16x-opc.c: Likewise.
1034         * xstormy16-opc.c: Likewise.
1035
1036 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1037
1038         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1039         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1040         calcsd, and calcxd instructions.
1041         * arc-opc.c (insert_nps_bitop_size): Delete.
1042         (extract_nps_bitop_size): Delete.
1043         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1044         (extract_nps_qcmp_m3): Define.
1045         (extract_nps_qcmp_m2): Define.
1046         (extract_nps_qcmp_m1): Define.
1047         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1048         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1049         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1050         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1051         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1052         NPS_QCMP_M3.
1053
1054 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1055
1056         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1057
1058 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1059
1060         * Makefile.in: Regenerated with automake 1.11.6.
1061         * aclocal.m4: Likewise.
1062
1063 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1064
1065         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1066         instructions.
1067         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1068         (extract_nps_cmem_uimm16): New function.
1069         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1070
1071 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1072
1073         * arc-dis.c (arc_insn_length): New function.
1074         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1075         (find_format): Change insnLen parameter to unsigned.
1076
1077 2016-04-13  Nick Clifton  <nickc@redhat.com>
1078
1079         PR target/19937
1080         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1081         the LD.B and LD.BU instructions.
1082
1083 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1084
1085         * arc-dis.c (find_format): Check for extension flags.
1086         (print_flags): New function.
1087         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1088         .extAuxRegister.
1089         * arc-ext.c (arcExtMap_coreRegName): Use
1090         LAST_EXTENSION_CORE_REGISTER.
1091         (arcExtMap_coreReadWrite): Likewise.
1092         (dump_ARC_extmap): Update printing.
1093         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1094         (arc_aux_regs): Add cpu field.
1095         * arc-regs.h: Add cpu field, lower case name aux registers.
1096
1097 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1098
1099         * arc-tbl.h: Add rtsc, sleep with no arguments.
1100
1101 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1102
1103         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1104         Initialize.
1105         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1106         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1107         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1108         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1109         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1110         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1111         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1112         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1113         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1114         (arc_opcode arc_opcodes): Null terminate the array.
1115         (arc_num_opcodes): Remove.
1116         * arc-ext.h (INSERT_XOP): Define.
1117         (extInstruction_t): Likewise.
1118         (arcExtMap_instName): Delete.
1119         (arcExtMap_insn): New function.
1120         (arcExtMap_genOpcode): Likewise.
1121         * arc-ext.c (ExtInstruction): Remove.
1122         (create_map): Zero initialize instruction fields.
1123         (arcExtMap_instName): Remove.
1124         (arcExtMap_insn): New function.
1125         (dump_ARC_extmap): More info while debuging.
1126         (arcExtMap_genOpcode): New function.
1127         * arc-dis.c (find_format): New function.
1128         (print_insn_arc): Use find_format.
1129         (arc_get_disassembler): Enable dump_ARC_extmap only when
1130         debugging.
1131
1132 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1133
1134         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1135         instruction bits out.
1136
1137 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1138
1139         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1140         * arc-opc.c (arc_flag_operands): Add new flags.
1141         (arc_flag_classes): Add new classes.
1142
1143 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1144
1145         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1146
1147 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1148
1149         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1150         encode1, rflt, crc16, and crc32 instructions.
1151         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1152         (arc_flag_classes): Add C_NPS_R.
1153         (insert_nps_bitop_size_2b): New function.
1154         (extract_nps_bitop_size_2b): Likewise.
1155         (insert_nps_bitop_uimm8): Likewise.
1156         (extract_nps_bitop_uimm8): Likewise.
1157         (arc_operands): Add new operand entries.
1158
1159 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1160
1161         * arc-regs.h: Add a new subclass field.  Add double assist
1162         accumulator register values.
1163         * arc-tbl.h: Use DPA subclass to mark the double assist
1164         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1165         * arc-opc.c (RSP): Define instead of SP.
1166         (arc_aux_regs): Add the subclass field.
1167
1168 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1169
1170         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1171
1172 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1173
1174         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1175         NPS_R_SRC1.
1176
1177 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1178
1179         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1180         issues.  No functional changes.
1181
1182 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1183
1184         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1185         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1186         (RTT): Remove duplicate.
1187         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1188         (PCT_CONFIG*): Remove.
1189         (D1L, D1H, D2H, D2L): Define.
1190
1191 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1192
1193         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1194
1195 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1196
1197         * arc-tbl.h (invld07): Remove.
1198         * arc-ext-tbl.h: New file.
1199         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1200         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1201
1202 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1203
1204         Fix -Wstack-usage warnings.
1205         * aarch64-dis.c (print_operands): Substitute size.
1206         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1207
1208 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1209
1210         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1211         to get a proper diagnostic when an invalid ASR register is used.
1212
1213 2016-03-22  Nick Clifton  <nickc@redhat.com>
1214
1215         * configure: Regenerate.
1216
1217 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1218
1219         * arc-nps400-tbl.h: New file.
1220         * arc-opc.c: Add top level comment.
1221         (insert_nps_3bit_dst): New function.
1222         (extract_nps_3bit_dst): New function.
1223         (insert_nps_3bit_src2): New function.
1224         (extract_nps_3bit_src2): New function.
1225         (insert_nps_bitop_size): New function.
1226         (extract_nps_bitop_size): New function.
1227         (arc_flag_operands): Add nps400 entries.
1228         (arc_flag_classes): Add nps400 entries.
1229         (arc_operands): Add nps400 entries.
1230         (arc_opcodes): Add nps400 include.
1231
1232 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1233
1234         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1235         the new class enum values.
1236
1237 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1238
1239         * arc-dis.c (print_insn_arc): Handle nps400.
1240
1241 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1242
1243         * arc-opc.c (BASE): Delete.
1244
1245 2016-03-18  Nick Clifton  <nickc@redhat.com>
1246
1247         PR target/19721
1248         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1249         of MOV insn that aliases an ORR insn.
1250
1251 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1252
1253         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1254
1255 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1256
1257         * mcore-opc.h: Add const qualifiers.
1258         * microblaze-opc.h (struct op_code_struct): Likewise.
1259         * sh-opc.h: Likewise.
1260         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1261         (tic4x_print_op): Likewise.
1262
1263 2016-03-02  Alan Modra  <amodra@gmail.com>
1264
1265         * or1k-desc.h: Regenerate.
1266         * fr30-ibld.c: Regenerate.
1267         * rl78-decode.c: Regenerate.
1268
1269 2016-03-01  Nick Clifton  <nickc@redhat.com>
1270
1271         PR target/19747
1272         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1273
1274 2016-02-24  Renlin Li  <renlin.li@arm.com>
1275
1276         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1277         (print_insn_coprocessor): Support fp16 instructions.
1278
1279 2016-02-24  Renlin Li  <renlin.li@arm.com>
1280
1281         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1282         vminnm, vrint(mpna).
1283
1284 2016-02-24  Renlin Li  <renlin.li@arm.com>
1285
1286         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1287         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1288
1289 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1290
1291         * i386-dis.c (print_insn): Parenthesize expression to prevent
1292         truncated addresses.
1293         (OP_J): Likewise.
1294
1295 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1296             Janek van Oirschot  <jvanoirs@synopsys.com>
1297
1298         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1299         variable.
1300
1301 2016-02-04  Nick Clifton  <nickc@redhat.com>
1302
1303         PR target/19561
1304         * msp430-dis.c (print_insn_msp430): Add a special case for
1305         decoding an RRC instruction with the ZC bit set in the extension
1306         word.
1307
1308 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1309
1310         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1311         * epiphany-ibld.c: Regenerate.
1312         * fr30-ibld.c: Regenerate.
1313         * frv-ibld.c: Regenerate.
1314         * ip2k-ibld.c: Regenerate.
1315         * iq2000-ibld.c: Regenerate.
1316         * lm32-ibld.c: Regenerate.
1317         * m32c-ibld.c: Regenerate.
1318         * m32r-ibld.c: Regenerate.
1319         * mep-ibld.c: Regenerate.
1320         * mt-ibld.c: Regenerate.
1321         * or1k-ibld.c: Regenerate.
1322         * xc16x-ibld.c: Regenerate.
1323         * xstormy16-ibld.c: Regenerate.
1324
1325 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1326
1327         * epiphany-dis.c: Regenerated from latest cpu files.
1328
1329 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1330
1331         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1332         test bit.
1333
1334 2016-01-25  Renlin Li  <renlin.li@arm.com>
1335
1336         * arm-dis.c (mapping_symbol_for_insn): New function.
1337         (find_ifthen_state): Call mapping_symbol_for_insn().
1338
1339 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1340
1341         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1342         of MSR UAO immediate operand.
1343
1344 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1345
1346         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1347         instruction support.
1348
1349 2016-01-17  Alan Modra  <amodra@gmail.com>
1350
1351         * configure: Regenerate.
1352
1353 2016-01-14  Nick Clifton  <nickc@redhat.com>
1354
1355         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1356         instructions that can support stack pointer operations.
1357         * rl78-decode.c: Regenerate.
1358         * rl78-dis.c: Fix display of stack pointer in MOVW based
1359         instructions.
1360
1361 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1362
1363         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1364         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1365         erxtatus_el1 and erxaddr_el1.
1366
1367 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1368
1369         * arm-dis.c (arm_opcodes): Add "esb".
1370         (thumb_opcodes): Likewise.
1371
1372 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1373
1374         * ppc-opc.c <xscmpnedp>: Delete.
1375         <xvcmpnedp>: Likewise.
1376         <xvcmpnedp.>: Likewise.
1377         <xvcmpnesp>: Likewise.
1378         <xvcmpnesp.>: Likewise.
1379
1380 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1381
1382         PR gas/13050
1383         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1384         addition to ISA_A.
1385
1386 2016-01-01  Alan Modra  <amodra@gmail.com>
1387
1388         Update year range in copyright notice of all files.
1389
1390 For older changes see ChangeLog-2015
1391 \f
1392 Copyright (C) 2016 Free Software Foundation, Inc.
1393
1394 Copying and distribution of this file, with or without modification,
1395 are permitted in any medium without royalty provided the copyright
1396 notice and this notice are preserved.
1397
1398 Local Variables:
1399 mode: change-log
1400 left-margin: 8
1401 fill-column: 74
1402 version-control: never
1403 End: