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MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
4 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
5 opcode).
6
7 2016-12-20 Andrew Waterman <andrew@sifive.com>
8
9 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
10 "*.aqrl".
11
12 2016-12-20 Andrew Waterman <andrew@sifive.com>
13
14 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
15 INSN_ALIAS.
16
17 2016-12-20 Andrew Waterman <andrew@sifive.com>
18
19 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
20 format.
21
22 2016-12-20 Andrew Waterman <andrew@sifive.com>
23
24 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
25 XLEN when none is provided.
26
27 2016-12-20 Andrew Waterman <andrew@sifive.com>
28
29 * riscv-opc.c: Formatting fixes.
30
31 2016-12-20 Alan Modra <amodra@gmail.com>
32
33 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
34 * Makefile.in: Regenerate.
35 * po/POTFILES.in: Regenerate.
36
37 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
38
39 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
40 Only examine ELF file structures here.
41
42 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
43
44 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
45 `bfd_mips_elf_get_abiflags' here.
46
47 2016-12-16 Nick Clifton <nickc@redhat.com>
48
49 * arm-dis.c (print_insn_thumb32): Fix compile time warning
50 computing value_in_comment.
51
52 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
53
54 * mips-dis.c (mips_convert_abiflags_ases): New function.
55 (set_default_mips_dis_options): Also infer ASE flags from ELF
56 file structures.
57
58 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
59
60 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
61 header flag interpretation code.
62
63 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
64
65 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
66 `pinfo2' with SP-relative "sd" entries.
67
68 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
69
70 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
71 compact jumps.
72
73 2016-12-13 Renlin Li <renlin.li@arm.com>
74
75 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
76 qualifier.
77 (operand_general_constraint_met_p): Remove case for CP_REG.
78 (aarch64_print_operand): Print CRn, CRm operand using imm field.
79 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
80 (QL_SYSL): Likewise.
81 (aarch64_opcode_table): Change CRn, CRm operand class and type.
82 * aarch64-opc-2.c : Regenerate.
83 * aarch64-asm-2.c : Likewise.
84 * aarch64-dis-2.c : Likewise.
85
86 2016-12-12 Yao Qi <yao.qi@linaro.org>
87
88 * rx-dis.c: Include <setjmp.h>
89 (struct private): New.
90 (rx_get_byte): Check return value of read_memory_func, and
91 call memory_error_func and OPCODES_SIGLONGJMP on error.
92 (print_insn_rx): Call OPCODES_SIGSETJMP.
93
94 2016-12-12 Yao Qi <yao.qi@linaro.org>
95
96 * rl78-dis.c: Include <setjmp.h>.
97 (struct private): New.
98 (rl78_get_byte): Check return value of read_memory_func, and
99 call memory_error_func and OPCODES_SIGLONGJMP on error.
100 (print_insn_rl78_common): Call OPCODES_SIGJMP.
101
102 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
103
104 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
105
106 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
107
108 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
109 than UINT.
110
111 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
112
113 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
114 to separate `extend' and its uninterpreted argument output.
115 Separate hexadecimal halves of undecoded extended instructions
116 output.
117
118 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
119
120 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
121 indentation space across.
122
123 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
124
125 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
126 adjustment for PC-relative operations following MIPS16e compact
127 jumps or undefined RR/J(AL)R(C) encodings.
128
129 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
130
131 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
132 variable to `reglane_index'.
133
134 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
135
136 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
137
138 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
139
140 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
141
142 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
143
144 * mips16-opc.c (mips16_opcodes): Update comment naming structure
145 members.
146
147 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
148
149 * mips-dis.c (print_mips_disassembler_options): Reformat output.
150
151 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
152
153 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
154 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
155
156 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
157
158 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
159
160 2016-12-01 Nick Clifton <nickc@redhat.com>
161
162 PR binutils/20893
163 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
164 opcode designator.
165
166 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
167
168 * arc-opc.c (insert_ra_chk): New function.
169 (insert_rb_chk): Likewise.
170 (insert_rad): Update text error message.
171 (insert_rcd): Likewise.
172 (insert_rhv2): Likewise.
173 (insert_r0): Likewise.
174 (insert_r1): Likewise.
175 (insert_r2): Likewise.
176 (insert_r3): Likewise.
177 (insert_sp): Likewise.
178 (insert_gp): Likewise.
179 (insert_pcl): Likewise.
180 (insert_blink): Likewise.
181 (insert_ilink1): Likewise.
182 (insert_ilink2): Likewise.
183 (insert_ras): Likewise.
184 (insert_rbs): Likewise.
185 (insert_rcs): Likewise.
186 (insert_simm3s): Likewise.
187 (insert_rrange): Likewise.
188 (insert_fpel): Likewise.
189 (insert_blinkel): Likewise.
190 (insert_pcel): Likewise.
191 (insert_nps_3bit_dst): Likewise.
192 (insert_nps_3bit_dst_short): Likewise.
193 (insert_nps_3bit_src2_short): Likewise.
194 (insert_nps_bitop_size_2b): Likewise.
195 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
196 (RA_CHK): Define.
197 (RB): Adjust.
198 (RB_CHK): Define.
199 (RC): Adjust.
200 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
201 * arc-tbl.h (div, divu): All instructions are DIVREM class.
202 Change first insn argument to check for LP_COUNT usage.
203 (rem): Likewise.
204 (ld, ldd): All instructions are LOAD class. Change first insn
205 argument to check for LP_COUNT usage.
206 (st, std): All instructions are STORE class.
207 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
208 Change first insn argument to check for LP_COUNT usage.
209 (mov): All instructions are MOVE class. Change first insn
210 argument to check for LP_COUNT usage.
211
212 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
213
214 * arc-dis.c (is_compatible_p): Remove function.
215 (skip_this_opcode): Don't add any decoding class to decode list.
216 Remove warning.
217 (find_format_from_table): Go through all opcodes, and warn if we
218 use a guessed mnemonic.
219
220 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
221 Amit Pawar <amit.pawar@amd.com>
222
223 PR binutils/20637
224 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
225 instructions.
226
227 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
228
229 * configure: Regenerate.
230
231 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
232
233 * sparc-opc.c (HWS_V8): Definition moved from
234 gas/config/tc-sparc.c.
235 (HWS_V9): Likewise.
236 (HWS_VA): Likewise.
237 (HWS_VB): Likewise.
238 (HWS_VC): Likewise.
239 (HWS_VD): Likewise.
240 (HWS_VE): Likewise.
241 (HWS_VV): Likewise.
242 (HWS_VM): Likewise.
243 (HWS2_VM): Likewise.
244 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
245 existing entries.
246
247 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
248
249 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
250 instructions.
251
252 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
253
254 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
255 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
256 (aarch64_opcode_table): Add fcmla and fcadd.
257 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
258 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
259 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
260 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
261 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
262 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
263 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
264 (operand_general_constraint_met_p): Rotate and index range check.
265 (aarch64_print_operand): Handle rotate operand.
266 * aarch64-asm-2.c: Regenerate.
267 * aarch64-dis-2.c: Likewise.
268 * aarch64-opc-2.c: Likewise.
269
270 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
271
272 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
273 * aarch64-asm-2.c: Regenerate.
274 * aarch64-dis-2.c: Regenerate.
275 * aarch64-opc-2.c: Regenerate.
276
277 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
278
279 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
280 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
281 * aarch64-asm-2.c: Regenerate.
282 * aarch64-dis-2.c: Regenerate.
283 * aarch64-opc-2.c: Regenerate.
284
285 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
286
287 * aarch64-tbl.h (QL_X1NIL): New.
288 (arch64_opcode_table): Add ldraa, ldrab.
289 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
290 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
291 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
292 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
293 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
294 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
295 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
296 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
297 (aarch64_print_operand): Likewise.
298 * aarch64-asm-2.c: Regenerate.
299 * aarch64-dis-2.c: Regenerate.
300 * aarch64-opc-2.c: Regenerate.
301
302 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
303
304 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
305 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
306 * aarch64-asm-2.c: Regenerate.
307 * aarch64-dis-2.c: Regenerate.
308 * aarch64-opc-2.c: Regenerate.
309
310 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
311
312 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
313 (AARCH64_OPERANDS): Add Rm_SP.
314 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
315 * aarch64-asm-2.c: Regenerate.
316 * aarch64-dis-2.c: Regenerate.
317 * aarch64-opc-2.c: Regenerate.
318
319 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
320
321 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
322 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
323 autdzb, xpaci, xpacd.
324 * aarch64-asm-2.c: Regenerate.
325 * aarch64-dis-2.c: Regenerate.
326 * aarch64-opc-2.c: Regenerate.
327
328 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
329
330 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
331 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
332 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
333 (aarch64_sys_reg_supported_p): Add feature test for new registers.
334
335 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
336
337 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
338 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
339 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
340 autibsp.
341 * aarch64-asm-2.c: Regenerate.
342 * aarch64-dis-2.c: Regenerate.
343
344 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
345
346 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
347
348 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
349
350 PR binutils/20799
351 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
352 * i386-dis.c (EdqwS): Removed.
353 (dqw_swap_mode): Likewise.
354 (intel_operand_size): Don't check dqw_swap_mode.
355 (OP_E_register): Likewise.
356 (OP_E_memory): Likewise.
357 (OP_G): Likewise.
358 (OP_EX): Likewise.
359 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
360 * i386-tbl.h: Regerated.
361
362 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
363
364 * i386-opc.tbl: Merge AVX512F vmovq.
365 * i386-tbl.h: Regerated.
366
367 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
368
369 PR binutils/20701
370 * i386-dis.c (THREE_BYTE_0F7A): Removed.
371 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
372 (three_byte_table): Remove THREE_BYTE_0F7A.
373
374 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
375
376 PR binutils/20775
377 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
378 (FGRPd9_4): Replace 1 with 2.
379 (FGRPd9_5): Replace 2 with 3.
380 (FGRPd9_6): Replace 3 with 4.
381 (FGRPd9_7): Replace 4 with 5.
382 (FGRPda_5): Replace 5 with 6.
383 (FGRPdb_4): Replace 6 with 7.
384 (FGRPde_3): Replace 7 with 8.
385 (FGRPdf_4): Replace 8 with 9.
386 (fgrps): Add an entry for Bad_Opcode.
387
388 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
389
390 * arc-opc.c (arc_flag_operands): Add F_DI14.
391 (arc_flag_classes): Add C_DI14.
392 * arc-nps400-tbl.h: Add new exc instructions.
393
394 2016-11-03 Graham Markall <graham.markall@embecosm.com>
395
396 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
397 major opcode 0xa.
398 * arc-nps-400-tbl.h: Add dcmac instruction.
399 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
400 (insert_nps_rbdouble_64): Added.
401 (extract_nps_rbdouble_64): Added.
402 (insert_nps_proto_size): Added.
403 (extract_nps_proto_size): Added.
404
405 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
406
407 * arc-dis.c (struct arc_operand_iterator): Remove all fields
408 relating to long instruction processing, add new limm field.
409 (OPCODE): Rename to...
410 (OPCODE_32BIT_INSN): ...this.
411 (OPCODE_AC): Delete.
412 (skip_this_opcode): Handle different instruction lengths, update
413 macro name.
414 (special_flag_p): Update parameter type.
415 (find_format_from_table): Update for more instruction lengths.
416 (find_format_long_instructions): Delete.
417 (find_format): Update for more instruction lengths.
418 (arc_insn_length): Likewise.
419 (extract_operand_value): Update for more instruction lengths.
420 (operand_iterator_next): Remove code relating to long
421 instructions.
422 (arc_opcode_to_insn_type): New function.
423 (print_insn_arc):Update for more instructions lengths.
424 * arc-ext.c (extInstruction_t): Change argument type.
425 * arc-ext.h (extInstruction_t): Change argument type.
426 * arc-fxi.h: Change type unsigned to unsigned long long
427 extensively throughout.
428 * arc-nps400-tbl.h: Add long instructions taken from
429 arc_long_opcodes table in arc-opc.c.
430 * arc-opc.c: Update parameter types on insert/extract handlers.
431 (arc_long_opcodes): Delete.
432 (arc_num_long_opcodes): Delete.
433 (arc_opcode_len): Update for more instruction lengths.
434
435 2016-11-03 Graham Markall <graham.markall@embecosm.com>
436
437 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
438
439 2016-11-03 Graham Markall <graham.markall@embecosm.com>
440
441 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
442 with arc_opcode_len.
443 (find_format_long_instructions): Likewise.
444 * arc-opc.c (arc_opcode_len): New function.
445
446 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
447
448 * arc-nps400-tbl.h: Fix some instruction masks.
449
450 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
451
452 * i386-dis.c (REG_82): Removed.
453 (X86_64_82_REG_0): Likewise.
454 (X86_64_82_REG_1): Likewise.
455 (X86_64_82_REG_2): Likewise.
456 (X86_64_82_REG_3): Likewise.
457 (X86_64_82_REG_4): Likewise.
458 (X86_64_82_REG_5): Likewise.
459 (X86_64_82_REG_6): Likewise.
460 (X86_64_82_REG_7): Likewise.
461 (X86_64_82): New.
462 (dis386): Use X86_64_82 instead of REG_82.
463 (reg_table): Remove REG_82.
464 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
465 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
466 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
467 X86_64_82_REG_7.
468
469 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
470
471 PR binutils/20754
472 * i386-dis.c (REG_82): New.
473 (X86_64_82_REG_0): Likewise.
474 (X86_64_82_REG_1): Likewise.
475 (X86_64_82_REG_2): Likewise.
476 (X86_64_82_REG_3): Likewise.
477 (X86_64_82_REG_4): Likewise.
478 (X86_64_82_REG_5): Likewise.
479 (X86_64_82_REG_6): Likewise.
480 (X86_64_82_REG_7): Likewise.
481 (dis386): Use REG_82.
482 (reg_table): Add REG_82.
483 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
484 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
485 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
486
487 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
488
489 * i386-dis.c (REG_82): Renamed to ...
490 (REG_83): This.
491 (dis386): Updated.
492 (reg_table): Likewise.
493
494 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
495
496 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
497 * i386-dis-evex.h (evex_table): Updated.
498 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
499 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
500 (cpu_flags): Add CpuAVX512_4VNNIW.
501 * i386-opc.h (enum): (AVX512_4VNNIW): New.
502 (i386_cpu_flags): Add cpuavx512_4vnniw.
503 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
504 * i386-init.h: Regenerate.
505 * i386-tbl.h: Ditto.
506
507 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
508
509 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
510 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
511 * i386-dis-evex.h (evex_table): Updated.
512 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
513 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
514 (cpu_flags): Add CpuAVX512_4FMAPS.
515 (opcode_modifiers): Add ImplicitQuadGroup modifier.
516 * i386-opc.h (AVX512_4FMAP): New.
517 (i386_cpu_flags): Add cpuavx512_4fmaps.
518 (ImplicitQuadGroup): New.
519 (i386_opcode_modifier): Add implicitquadgroup.
520 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
521 * i386-init.h: Regenerate.
522 * i386-tbl.h: Ditto.
523
524 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
525 Andrew Waterman <andrew@sifive.com>
526
527 Add support for RISC-V architecture.
528 * configure.ac: Add entry for bfd_riscv_arch.
529 * configure: Regenerate.
530 * disassemble.c (disassembler): Add support for riscv.
531 (disassembler_usage): Likewise.
532 * riscv-dis.c: New file.
533 * riscv-opc.c: New file.
534
535 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
536
537 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
538 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
539 (rm_table): Update the RM_0FAE_REG_7 entry.
540 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
541 (cpu_flags): Remove CpuPCOMMIT.
542 * i386-opc.h (CpuPCOMMIT): Removed.
543 (i386_cpu_flags): Remove cpupcommit.
544 * i386-opc.tbl: Remove pcommit.
545 * i386-init.h: Regenerated.
546 * i386-tbl.h: Likewise.
547
548 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
549
550 PR binutis/20705
551 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
552 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
553 32-bit mode. Don't check vex.register_specifier in 32-bit
554 mode.
555 (OP_VEX): Check for invalid mask registers.
556
557 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
558
559 PR binutis/20699
560 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
561 sizeflag.
562
563 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
564
565 PR binutis/20704
566 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
567
568 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
569
570 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
571 local variable to `index_regno'.
572
573 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
574
575 * arc-tbl.h: Removed any "inv.+" instructions from the table.
576
577 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
578
579 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
580 usage on ISA basis.
581
582 2016-10-11 Jiong Wang <jiong.wang@arm.com>
583
584 PR target/20666
585 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
586
587 2016-10-07 Jiong Wang <jiong.wang@arm.com>
588
589 PR target/20667
590 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
591 available.
592
593 2016-10-07 Alan Modra <amodra@gmail.com>
594
595 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
596
597 2016-10-06 Alan Modra <amodra@gmail.com>
598
599 * aarch64-opc.c: Spell fall through comments consistently.
600 * i386-dis.c: Likewise.
601 * aarch64-dis.c: Add missing fall through comments.
602 * aarch64-opc.c: Likewise.
603 * arc-dis.c: Likewise.
604 * arm-dis.c: Likewise.
605 * i386-dis.c: Likewise.
606 * m68k-dis.c: Likewise.
607 * mep-asm.c: Likewise.
608 * ns32k-dis.c: Likewise.
609 * sh-dis.c: Likewise.
610 * tic4x-dis.c: Likewise.
611 * tic6x-dis.c: Likewise.
612 * vax-dis.c: Likewise.
613
614 2016-10-06 Alan Modra <amodra@gmail.com>
615
616 * arc-ext.c (create_map): Add missing break.
617 * msp430-decode.opc (encode_as): Likewise.
618 * msp430-decode.c: Regenerate.
619
620 2016-10-06 Alan Modra <amodra@gmail.com>
621
622 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
623 * crx-dis.c (print_insn_crx): Likewise.
624
625 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
626
627 PR binutils/20657
628 * i386-dis.c (putop): Don't assign alt twice.
629
630 2016-09-29 Jiong Wang <jiong.wang@arm.com>
631
632 PR target/20553
633 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
634
635 2016-09-29 Alan Modra <amodra@gmail.com>
636
637 * ppc-opc.c (L): Make compulsory.
638 (LOPT): New, optional form of L.
639 (HTM_R): Define as LOPT.
640 (L0, L1): Delete.
641 (L32OPT): New, optional for 32-bit L.
642 (L2OPT): New, 2-bit L for dcbf.
643 (SVC_LEC): Update.
644 (L2): Define.
645 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
646 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
647 <dcbf>: Use L2OPT.
648 <tlbiel, tlbie>: Use LOPT.
649 <wclr, wclrall>: Use L2.
650
651 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
652
653 * Makefile.in: Regenerate.
654 * configure: Likewise.
655
656 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
657
658 * arc-ext-tbl.h (EXTINSN2OPF): Define.
659 (EXTINSN2OP): Use EXTINSN2OPF.
660 (bspeekm, bspop, modapp): New extension instructions.
661 * arc-opc.c (F_DNZ_ND): Define.
662 (F_DNZ_D): Likewise.
663 (F_SIZEB1): Changed.
664 (C_DNZ_D): Define.
665 (C_HARD): Changed.
666 * arc-tbl.h (dbnz): New instruction.
667 (prealloc): Allow it for ARC EM.
668 (xbfu): Likewise.
669
670 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
671
672 * aarch64-opc.c (print_immediate_offset_address): Print spaces
673 after commas in addresses.
674 (aarch64_print_operand): Likewise.
675
676 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
677
678 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
679 rather than "should be" or "expected to be" in error messages.
680
681 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
682
683 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
684 (print_mnemonic_name): ...here.
685 (print_comment): New function.
686 (print_aarch64_insn): Call it.
687 * aarch64-opc.c (aarch64_conds): Add SVE names.
688 (aarch64_print_operand): Print alternative condition names in
689 a comment.
690
691 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
692
693 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
694 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
695 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
696 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
697 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
698 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
699 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
700 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
701 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
702 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
703 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
704 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
705 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
706 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
707 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
708 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
709 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
710 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
711 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
712 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
713 (OP_SVE_XWU, OP_SVE_XXU): New macros.
714 (aarch64_feature_sve): New variable.
715 (SVE): New macro.
716 (_SVE_INSN): Likewise.
717 (aarch64_opcode_table): Add SVE instructions.
718 * aarch64-opc.h (extract_fields): Declare.
719 * aarch64-opc-2.c: Regenerate.
720 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
721 * aarch64-asm-2.c: Regenerate.
722 * aarch64-dis.c (extract_fields): Make global.
723 (do_misc_decoding): Handle the new SVE aarch64_ops.
724 * aarch64-dis-2.c: Regenerate.
725
726 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
727
728 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
729 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
730 aarch64_field_kinds.
731 * aarch64-opc.c (fields): Add corresponding entries.
732 * aarch64-asm.c (aarch64_get_variant): New function.
733 (aarch64_encode_variant_using_iclass): Likewise.
734 (aarch64_opcode_encode): Call it.
735 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
736 (aarch64_opcode_decode): Call it.
737
738 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
739
740 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
741 and FP register operands.
742 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
743 (FLD_SVE_Vn): New aarch64_field_kinds.
744 * aarch64-opc.c (fields): Add corresponding entries.
745 (aarch64_print_operand): Handle the new SVE core and FP register
746 operands.
747 * aarch64-opc-2.c: Regenerate.
748 * aarch64-asm-2.c: Likewise.
749 * aarch64-dis-2.c: Likewise.
750
751 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
752
753 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
754 immediate operands.
755 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
756 * aarch64-opc.c (fields): Add corresponding entry.
757 (operand_general_constraint_met_p): Handle the new SVE FP immediate
758 operands.
759 (aarch64_print_operand): Likewise.
760 * aarch64-opc-2.c: Regenerate.
761 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
762 (ins_sve_float_zero_one): New inserters.
763 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
764 (aarch64_ins_sve_float_half_two): Likewise.
765 (aarch64_ins_sve_float_zero_one): Likewise.
766 * aarch64-asm-2.c: Regenerate.
767 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
768 (ext_sve_float_zero_one): New extractors.
769 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
770 (aarch64_ext_sve_float_half_two): Likewise.
771 (aarch64_ext_sve_float_zero_one): Likewise.
772 * aarch64-dis-2.c: Regenerate.
773
774 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
775
776 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
777 integer immediate operands.
778 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
779 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
780 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
781 * aarch64-opc.c (fields): Add corresponding entries.
782 (operand_general_constraint_met_p): Handle the new SVE integer
783 immediate operands.
784 (aarch64_print_operand): Likewise.
785 (aarch64_sve_dupm_mov_immediate_p): New function.
786 * aarch64-opc-2.c: Regenerate.
787 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
788 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
789 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
790 (aarch64_ins_limm): ...here.
791 (aarch64_ins_inv_limm): New function.
792 (aarch64_ins_sve_aimm): Likewise.
793 (aarch64_ins_sve_asimm): Likewise.
794 (aarch64_ins_sve_limm_mov): Likewise.
795 (aarch64_ins_sve_shlimm): Likewise.
796 (aarch64_ins_sve_shrimm): Likewise.
797 * aarch64-asm-2.c: Regenerate.
798 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
799 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
800 * aarch64-dis.c (decode_limm): New function, split out from...
801 (aarch64_ext_limm): ...here.
802 (aarch64_ext_inv_limm): New function.
803 (decode_sve_aimm): Likewise.
804 (aarch64_ext_sve_aimm): Likewise.
805 (aarch64_ext_sve_asimm): Likewise.
806 (aarch64_ext_sve_limm_mov): Likewise.
807 (aarch64_top_bit): Likewise.
808 (aarch64_ext_sve_shlimm): Likewise.
809 (aarch64_ext_sve_shrimm): Likewise.
810 * aarch64-dis-2.c: Regenerate.
811
812 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
813
814 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
815 operands.
816 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
817 the AARCH64_MOD_MUL_VL entry.
818 (value_aligned_p): Cope with non-power-of-two alignments.
819 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
820 (print_immediate_offset_address): Likewise.
821 (aarch64_print_operand): Likewise.
822 * aarch64-opc-2.c: Regenerate.
823 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
824 (ins_sve_addr_ri_s9xvl): New inserters.
825 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
826 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
827 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
828 * aarch64-asm-2.c: Regenerate.
829 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
830 (ext_sve_addr_ri_s9xvl): New extractors.
831 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
832 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
833 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
834 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
835 * aarch64-dis-2.c: Regenerate.
836
837 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
838
839 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
840 address operands.
841 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
842 (FLD_SVE_xs_22): New aarch64_field_kinds.
843 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
844 (get_operand_specific_data): New function.
845 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
846 FLD_SVE_xs_14 and FLD_SVE_xs_22.
847 (operand_general_constraint_met_p): Handle the new SVE address
848 operands.
849 (sve_reg): New array.
850 (get_addr_sve_reg_name): New function.
851 (aarch64_print_operand): Handle the new SVE address operands.
852 * aarch64-opc-2.c: Regenerate.
853 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
854 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
855 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
856 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
857 (aarch64_ins_sve_addr_rr_lsl): Likewise.
858 (aarch64_ins_sve_addr_rz_xtw): Likewise.
859 (aarch64_ins_sve_addr_zi_u5): Likewise.
860 (aarch64_ins_sve_addr_zz): Likewise.
861 (aarch64_ins_sve_addr_zz_lsl): Likewise.
862 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
863 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
864 * aarch64-asm-2.c: Regenerate.
865 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
866 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
867 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
868 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
869 (aarch64_ext_sve_addr_ri_u6): Likewise.
870 (aarch64_ext_sve_addr_rr_lsl): Likewise.
871 (aarch64_ext_sve_addr_rz_xtw): Likewise.
872 (aarch64_ext_sve_addr_zi_u5): Likewise.
873 (aarch64_ext_sve_addr_zz): Likewise.
874 (aarch64_ext_sve_addr_zz_lsl): Likewise.
875 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
876 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
877 * aarch64-dis-2.c: Regenerate.
878
879 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
880
881 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
882 AARCH64_OPND_SVE_PATTERN_SCALED.
883 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
884 * aarch64-opc.c (fields): Add a corresponding entry.
885 (set_multiplier_out_of_range_error): New function.
886 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
887 (operand_general_constraint_met_p): Handle
888 AARCH64_OPND_SVE_PATTERN_SCALED.
889 (print_register_offset_address): Use PRIi64 to print the
890 shift amount.
891 (aarch64_print_operand): Likewise. Handle
892 AARCH64_OPND_SVE_PATTERN_SCALED.
893 * aarch64-opc-2.c: Regenerate.
894 * aarch64-asm.h (ins_sve_scale): New inserter.
895 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
896 * aarch64-asm-2.c: Regenerate.
897 * aarch64-dis.h (ext_sve_scale): New inserter.
898 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
899 * aarch64-dis-2.c: Regenerate.
900
901 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
902
903 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
904 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
905 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
906 (FLD_SVE_prfop): Likewise.
907 * aarch64-opc.c: Include libiberty.h.
908 (aarch64_sve_pattern_array): New variable.
909 (aarch64_sve_prfop_array): Likewise.
910 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
911 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
912 AARCH64_OPND_SVE_PRFOP.
913 * aarch64-asm-2.c: Regenerate.
914 * aarch64-dis-2.c: Likewise.
915 * aarch64-opc-2.c: Likewise.
916
917 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
918
919 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
920 AARCH64_OPND_QLF_P_[ZM].
921 (aarch64_print_operand): Print /z and /m where appropriate.
922
923 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
924
925 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
926 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
927 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
928 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
929 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
930 * aarch64-opc.c (fields): Add corresponding entries here.
931 (operand_general_constraint_met_p): Check that SVE register lists
932 have the correct length. Check the ranges of SVE index registers.
933 Check for cases where p8-p15 are used in 3-bit predicate fields.
934 (aarch64_print_operand): Handle the new SVE operands.
935 * aarch64-opc-2.c: Regenerate.
936 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
937 * aarch64-asm.c (aarch64_ins_sve_index): New function.
938 (aarch64_ins_sve_reglist): Likewise.
939 * aarch64-asm-2.c: Regenerate.
940 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
941 * aarch64-dis.c (aarch64_ext_sve_index): New function.
942 (aarch64_ext_sve_reglist): Likewise.
943 * aarch64-dis-2.c: Regenerate.
944
945 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
946
947 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
948 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
949 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
950 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
951 tied operands.
952
953 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
954
955 * aarch64-opc.c (get_offset_int_reg_name): New function.
956 (print_immediate_offset_address): Likewise.
957 (print_register_offset_address): Take the base and offset
958 registers as parameters.
959 (aarch64_print_operand): Update caller accordingly. Use
960 print_immediate_offset_address.
961
962 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
963
964 * aarch64-opc.c (BANK): New macro.
965 (R32, R64): Take a register number as argument
966 (int_reg): Use BANK.
967
968 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
969
970 * aarch64-opc.c (print_register_list): Add a prefix parameter.
971 (aarch64_print_operand): Update accordingly.
972
973 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
974
975 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
976 for FPIMM.
977 * aarch64-asm.h (ins_fpimm): New inserter.
978 * aarch64-asm.c (aarch64_ins_fpimm): New function.
979 * aarch64-asm-2.c: Regenerate.
980 * aarch64-dis.h (ext_fpimm): New extractor.
981 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
982 (aarch64_ext_fpimm): New function.
983 * aarch64-dis-2.c: Regenerate.
984
985 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
986
987 * aarch64-asm.c: Include libiberty.h.
988 (insert_fields): New function.
989 (aarch64_ins_imm): Use it.
990 * aarch64-dis.c (extract_fields): New function.
991 (aarch64_ext_imm): Use it.
992
993 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
994
995 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
996 with an esize parameter.
997 (operand_general_constraint_met_p): Update accordingly.
998 Fix misindented code.
999 * aarch64-asm.c (aarch64_ins_limm): Update call to
1000 aarch64_logical_immediate_p.
1001
1002 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1003
1004 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1005
1006 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1007
1008 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1009
1010 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1011
1012 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1013
1014 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1015
1016 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1017 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1018 xor3>: Delete mnemonics.
1019 <cp_abort>: Rename mnemonic from ...
1020 <cpabort>: ...to this.
1021 <setb>: Change to a X form instruction.
1022 <sync>: Change to 1 operand form.
1023 <copy>: Delete mnemonic.
1024 <copy_first>: Rename mnemonic from ...
1025 <copy>: ...to this.
1026 <paste, paste.>: Delete mnemonics.
1027 <paste_last>: Rename mnemonic from ...
1028 <paste.>: ...to this.
1029
1030 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1031
1032 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1033
1034 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1035
1036 * s390-mkopc.c (main): Support alternate arch strings.
1037
1038 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1039
1040 * s390-opc.txt: Fix kmctr instruction type.
1041
1042 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1043
1044 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1045 * i386-init.h: Regenerated.
1046
1047 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1048
1049 * opcodes/arc-dis.c (print_insn_arc): Changed.
1050
1051 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1052
1053 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1054 camellia_fl.
1055
1056 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1057
1058 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1059 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1060 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1061
1062 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1063
1064 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1065 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1066 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1067 PREFIX_MOD_3_0FAE_REG_4.
1068 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1069 PREFIX_MOD_3_0FAE_REG_4.
1070 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1071 (cpu_flags): Add CpuPTWRITE.
1072 * i386-opc.h (CpuPTWRITE): New.
1073 (i386_cpu_flags): Add cpuptwrite.
1074 * i386-opc.tbl: Add ptwrite instruction.
1075 * i386-init.h: Regenerated.
1076 * i386-tbl.h: Likewise.
1077
1078 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1079
1080 * arc-dis.h: Wrap around in extern "C".
1081
1082 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1083
1084 * aarch64-tbl.h (V8_2_INSN): New macro.
1085 (aarch64_opcode_table): Use it.
1086
1087 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1088
1089 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1090 CORE_INSN, __FP_INSN and SIMD_INSN.
1091
1092 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1093
1094 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1095 (aarch64_opcode_table): Update uses accordingly.
1096
1097 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1098 Kwok Cheung Yeung <kcy@codesourcery.com>
1099
1100 opcodes/
1101 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1102 'e_cmplwi' to 'e_cmpli' instead.
1103 (OPVUPRT, OPVUPRT_MASK): Define.
1104 (powerpc_opcodes): Add E200Z4 insns.
1105 (vle_opcodes): Add context save/restore insns.
1106
1107 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1108
1109 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1110 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1111 "j".
1112
1113 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1114
1115 * arc-nps400-tbl.h: Change block comments to GNU format.
1116 * arc-dis.c: Add new globals addrtypenames,
1117 addrtypenames_max, and addtypeunknown.
1118 (get_addrtype): New function.
1119 (print_insn_arc): Print colons and address types when
1120 required.
1121 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1122 define insert and extract functions for all address types.
1123 (arc_operands): Add operands for colon and all address
1124 types.
1125 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1126 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1127 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1128 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1129 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1130 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1131
1132 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1133
1134 * configure: Regenerated.
1135
1136 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1137
1138 * arc-dis.c (skipclass): New structure.
1139 (decodelist): New variable.
1140 (is_compatible_p): New function.
1141 (new_element): Likewise.
1142 (skip_class_p): Likewise.
1143 (find_format_from_table): Use skip_class_p function.
1144 (find_format): Decode first the extension instructions.
1145 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1146 e_flags.
1147 (parse_option): New function.
1148 (parse_disassembler_options): Likewise.
1149 (print_arc_disassembler_options): Likewise.
1150 (print_insn_arc): Use parse_disassembler_options function. Proper
1151 select ARCv2 cpu variant.
1152 * disassemble.c (disassembler_usage): Add ARC disassembler
1153 options.
1154
1155 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1156
1157 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1158 annotation from the "nal" entry and reorder it beyond "bltzal".
1159
1160 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1161
1162 * sparc-opc.c (ldtxa): New macro.
1163 (sparc_opcodes): Use the macro defined above to add entries for
1164 the LDTXA instructions.
1165 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1166 instruction.
1167
1168 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1169
1170 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1171 and "jmpc".
1172
1173 2016-07-01 Jan Beulich <jbeulich@suse.com>
1174
1175 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1176 (movzb): Adjust to cover all permitted suffixes.
1177 (movzw): New.
1178 * i386-tbl.h: Re-generate.
1179
1180 2016-07-01 Jan Beulich <jbeulich@suse.com>
1181
1182 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1183 (lgdt): Remove Tbyte from non-64-bit variant.
1184 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1185 xsaves64, xsavec64): Remove Disp16.
1186 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1187 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1188 64-bit variants.
1189 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1190 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1191 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1192 64-bit variants.
1193 * i386-tbl.h: Re-generate.
1194
1195 2016-07-01 Jan Beulich <jbeulich@suse.com>
1196
1197 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1198 * i386-tbl.h: Re-generate.
1199
1200 2016-06-30 Yao Qi <yao.qi@linaro.org>
1201
1202 * arm-dis.c (print_insn): Fix typo in comment.
1203
1204 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1205
1206 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1207 range of ldst_elemlist operands.
1208 (print_register_list): Use PRIi64 to print the index.
1209 (aarch64_print_operand): Likewise.
1210
1211 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1212
1213 * mcore-opc.h: Remove sentinal.
1214 * mcore-dis.c (print_insn_mcore): Adjust.
1215
1216 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1217
1218 * arc-opc.c: Correct description of availability of NPS400
1219 features.
1220
1221 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1222
1223 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1224 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1225 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1226 xor3>: New mnemonics.
1227 <setb>: Change to a VX form instruction.
1228 (insert_sh6): Add support for rldixor.
1229 (extract_sh6): Likewise.
1230
1231 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1232
1233 * arc-ext.h: Wrap in extern C.
1234
1235 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1236
1237 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1238 Use same method for determining instruction length on ARC700 and
1239 NPS-400.
1240 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1241 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1242 with the NPS400 subclass.
1243 * arc-opc.c: Likewise.
1244
1245 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1246
1247 * sparc-opc.c (rdasr): New macro.
1248 (wrasr): Likewise.
1249 (rdpr): Likewise.
1250 (wrpr): Likewise.
1251 (rdhpr): Likewise.
1252 (wrhpr): Likewise.
1253 (sparc_opcodes): Use the macros above to fix and expand the
1254 definition of read/write instructions from/to
1255 asr/privileged/hyperprivileged instructions.
1256 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1257 %hva_mask_nz. Prefer softint_set and softint_clear over
1258 set_softint and clear_softint.
1259 (print_insn_sparc): Support %ver in Rd.
1260
1261 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1262
1263 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1264 architecture according to the hardware capabilities they require.
1265
1266 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1267
1268 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1269 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1270 bfd_mach_sparc_v9{c,d,e,v,m}.
1271 * sparc-opc.c (MASK_V9C): Define.
1272 (MASK_V9D): Likewise.
1273 (MASK_V9E): Likewise.
1274 (MASK_V9V): Likewise.
1275 (MASK_V9M): Likewise.
1276 (v6): Add MASK_V9{C,D,E,V,M}.
1277 (v6notlet): Likewise.
1278 (v7): Likewise.
1279 (v8): Likewise.
1280 (v9): Likewise.
1281 (v9andleon): Likewise.
1282 (v9a): Likewise.
1283 (v9b): Likewise.
1284 (v9c): Define.
1285 (v9d): Likewise.
1286 (v9e): Likewise.
1287 (v9v): Likewise.
1288 (v9m): Likewise.
1289 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1290
1291 2016-06-15 Nick Clifton <nickc@redhat.com>
1292
1293 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1294 constants to match expected behaviour.
1295 (nds32_parse_opcode): Likewise. Also for whitespace.
1296
1297 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1298
1299 * arc-opc.c (extract_rhv1): Extract value from insn.
1300
1301 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1302
1303 * arc-nps400-tbl.h: Add ldbit instruction.
1304 * arc-opc.c: Add flag classes required for ldbit.
1305
1306 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1307
1308 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1309 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1310 support the above instructions.
1311
1312 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1313
1314 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1315 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1316 csma, cbba, zncv, and hofs.
1317 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1318 support the above instructions.
1319
1320 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1321
1322 * arc-nps400-tbl.h: Add andab and orab instructions.
1323
1324 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1325
1326 * arc-nps400-tbl.h: Add addl-like instructions.
1327
1328 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1329
1330 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1331
1332 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1333
1334 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1335 instructions.
1336
1337 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1338
1339 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1340 variable.
1341 (init_disasm): Handle new command line option "insnlength".
1342 (print_s390_disassembler_options): Mention new option in help
1343 output.
1344 (print_insn_s390): Use the encoded insn length when dumping
1345 unknown instructions.
1346
1347 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1348
1349 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1350 to the address and set as symbol address for LDS/ STS immediate operands.
1351
1352 2016-06-07 Alan Modra <amodra@gmail.com>
1353
1354 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1355 cpu for "vle" to e500.
1356 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1357 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1358 (PPCNONE): Delete, substitute throughout.
1359 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1360 except for major opcode 4 and 31.
1361 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1362
1363 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1364
1365 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1366 ARM_EXT_RAS in relevant entries.
1367
1368 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1369
1370 PR binutils/20196
1371 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1372 opcodes for E6500.
1373
1374 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1375
1376 PR binutis/18386
1377 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1378 (indir_v_mode): New.
1379 Add comments for '&'.
1380 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1381 (putop): Handle '&'.
1382 (intel_operand_size): Handle indir_v_mode.
1383 (OP_E_register): Likewise.
1384 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1385 64-bit indirect call/jmp for AMD64.
1386 * i386-tbl.h: Regenerated
1387
1388 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1389
1390 * arc-dis.c (struct arc_operand_iterator): New structure.
1391 (find_format_from_table): All the old content from find_format,
1392 with some minor adjustments, and parameter renaming.
1393 (find_format_long_instructions): New function.
1394 (find_format): Rewritten.
1395 (arc_insn_length): Add LSB parameter.
1396 (extract_operand_value): New function.
1397 (operand_iterator_next): New function.
1398 (print_insn_arc): Use new functions to find opcode, and iterator
1399 over operands.
1400 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1401 (extract_nps_3bit_dst_short): New function.
1402 (insert_nps_3bit_src2_short): New function.
1403 (extract_nps_3bit_src2_short): New function.
1404 (insert_nps_bitop1_size): New function.
1405 (extract_nps_bitop1_size): New function.
1406 (insert_nps_bitop2_size): New function.
1407 (extract_nps_bitop2_size): New function.
1408 (insert_nps_bitop_mod4_msb): New function.
1409 (extract_nps_bitop_mod4_msb): New function.
1410 (insert_nps_bitop_mod4_lsb): New function.
1411 (extract_nps_bitop_mod4_lsb): New function.
1412 (insert_nps_bitop_dst_pos3_pos4): New function.
1413 (extract_nps_bitop_dst_pos3_pos4): New function.
1414 (insert_nps_bitop_ins_ext): New function.
1415 (extract_nps_bitop_ins_ext): New function.
1416 (arc_operands): Add new operands.
1417 (arc_long_opcodes): New global array.
1418 (arc_num_long_opcodes): New global.
1419 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1420
1421 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1422
1423 * nds32-asm.h: Add extern "C".
1424 * sh-opc.h: Likewise.
1425
1426 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1427
1428 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1429 0,b,limm to the rflt instruction.
1430
1431 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1432
1433 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1434 constant.
1435
1436 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1437
1438 PR gas/20145
1439 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1440 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1441 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1442 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1443 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1444 * i386-init.h: Regenerated.
1445
1446 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1447
1448 PR gas/20145
1449 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1450 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1451 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1452 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1453 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1454 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1455 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1456 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1457 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1458 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1459 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1460 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1461 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1462 CpuRegMask for AVX512.
1463 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1464 and CpuRegMask.
1465 (set_bitfield_from_cpu_flag_init): New function.
1466 (set_bitfield): Remove const on f. Call
1467 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1468 * i386-opc.h (CpuRegMMX): New.
1469 (CpuRegXMM): Likewise.
1470 (CpuRegYMM): Likewise.
1471 (CpuRegZMM): Likewise.
1472 (CpuRegMask): Likewise.
1473 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1474 and cpuregmask.
1475 * i386-init.h: Regenerated.
1476 * i386-tbl.h: Likewise.
1477
1478 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1479
1480 PR gas/20154
1481 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1482 (opcode_modifiers): Add AMD64 and Intel64.
1483 (main): Properly verify CpuMax.
1484 * i386-opc.h (CpuAMD64): Removed.
1485 (CpuIntel64): Likewise.
1486 (CpuMax): Set to CpuNo64.
1487 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1488 (AMD64): New.
1489 (Intel64): Likewise.
1490 (i386_opcode_modifier): Add amd64 and intel64.
1491 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1492 on call and jmp.
1493 * i386-init.h: Regenerated.
1494 * i386-tbl.h: Likewise.
1495
1496 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1497
1498 PR gas/20154
1499 * i386-gen.c (main): Fail if CpuMax is incorrect.
1500 * i386-opc.h (CpuMax): Set to CpuIntel64.
1501 * i386-tbl.h: Regenerated.
1502
1503 2016-05-27 Nick Clifton <nickc@redhat.com>
1504
1505 PR target/20150
1506 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1507 (msp430dis_opcode_unsigned): New function.
1508 (msp430dis_opcode_signed): New function.
1509 (msp430_singleoperand): Use the new opcode reading functions.
1510 Only disassenmble bytes if they were successfully read.
1511 (msp430_doubleoperand): Likewise.
1512 (msp430_branchinstr): Likewise.
1513 (msp430x_callx_instr): Likewise.
1514 (print_insn_msp430): Check that it is safe to read bytes before
1515 attempting disassembly. Use the new opcode reading functions.
1516
1517 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1518
1519 * ppc-opc.c (CY): New define. Document it.
1520 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1521
1522 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1523
1524 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1525 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1526 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1527 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1528 CPU_ANY_AVX_FLAGS.
1529 * i386-init.h: Regenerated.
1530
1531 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1532
1533 PR gas/20141
1534 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1535 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1536 * i386-init.h: Regenerated.
1537
1538 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1539
1540 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1541 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1542 * i386-init.h: Regenerated.
1543
1544 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1545
1546 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1547 information.
1548 (print_insn_arc): Set insn_type information.
1549 * arc-opc.c (C_CC): Add F_CLASS_COND.
1550 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1551 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1552 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1553 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1554 (brne, brne_s, jeq_s, jne_s): Likewise.
1555
1556 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1557
1558 * arc-tbl.h (neg): New instruction variant.
1559
1560 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1561
1562 * arc-dis.c (find_format, find_format, get_auxreg)
1563 (print_insn_arc): Changed.
1564 * arc-ext.h (INSERT_XOP): Likewise.
1565
1566 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1567
1568 * tic54x-dis.c (sprint_mmr): Adjust.
1569 * tic54x-opc.c: Likewise.
1570
1571 2016-05-19 Alan Modra <amodra@gmail.com>
1572
1573 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1574
1575 2016-05-19 Alan Modra <amodra@gmail.com>
1576
1577 * ppc-opc.c: Formatting.
1578 (NSISIGNOPT): Define.
1579 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1580
1581 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1582
1583 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1584 replacing references to `micromips_ase' throughout.
1585 (_print_insn_mips): Don't use file-level microMIPS annotation to
1586 determine the disassembly mode with the symbol table.
1587
1588 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1589
1590 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1591
1592 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1593
1594 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1595 mips64r6.
1596 * mips-opc.c (D34): New macro.
1597 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1598
1599 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1600
1601 * i386-dis.c (prefix_table): Add RDPID instruction.
1602 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1603 (cpu_flags): Add RDPID bitfield.
1604 * i386-opc.h (enum): Add RDPID element.
1605 (i386_cpu_flags): Add RDPID field.
1606 * i386-opc.tbl: Add RDPID instruction.
1607 * i386-init.h: Regenerate.
1608 * i386-tbl.h: Regenerate.
1609
1610 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1611
1612 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1613 branch type of a symbol.
1614 (print_insn): Likewise.
1615
1616 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1617
1618 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1619 Mainline Security Extensions instructions.
1620 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1621 Extensions instructions.
1622 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1623 instructions.
1624 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1625 special registers.
1626
1627 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1628
1629 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1630
1631 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1632
1633 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1634 (arcExtMap_genOpcode): Likewise.
1635 * arc-opc.c (arg_32bit_rc): Define new variable.
1636 (arg_32bit_u6): Likewise.
1637 (arg_32bit_limm): Likewise.
1638
1639 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1640
1641 * aarch64-gen.c (VERIFIER): Define.
1642 * aarch64-opc.c (VERIFIER): Define.
1643 (verify_ldpsw): Use static linkage.
1644 * aarch64-opc.h (verify_ldpsw): Remove.
1645 * aarch64-tbl.h: Use VERIFIER for verifiers.
1646
1647 2016-04-28 Nick Clifton <nickc@redhat.com>
1648
1649 PR target/19722
1650 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1651 * aarch64-opc.c (verify_ldpsw): New function.
1652 * aarch64-opc.h (verify_ldpsw): New prototype.
1653 * aarch64-tbl.h: Add initialiser for verifier field.
1654 (LDPSW): Set verifier to verify_ldpsw.
1655
1656 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1657
1658 PR binutils/19983
1659 PR binutils/19984
1660 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1661 smaller than address size.
1662
1663 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1664
1665 * alpha-dis.c: Regenerate.
1666 * crx-dis.c: Likewise.
1667 * disassemble.c: Likewise.
1668 * epiphany-opc.c: Likewise.
1669 * fr30-opc.c: Likewise.
1670 * frv-opc.c: Likewise.
1671 * ip2k-opc.c: Likewise.
1672 * iq2000-opc.c: Likewise.
1673 * lm32-opc.c: Likewise.
1674 * lm32-opinst.c: Likewise.
1675 * m32c-opc.c: Likewise.
1676 * m32r-opc.c: Likewise.
1677 * m32r-opinst.c: Likewise.
1678 * mep-opc.c: Likewise.
1679 * mt-opc.c: Likewise.
1680 * or1k-opc.c: Likewise.
1681 * or1k-opinst.c: Likewise.
1682 * tic80-opc.c: Likewise.
1683 * xc16x-opc.c: Likewise.
1684 * xstormy16-opc.c: Likewise.
1685
1686 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1687
1688 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1689 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1690 calcsd, and calcxd instructions.
1691 * arc-opc.c (insert_nps_bitop_size): Delete.
1692 (extract_nps_bitop_size): Delete.
1693 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1694 (extract_nps_qcmp_m3): Define.
1695 (extract_nps_qcmp_m2): Define.
1696 (extract_nps_qcmp_m1): Define.
1697 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1698 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1699 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1700 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1701 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1702 NPS_QCMP_M3.
1703
1704 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1705
1706 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1707
1708 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1709
1710 * Makefile.in: Regenerated with automake 1.11.6.
1711 * aclocal.m4: Likewise.
1712
1713 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1714
1715 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1716 instructions.
1717 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1718 (extract_nps_cmem_uimm16): New function.
1719 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1720
1721 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1722
1723 * arc-dis.c (arc_insn_length): New function.
1724 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1725 (find_format): Change insnLen parameter to unsigned.
1726
1727 2016-04-13 Nick Clifton <nickc@redhat.com>
1728
1729 PR target/19937
1730 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1731 the LD.B and LD.BU instructions.
1732
1733 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1734
1735 * arc-dis.c (find_format): Check for extension flags.
1736 (print_flags): New function.
1737 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1738 .extAuxRegister.
1739 * arc-ext.c (arcExtMap_coreRegName): Use
1740 LAST_EXTENSION_CORE_REGISTER.
1741 (arcExtMap_coreReadWrite): Likewise.
1742 (dump_ARC_extmap): Update printing.
1743 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1744 (arc_aux_regs): Add cpu field.
1745 * arc-regs.h: Add cpu field, lower case name aux registers.
1746
1747 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1748
1749 * arc-tbl.h: Add rtsc, sleep with no arguments.
1750
1751 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1752
1753 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1754 Initialize.
1755 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1756 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1757 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1758 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1759 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1760 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1761 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1762 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1763 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1764 (arc_opcode arc_opcodes): Null terminate the array.
1765 (arc_num_opcodes): Remove.
1766 * arc-ext.h (INSERT_XOP): Define.
1767 (extInstruction_t): Likewise.
1768 (arcExtMap_instName): Delete.
1769 (arcExtMap_insn): New function.
1770 (arcExtMap_genOpcode): Likewise.
1771 * arc-ext.c (ExtInstruction): Remove.
1772 (create_map): Zero initialize instruction fields.
1773 (arcExtMap_instName): Remove.
1774 (arcExtMap_insn): New function.
1775 (dump_ARC_extmap): More info while debuging.
1776 (arcExtMap_genOpcode): New function.
1777 * arc-dis.c (find_format): New function.
1778 (print_insn_arc): Use find_format.
1779 (arc_get_disassembler): Enable dump_ARC_extmap only when
1780 debugging.
1781
1782 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1783
1784 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1785 instruction bits out.
1786
1787 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1788
1789 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1790 * arc-opc.c (arc_flag_operands): Add new flags.
1791 (arc_flag_classes): Add new classes.
1792
1793 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1794
1795 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1796
1797 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1798
1799 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1800 encode1, rflt, crc16, and crc32 instructions.
1801 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1802 (arc_flag_classes): Add C_NPS_R.
1803 (insert_nps_bitop_size_2b): New function.
1804 (extract_nps_bitop_size_2b): Likewise.
1805 (insert_nps_bitop_uimm8): Likewise.
1806 (extract_nps_bitop_uimm8): Likewise.
1807 (arc_operands): Add new operand entries.
1808
1809 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1810
1811 * arc-regs.h: Add a new subclass field. Add double assist
1812 accumulator register values.
1813 * arc-tbl.h: Use DPA subclass to mark the double assist
1814 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1815 * arc-opc.c (RSP): Define instead of SP.
1816 (arc_aux_regs): Add the subclass field.
1817
1818 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1819
1820 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1821
1822 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1823
1824 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1825 NPS_R_SRC1.
1826
1827 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1828
1829 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1830 issues. No functional changes.
1831
1832 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1833
1834 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1835 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1836 (RTT): Remove duplicate.
1837 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1838 (PCT_CONFIG*): Remove.
1839 (D1L, D1H, D2H, D2L): Define.
1840
1841 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1842
1843 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1844
1845 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1846
1847 * arc-tbl.h (invld07): Remove.
1848 * arc-ext-tbl.h: New file.
1849 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1850 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1851
1852 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1853
1854 Fix -Wstack-usage warnings.
1855 * aarch64-dis.c (print_operands): Substitute size.
1856 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1857
1858 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1859
1860 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1861 to get a proper diagnostic when an invalid ASR register is used.
1862
1863 2016-03-22 Nick Clifton <nickc@redhat.com>
1864
1865 * configure: Regenerate.
1866
1867 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1868
1869 * arc-nps400-tbl.h: New file.
1870 * arc-opc.c: Add top level comment.
1871 (insert_nps_3bit_dst): New function.
1872 (extract_nps_3bit_dst): New function.
1873 (insert_nps_3bit_src2): New function.
1874 (extract_nps_3bit_src2): New function.
1875 (insert_nps_bitop_size): New function.
1876 (extract_nps_bitop_size): New function.
1877 (arc_flag_operands): Add nps400 entries.
1878 (arc_flag_classes): Add nps400 entries.
1879 (arc_operands): Add nps400 entries.
1880 (arc_opcodes): Add nps400 include.
1881
1882 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1883
1884 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1885 the new class enum values.
1886
1887 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1888
1889 * arc-dis.c (print_insn_arc): Handle nps400.
1890
1891 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1892
1893 * arc-opc.c (BASE): Delete.
1894
1895 2016-03-18 Nick Clifton <nickc@redhat.com>
1896
1897 PR target/19721
1898 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1899 of MOV insn that aliases an ORR insn.
1900
1901 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1902
1903 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1904
1905 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1906
1907 * mcore-opc.h: Add const qualifiers.
1908 * microblaze-opc.h (struct op_code_struct): Likewise.
1909 * sh-opc.h: Likewise.
1910 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1911 (tic4x_print_op): Likewise.
1912
1913 2016-03-02 Alan Modra <amodra@gmail.com>
1914
1915 * or1k-desc.h: Regenerate.
1916 * fr30-ibld.c: Regenerate.
1917 * rl78-decode.c: Regenerate.
1918
1919 2016-03-01 Nick Clifton <nickc@redhat.com>
1920
1921 PR target/19747
1922 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1923
1924 2016-02-24 Renlin Li <renlin.li@arm.com>
1925
1926 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1927 (print_insn_coprocessor): Support fp16 instructions.
1928
1929 2016-02-24 Renlin Li <renlin.li@arm.com>
1930
1931 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1932 vminnm, vrint(mpna).
1933
1934 2016-02-24 Renlin Li <renlin.li@arm.com>
1935
1936 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1937 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1938
1939 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1940
1941 * i386-dis.c (print_insn): Parenthesize expression to prevent
1942 truncated addresses.
1943 (OP_J): Likewise.
1944
1945 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1946 Janek van Oirschot <jvanoirs@synopsys.com>
1947
1948 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1949 variable.
1950
1951 2016-02-04 Nick Clifton <nickc@redhat.com>
1952
1953 PR target/19561
1954 * msp430-dis.c (print_insn_msp430): Add a special case for
1955 decoding an RRC instruction with the ZC bit set in the extension
1956 word.
1957
1958 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1959
1960 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1961 * epiphany-ibld.c: Regenerate.
1962 * fr30-ibld.c: Regenerate.
1963 * frv-ibld.c: Regenerate.
1964 * ip2k-ibld.c: Regenerate.
1965 * iq2000-ibld.c: Regenerate.
1966 * lm32-ibld.c: Regenerate.
1967 * m32c-ibld.c: Regenerate.
1968 * m32r-ibld.c: Regenerate.
1969 * mep-ibld.c: Regenerate.
1970 * mt-ibld.c: Regenerate.
1971 * or1k-ibld.c: Regenerate.
1972 * xc16x-ibld.c: Regenerate.
1973 * xstormy16-ibld.c: Regenerate.
1974
1975 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1976
1977 * epiphany-dis.c: Regenerated from latest cpu files.
1978
1979 2016-02-01 Michael McConville <mmcco@mykolab.com>
1980
1981 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1982 test bit.
1983
1984 2016-01-25 Renlin Li <renlin.li@arm.com>
1985
1986 * arm-dis.c (mapping_symbol_for_insn): New function.
1987 (find_ifthen_state): Call mapping_symbol_for_insn().
1988
1989 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1990
1991 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1992 of MSR UAO immediate operand.
1993
1994 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1995
1996 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1997 instruction support.
1998
1999 2016-01-17 Alan Modra <amodra@gmail.com>
2000
2001 * configure: Regenerate.
2002
2003 2016-01-14 Nick Clifton <nickc@redhat.com>
2004
2005 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2006 instructions that can support stack pointer operations.
2007 * rl78-decode.c: Regenerate.
2008 * rl78-dis.c: Fix display of stack pointer in MOVW based
2009 instructions.
2010
2011 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2012
2013 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2014 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2015 erxtatus_el1 and erxaddr_el1.
2016
2017 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2018
2019 * arm-dis.c (arm_opcodes): Add "esb".
2020 (thumb_opcodes): Likewise.
2021
2022 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2023
2024 * ppc-opc.c <xscmpnedp>: Delete.
2025 <xvcmpnedp>: Likewise.
2026 <xvcmpnedp.>: Likewise.
2027 <xvcmpnesp>: Likewise.
2028 <xvcmpnesp.>: Likewise.
2029
2030 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2031
2032 PR gas/13050
2033 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2034 addition to ISA_A.
2035
2036 2016-01-01 Alan Modra <amodra@gmail.com>
2037
2038 Update year range in copyright notice of all files.
2039
2040 For older changes see ChangeLog-2015
2041 \f
2042 Copyright (C) 2016 Free Software Foundation, Inc.
2043
2044 Copying and distribution of this file, with or without modification,
2045 are permitted in any medium without royalty provided the copyright
2046 notice and this notice are preserved.
2047
2048 Local Variables:
2049 mode: change-log
2050 left-margin: 8
2051 fill-column: 74
2052 version-control: never
2053 End:
GDB Binutils - Deliverables
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