opcodes/ChangeLog

   1 2020-06-05  Alan Modra  <amodra@gmail.com>
   2
   3         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
   4         size is large enough.
   5
   6 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
   7
   8         * disassemble.c (disassemble_init_for_target): Set endian_code for
   9         bpf targets.
  10         * bpf-desc.c: Regenerate.
  11         * bpf-opc.c: Likewise.
  12         * bpf-dis.c: Likewise.
  13
  14 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
  15
  16         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
  17         (cgen_put_insn_value): Likewise.
  18         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
  19         * cgen-dis.in (print_insn): Likewise.
  20         * cgen-ibld.in (insert_1): Likewise.
  21         (insert_1): Likewise.
  22         (insert_insn_normal): Likewise.
  23         (extract_1): Likewise.
  24         * bpf-dis.c: Regenerate.
  25         * bpf-ibld.c: Likewise.
  26         * bpf-ibld.c: Likewise.
  27         * cgen-dis.in: Likewise.
  28         * cgen-ibld.in: Likewise.
  29         * cgen-opc.c: Likewise.
  30         * epiphany-dis.c: Likewise.
  31         * epiphany-ibld.c: Likewise.
  32         * fr30-dis.c: Likewise.
  33         * fr30-ibld.c: Likewise.
  34         * frv-dis.c: Likewise.
  35         * frv-ibld.c: Likewise.
  36         * ip2k-dis.c: Likewise.
  37         * ip2k-ibld.c: Likewise.
  38         * iq2000-dis.c: Likewise.
  39         * iq2000-ibld.c: Likewise.
  40         * lm32-dis.c: Likewise.
  41         * lm32-ibld.c: Likewise.
  42         * m32c-dis.c: Likewise.
  43         * m32c-ibld.c: Likewise.
  44         * m32r-dis.c: Likewise.
  45         * m32r-ibld.c: Likewise.
  46         * mep-dis.c: Likewise.
  47         * mep-ibld.c: Likewise.
  48         * mt-dis.c: Likewise.
  49         * mt-ibld.c: Likewise.
  50         * or1k-dis.c: Likewise.
  51         * or1k-ibld.c: Likewise.
  52         * xc16x-dis.c: Likewise.
  53         * xc16x-ibld.c: Likewise.
  54         * xstormy16-dis.c: Likewise.
  55         * xstormy16-ibld.c: Likewise.
  56
  57 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
  58
  59         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
  60         (print_insn_): Handle instruction endian.
  61         * bpf-dis.c: Regenerate.
  62         * bpf-desc.c: Regenerate.
  63         * epiphany-dis.c: Likewise.
  64         * epiphany-desc.c: Likewise.
  65         * fr30-dis.c: Likewise.
  66         * fr30-desc.c: Likewise.
  67         * frv-dis.c: Likewise.
  68         * frv-desc.c: Likewise.
  69         * ip2k-dis.c: Likewise.
  70         * ip2k-desc.c: Likewise.
  71         * iq2000-dis.c: Likewise.
  72         * iq2000-desc.c: Likewise.
  73         * lm32-dis.c: Likewise.
  74         * lm32-desc.c: Likewise.
  75         * m32c-dis.c: Likewise.
  76         * m32c-desc.c: Likewise.
  77         * m32r-dis.c: Likewise.
  78         * m32r-desc.c: Likewise.
  79         * mep-dis.c: Likewise.
  80         * mep-desc.c: Likewise.
  81         * mt-dis.c: Likewise.
  82         * mt-desc.c: Likewise.
  83         * or1k-dis.c: Likewise.
  84         * or1k-desc.c: Likewise.
  85         * xc16x-dis.c: Likewise.
  86         * xc16x-desc.c: Likewise.
  87         * xstormy16-dis.c: Likewise.
  88         * xstormy16-desc.c: Likewise.
  89
  90 2020-06-03  Nick Clifton  <nickc@redhat.com>
  91
  92         * po/sr.po: Updated Serbian translation.
  93
  94 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
  95
  96         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
  97         (riscv_get_priv_spec_class): Likewise.
  98
  99 2020-06-01  Alan Modra  <amodra@gmail.com>
 100
 101         * bpf-desc.c: Regenerate.
 102
 103 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 104             David Faust <david.faust@oracle.com>
 105
 106         * bpf-desc.c: Regenerate.
 107         * bpf-opc.h: Likewise.
 108         * bpf-opc.c: Likewise.
 109         * bpf-dis.c: Likewise.
 110
 111 2020-05-28  Alan Modra  <amodra@gmail.com>
 112
 113         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 114         values.
 115
 116 2020-05-28  Alan Modra  <amodra@gmail.com>
 117
 118         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 119         immediates.
 120         (print_insn_ns32k): Revert last change.
 121
 122 2020-05-28  Nick Clifton  <nickc@redhat.com>
 123
 124         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 125         static.
 126
 127 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 128
 129         Fix extraction of signed constants in nios2 disassembler (again).
 130
 131         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 132         extractions of signed fields.
 133
 134 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 135
 136         * s390-opc.txt: Relocate vector load/store instructions with
 137         additional alignment parameter and change architecture level
 138         constraint from z14 to z13.
 139
 140 2020-05-21  Alan Modra  <amodra@gmail.com>
 141
 142         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 143         * sparc-dis.c: Likewise.
 144         * tic4x-dis.c: Likewise.
 145         * xtensa-dis.c: Likewise.
 146         * bpf-desc.c: Regenerate.
 147         * epiphany-desc.c: Regenerate.
 148         * fr30-desc.c: Regenerate.
 149         * frv-desc.c: Regenerate.
 150         * ip2k-desc.c: Regenerate.
 151         * iq2000-desc.c: Regenerate.
 152         * lm32-desc.c: Regenerate.
 153         * m32c-desc.c: Regenerate.
 154         * m32r-desc.c: Regenerate.
 155         * mep-asm.c: Regenerate.
 156         * mep-desc.c: Regenerate.
 157         * mt-desc.c: Regenerate.
 158         * or1k-desc.c: Regenerate.
 159         * xc16x-desc.c: Regenerate.
 160         * xstormy16-desc.c: Regenerate.
 161
 162 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 163
 164         * riscv-opc.c (riscv_ext_version_table): The table used to store
 165         all information about the supported spec and the corresponding ISA
 166         versions.  Currently, only Zicsr is supported to verify the
 167         correctness of Z sub extension settings.  Others will be supported
 168         in the future patches.
 169         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 170         classes and the corresponding strings.
 171         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 172         spec class by giving a ISA spec string.
 173         * riscv-opc.c (struct priv_spec_t): New structure.
 174         (struct priv_spec_t priv_specs): List for all supported privilege spec
 175         classes and the corresponding strings.
 176         (riscv_get_priv_spec_class): New function.  Get the corresponding
 177         privilege spec class by giving a spec string.
 178         (riscv_get_priv_spec_name): New function.  Get the corresponding
 179         privilege spec string by giving a CSR version class.
 180         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 181         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 182         according to the chosen version.  Build a hash table riscv_csr_hash to
 183         store the valid CSR for the chosen pirv verison.  Dump the direct
 184         CSR address rather than it's name if it is invalid.
 185         (parse_riscv_dis_option_without_args): New function.  Parse the options
 186         without arguments.
 187         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 188         parse the options without arguments first, and then handle the options
 189         with arguments.  Add the new option -Mpriv-spec, which has argument.
 190         * riscv-dis.c (print_riscv_disassembler_options): Add description
 191         about the new OBJDUMP option.
 192
 193 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 194
 195         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 196         WC values on POWER10 sync, dcbf  and wait instructions.
 197         (insert_pl, extract_pl): New functions.
 198         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 199         (LS3): New , 3-bit L for sync.
 200         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 201         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 202         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 203         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 204         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 205         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 206         <wait>: Enable PL operand on POWER10.
 207         <dcbf>: Enable L3OPT operand on POWER10.
 208         <sync>: Enable SC2 operand on POWER10.
 209
 210 2020-05-19  Stafford Horne  <shorne@gmail.com>
 211
 212         PR 25184
 213         * or1k-asm.c: Regenerate.
 214         * or1k-desc.c: Regenerate.
 215         * or1k-desc.h: Regenerate.
 216         * or1k-dis.c: Regenerate.
 217         * or1k-ibld.c: Regenerate.
 218         * or1k-opc.c: Regenerate.
 219         * or1k-opc.h: Regenerate.
 220         * or1k-opinst.c: Regenerate.
 221
 222 2020-05-11  Alan Modra  <amodra@gmail.com>
 223
 224         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 225         xsmaxcqp, xsmincqp.
 226
 227 2020-05-11  Alan Modra  <amodra@gmail.com>
 228
 229         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 230         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 231
 232 2020-05-11  Alan Modra  <amodra@gmail.com>
 233
 234         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 235
 236 2020-05-11  Alan Modra  <amodra@gmail.com>
 237
 238         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 239         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 240
 241 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 242
 243         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 244         mnemonics.
 245
 246 2020-05-11  Alan Modra  <amodra@gmail.com>
 247
 248         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 249         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 250         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 251         (prefix_opcodes): Add xxeval.
 252
 253 2020-05-11  Alan Modra  <amodra@gmail.com>
 254
 255         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 256         xxgenpcvwm, xxgenpcvdm.
 257
 258 2020-05-11  Alan Modra  <amodra@gmail.com>
 259
 260         * ppc-opc.c (MP, VXVAM_MASK): Define.
 261         (VXVAPS_MASK): Use VXVA_MASK.
 262         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 263         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 264         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 265         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 266
 267 2020-05-11  Alan Modra  <amodra@gmail.com>
 268             Peter Bergner  <bergner@linux.ibm.com>
 269
 270         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 271         New functions.
 272         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 273         YMSK2, XA6a, XA6ap, XB6a entries.
 274         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 275         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 276         (PPCVSX4): Define.
 277         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 278         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 279         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 280         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 281         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 282         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 283         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 284         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 285         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 286         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 287         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 288         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 289         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 290         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 291
 292 2020-05-11  Alan Modra  <amodra@gmail.com>
 293
 294         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 295         (insert_xts, extract_xts): New functions.
 296         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 297         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 298         (VXRC_MASK, VXSH_MASK): Define.
 299         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 300         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 301         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 302         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 303         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 304         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 305         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 306
 307 2020-05-11  Alan Modra  <amodra@gmail.com>
 308
 309         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 310         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 311         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 312         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 313         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 314
 315 2020-05-11  Alan Modra  <amodra@gmail.com>
 316
 317         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 318         (XTP, DQXP, DQXP_MASK): Define.
 319         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 320         (prefix_opcodes): Add plxvp and pstxvp.
 321
 322 2020-05-11  Alan Modra  <amodra@gmail.com>
 323
 324         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 325         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 326         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 327
 328 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 329
 330         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 331
 332 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 333
 334         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 335         (L1OPT): Define.
 336         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 337
 338 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 339
 340         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 341
 342 2020-05-11  Alan Modra  <amodra@gmail.com>
 343
 344         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 345
 346 2020-05-11  Alan Modra  <amodra@gmail.com>
 347
 348         * ppc-dis.c (ppc_opts): Add "power10" entry.
 349         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 350         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 351
 352 2020-05-11  Nick Clifton  <nickc@redhat.com>
 353
 354         * po/fr.po: Updated French translation.
 355
 356 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 357
 358         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 359         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 360         (operand_general_constraint_met_p): validate
 361         AARCH64_OPND_UNDEFINED.
 362         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 363         for FLD_imm16_2.
 364         * aarch64-asm-2.c: Regenerated.
 365         * aarch64-dis-2.c: Regenerated.
 366         * aarch64-opc-2.c: Regenerated.
 367
 368 2020-04-29  Nick Clifton  <nickc@redhat.com>
 369
 370         PR 22699
 371         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 372         and SETRC insns.
 373
 374 2020-04-29  Nick Clifton  <nickc@redhat.com>
 375
 376         * po/sv.po: Updated Swedish translation.
 377
 378 2020-04-29  Nick Clifton  <nickc@redhat.com>
 379
 380         PR 22699
 381         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 382         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 383         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 384         IMM0_8U case.
 385
 386 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 387
 388         PR 25848
 389         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 390         cmpi only on m68020up and cpu32.
 391
 392 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 393
 394         * aarch64-asm.c (aarch64_ins_none): New.
 395         * aarch64-asm.h (ins_none): New declaration.
 396         * aarch64-dis.c (aarch64_ext_none): New.
 397         * aarch64-dis.h (ext_none): New declaration.
 398         * aarch64-opc.c (aarch64_print_operand): Update case for
 399         AARCH64_OPND_BARRIER_PSB.
 400         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 401         (AARCH64_OPERANDS): Update inserter/extracter for
 402         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 403         * aarch64-asm-2.c: Regenerated.
 404         * aarch64-dis-2.c: Regenerated.
 405         * aarch64-opc-2.c: Regenerated.
 406
 407 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 408
 409         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 410         (aarch64_feature_ras, RAS): Likewise.
 411         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 412         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 413         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 414         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 415         * aarch64-asm-2.c: Regenerated.
 416         * aarch64-dis-2.c: Regenerated.
 417         * aarch64-opc-2.c: Regenerated.
 418
 419 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 420
 421         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 422         (print_insn_neon): Support disassembly of conditional
 423         instructions.
 424
 425 2020-02-16  David Faust  <david.faust@oracle.com>
 426
 427         * bpf-desc.c: Regenerate.
 428         * bpf-desc.h: Likewise.
 429         * bpf-opc.c: Regenerate.
 430         * bpf-opc.h: Likewise.
 431
 432 2020-04-07  Lili Cui  <lili.cui@intel.com>
 433
 434         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 435         (prefix_table): New instructions (see prefixes above).
 436         (rm_table): Likewise
 437         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 438         CPU_ANY_TSXLDTRK_FLAGS.
 439         (cpu_flags): Add CpuTSXLDTRK.
 440         * i386-opc.h (enum): Add CpuTSXLDTRK.
 441         (i386_cpu_flags): Add cputsxldtrk.
 442         * i386-opc.tbl: Add XSUSPLDTRK insns.
 443         * i386-init.h: Regenerate.
 444         * i386-tbl.h: Likewise.
 445
 446 2020-04-02  Lili Cui  <lili.cui@intel.com>
 447
 448         * i386-dis.c (prefix_table): New instructions serialize.
 449         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 450         CPU_ANY_SERIALIZE_FLAGS.
 451         (cpu_flags): Add CpuSERIALIZE.
 452         * i386-opc.h (enum): Add CpuSERIALIZE.
 453         (i386_cpu_flags): Add cpuserialize.
 454         * i386-opc.tbl: Add SERIALIZE insns.
 455         * i386-init.h: Regenerate.
 456         * i386-tbl.h: Likewise.
 457
 458 2020-03-26  Alan Modra  <amodra@gmail.com>
 459
 460         * disassemble.h (opcodes_assert): Declare.
 461         (OPCODES_ASSERT): Define.
 462         * disassemble.c: Don't include assert.h.  Include opintl.h.
 463         (opcodes_assert): New function.
 464         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 465         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 466         calculate maxlen.  Omit insn decoding when insn length exceeds
 467         maxlen.  Exit from nibble loop when looking for E, before
 468         accessing next data byte.  Move processing of E outside loop.
 469         Replace tests of maxlen in loop with assertions.
 470
 471 2020-03-26  Alan Modra  <amodra@gmail.com>
 472
 473         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 474
 475 2020-03-25  Alan Modra  <amodra@gmail.com>
 476
 477         * z80-dis.c (suffix): Init mybuf.
 478
 479 2020-03-22  Alan Modra  <amodra@gmail.com>
 480
 481         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 482         successflly read from section.
 483
 484 2020-03-22  Alan Modra  <amodra@gmail.com>
 485
 486         * arc-dis.c (find_format): Use ISO C string concatenation rather
 487         than line continuation within a string.  Don't access needs_limm
 488         before testing opcode != NULL.
 489
 490 2020-03-22  Alan Modra  <amodra@gmail.com>
 491
 492         * ns32k-dis.c (print_insn_arg): Update comment.
 493         (print_insn_ns32k): Reduce size of index_offset array, and
 494         initialize, passing -1 to print_insn_arg for args that are not
 495         an index.  Don't exit arg loop early.  Abort on bad arg number.
 496
 497 2020-03-22  Alan Modra  <amodra@gmail.com>
 498
 499         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 500         * s12z-opc.c: Formatting.
 501         (operands_f): Return an int.
 502         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 503         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 504         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 505         (exg_sex_discrim): Likewise.
 506         (create_immediate_operand, create_bitfield_operand),
 507         (create_register_operand_with_size, create_register_all_operand),
 508         (create_register_all16_operand, create_simple_memory_operand),
 509         (create_memory_operand, create_memory_auto_operand): Don't
 510         segfault on malloc failure.
 511         (z_ext24_decode): Return an int status, negative on fail, zero
 512         on success.
 513         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 514         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 515         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 516         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 517         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 518         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 519         (loop_primitive_decode, shift_decode, psh_pul_decode),
 520         (bit_field_decode): Similarly.
 521         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 522         to return value, update callers.
 523         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 524         Don't segfault on NULL operand.
 525         (decode_operation): Return OP_INVALID on first fail.
 526         (decode_s12z): Check all reads, returning -1 on fail.
 527
 528 2020-03-20  Alan Modra  <amodra@gmail.com>
 529
 530         * metag-dis.c (print_insn_metag): Don't ignore status from
 531         read_memory_func.
 532
 533 2020-03-20  Alan Modra  <amodra@gmail.com>
 534
 535         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 536         Initialize parts of buffer not written when handling a possible
 537         2-byte insn at end of section.  Don't attempt decoding of such
 538         an insn by the 4-byte machinery.
 539
 540 2020-03-20  Alan Modra  <amodra@gmail.com>
 541
 542         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 543         partially filled buffer.  Prevent lookup of 4-byte insns when
 544         only VLE 2-byte insns are possible due to section size.  Print
 545         ".word" rather than ".long" for 2-byte leftovers.
 546
 547 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 548
 549         PR 25641
 550         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 551
 552 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 553
 554         * i386-dis.c (X86_64_0D): Rename to ...
 555         (X86_64_0E): ... this.
 556
 557 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 558
 559         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 560         * Makefile.in: Regenerated.
 561
 562 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 563
 564         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 565         3-operand pseudos.
 566         * i386-tbl.h: Re-generate.
 567
 568 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 571         vprot*, vpsha*, and vpshl*.
 572         * i386-tbl.h: Re-generate.
 573
 574 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 575
 576         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 577         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 578         * i386-tbl.h: Re-generate.
 579
 580 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 581
 582         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 583         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 584         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 585         * i386-tbl.h: Re-generate.
 586
 587 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-gen.c (struct template_arg, struct template_instance,
 590         struct template_param, struct template, templates,
 591         parse_template, expand_templates): New.
 592         (process_i386_opcodes): Various local variables moved to
 593         expand_templates. Call parse_template and expand_templates.
 594         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 595         * i386-tbl.h: Re-generate.
 596
 597 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 600         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 601         register and memory source templates. Replace VexW= by VexW*
 602         where applicable.
 603         * i386-tbl.h: Re-generate.
 604
 605 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 606
 607         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 608         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 609         * i386-tbl.h: Re-generate.
 610
 611 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 614         * i386-tbl.h: Re-generate.
 615
 616 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 619         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 620         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 621         VexW0 on SSE2AVX variants.
 622         (vmovq): Drop NoRex64 from XMM/XMM variants.
 623         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 624         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 625         applicable use VexW0.
 626         * i386-tbl.h: Re-generate.
 627
 628 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 629
 630         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 631         * i386-opc.h (Rex64): Delete.
 632         (struct i386_opcode_modifier): Remove rex64 field.
 633         * i386-opc.tbl (crc32): Drop Rex64.
 634         Replace Rex64 with Size64 everywhere else.
 635         * i386-tbl.h: Re-generate.
 636
 637 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-dis.c (OP_E_memory): Exclude recording of used address
 640         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 641         addressed memory operands for MPX insns.
 642
 643 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 644
 645         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 646         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 647         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 648         (ptwrite): Split into non-64-bit and 64-bit forms.
 649         * i386-tbl.h: Re-generate.
 650
 651 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 654         template.
 655         * i386-tbl.h: Re-generate.
 656
 657 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 660         (prefix_table): Move vmmcall here. Add vmgexit.
 661         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 662         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 663         (cpu_flags): Add CpuSEV_ES entry.
 664         * i386-opc.h (CpuSEV_ES): New.
 665         (union i386_cpu_flags): Add cpusev_es field.
 666         * i386-opc.tbl (vmgexit): New.
 667         * i386-init.h, i386-tbl.h: Re-generate.
 668
 669 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 670
 671         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 672         with MnemonicSize.
 673         * i386-opc.h (IGNORESIZE): New.
 674         (DEFAULTSIZE): Likewise.
 675         (IgnoreSize): Removed.
 676         (DefaultSize): Likewise.
 677         (MnemonicSize): New.
 678         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 679         mnemonicsize.
 680         * i386-opc.tbl (IgnoreSize): New.
 681         (DefaultSize): Likewise.
 682         * i386-tbl.h: Regenerated.
 683
 684 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 685
 686         PR 25627
 687         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 688         instructions.
 689
 690 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 691
 692         PR gas/25622
 693         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 694         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 695         * i386-tbl.h: Regenerated.
 696
 697 2020-02-26  Alan Modra  <amodra@gmail.com>
 698
 699         * aarch64-asm.c: Indent labels correctly.
 700         * aarch64-dis.c: Likewise.
 701         * aarch64-gen.c: Likewise.
 702         * aarch64-opc.c: Likewise.
 703         * alpha-dis.c: Likewise.
 704         * i386-dis.c: Likewise.
 705         * nds32-asm.c: Likewise.
 706         * nfp-dis.c: Likewise.
 707         * visium-dis.c: Likewise.
 708
 709 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 710
 711         * arc-regs.h (int_vector_base): Make it available for all ARC
 712         CPUs.
 713
 714 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 715
 716         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 717         changed.
 718
 719 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 720
 721         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 722         c.mv/c.li if rs1 is zero.
 723
 724 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 725
 726         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 727         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 728         CPU_POPCNT_FLAGS.
 729         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 730         * i386-opc.h (CpuABM): Removed.
 731         (CpuPOPCNT): New.
 732         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 733         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 734         popcnt.  Remove CpuABM from lzcnt.
 735         * i386-init.h: Regenerated.
 736         * i386-tbl.h: Likewise.
 737
 738 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 739
 740         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 741         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 742         VexW1 instead of open-coding them.
 743         * i386-tbl.h: Re-generate.
 744
 745 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 746
 747         * i386-opc.tbl (AddrPrefixOpReg): Define.
 748         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 749         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 750         templates. Drop NoRex64.
 751         * i386-tbl.h: Re-generate.
 752
 753 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 754
 755         PR gas/6518
 756         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 757         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 758         into Intel syntax instance (with Unpsecified) and AT&T one
 759         (without).
 760         (vcvtneps2bf16): Likewise, along with folding the two so far
 761         separate ones.
 762         * i386-tbl.h: Re-generate.
 763
 764 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 765
 766         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 767         CPU_ANY_SSE4A_FLAGS.
 768
 769 2020-02-17  Alan Modra  <amodra@gmail.com>
 770
 771         * i386-gen.c (cpu_flag_init): Correct last change.
 772
 773 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 774
 775         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 776         CPU_ANY_SSE4_FLAGS.
 777
 778 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 779
 780         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 781         (movzx): Likewise.
 782
 783 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 784
 785         PR gas/25438
 786         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 787         destination for Cpu64-only variant.
 788         (movzx): Fold patterns.
 789         * i386-tbl.h: Re-generate.
 790
 791 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 792
 793         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 794         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 795         CPU_ANY_SSE4_FLAGS entry.
 796         * i386-init.h: Re-generate.
 797
 798 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 799
 800         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 801         with Unspecified, making the present one AT&T syntax only.
 802         * i386-tbl.h: Re-generate.
 803
 804 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 807         * i386-tbl.h: Re-generate.
 808
 809 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 810
 811         PR gas/24546
 812         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 813         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 814         Amd64 and Intel64 templates.
 815         (call, jmp): Likewise for far indirect variants. Dro
 816         Unspecified.
 817         * i386-tbl.h: Re-generate.
 818
 819 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 820
 821         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 822         * i386-opc.h (ShortForm): Delete.
 823         (struct i386_opcode_modifier): Remove shortform field.
 824         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 825         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 826         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 827         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 828         Drop ShortForm.
 829         * i386-tbl.h: Re-generate.
 830
 831 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 832
 833         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 834         fucompi): Drop ShortForm from operand-less templates.
 835         * i386-tbl.h: Re-generate.
 836
 837 2020-02-11  Alan Modra  <amodra@gmail.com>
 838
 839         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 840         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 841         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 842         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 843         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 844
 845 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 846
 847         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 848         (cde_opcodes): Add VCX* instructions.
 849
 850 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 851             Matthew Malcomson  <matthew.malcomson@arm.com>
 852
 853         * arm-dis.c (struct cdeopcode32): New.
 854         (CDE_OPCODE): New macro.
 855         (cde_opcodes): New disassembly table.
 856         (regnames): New option to table.
 857         (cde_coprocs): New global variable.
 858         (print_insn_cde): New
 859         (print_insn_thumb32): Use print_insn_cde.
 860         (parse_arm_disassembler_options): Parse coprocN args.
 861
 862 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 863
 864         PR gas/25516
 865         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 866         with ISA64.
 867         * i386-opc.h (AMD64): Removed.
 868         (Intel64): Likewose.
 869         (AMD64): New.
 870         (INTEL64): Likewise.
 871         (INTEL64ONLY): Likewise.
 872         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 873         * i386-opc.tbl (Amd64): New.
 874         (Intel64): Likewise.
 875         (Intel64Only): Likewise.
 876         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 877         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 878         * i386-tbl.h: Regenerated.
 879
 880 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 881
 882         PR 25469
 883         * z80-dis.c: Add support for GBZ80 opcodes.
 884
 885 2020-02-04  Alan Modra  <amodra@gmail.com>
 886
 887         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 888
 889 2020-02-03  Alan Modra  <amodra@gmail.com>
 890
 891         * m32c-ibld.c: Regenerate.
 892
 893 2020-02-01  Alan Modra  <amodra@gmail.com>
 894
 895         * frv-ibld.c: Regenerate.
 896
 897 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 898
 899         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 900         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 901         (OP_E_memory): Replace xmm_mdq_mode case label by
 902         vex_scalar_w_dq_mode one.
 903         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 904
 905 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 906
 907         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 908         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 909         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 910         (intel_operand_size): Drop vex_w_dq_mode case label.
 911
 912 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 913
 914         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 915         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 916
 917 2020-01-30  Alan Modra  <amodra@gmail.com>
 918
 919         * m32c-ibld.c: Regenerate.
 920
 921 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 922
 923         * bpf-opc.c: Regenerate.
 924
 925 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 926
 927         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 928         (dis386): Use them to replace C2/C3 table entries.
 929         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 930         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 931         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 932         * i386-tbl.h: Re-generate.
 933
 934 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 937         forms.
 938         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 939         DefaultSize.
 940         * i386-tbl.h: Re-generate.
 941
 942 2020-01-30  Alan Modra  <amodra@gmail.com>
 943
 944         * tic4x-dis.c (tic4x_dp): Make unsigned.
 945
 946 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 947             Jan Beulich  <jbeulich@suse.com>
 948
 949         PR binutils/25445
 950         * i386-dis.c (MOVSXD_Fixup): New function.
 951         (movsxd_mode): New enum.
 952         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 953         (intel_operand_size): Handle movsxd_mode.
 954         (OP_E_register): Likewise.
 955         (OP_G): Likewise.
 956         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 957         register on movsxd.  Add movsxd with 16-bit destination register
 958         for AMD64 and Intel64 ISAs.
 959         * i386-tbl.h: Regenerated.
 960
 961 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 962
 963         PR 25403
 964         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 965         * aarch64-asm-2.c: Regenerate
 966         * aarch64-dis-2.c: Likewise.
 967         * aarch64-opc-2.c: Likewise.
 968
 969 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-opc.tbl (sysret): Drop DefaultSize.
 972         * i386-tbl.h: Re-generate.
 973
 974 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 975
 976         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 977         Dword.
 978         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 979         * i386-tbl.h: Re-generate.
 980
 981 2020-01-20  Nick Clifton  <nickc@redhat.com>
 982
 983         * po/de.po: Updated German translation.
 984         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 985         * po/uk.po: Updated Ukranian translation.
 986
 987 2020-01-20  Alan Modra  <amodra@gmail.com>
 988
 989         * hppa-dis.c (fput_const): Remove useless cast.
 990
 991 2020-01-20  Alan Modra  <amodra@gmail.com>
 992
 993         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 994
 995 2020-01-18  Nick Clifton  <nickc@redhat.com>
 996
 997         * configure: Regenerate.
 998         * po/opcodes.pot: Regenerate.
 999
1000 2020-01-18  Nick Clifton  <nickc@redhat.com>
1001
1002         Binutils 2.34 branch created.
1003
1004 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1005
1006         * opintl.h: Fix spelling error (seperate).
1007
1008 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1009
1010         * i386-opc.tbl: Add {vex} pseudo prefix.
1011         * i386-tbl.h: Regenerated.
1012
1013 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1014
1015         PR 25376
1016         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1017         (neon_opcodes): Likewise.
1018         (select_arm_features): Make sure we enable MVE bits when selecting
1019         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1020         any architecture.
1021
1022 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1023
1024         * i386-opc.tbl: Drop stale comment from XOP section.
1025
1026 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1027
1028         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1029         (extractps): Add VexWIG to SSE2AVX forms.
1030         * i386-tbl.h: Re-generate.
1031
1032 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1035         Size64 from and use VexW1 on SSE2AVX forms.
1036         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1037         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1038         * i386-tbl.h: Re-generate.
1039
1040 2020-01-15  Alan Modra  <amodra@gmail.com>
1041
1042         * tic4x-dis.c (tic4x_version): Make unsigned long.
1043         (optab, optab_special, registernames): New file scope vars.
1044         (tic4x_print_register): Set up registernames rather than
1045         malloc'd registertable.
1046         (tic4x_disassemble): Delete optable and optable_special.  Use
1047         optab and optab_special instead.  Throw away old optab,
1048         optab_special and registernames when info->mach changes.
1049
1050 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1051
1052         PR 25377
1053         * z80-dis.c (suffix): Use .db instruction to generate double
1054         prefix.
1055
1056 2020-01-14  Alan Modra  <amodra@gmail.com>
1057
1058         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1059         values to unsigned before shifting.
1060
1061 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1062
1063         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1064         flow instructions.
1065         (print_insn_thumb16, print_insn_thumb32): Likewise.
1066         (print_insn): Initialize the insn info.
1067         * i386-dis.c (print_insn): Initialize the insn info fields, and
1068         detect jumps.
1069
1070 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1071
1072         * arc-opc.c (C_NE): Make it required.
1073
1074 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1075
1076         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1077         reserved register name.
1078
1079 2020-01-13  Alan Modra  <amodra@gmail.com>
1080
1081         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1082         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1083
1084 2020-01-13  Alan Modra  <amodra@gmail.com>
1085
1086         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1087         result of wasm_read_leb128 in a uint64_t and check that bits
1088         are not lost when copying to other locals.  Use uint32_t for
1089         most locals.  Use PRId64 when printing int64_t.
1090
1091 2020-01-13  Alan Modra  <amodra@gmail.com>
1092
1093         * score-dis.c: Formatting.
1094         * score7-dis.c: Formatting.
1095
1096 2020-01-13  Alan Modra  <amodra@gmail.com>
1097
1098         * score-dis.c (print_insn_score48): Use unsigned variables for
1099         unsigned values.  Don't left shift negative values.
1100         (print_insn_score32): Likewise.
1101         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1102
1103 2020-01-13  Alan Modra  <amodra@gmail.com>
1104
1105         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1106
1107 2020-01-13  Alan Modra  <amodra@gmail.com>
1108
1109         * fr30-ibld.c: Regenerate.
1110
1111 2020-01-13  Alan Modra  <amodra@gmail.com>
1112
1113         * xgate-dis.c (print_insn): Don't left shift signed value.
1114         (ripBits): Formatting, use 1u.
1115
1116 2020-01-10  Alan Modra  <amodra@gmail.com>
1117
1118         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1119         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1120
1121 2020-01-10  Alan Modra  <amodra@gmail.com>
1122
1123         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1124         and XRREG value earlier to avoid a shift with negative exponent.
1125         * m10200-dis.c (disassemble): Similarly.
1126
1127 2020-01-09  Nick Clifton  <nickc@redhat.com>
1128
1129         PR 25224
1130         * z80-dis.c (ld_ii_ii): Use correct cast.
1131
1132 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1133
1134         PR 25224
1135         * z80-dis.c (ld_ii_ii): Use character constant when checking
1136         opcode byte value.
1137
1138 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1139
1140         * i386-dis.c (SEP_Fixup): New.
1141         (SEP): Define.
1142         (dis386_twobyte): Use it for sysenter/sysexit.
1143         (enum x86_64_isa): Change amd64 enumerator to value 1.
1144         (OP_J): Compare isa64 against intel64 instead of amd64.
1145         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1146         forms.
1147         * i386-tbl.h: Re-generate.
1148
1149 2020-01-08  Alan Modra  <amodra@gmail.com>
1150
1151         * z8k-dis.c: Include libiberty.h
1152         (instr_data_s): Make max_fetched unsigned.
1153         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1154         Don't exceed byte_info bounds.
1155         (output_instr): Make num_bytes unsigned.
1156         (unpack_instr): Likewise for nibl_count and loop.
1157         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1158         idx unsigned.
1159         * z8k-opc.h: Regenerate.
1160
1161 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1162
1163         * arc-tbl.h (llock): Use 'LLOCK' as class.
1164         (llockd): Likewise.
1165         (scond): Use 'SCOND' as class.
1166         (scondd): Likewise.
1167         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1168         (scondd): Likewise.
1169
1170 2020-01-06  Alan Modra  <amodra@gmail.com>
1171
1172         * m32c-ibld.c: Regenerate.
1173
1174 2020-01-06  Alan Modra  <amodra@gmail.com>
1175
1176         PR 25344
1177         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1178         Peek at next byte to prevent recursion on repeated prefix bytes.
1179         Ensure uninitialised "mybuf" is not accessed.
1180         (print_insn_z80): Don't zero n_fetch and n_used here,..
1181         (print_insn_z80_buf): ..do it here instead.
1182
1183 2020-01-04  Alan Modra  <amodra@gmail.com>
1184
1185         * m32r-ibld.c: Regenerate.
1186
1187 2020-01-04  Alan Modra  <amodra@gmail.com>
1188
1189         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1190
1191 2020-01-04  Alan Modra  <amodra@gmail.com>
1192
1193         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1194
1195 2020-01-04  Alan Modra  <amodra@gmail.com>
1196
1197         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1198
1199 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1200
1201         * aarch64-tbl.h (aarch64_opcode_table): Use
1202         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1203
1204 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1205
1206         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1207         forms of SUDOT and USDOT.
1208
1209 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1210
1211         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1212         uzip{1,2}.
1213         * opcodes/aarch64-dis-2.c: Re-generate.
1214
1215 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1216
1217         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1218         FMMLA encoding.
1219         * opcodes/aarch64-dis-2.c: Re-generate.
1220
1221 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1222
1223         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1224
1225 2020-01-01  Alan Modra  <amodra@gmail.com>
1226
1227         Update year range in copyright notice of all files.
1228
1229 For older changes see ChangeLog-2019
1230 \f
1231 Copyright (C) 2020 Free Software Foundation, Inc.
1232
1233 Copying and distribution of this file, with or without modification,
1234 are permitted in any medium without royalty provided the copyright
1235 notice and this notice are preserved.
1236
1237 Local Variables:
1238 mode: change-log
1239 left-margin: 8
1240 fill-column: 74
1241 version-control: never
1242 End: