opcodes/ChangeLog

   1 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
   4         AARCH64_OPND_QLF_P_[ZM].
   5         (aarch64_print_operand): Print /z and /m where appropriate.
   6
   7 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
   8
   9         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
  10         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
  11         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
  12         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
  13         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
  14         * aarch64-opc.c (fields): Add corresponding entries here.
  15         (operand_general_constraint_met_p): Check that SVE register lists
  16         have the correct length.  Check the ranges of SVE index registers.
  17         Check for cases where p8-p15 are used in 3-bit predicate fields.
  18         (aarch64_print_operand): Handle the new SVE operands.
  19         * aarch64-opc-2.c: Regenerate.
  20         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
  21         * aarch64-asm.c (aarch64_ins_sve_index): New function.
  22         (aarch64_ins_sve_reglist): Likewise.
  23         * aarch64-asm-2.c: Regenerate.
  24         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
  25         * aarch64-dis.c (aarch64_ext_sve_index): New function.
  26         (aarch64_ext_sve_reglist): Likewise.
  27         * aarch64-dis-2.c: Regenerate.
  28
  29 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  30
  31         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
  32         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
  33         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
  34         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
  35         tied operands.
  36
  37 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  38
  39         * aarch64-opc.c (get_offset_int_reg_name): New function.
  40         (print_immediate_offset_address): Likewise.
  41         (print_register_offset_address): Take the base and offset
  42         registers as parameters.
  43         (aarch64_print_operand): Update caller accordingly.  Use
  44         print_immediate_offset_address.
  45
  46 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  47
  48         * aarch64-opc.c (BANK): New macro.
  49         (R32, R64): Take a register number as argument
  50         (int_reg): Use BANK.
  51
  52 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  53
  54         * aarch64-opc.c (print_register_list): Add a prefix parameter.
  55         (aarch64_print_operand): Update accordingly.
  56
  57 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  58
  59         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
  60         for FPIMM.
  61         * aarch64-asm.h (ins_fpimm): New inserter.
  62         * aarch64-asm.c (aarch64_ins_fpimm): New function.
  63         * aarch64-asm-2.c: Regenerate.
  64         * aarch64-dis.h (ext_fpimm): New extractor.
  65         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
  66         (aarch64_ext_fpimm): New function.
  67         * aarch64-dis-2.c: Regenerate.
  68
  69 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  70
  71         * aarch64-asm.c: Include libiberty.h.
  72         (insert_fields): New function.
  73         (aarch64_ins_imm): Use it.
  74         * aarch64-dis.c (extract_fields): New function.
  75         (aarch64_ext_imm): Use it.
  76
  77 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  78
  79         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
  80         with an esize parameter.
  81         (operand_general_constraint_met_p): Update accordingly.
  82         Fix misindented code.
  83         * aarch64-asm.c (aarch64_ins_limm): Update call to
  84         aarch64_logical_immediate_p.
  85
  86 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  87
  88         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
  89
  90 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  91
  92         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
  93
  94 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
  95
  96         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
  97
  98 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
  99
 100         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 101         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 102         xor3>: Delete mnemonics.
 103         <cp_abort>: Rename mnemonic from ...
 104         <cpabort>: ...to this.
 105         <setb>: Change to a X form instruction.
 106         <sync>: Change to 1 operand form.
 107         <copy>: Delete mnemonic.
 108         <copy_first>: Rename mnemonic from ...
 109         <copy>: ...to this.
 110         <paste, paste.>: Delete mnemonics.
 111         <paste_last>: Rename mnemonic from ...
 112         <paste.>: ...to this.
 113
 114 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 115
 116         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 117
 118 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 119
 120         * s390-mkopc.c (main): Support alternate arch strings.
 121
 122 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 123
 124         * s390-opc.txt: Fix kmctr instruction type.
 125
 126 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 127
 128         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 129         * i386-init.h: Regenerated.
 130
 131 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 132
 133         * opcodes/arc-dis.c (print_insn_arc): Changed.
 134
 135 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 136
 137         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 138         camellia_fl.
 139
 140 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 141
 142         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 143         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 144         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 145
 146 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 147
 148         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 149         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 150         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 151         PREFIX_MOD_3_0FAE_REG_4.
 152         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 153         PREFIX_MOD_3_0FAE_REG_4.
 154         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 155         (cpu_flags): Add CpuPTWRITE.
 156         * i386-opc.h (CpuPTWRITE): New.
 157         (i386_cpu_flags): Add cpuptwrite.
 158         * i386-opc.tbl: Add ptwrite instruction.
 159         * i386-init.h: Regenerated.
 160         * i386-tbl.h: Likewise.
 161
 162 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 163
 164         * arc-dis.h: Wrap around in extern "C".
 165
 166 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 167
 168         * aarch64-tbl.h (V8_2_INSN): New macro.
 169         (aarch64_opcode_table): Use it.
 170
 171 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 172
 173         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 174         CORE_INSN, __FP_INSN and SIMD_INSN.
 175
 176 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 177
 178         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 179         (aarch64_opcode_table): Update uses accordingly.
 180
 181 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 182         Kwok Cheung Yeung  <kcy@codesourcery.com>
 183
 184         opcodes/
 185         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 186         'e_cmplwi' to 'e_cmpli' instead.
 187         (OPVUPRT, OPVUPRT_MASK): Define.
 188         (powerpc_opcodes): Add E200Z4 insns.
 189         (vle_opcodes): Add context save/restore insns.
 190
 191 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 192
 193         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 194         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 195         "j".
 196
 197 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 198
 199         * arc-nps400-tbl.h: Change block comments to GNU format.
 200         * arc-dis.c: Add new globals addrtypenames,
 201         addrtypenames_max, and addtypeunknown.
 202         (get_addrtype): New function.
 203         (print_insn_arc): Print colons and address types when
 204         required.
 205         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 206         define insert and extract functions for all address types.
 207         (arc_operands): Add operands for colon and all address
 208         types.
 209         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 210         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 211         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 212         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 213         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 214         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 215
 216 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 217
 218         * configure: Regenerated.
 219
 220 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 221
 222         * arc-dis.c (skipclass): New structure.
 223         (decodelist): New variable.
 224         (is_compatible_p): New function.
 225         (new_element): Likewise.
 226         (skip_class_p): Likewise.
 227         (find_format_from_table): Use skip_class_p function.
 228         (find_format): Decode first the extension instructions.
 229         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 230         e_flags.
 231         (parse_option): New function.
 232         (parse_disassembler_options): Likewise.
 233         (print_arc_disassembler_options): Likewise.
 234         (print_insn_arc): Use parse_disassembler_options function.  Proper
 235         select ARCv2 cpu variant.
 236         * disassemble.c (disassembler_usage): Add ARC disassembler
 237         options.
 238
 239 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 240
 241         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 242         annotation from the "nal" entry and reorder it beyond "bltzal".
 243
 244 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 245
 246         * sparc-opc.c (ldtxa): New macro.
 247         (sparc_opcodes): Use the macro defined above to add entries for
 248         the LDTXA instructions.
 249         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 250         instruction.
 251
 252 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 253
 254         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 255         and "jmpc".
 256
 257 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 258
 259         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 260         (movzb): Adjust to cover all permitted suffixes.
 261         (movzw): New.
 262         * i386-tbl.h: Re-generate.
 263
 264 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 267         (lgdt): Remove Tbyte from non-64-bit variant.
 268         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 269         xsaves64, xsavec64): Remove Disp16.
 270         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 271         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 272         64-bit variants.
 273         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 274         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 275         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 276         64-bit variants.
 277         * i386-tbl.h: Re-generate.
 278
 279 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 280
 281         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 282         * i386-tbl.h: Re-generate.
 283
 284 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 285
 286         * arm-dis.c (print_insn): Fix typo in comment.
 287
 288 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 289
 290         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 291         range of ldst_elemlist operands.
 292         (print_register_list): Use PRIi64 to print the index.
 293         (aarch64_print_operand): Likewise.
 294
 295 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 296
 297         * mcore-opc.h: Remove sentinal.
 298         * mcore-dis.c (print_insn_mcore): Adjust.
 299
 300 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 301
 302         * arc-opc.c: Correct description of availability of NPS400
 303         features.
 304
 305 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 306
 307         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 308         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 309         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 310         xor3>: New mnemonics.
 311         <setb>: Change to a VX form instruction.
 312         (insert_sh6): Add support for rldixor.
 313         (extract_sh6): Likewise.
 314
 315 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 316
 317         * arc-ext.h: Wrap in extern C.
 318
 319 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 320
 321         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 322         Use same method for determining instruction length on ARC700 and
 323         NPS-400.
 324         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 325         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 326         with the NPS400 subclass.
 327         * arc-opc.c: Likewise.
 328
 329 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 330
 331         * sparc-opc.c (rdasr): New macro.
 332         (wrasr): Likewise.
 333         (rdpr): Likewise.
 334         (wrpr): Likewise.
 335         (rdhpr): Likewise.
 336         (wrhpr): Likewise.
 337         (sparc_opcodes): Use the macros above to fix and expand the
 338         definition of read/write instructions from/to
 339         asr/privileged/hyperprivileged instructions.
 340         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 341         %hva_mask_nz.  Prefer softint_set and softint_clear over
 342         set_softint and clear_softint.
 343         (print_insn_sparc): Support %ver in Rd.
 344
 345 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 346
 347         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 348         architecture according to the hardware capabilities they require.
 349
 350 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 351
 352         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 353         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 354         bfd_mach_sparc_v9{c,d,e,v,m}.
 355         * sparc-opc.c (MASK_V9C): Define.
 356         (MASK_V9D): Likewise.
 357         (MASK_V9E): Likewise.
 358         (MASK_V9V): Likewise.
 359         (MASK_V9M): Likewise.
 360         (v6): Add MASK_V9{C,D,E,V,M}.
 361         (v6notlet): Likewise.
 362         (v7): Likewise.
 363         (v8): Likewise.
 364         (v9): Likewise.
 365         (v9andleon): Likewise.
 366         (v9a): Likewise.
 367         (v9b): Likewise.
 368         (v9c): Define.
 369         (v9d): Likewise.
 370         (v9e): Likewise.
 371         (v9v): Likewise.
 372         (v9m): Likewise.
 373         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 374
 375 2016-06-15  Nick Clifton  <nickc@redhat.com>
 376
 377         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 378         constants to match expected behaviour.
 379         (nds32_parse_opcode): Likewise.  Also for whitespace.
 380
 381 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 382
 383         * arc-opc.c (extract_rhv1): Extract value from insn.
 384
 385 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 386
 387         * arc-nps400-tbl.h: Add ldbit instruction.
 388         * arc-opc.c: Add flag classes required for ldbit.
 389
 390 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 391
 392         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 393         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 394         support the above instructions.
 395
 396 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 397
 398         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 399         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 400         csma, cbba, zncv, and hofs.
 401         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 402         support the above instructions.
 403
 404 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 405
 406         * arc-nps400-tbl.h: Add andab and orab instructions.
 407
 408 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 409
 410         * arc-nps400-tbl.h: Add addl-like instructions.
 411
 412 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 413
 414         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 415
 416 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 417
 418         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 419         instructions.
 420
 421 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 422
 423         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 424         variable.
 425         (init_disasm): Handle new command line option "insnlength".
 426         (print_s390_disassembler_options): Mention new option in help
 427         output.
 428         (print_insn_s390): Use the encoded insn length when dumping
 429         unknown instructions.
 430
 431 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 432
 433         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 434          to the address and set as symbol address for LDS/ STS immediate operands.
 435
 436 2016-06-07  Alan Modra  <amodra@gmail.com>
 437
 438         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 439         cpu for "vle" to e500.
 440         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 441         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 442         (PPCNONE): Delete, substitute throughout.
 443         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 444         except for major opcode 4 and 31.
 445         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 446
 447 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 448
 449         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 450         ARM_EXT_RAS in relevant entries.
 451
 452 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 453
 454         PR binutils/20196
 455         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 456         opcodes for E6500.
 457
 458 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         PR binutis/18386
 461         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 462         (indir_v_mode): New.
 463         Add comments for '&'.
 464         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 465         (putop): Handle '&'.
 466         (intel_operand_size): Handle indir_v_mode.
 467         (OP_E_register): Likewise.
 468         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 469         64-bit indirect call/jmp for AMD64.
 470         * i386-tbl.h: Regenerated
 471
 472 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 473
 474         * arc-dis.c (struct arc_operand_iterator): New structure.
 475         (find_format_from_table): All the old content from find_format,
 476         with some minor adjustments, and parameter renaming.
 477         (find_format_long_instructions): New function.
 478         (find_format): Rewritten.
 479         (arc_insn_length): Add LSB parameter.
 480         (extract_operand_value): New function.
 481         (operand_iterator_next): New function.
 482         (print_insn_arc): Use new functions to find opcode, and iterator
 483         over operands.
 484         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 485         (extract_nps_3bit_dst_short): New function.
 486         (insert_nps_3bit_src2_short): New function.
 487         (extract_nps_3bit_src2_short): New function.
 488         (insert_nps_bitop1_size): New function.
 489         (extract_nps_bitop1_size): New function.
 490         (insert_nps_bitop2_size): New function.
 491         (extract_nps_bitop2_size): New function.
 492         (insert_nps_bitop_mod4_msb): New function.
 493         (extract_nps_bitop_mod4_msb): New function.
 494         (insert_nps_bitop_mod4_lsb): New function.
 495         (extract_nps_bitop_mod4_lsb): New function.
 496         (insert_nps_bitop_dst_pos3_pos4): New function.
 497         (extract_nps_bitop_dst_pos3_pos4): New function.
 498         (insert_nps_bitop_ins_ext): New function.
 499         (extract_nps_bitop_ins_ext): New function.
 500         (arc_operands): Add new operands.
 501         (arc_long_opcodes): New global array.
 502         (arc_num_long_opcodes): New global.
 503         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 504
 505 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 506
 507         * nds32-asm.h: Add extern "C".
 508         * sh-opc.h: Likewise.
 509
 510 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 511
 512         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 513         0,b,limm to the rflt instruction.
 514
 515 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 516
 517         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 518         constant.
 519
 520 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 521
 522         PR gas/20145
 523         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 524         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 525         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 526         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 527         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 528         * i386-init.h: Regenerated.
 529
 530 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 531
 532         PR gas/20145
 533         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 534         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 535         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 536         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 537         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 538         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 539         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 540         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 541         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 542         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 543         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 544         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 545         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 546         CpuRegMask for AVX512.
 547         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 548         and CpuRegMask.
 549         (set_bitfield_from_cpu_flag_init): New function.
 550         (set_bitfield): Remove const on f.  Call
 551         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 552         * i386-opc.h (CpuRegMMX): New.
 553         (CpuRegXMM): Likewise.
 554         (CpuRegYMM): Likewise.
 555         (CpuRegZMM): Likewise.
 556         (CpuRegMask): Likewise.
 557         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 558         and cpuregmask.
 559         * i386-init.h: Regenerated.
 560         * i386-tbl.h: Likewise.
 561
 562 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 563
 564         PR gas/20154
 565         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 566         (opcode_modifiers): Add AMD64 and Intel64.
 567         (main): Properly verify CpuMax.
 568         * i386-opc.h (CpuAMD64): Removed.
 569         (CpuIntel64): Likewise.
 570         (CpuMax): Set to CpuNo64.
 571         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 572         (AMD64): New.
 573         (Intel64): Likewise.
 574         (i386_opcode_modifier): Add amd64 and intel64.
 575         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 576         on call and jmp.
 577         * i386-init.h: Regenerated.
 578         * i386-tbl.h: Likewise.
 579
 580 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 581
 582         PR gas/20154
 583         * i386-gen.c (main): Fail if CpuMax is incorrect.
 584         * i386-opc.h (CpuMax): Set to CpuIntel64.
 585         * i386-tbl.h: Regenerated.
 586
 587 2016-05-27  Nick Clifton  <nickc@redhat.com>
 588
 589         PR target/20150
 590         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 591         (msp430dis_opcode_unsigned): New function.
 592         (msp430dis_opcode_signed): New function.
 593         (msp430_singleoperand): Use the new opcode reading functions.
 594         Only disassenmble bytes if they were successfully read.
 595         (msp430_doubleoperand): Likewise.
 596         (msp430_branchinstr): Likewise.
 597         (msp430x_callx_instr): Likewise.
 598         (print_insn_msp430): Check that it is safe to read bytes before
 599         attempting disassembly.  Use the new opcode reading functions.
 600
 601 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 602
 603         * ppc-opc.c (CY): New define.  Document it.
 604         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 605
 606 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 607
 608         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 609         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 610         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 611         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 612         CPU_ANY_AVX_FLAGS.
 613         * i386-init.h: Regenerated.
 614
 615 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 616
 617         PR gas/20141
 618         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 619         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 620         * i386-init.h: Regenerated.
 621
 622 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 623
 624         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 625         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 626         * i386-init.h: Regenerated.
 627
 628 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 629
 630         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 631         information.
 632         (print_insn_arc): Set insn_type information.
 633         * arc-opc.c (C_CC): Add F_CLASS_COND.
 634         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 635         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 636         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 637         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 638         (brne, brne_s, jeq_s, jne_s): Likewise.
 639
 640 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 641
 642         * arc-tbl.h (neg): New instruction variant.
 643
 644 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 645
 646         * arc-dis.c (find_format, find_format, get_auxreg)
 647         (print_insn_arc): Changed.
 648         * arc-ext.h (INSERT_XOP): Likewise.
 649
 650 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 651
 652         * tic54x-dis.c (sprint_mmr): Adjust.
 653         * tic54x-opc.c: Likewise.
 654
 655 2016-05-19  Alan Modra  <amodra@gmail.com>
 656
 657         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 658
 659 2016-05-19  Alan Modra  <amodra@gmail.com>
 660
 661         * ppc-opc.c: Formatting.
 662         (NSISIGNOPT): Define.
 663         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 664
 665 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 666
 667         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 668         replacing references to `micromips_ase' throughout.
 669         (_print_insn_mips): Don't use file-level microMIPS annotation to
 670         determine the disassembly mode with the symbol table.
 671
 672 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 673
 674         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 675
 676 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 677
 678         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 679         mips64r6.
 680         * mips-opc.c (D34): New macro.
 681         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 682
 683 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 684
 685         * i386-dis.c (prefix_table): Add RDPID instruction.
 686         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 687         (cpu_flags): Add RDPID bitfield.
 688         * i386-opc.h (enum): Add RDPID element.
 689         (i386_cpu_flags): Add RDPID field.
 690         * i386-opc.tbl: Add RDPID instruction.
 691         * i386-init.h: Regenerate.
 692         * i386-tbl.h: Regenerate.
 693
 694 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 695
 696         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 697         branch type of a symbol.
 698         (print_insn): Likewise.
 699
 700 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 701
 702         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 703         Mainline Security Extensions instructions.
 704         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 705         Extensions instructions.
 706         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 707         instructions.
 708         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 709         special registers.
 710
 711 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 712
 713         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 714
 715 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 716
 717         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 718         (arcExtMap_genOpcode): Likewise.
 719         * arc-opc.c (arg_32bit_rc): Define new variable.
 720         (arg_32bit_u6): Likewise.
 721         (arg_32bit_limm): Likewise.
 722
 723 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 724
 725         * aarch64-gen.c (VERIFIER): Define.
 726         * aarch64-opc.c (VERIFIER): Define.
 727         (verify_ldpsw): Use static linkage.
 728         * aarch64-opc.h (verify_ldpsw): Remove.
 729         * aarch64-tbl.h: Use VERIFIER for verifiers.
 730
 731 2016-04-28  Nick Clifton  <nickc@redhat.com>
 732
 733         PR target/19722
 734         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 735         * aarch64-opc.c (verify_ldpsw): New function.
 736         * aarch64-opc.h (verify_ldpsw): New prototype.
 737         * aarch64-tbl.h: Add initialiser for verifier field.
 738         (LDPSW): Set verifier to verify_ldpsw.
 739
 740 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 741
 742         PR binutils/19983
 743         PR binutils/19984
 744         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 745         smaller than address size.
 746
 747 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 748
 749         * alpha-dis.c: Regenerate.
 750         * crx-dis.c: Likewise.
 751         * disassemble.c: Likewise.
 752         * epiphany-opc.c: Likewise.
 753         * fr30-opc.c: Likewise.
 754         * frv-opc.c: Likewise.
 755         * ip2k-opc.c: Likewise.
 756         * iq2000-opc.c: Likewise.
 757         * lm32-opc.c: Likewise.
 758         * lm32-opinst.c: Likewise.
 759         * m32c-opc.c: Likewise.
 760         * m32r-opc.c: Likewise.
 761         * m32r-opinst.c: Likewise.
 762         * mep-opc.c: Likewise.
 763         * mt-opc.c: Likewise.
 764         * or1k-opc.c: Likewise.
 765         * or1k-opinst.c: Likewise.
 766         * tic80-opc.c: Likewise.
 767         * xc16x-opc.c: Likewise.
 768         * xstormy16-opc.c: Likewise.
 769
 770 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 771
 772         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 773         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 774         calcsd, and calcxd instructions.
 775         * arc-opc.c (insert_nps_bitop_size): Delete.
 776         (extract_nps_bitop_size): Delete.
 777         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 778         (extract_nps_qcmp_m3): Define.
 779         (extract_nps_qcmp_m2): Define.
 780         (extract_nps_qcmp_m1): Define.
 781         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 782         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 783         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 784         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 785         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 786         NPS_QCMP_M3.
 787
 788 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 789
 790         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 791
 792 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 793
 794         * Makefile.in: Regenerated with automake 1.11.6.
 795         * aclocal.m4: Likewise.
 796
 797 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 798
 799         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 800         instructions.
 801         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 802         (extract_nps_cmem_uimm16): New function.
 803         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 804
 805 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 806
 807         * arc-dis.c (arc_insn_length): New function.
 808         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 809         (find_format): Change insnLen parameter to unsigned.
 810
 811 2016-04-13  Nick Clifton  <nickc@redhat.com>
 812
 813         PR target/19937
 814         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 815         the LD.B and LD.BU instructions.
 816
 817 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 818
 819         * arc-dis.c (find_format): Check for extension flags.
 820         (print_flags): New function.
 821         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 822         .extAuxRegister.
 823         * arc-ext.c (arcExtMap_coreRegName): Use
 824         LAST_EXTENSION_CORE_REGISTER.
 825         (arcExtMap_coreReadWrite): Likewise.
 826         (dump_ARC_extmap): Update printing.
 827         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 828         (arc_aux_regs): Add cpu field.
 829         * arc-regs.h: Add cpu field, lower case name aux registers.
 830
 831 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 832
 833         * arc-tbl.h: Add rtsc, sleep with no arguments.
 834
 835 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 836
 837         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 838         Initialize.
 839         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 840         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 841         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 842         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 843         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 844         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 845         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 846         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 847         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 848         (arc_opcode arc_opcodes): Null terminate the array.
 849         (arc_num_opcodes): Remove.
 850         * arc-ext.h (INSERT_XOP): Define.
 851         (extInstruction_t): Likewise.
 852         (arcExtMap_instName): Delete.
 853         (arcExtMap_insn): New function.
 854         (arcExtMap_genOpcode): Likewise.
 855         * arc-ext.c (ExtInstruction): Remove.
 856         (create_map): Zero initialize instruction fields.
 857         (arcExtMap_instName): Remove.
 858         (arcExtMap_insn): New function.
 859         (dump_ARC_extmap): More info while debuging.
 860         (arcExtMap_genOpcode): New function.
 861         * arc-dis.c (find_format): New function.
 862         (print_insn_arc): Use find_format.
 863         (arc_get_disassembler): Enable dump_ARC_extmap only when
 864         debugging.
 865
 866 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 867
 868         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 869         instruction bits out.
 870
 871 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 872
 873         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 874         * arc-opc.c (arc_flag_operands): Add new flags.
 875         (arc_flag_classes): Add new classes.
 876
 877 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 878
 879         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 880
 881 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 882
 883         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 884         encode1, rflt, crc16, and crc32 instructions.
 885         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 886         (arc_flag_classes): Add C_NPS_R.
 887         (insert_nps_bitop_size_2b): New function.
 888         (extract_nps_bitop_size_2b): Likewise.
 889         (insert_nps_bitop_uimm8): Likewise.
 890         (extract_nps_bitop_uimm8): Likewise.
 891         (arc_operands): Add new operand entries.
 892
 893 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 894
 895         * arc-regs.h: Add a new subclass field.  Add double assist
 896         accumulator register values.
 897         * arc-tbl.h: Use DPA subclass to mark the double assist
 898         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 899         * arc-opc.c (RSP): Define instead of SP.
 900         (arc_aux_regs): Add the subclass field.
 901
 902 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 903
 904         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 905
 906 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 907
 908         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 909         NPS_R_SRC1.
 910
 911 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 912
 913         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 914         issues.  No functional changes.
 915
 916 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 917
 918         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 919         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 920         (RTT): Remove duplicate.
 921         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 922         (PCT_CONFIG*): Remove.
 923         (D1L, D1H, D2H, D2L): Define.
 924
 925 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 926
 927         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 928
 929 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 930
 931         * arc-tbl.h (invld07): Remove.
 932         * arc-ext-tbl.h: New file.
 933         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 934         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 935
 936 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 937
 938         Fix -Wstack-usage warnings.
 939         * aarch64-dis.c (print_operands): Substitute size.
 940         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 941
 942 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 943
 944         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 945         to get a proper diagnostic when an invalid ASR register is used.
 946
 947 2016-03-22  Nick Clifton  <nickc@redhat.com>
 948
 949         * configure: Regenerate.
 950
 951 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 952
 953         * arc-nps400-tbl.h: New file.
 954         * arc-opc.c: Add top level comment.
 955         (insert_nps_3bit_dst): New function.
 956         (extract_nps_3bit_dst): New function.
 957         (insert_nps_3bit_src2): New function.
 958         (extract_nps_3bit_src2): New function.
 959         (insert_nps_bitop_size): New function.
 960         (extract_nps_bitop_size): New function.
 961         (arc_flag_operands): Add nps400 entries.
 962         (arc_flag_classes): Add nps400 entries.
 963         (arc_operands): Add nps400 entries.
 964         (arc_opcodes): Add nps400 include.
 965
 966 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 967
 968         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 969         the new class enum values.
 970
 971 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 972
 973         * arc-dis.c (print_insn_arc): Handle nps400.
 974
 975 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 976
 977         * arc-opc.c (BASE): Delete.
 978
 979 2016-03-18  Nick Clifton  <nickc@redhat.com>
 980
 981         PR target/19721
 982         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 983         of MOV insn that aliases an ORR insn.
 984
 985 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 986
 987         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 988
 989 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 990
 991         * mcore-opc.h: Add const qualifiers.
 992         * microblaze-opc.h (struct op_code_struct): Likewise.
 993         * sh-opc.h: Likewise.
 994         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 995         (tic4x_print_op): Likewise.
 996
 997 2016-03-02  Alan Modra  <amodra@gmail.com>
 998
 999         * or1k-desc.h: Regenerate.
1000         * fr30-ibld.c: Regenerate.
1001         * rl78-decode.c: Regenerate.
1002
1003 2016-03-01  Nick Clifton  <nickc@redhat.com>
1004
1005         PR target/19747
1006         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1007
1008 2016-02-24  Renlin Li  <renlin.li@arm.com>
1009
1010         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1011         (print_insn_coprocessor): Support fp16 instructions.
1012
1013 2016-02-24  Renlin Li  <renlin.li@arm.com>
1014
1015         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1016         vminnm, vrint(mpna).
1017
1018 2016-02-24  Renlin Li  <renlin.li@arm.com>
1019
1020         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1021         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1022
1023 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1024
1025         * i386-dis.c (print_insn): Parenthesize expression to prevent
1026         truncated addresses.
1027         (OP_J): Likewise.
1028
1029 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1030             Janek van Oirschot  <jvanoirs@synopsys.com>
1031
1032         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1033         variable.
1034
1035 2016-02-04  Nick Clifton  <nickc@redhat.com>
1036
1037         PR target/19561
1038         * msp430-dis.c (print_insn_msp430): Add a special case for
1039         decoding an RRC instruction with the ZC bit set in the extension
1040         word.
1041
1042 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1043
1044         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1045         * epiphany-ibld.c: Regenerate.
1046         * fr30-ibld.c: Regenerate.
1047         * frv-ibld.c: Regenerate.
1048         * ip2k-ibld.c: Regenerate.
1049         * iq2000-ibld.c: Regenerate.
1050         * lm32-ibld.c: Regenerate.
1051         * m32c-ibld.c: Regenerate.
1052         * m32r-ibld.c: Regenerate.
1053         * mep-ibld.c: Regenerate.
1054         * mt-ibld.c: Regenerate.
1055         * or1k-ibld.c: Regenerate.
1056         * xc16x-ibld.c: Regenerate.
1057         * xstormy16-ibld.c: Regenerate.
1058
1059 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1060
1061         * epiphany-dis.c: Regenerated from latest cpu files.
1062
1063 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1064
1065         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1066         test bit.
1067
1068 2016-01-25  Renlin Li  <renlin.li@arm.com>
1069
1070         * arm-dis.c (mapping_symbol_for_insn): New function.
1071         (find_ifthen_state): Call mapping_symbol_for_insn().
1072
1073 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1074
1075         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1076         of MSR UAO immediate operand.
1077
1078 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1079
1080         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1081         instruction support.
1082
1083 2016-01-17  Alan Modra  <amodra@gmail.com>
1084
1085         * configure: Regenerate.
1086
1087 2016-01-14  Nick Clifton  <nickc@redhat.com>
1088
1089         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1090         instructions that can support stack pointer operations.
1091         * rl78-decode.c: Regenerate.
1092         * rl78-dis.c: Fix display of stack pointer in MOVW based
1093         instructions.
1094
1095 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1096
1097         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1098         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1099         erxtatus_el1 and erxaddr_el1.
1100
1101 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1102
1103         * arm-dis.c (arm_opcodes): Add "esb".
1104         (thumb_opcodes): Likewise.
1105
1106 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1107
1108         * ppc-opc.c <xscmpnedp>: Delete.
1109         <xvcmpnedp>: Likewise.
1110         <xvcmpnedp.>: Likewise.
1111         <xvcmpnesp>: Likewise.
1112         <xvcmpnesp.>: Likewise.
1113
1114 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1115
1116         PR gas/13050
1117         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1118         addition to ISA_A.
1119
1120 2016-01-01  Alan Modra  <amodra@gmail.com>
1121
1122         Update year range in copyright notice of all files.
1123
1124 For older changes see ChangeLog-2015
1125 \f
1126 Copyright (C) 2016 Free Software Foundation, Inc.
1127
1128 Copying and distribution of this file, with or without modification,
1129 are permitted in any medium without royalty provided the copyright
1130 notice and this notice are preserved.
1131
1132 Local Variables:
1133 mode: change-log
1134 left-margin: 8
1135 fill-column: 74
1136 version-control: never
1137 End: