opcodes/ChangeLog

   1 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/23665
   4         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
   5         VEX_LEN_0F7E_P_2 entries.
   6         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
   7         * i386-tbl.h: Regenerated.
   8
   9 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
  10
  11         * i386-dis.c (VZERO_Fixup): Removed.
  12         (VZERO): Likewise.
  13         (VEX_LEN_0F10_P_1): Likewise.
  14         (VEX_LEN_0F10_P_3): Likewise.
  15         (VEX_LEN_0F11_P_1): Likewise.
  16         (VEX_LEN_0F11_P_3): Likewise.
  17         (VEX_LEN_0F2E_P_0): Likewise.
  18         (VEX_LEN_0F2E_P_2): Likewise.
  19         (VEX_LEN_0F2F_P_0): Likewise.
  20         (VEX_LEN_0F2F_P_2): Likewise.
  21         (VEX_LEN_0F51_P_1): Likewise.
  22         (VEX_LEN_0F51_P_3): Likewise.
  23         (VEX_LEN_0F52_P_1): Likewise.
  24         (VEX_LEN_0F53_P_1): Likewise.
  25         (VEX_LEN_0F58_P_1): Likewise.
  26         (VEX_LEN_0F58_P_3): Likewise.
  27         (VEX_LEN_0F59_P_1): Likewise.
  28         (VEX_LEN_0F59_P_3): Likewise.
  29         (VEX_LEN_0F5A_P_1): Likewise.
  30         (VEX_LEN_0F5A_P_3): Likewise.
  31         (VEX_LEN_0F5C_P_1): Likewise.
  32         (VEX_LEN_0F5C_P_3): Likewise.
  33         (VEX_LEN_0F5D_P_1): Likewise.
  34         (VEX_LEN_0F5D_P_3): Likewise.
  35         (VEX_LEN_0F5E_P_1): Likewise.
  36         (VEX_LEN_0F5E_P_3): Likewise.
  37         (VEX_LEN_0F5F_P_1): Likewise.
  38         (VEX_LEN_0F5F_P_3): Likewise.
  39         (VEX_LEN_0FC2_P_1): Likewise.
  40         (VEX_LEN_0FC2_P_3): Likewise.
  41         (VEX_LEN_0F3A0A_P_2): Likewise.
  42         (VEX_LEN_0F3A0B_P_2): Likewise.
  43         (VEX_W_0F10_P_0): Likewise.
  44         (VEX_W_0F10_P_1): Likewise.
  45         (VEX_W_0F10_P_2): Likewise.
  46         (VEX_W_0F10_P_3): Likewise.
  47         (VEX_W_0F11_P_0): Likewise.
  48         (VEX_W_0F11_P_1): Likewise.
  49         (VEX_W_0F11_P_2): Likewise.
  50         (VEX_W_0F11_P_3): Likewise.
  51         (VEX_W_0F12_P_0_M_0): Likewise.
  52         (VEX_W_0F12_P_0_M_1): Likewise.
  53         (VEX_W_0F12_P_1): Likewise.
  54         (VEX_W_0F12_P_2): Likewise.
  55         (VEX_W_0F12_P_3): Likewise.
  56         (VEX_W_0F13_M_0): Likewise.
  57         (VEX_W_0F14): Likewise.
  58         (VEX_W_0F15): Likewise.
  59         (VEX_W_0F16_P_0_M_0): Likewise.
  60         (VEX_W_0F16_P_0_M_1): Likewise.
  61         (VEX_W_0F16_P_1): Likewise.
  62         (VEX_W_0F16_P_2): Likewise.
  63         (VEX_W_0F17_M_0): Likewise.
  64         (VEX_W_0F28): Likewise.
  65         (VEX_W_0F29): Likewise.
  66         (VEX_W_0F2B_M_0): Likewise.
  67         (VEX_W_0F2E_P_0): Likewise.
  68         (VEX_W_0F2E_P_2): Likewise.
  69         (VEX_W_0F2F_P_0): Likewise.
  70         (VEX_W_0F2F_P_2): Likewise.
  71         (VEX_W_0F50_M_0): Likewise.
  72         (VEX_W_0F51_P_0): Likewise.
  73         (VEX_W_0F51_P_1): Likewise.
  74         (VEX_W_0F51_P_2): Likewise.
  75         (VEX_W_0F51_P_3): Likewise.
  76         (VEX_W_0F52_P_0): Likewise.
  77         (VEX_W_0F52_P_1): Likewise.
  78         (VEX_W_0F53_P_0): Likewise.
  79         (VEX_W_0F53_P_1): Likewise.
  80         (VEX_W_0F58_P_0): Likewise.
  81         (VEX_W_0F58_P_1): Likewise.
  82         (VEX_W_0F58_P_2): Likewise.
  83         (VEX_W_0F58_P_3): Likewise.
  84         (VEX_W_0F59_P_0): Likewise.
  85         (VEX_W_0F59_P_1): Likewise.
  86         (VEX_W_0F59_P_2): Likewise.
  87         (VEX_W_0F59_P_3): Likewise.
  88         (VEX_W_0F5A_P_0): Likewise.
  89         (VEX_W_0F5A_P_1): Likewise.
  90         (VEX_W_0F5A_P_3): Likewise.
  91         (VEX_W_0F5B_P_0): Likewise.
  92         (VEX_W_0F5B_P_1): Likewise.
  93         (VEX_W_0F5B_P_2): Likewise.
  94         (VEX_W_0F5C_P_0): Likewise.
  95         (VEX_W_0F5C_P_1): Likewise.
  96         (VEX_W_0F5C_P_2): Likewise.
  97         (VEX_W_0F5C_P_3): Likewise.
  98         (VEX_W_0F5D_P_0): Likewise.
  99         (VEX_W_0F5D_P_1): Likewise.
 100         (VEX_W_0F5D_P_2): Likewise.
 101         (VEX_W_0F5D_P_3): Likewise.
 102         (VEX_W_0F5E_P_0): Likewise.
 103         (VEX_W_0F5E_P_1): Likewise.
 104         (VEX_W_0F5E_P_2): Likewise.
 105         (VEX_W_0F5E_P_3): Likewise.
 106         (VEX_W_0F5F_P_0): Likewise.
 107         (VEX_W_0F5F_P_1): Likewise.
 108         (VEX_W_0F5F_P_2): Likewise.
 109         (VEX_W_0F5F_P_3): Likewise.
 110         (VEX_W_0F60_P_2): Likewise.
 111         (VEX_W_0F61_P_2): Likewise.
 112         (VEX_W_0F62_P_2): Likewise.
 113         (VEX_W_0F63_P_2): Likewise.
 114         (VEX_W_0F64_P_2): Likewise.
 115         (VEX_W_0F65_P_2): Likewise.
 116         (VEX_W_0F66_P_2): Likewise.
 117         (VEX_W_0F67_P_2): Likewise.
 118         (VEX_W_0F68_P_2): Likewise.
 119         (VEX_W_0F69_P_2): Likewise.
 120         (VEX_W_0F6A_P_2): Likewise.
 121         (VEX_W_0F6B_P_2): Likewise.
 122         (VEX_W_0F6C_P_2): Likewise.
 123         (VEX_W_0F6D_P_2): Likewise.
 124         (VEX_W_0F6F_P_1): Likewise.
 125         (VEX_W_0F6F_P_2): Likewise.
 126         (VEX_W_0F70_P_1): Likewise.
 127         (VEX_W_0F70_P_2): Likewise.
 128         (VEX_W_0F70_P_3): Likewise.
 129         (VEX_W_0F71_R_2_P_2): Likewise.
 130         (VEX_W_0F71_R_4_P_2): Likewise.
 131         (VEX_W_0F71_R_6_P_2): Likewise.
 132         (VEX_W_0F72_R_2_P_2): Likewise.
 133         (VEX_W_0F72_R_4_P_2): Likewise.
 134         (VEX_W_0F72_R_6_P_2): Likewise.
 135         (VEX_W_0F73_R_2_P_2): Likewise.
 136         (VEX_W_0F73_R_3_P_2): Likewise.
 137         (VEX_W_0F73_R_6_P_2): Likewise.
 138         (VEX_W_0F73_R_7_P_2): Likewise.
 139         (VEX_W_0F74_P_2): Likewise.
 140         (VEX_W_0F75_P_2): Likewise.
 141         (VEX_W_0F76_P_2): Likewise.
 142         (VEX_W_0F77_P_0): Likewise.
 143         (VEX_W_0F7C_P_2): Likewise.
 144         (VEX_W_0F7C_P_3): Likewise.
 145         (VEX_W_0F7D_P_2): Likewise.
 146         (VEX_W_0F7D_P_3): Likewise.
 147         (VEX_W_0F7E_P_1): Likewise.
 148         (VEX_W_0F7F_P_1): Likewise.
 149         (VEX_W_0F7F_P_2): Likewise.
 150         (VEX_W_0FAE_R_2_M_0): Likewise.
 151         (VEX_W_0FAE_R_3_M_0): Likewise.
 152         (VEX_W_0FC2_P_0): Likewise.
 153         (VEX_W_0FC2_P_1): Likewise.
 154         (VEX_W_0FC2_P_2): Likewise.
 155         (VEX_W_0FC2_P_3): Likewise.
 156         (VEX_W_0FD0_P_2): Likewise.
 157         (VEX_W_0FD0_P_3): Likewise.
 158         (VEX_W_0FD1_P_2): Likewise.
 159         (VEX_W_0FD2_P_2): Likewise.
 160         (VEX_W_0FD3_P_2): Likewise.
 161         (VEX_W_0FD4_P_2): Likewise.
 162         (VEX_W_0FD5_P_2): Likewise.
 163         (VEX_W_0FD6_P_2): Likewise.
 164         (VEX_W_0FD7_P_2_M_1): Likewise.
 165         (VEX_W_0FD8_P_2): Likewise.
 166         (VEX_W_0FD9_P_2): Likewise.
 167         (VEX_W_0FDA_P_2): Likewise.
 168         (VEX_W_0FDB_P_2): Likewise.
 169         (VEX_W_0FDC_P_2): Likewise.
 170         (VEX_W_0FDD_P_2): Likewise.
 171         (VEX_W_0FDE_P_2): Likewise.
 172         (VEX_W_0FDF_P_2): Likewise.
 173         (VEX_W_0FE0_P_2): Likewise.
 174         (VEX_W_0FE1_P_2): Likewise.
 175         (VEX_W_0FE2_P_2): Likewise.
 176         (VEX_W_0FE3_P_2): Likewise.
 177         (VEX_W_0FE4_P_2): Likewise.
 178         (VEX_W_0FE5_P_2): Likewise.
 179         (VEX_W_0FE6_P_1): Likewise.
 180         (VEX_W_0FE6_P_2): Likewise.
 181         (VEX_W_0FE6_P_3): Likewise.
 182         (VEX_W_0FE7_P_2_M_0): Likewise.
 183         (VEX_W_0FE8_P_2): Likewise.
 184         (VEX_W_0FE9_P_2): Likewise.
 185         (VEX_W_0FEA_P_2): Likewise.
 186         (VEX_W_0FEB_P_2): Likewise.
 187         (VEX_W_0FEC_P_2): Likewise.
 188         (VEX_W_0FED_P_2): Likewise.
 189         (VEX_W_0FEE_P_2): Likewise.
 190         (VEX_W_0FEF_P_2): Likewise.
 191         (VEX_W_0FF0_P_3_M_0): Likewise.
 192         (VEX_W_0FF1_P_2): Likewise.
 193         (VEX_W_0FF2_P_2): Likewise.
 194         (VEX_W_0FF3_P_2): Likewise.
 195         (VEX_W_0FF4_P_2): Likewise.
 196         (VEX_W_0FF5_P_2): Likewise.
 197         (VEX_W_0FF6_P_2): Likewise.
 198         (VEX_W_0FF7_P_2): Likewise.
 199         (VEX_W_0FF8_P_2): Likewise.
 200         (VEX_W_0FF9_P_2): Likewise.
 201         (VEX_W_0FFA_P_2): Likewise.
 202         (VEX_W_0FFB_P_2): Likewise.
 203         (VEX_W_0FFC_P_2): Likewise.
 204         (VEX_W_0FFD_P_2): Likewise.
 205         (VEX_W_0FFE_P_2): Likewise.
 206         (VEX_W_0F3800_P_2): Likewise.
 207         (VEX_W_0F3801_P_2): Likewise.
 208         (VEX_W_0F3802_P_2): Likewise.
 209         (VEX_W_0F3803_P_2): Likewise.
 210         (VEX_W_0F3804_P_2): Likewise.
 211         (VEX_W_0F3805_P_2): Likewise.
 212         (VEX_W_0F3806_P_2): Likewise.
 213         (VEX_W_0F3807_P_2): Likewise.
 214         (VEX_W_0F3808_P_2): Likewise.
 215         (VEX_W_0F3809_P_2): Likewise.
 216         (VEX_W_0F380A_P_2): Likewise.
 217         (VEX_W_0F380B_P_2): Likewise.
 218         (VEX_W_0F3817_P_2): Likewise.
 219         (VEX_W_0F381C_P_2): Likewise.
 220         (VEX_W_0F381D_P_2): Likewise.
 221         (VEX_W_0F381E_P_2): Likewise.
 222         (VEX_W_0F3820_P_2): Likewise.
 223         (VEX_W_0F3821_P_2): Likewise.
 224         (VEX_W_0F3822_P_2): Likewise.
 225         (VEX_W_0F3823_P_2): Likewise.
 226         (VEX_W_0F3824_P_2): Likewise.
 227         (VEX_W_0F3825_P_2): Likewise.
 228         (VEX_W_0F3828_P_2): Likewise.
 229         (VEX_W_0F3829_P_2): Likewise.
 230         (VEX_W_0F382A_P_2_M_0): Likewise.
 231         (VEX_W_0F382B_P_2): Likewise.
 232         (VEX_W_0F3830_P_2): Likewise.
 233         (VEX_W_0F3831_P_2): Likewise.
 234         (VEX_W_0F3832_P_2): Likewise.
 235         (VEX_W_0F3833_P_2): Likewise.
 236         (VEX_W_0F3834_P_2): Likewise.
 237         (VEX_W_0F3835_P_2): Likewise.
 238         (VEX_W_0F3837_P_2): Likewise.
 239         (VEX_W_0F3838_P_2): Likewise.
 240         (VEX_W_0F3839_P_2): Likewise.
 241         (VEX_W_0F383A_P_2): Likewise.
 242         (VEX_W_0F383B_P_2): Likewise.
 243         (VEX_W_0F383C_P_2): Likewise.
 244         (VEX_W_0F383D_P_2): Likewise.
 245         (VEX_W_0F383E_P_2): Likewise.
 246         (VEX_W_0F383F_P_2): Likewise.
 247         (VEX_W_0F3840_P_2): Likewise.
 248         (VEX_W_0F3841_P_2): Likewise.
 249         (VEX_W_0F38DB_P_2): Likewise.
 250         (VEX_W_0F3A08_P_2): Likewise.
 251         (VEX_W_0F3A09_P_2): Likewise.
 252         (VEX_W_0F3A0A_P_2): Likewise.
 253         (VEX_W_0F3A0B_P_2): Likewise.
 254         (VEX_W_0F3A0C_P_2): Likewise.
 255         (VEX_W_0F3A0D_P_2): Likewise.
 256         (VEX_W_0F3A0E_P_2): Likewise.
 257         (VEX_W_0F3A0F_P_2): Likewise.
 258         (VEX_W_0F3A21_P_2): Likewise.
 259         (VEX_W_0F3A40_P_2): Likewise.
 260         (VEX_W_0F3A41_P_2): Likewise.
 261         (VEX_W_0F3A42_P_2): Likewise.
 262         (VEX_W_0F3A62_P_2): Likewise.
 263         (VEX_W_0F3A63_P_2): Likewise.
 264         (VEX_W_0F3ADF_P_2): Likewise.
 265         (VEX_LEN_0F77_P_0): New.
 266         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 267         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 268         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 269         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 270         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 271         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 272         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 273         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 274         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 275         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 276         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 277         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 278         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 279         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 280         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 281         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 282         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 283         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 284         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 285         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 286         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 287         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 288         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 289         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 290         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 291         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 292         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 293         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 294         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 295         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 296         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 297         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 298         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 299         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 300         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 301         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 302         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 303         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 304         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 305         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 306         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 307         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 308         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 309         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 310         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 311         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 312         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 313         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 314         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 315         (vex_table): Update VEX 0F28 and 0F29 entries.
 316         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 317         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 318         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 319         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 320         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 321         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 322         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 323         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 324         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 325         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 326         VEX_LEN_0F3A0B_P_2 entries.
 327         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 328         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 329         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 330         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 331         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 332         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 333         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 334         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 335         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 336         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 337         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 338         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 339         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 340         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 341         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 342         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 343         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 344         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 345         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 346         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 347         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 348         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 349         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 350         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 351         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 352         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 353         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 354         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 355         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 356         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 357         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 358         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 359         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 360         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 361         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 362         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 363         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 364         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 365         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 366         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 367         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 368         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 369         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 370         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 371         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 372         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 373         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 374         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 375         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 376         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 377         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 378         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 379         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 380         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 381         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 382         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 383         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 384         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 385         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 386         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 387         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 388         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 389         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 390         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 391         VEX_W_0F3ADF_P_2 entries.
 392         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 393         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 394         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 395
 396 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 397
 398         * i386-opc.tbl (VexWIG): New.
 399         Replace VexW=3 with VexWIG.
 400
 401 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 402
 403         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 404         * i386-tbl.h: Regenerated.
 405
 406 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 407
 408         PR gas/23665
 409         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 410         VEX_LEN_0FD6_P_2 entries.
 411         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 412         * i386-tbl.h: Regenerated.
 413
 414 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 415
 416         PR gas/23642
 417         * i386-opc.h (VEXWIG): New.
 418         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 419         * i386-tbl.h: Regenerated.
 420
 421 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 422
 423         PR binutils/23655
 424         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 425         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 426         * i386-dis.c (EXxEVexR64): New.
 427         (evex_rounding_64_mode): Likewise.
 428         (OP_Rounding): Handle evex_rounding_64_mode.
 429
 430 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 431
 432         PR binutils/23655
 433         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 434         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 435         * i386-dis.c (Edqa): New.
 436         (dqa_mode): Likewise.
 437         (intel_operand_size): Handle dqa_mode as m_mode.
 438         (OP_E_register): Handle dqa_mode as dq_mode.
 439         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 440
 441 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 442
 443         * i386-dis.c (OP_E_memory): Reformat.
 444
 445 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 446
 447         * i386-opc.tbl (crc32): Fold byte and word forms.
 448         * i386-tbl.h: Re-generate.
 449
 450 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 453         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 454         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 455         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 456         * i386-tbl.h: Regenerated.
 457
 458 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 461         meaningless.
 462         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 463         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 464         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 465         * i386-tbl.h: Re-generate.
 466
 467 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 468
 469         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 470         AVX512_4VNNIW insns.
 471         * i386-tbl.h: Re-generate.
 472
 473 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 474
 475         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 476         meaningless.
 477         * i386-tbl.h: Re-generate.
 478
 479 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 480
 481         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 482         meaningless.
 483         * i386-tbl.h: Re-generate.
 484
 485 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 488         meaningless.
 489         * i386-tbl.h: Re-generate.
 490
 491 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 494         meaningless.
 495         * i386-tbl.h: Re-generate.
 496
 497 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 498
 499         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 500         meaningless.
 501         * i386-tbl.h: Re-generate.
 502
 503 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 504
 505         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 506         * i386-tbl.h: Re-generate.
 507
 508 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 509
 510         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 511         * i386-tbl.h: Re-generate.
 512
 513 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 514
 515         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 516         meaningless.
 517         * i386-tbl.h: Re-generate.
 518
 519 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 520
 521         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 522         meaningless.
 523         * i386-tbl.h: Re-generate.
 524
 525 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 526
 527         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 528         * i386-tbl.h: Re-generate.
 529
 530 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 533         * i386-tbl.h: Re-generate.
 534
 535 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 536
 537         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 538         * i386-tbl.h: Re-generate.
 539
 540 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 541
 542         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 543         meaningless.
 544         * i386-tbl.h: Re-generate.
 545
 546 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 549         meaningless.
 550         * i386-tbl.h: Re-generate.
 551
 552 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 553
 554         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 555         meaningless.
 556         * i386-tbl.h: Re-generate.
 557
 558 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 561         * i386-tbl.h: Re-generate.
 562
 563 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 564
 565         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 566         * i386-tbl.h: Re-generate.
 567
 568 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 571         * i386-tbl.h: Re-generate.
 572
 573 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 576         (vpbroadcastw, rdpid): Drop NoRex64.
 577         * i386-tbl.h: Re-generate.
 578
 579 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 580
 581         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 582         store templates, adding D.
 583         * i386-tbl.h: Re-generate.
 584
 585 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 586
 587         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 588         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 589         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 590         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 591         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 592         Fold load and store templates where possible, adding D. Drop
 593         IgnoreSize where it was pointlessly present. Drop redundant
 594         *word.
 595         * i386-tbl.h: Re-generate.
 596
 597 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 600         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 601         (intel_operand_size): Handle v_bndmk_mode.
 602         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 603
 604 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 605
 606         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 607
 608 2018-08-31  Kito Cheng  <kito@andestech.com>
 609
 610         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 611         compressed floating point instructions.
 612
 613 2018-08-30  Kito Cheng  <kito@andestech.com>
 614
 615         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 616         riscv_opcode.xlen_requirement.
 617         * riscv-opc.c (riscv_opcodes): Update for struct change.
 618
 619 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 620
 621         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 622         psr (PWRPSR) instruction.
 623
 624 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 625
 626         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 627
 628 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 629
 630         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 631
 632 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 633
 634         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 635         loongson3a as an alias of gs464 for compatibility.
 636         * mips-opc.c (mips_opcodes): Change Comments.
 637
 638 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 639
 640         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 641         option.
 642         (print_mips_disassembler_options): Document -M loongson-ext.
 643         * mips-opc.c (LEXT2): New macro.
 644         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 645
 646 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 647
 648          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 649          descriptors.
 650          (parse_mips_ase_option): Handle -M loongson-ext option.
 651          (print_mips_disassembler_options): Document -M loongson-ext.
 652          * mips-opc.c (IL3A): Delete.
 653          * mips-opc.c (LEXT): New macro.
 654          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 655          instructions.
 656
 657 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 658
 659         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 660         descriptors.
 661         (parse_mips_ase_option): Handle -M loongson-cam option.
 662         (print_mips_disassembler_options): Document -M loongson-cam.
 663         * mips-opc.c (LCAM): New macro.
 664         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 665         instructions.
 666
 667 2018-08-21  Alan Modra  <amodra@gmail.com>
 668
 669         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 670         (skip_optional_operands): Count optional operands, and update
 671         ppc_optional_operand_value call.
 672         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 673         (extract_vlensi): Likewise.
 674         (extract_fxm): Return default value for missing optional operand.
 675         (extract_ls, extract_raq, extract_tbr): Likewise.
 676         (insert_sxl, extract_sxl): New functions.
 677         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 678         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 679         flag and extra entry.
 680         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 681         extract_sxl.
 682
 683 2018-08-20  Alan Modra  <amodra@gmail.com>
 684
 685         * sh-opc.h (MASK): Simplify.
 686
 687 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 688
 689         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 690         BM_RESERVED0 or BM_RESERVED1
 691         (bm_rel_decode, bm_n_bytes): Ditto.
 692
 693 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 694
 695         * s12z.h: Delete.
 696
 697 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 698
 699         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 700         address with the addr32 prefix and without base nor index
 701         registers.
 702
 703 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 704
 705         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 706         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 707         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 708         (cpu_flags): Add CpuCMOV and CpuFXSR.
 709         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 710         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 711         * i386-init.h: Regenerated.
 712         * i386-tbl.h: Likewise.
 713
 714 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 715
 716         * arc-regs.h: Update auxiliary registers.
 717
 718 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 719
 720         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 721         (RegIP, RegIZ): Define.
 722         * i386-reg.tbl: Adjust comments.
 723         (rip): Use Qword instead of BaseIndex. Use RegIP.
 724         (eip): Use Dword instead of BaseIndex. Use RegIP.
 725         (riz): Add Qword. Use RegIZ.
 726         (eiz): Add Dword. Use RegIZ.
 727         * i386-tbl.h: Re-generate.
 728
 729 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 730
 731         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 732         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 733         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 734         * i386-tbl.h: Re-generate.
 735
 736 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-gen.c (operand_types): Remove Mem field.
 739         * i386-opc.h (union i386_operand_type): Remove mem field.
 740         * i386-init.h, i386-tbl.h: Re-generate.
 741
 742 2018-08-01  Alan Modra  <amodra@gmail.com>
 743
 744         * po/POTFILES.in: Regenerate.
 745
 746 2018-07-31  Nick Clifton  <nickc@redhat.com>
 747
 748         * po/sv.po: Updated Swedish translation.
 749
 750 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 753         * i386-init.h, i386-tbl.h: Re-generate.
 754
 755 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 756
 757         * i386-opc.h (ZEROING_MASKING) Rename to ...
 758         (DYNAMIC_MASKING): ... this. Adjust comment.
 759         * i386-opc.tbl (MaskingMorZ): Define.
 760         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 761         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 762         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 763         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 764         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 765         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 766         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 767         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 768         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 769
 770 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-opc.tbl: Use element rather than vector size for AVX512*
 773         scatter/gather insns.
 774         * i386-tbl.h: Re-generate.
 775
 776 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 779         (cpu_flags): Drop CpuVREX.
 780         * i386-opc.h (CpuVREX): Delete.
 781         (union i386_cpu_flags): Remove cpuvrex.
 782         * i386-init.h, i386-tbl.h: Re-generate.
 783
 784 2018-07-30  Jim Wilson  <jimw@sifive.com>
 785
 786         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 787         fields.
 788         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 789
 790 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 791
 792         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 793         * Makefile.in: Regenerated.
 794         * configure.ac: Add C-SKY.
 795         * configure: Regenerated.
 796         * csky-dis.c: New file.
 797         * csky-opc.h: New file.
 798         * disassemble.c (ARCH_csky): Define.
 799         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 800         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 801
 802 2018-07-27  Alan Modra  <amodra@gmail.com>
 803
 804         * ppc-opc.c (insert_sprbat): Correct function parameter and
 805         return type.
 806         (extract_sprbat): Likewise, variable too.
 807
 808 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 809             Alan Modra  <amodra@gmail.com>
 810
 811         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 812         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 813         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 814         support disjointed BAT.
 815         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 816         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 817         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 818
 819 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 820             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 821
 822         * i386-gen.c (adjust_broadcast_modifier): New function.
 823         (process_i386_opcode_modifier): Add an argument for operands.
 824         Adjust the Broadcast value based on operands.
 825         (output_i386_opcode): Pass operand_types to
 826         process_i386_opcode_modifier.
 827         (process_i386_opcodes): Pass NULL as operands to
 828         process_i386_opcode_modifier.
 829         * i386-opc.h (BYTE_BROADCAST): New.
 830         (WORD_BROADCAST): Likewise.
 831         (DWORD_BROADCAST): Likewise.
 832         (QWORD_BROADCAST): Likewise.
 833         (i386_opcode_modifier): Expand broadcast to 3 bits.
 834         * i386-tbl.h: Regenerated.
 835
 836 2018-07-24  Alan Modra  <amodra@gmail.com>
 837
 838         PR 23430
 839         * or1k-desc.h: Regenerate.
 840
 841 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 842
 843         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 844         vcvtusi2ss, and vcvtusi2sd.
 845         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 846         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 847         * i386-tbl.h: Re-generate.
 848
 849 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 850
 851         * arc-opc.c (extract_w6): Fix extending the sign.
 852
 853 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 854
 855         * arc-tbl.h (vewt): Allow it for ARC EM family.
 856
 857 2018-07-23  Alan Modra  <amodra@gmail.com>
 858
 859         PR 23419
 860         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 861         opcode variants for mtspr/mfspr encodings.
 862
 863 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 864             Maciej W. Rozycki  <macro@mips.com>
 865
 866         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 867         loongson3a descriptors.
 868         (parse_mips_ase_option): Handle -M loongson-mmi option.
 869         (print_mips_disassembler_options): Document -M loongson-mmi.
 870         * mips-opc.c (LMMI): New macro.
 871         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 872         instructions.
 873
 874 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 875
 876         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 877         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 878         IgnoreSize and [XYZ]MMword where applicable.
 879         * i386-tbl.h: Re-generate.
 880
 881 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 882
 883         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 884         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 885         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 886         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 887         * i386-tbl.h: Re-generate.
 888
 889 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 890
 891         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 892         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 893         VPCLMULQDQ templates into their respective AVX512VL counterparts
 894         where possible, using Disp8ShiftVL and CheckRegSize instead of
 895         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 896         * i386-tbl.h: Re-generate.
 897
 898 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 899
 900         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 901         AVX512VL counterparts where possible, using Disp8ShiftVL and
 902         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 903         IgnoreSize) as appropriate.
 904         * i386-tbl.h: Re-generate.
 905
 906 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 907
 908         * i386-opc.tbl: Fold AVX512BW templates into their respective
 909         AVX512VL counterparts where possible, using Disp8ShiftVL and
 910         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 911         IgnoreSize) as appropriate.
 912         * i386-tbl.h: Re-generate.
 913
 914 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 915
 916         * i386-opc.tbl: Fold AVX512CD templates into their respective
 917         AVX512VL counterparts where possible, using Disp8ShiftVL and
 918         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 919         IgnoreSize) as appropriate.
 920         * i386-tbl.h: Re-generate.
 921
 922 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 923
 924         * i386-opc.h (DISP8_SHIFT_VL): New.
 925         * i386-opc.tbl (Disp8ShiftVL):  Define.
 926         (various): Fold AVX512VL templates into their respective
 927         AVX512F counterparts where possible, using Disp8ShiftVL and
 928         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 929         IgnoreSize) as appropriate.
 930         * i386-tbl.h: Re-generate.
 931
 932 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 933
 934         * Makefile.am: Change dependencies and rule for
 935         $(srcdir)/i386-init.h.
 936         * Makefile.in: Re-generate.
 937         * i386-gen.c (process_i386_opcodes): New local variable
 938         "marker". Drop opening of input file. Recognize marker and line
 939         number directives.
 940         * i386-opc.tbl (OPCODE_I386_H): Define.
 941         (i386-opc.h): Include it.
 942         (None): Undefine.
 943
 944 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 945
 946         PR gas/23418
 947         * i386-opc.h (Byte): Update comments.
 948         (Word): Likewise.
 949         (Dword): Likewise.
 950         (Fword): Likewise.
 951         (Qword): Likewise.
 952         (Tbyte): Likewise.
 953         (Xmmword): Likewise.
 954         (Ymmword): Likewise.
 955         (Zmmword): Likewise.
 956         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 957         vcvttps2uqq.
 958         * i386-tbl.h: Regenerated.
 959
 960 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 961
 962         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 963         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 964         * aarch64-asm-2.c: Regenerate.
 965         * aarch64-dis-2.c: Regenerate.
 966         * aarch64-opc-2.c: Regenerate.
 967
 968 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 969
 970         PR binutils/23192
 971         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 972         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 973         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 974         sqdmulh, sqrdmulh): Use Em16.
 975
 976 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 977
 978         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 979         csdb together with them.
 980         (thumb32_opcodes): Likewise.
 981
 982 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 985         requiring 32-bit registers as operands 2 and 3. Improve
 986         comments.
 987         (mwait, mwaitx): Fold templates. Improve comments.
 988         OPERAND_TYPE_INOUTPORTREG.
 989         * i386-tbl.h: Re-generate.
 990
 991 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 992
 993         * i386-gen.c (operand_type_init): Remove
 994         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 995         OPERAND_TYPE_INOUTPORTREG.
 996         * i386-init.h: Re-generate.
 997
 998 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 999
1000         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1001         (wrssq, wrussq): Add Qword.
1002         * i386-tbl.h: Re-generate.
1003
1004 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1005
1006         * i386-opc.h: Rename OTMax to OTNum.
1007         (OTNumOfUints): Adjust calculation.
1008         (OTUnused): Directly alias to OTNum.
1009
1010 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1011
1012         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1013         `reg_xys'.
1014         (lea_reg_xys): Likewise.
1015         (print_insn_loop_primitive): Rename `reg' local variable to
1016         `reg_dxy'.
1017
1018 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1019
1020         PR binutils/23242
1021         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1022
1023 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1024
1025         PR binutils/23369
1026         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1027         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1028
1029 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1030
1031         PR tdep/8282
1032         * mips-dis.c (mips_option_arg_t): New enumeration.
1033         (mips_options): New variable.
1034         (disassembler_options_mips): New function.
1035         (print_mips_disassembler_options): Reimplement in terms of
1036         `disassembler_options_mips'.
1037         * arm-dis.c (disassembler_options_arm): Adapt to using the
1038         `disasm_options_and_args_t' structure.
1039         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1040         * s390-dis.c (disassembler_options_s390): Likewise.
1041
1042 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1043
1044         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1045         expected result.
1046         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1047         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1048         * testsuite/ld-arm/tls-longplt.d: Likewise.
1049
1050 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1051
1052         PR binutils/23192
1053         * aarch64-asm-2.c: Regenerate.
1054         * aarch64-dis-2.c: Likewise.
1055         * aarch64-opc-2.c: Likewise.
1056         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1057         * aarch64-opc.c (operand_general_constraint_met_p,
1058         aarch64_print_operand): Likewise.
1059         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1060         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1061         fmlal2, fmlsl2.
1062         (AARCH64_OPERANDS): Add Em2.
1063
1064 2018-06-26  Nick Clifton  <nickc@redhat.com>
1065
1066         * po/uk.po: Updated Ukranian translation.
1067         * po/de.po: Updated German translation.
1068         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1069
1070 2018-06-26  Nick Clifton  <nickc@redhat.com>
1071
1072         * nfp-dis.c: Fix spelling mistake.
1073
1074 2018-06-24  Nick Clifton  <nickc@redhat.com>
1075
1076         * configure: Regenerate.
1077         * po/opcodes.pot: Regenerate.
1078
1079 2018-06-24  Nick Clifton  <nickc@redhat.com>
1080
1081         2.31 branch created.
1082
1083 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1084
1085         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1086         * aarch64-asm-2.c: Regenerate.
1087         * aarch64-dis-2.c: Likewise.
1088
1089 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1090
1091         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1092         `-M ginv' option description.
1093
1094 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1095
1096         PR gas/23305
1097         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1098         la and lla.
1099
1100 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1101
1102         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1103         * configure.ac: Remove AC_PREREQ.
1104         * Makefile.in: Re-generate.
1105         * aclocal.m4: Re-generate.
1106         * configure: Re-generate.
1107
1108 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1109
1110         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1111         mips64r6 descriptors.
1112         (parse_mips_ase_option): Handle -Mginv option.
1113         (print_mips_disassembler_options): Document -Mginv.
1114         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1115         (GINV): New macro.
1116         (mips_opcodes): Define ginvi and ginvt.
1117
1118 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1119             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1120
1121         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1122         * mips-opc.c (CRC, CRC64): New macros.
1123         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1124         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1125         crc32cd for CRC64.
1126
1127 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1128
1129         PR 20319
1130         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1131         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1132
1133 2018-06-06  Alan Modra  <amodra@gmail.com>
1134
1135         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1136         setjmp.  Move init for some other vars later too.
1137
1138 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1139
1140         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1141         (dis_private): Add new fields for property section tracking.
1142         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1143         (xtensa_instruction_fits): New functions.
1144         (fetch_data): Bump minimal fetch size to 4.
1145         (print_insn_xtensa): Make struct dis_private static.
1146         Load and prepare property table on section change.
1147         Don't disassemble literals. Don't disassemble instructions that
1148         cross property table boundaries.
1149
1150 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1151
1152         * configure: Regenerated.
1153
1154 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1155
1156         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1157         * i386-tbl.h: Re-generate.
1158
1159 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1160
1161         * i386-opc.tbl (sldt, str): Add NoRex64.
1162         * i386-tbl.h: Re-generate.
1163
1164 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1165
1166         * i386-opc.tbl (invpcid): Add Oword.
1167         * i386-tbl.h: Re-generate.
1168
1169 2018-06-01  Alan Modra  <amodra@gmail.com>
1170
1171         * sysdep.h (_bfd_error_handler): Don't declare.
1172         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1173         * rl78-decode.opc: Likewise.
1174         * msp430-decode.c: Regenerate.
1175         * rl78-decode.c: Regenerate.
1176
1177 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1178
1179         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1180         * i386-init.h : Regenerated.
1181
1182 2018-05-25  Alan Modra  <amodra@gmail.com>
1183
1184         * Makefile.in: Regenerate.
1185         * po/POTFILES.in: Regenerate.
1186
1187 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1188
1189         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1190         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1191         (insert_bab, extract_bab, insert_btab, extract_btab,
1192         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1193         (BAT, BBA VBA RBS XB6S): Delete macros.
1194         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1195         (BB, BD, RBX, XC6): Update for new macros.
1196         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1197         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1198         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1199         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1200
1201 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1202
1203         * Makefile.am: Add support for s12z architecture.
1204         * configure.ac: Likewise.
1205         * disassemble.c: Likewise.
1206         * disassemble.h: Likewise.
1207         * Makefile.in: Regenerate.
1208         * configure: Regenerate.
1209         * s12z-dis.c: New file.
1210         * s12z.h: New file.
1211
1212 2018-05-18  Alan Modra  <amodra@gmail.com>
1213
1214         * nfp-dis.c: Don't #include libbfd.h.
1215         (init_nfp3200_priv): Use bfd_get_section_contents.
1216         (nit_nfp6000_mecsr_sec): Likewise.
1217
1218 2018-05-17  Nick Clifton  <nickc@redhat.com>
1219
1220         * po/zh_CN.po: Updated simplified Chinese translation.
1221
1222 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1223
1224         PR binutils/23109
1225         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1226         * aarch64-dis-2.c: Regenerate.
1227
1228 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1229
1230         PR binutils/21446
1231         * aarch64-asm.c (opintl.h): Include.
1232         (aarch64_ins_sysreg): Enforce read/write constraints.
1233         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1234         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1235         (F_REG_READ, F_REG_WRITE): New.
1236         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1237         AARCH64_OPND_SYSREG.
1238         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1239         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1240         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1241         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1242         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1243         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1244         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1245         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1246         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1247         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1248         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1249         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1250         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1251         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1252         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1253         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1254         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1255
1256 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1257
1258         PR binutils/21446
1259         * aarch64-dis.c (no_notes: New.
1260         (parse_aarch64_dis_option): Support notes.
1261         (aarch64_decode_insn, print_operands): Likewise.
1262         (print_aarch64_disassembler_options): Document notes.
1263         * aarch64-opc.c (aarch64_print_operand): Support notes.
1264
1265 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1266
1267         PR binutils/21446
1268         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1269         and take error struct.
1270         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1271         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1272         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1273         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1274         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1275         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1276         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1277         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1278         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1279         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1280         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1281         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1282         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1283         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1284         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1285         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1286         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1287         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1288         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1289         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1290         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1291         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1292         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1293         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1294         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1295         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1296         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1297         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1298         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1299         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1300         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1301         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1302         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1303         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1304         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1305         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1306         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1307         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1308         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1309         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1310         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1311         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1312         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1313         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1314         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1315         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1316         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1317         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1318         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1319         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1320         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1321         (determine_disassembling_preference, aarch64_decode_insn,
1322         print_insn_aarch64_word, print_insn_data): Take errors struct.
1323         (print_insn_aarch64): Use errors.
1324         * aarch64-asm-2.c: Regenerate.
1325         * aarch64-dis-2.c: Regenerate.
1326         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1327         boolean in aarch64_insert_operan.
1328         (print_operand_extractor): Likewise.
1329         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1330
1331 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1332
1333         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1334
1335 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1336
1337         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1338
1339 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1340
1341         * cr16-opc.c (cr16_instruction): Comment typo fix.
1342         * hppa-dis.c (print_insn_hppa): Likewise.
1343
1344 2018-05-08  Jim Wilson  <jimw@sifive.com>
1345
1346         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1347         (match_c_slli64, match_srxi_as_c_srxi): New.
1348         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1349         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1350         <c.slli, c.srli, c.srai>: Use match_s_slli.
1351         <c.slli64, c.srli64, c.srai64>: New.
1352
1353 2018-05-08  Alan Modra  <amodra@gmail.com>
1354
1355         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1356         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1357         partition opcode space for index lookup.
1358
1359 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1360
1361         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1362         <insn_length>: ...with this.  Update usage.
1363         Remove duplicate call to *info->memory_error_func.
1364
1365 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1366             H.J. Lu  <hongjiu.lu@intel.com>
1367
1368         * i386-dis.c (Gva): New.
1369         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1370         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1371         (prefix_table): New instructions (see prefix above).
1372         (mod_table): New instructions (see prefix above).
1373         (OP_G): Handle va_mode.
1374         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1375         CPU_MOVDIR64B_FLAGS.
1376         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1377         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1378         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1379         * i386-opc.tbl: Add movidir{i,64b}.
1380         * i386-init.h: Regenerated.
1381         * i386-tbl.h: Likewise.
1382
1383 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1384
1385         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1386         AddrPrefixOpReg.
1387         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1388         (AddrPrefixOpReg): This.
1389         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1390         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1391
1392 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1393
1394         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1395         (vle_num_opcodes): Likewise.
1396         (spe2_num_opcodes): Likewise.
1397         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1398         initialization loop.
1399         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1400         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1401         only once.
1402
1403 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1404
1405         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1406
1407 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1408
1409         Makefile.am: Added nfp-dis.c.
1410         configure.ac: Added bfd_nfp_arch.
1411         disassemble.h: Added print_insn_nfp prototype.
1412         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1413         nfp-dis.c: New, for NFP support.
1414         po/POTFILES.in: Added nfp-dis.c to the list.
1415         Makefile.in: Regenerate.
1416         configure: Regenerate.
1417
1418 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1419
1420         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1421         templates into their base ones.
1422         * i386-tlb.h: Re-generate.
1423
1424 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1425
1426         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1427         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1428         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1429         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1430         * i386-init.h: Re-generate.
1431
1432 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1433
1434         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1435         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1436         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1437         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1438         comment.
1439         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1440         and CpuRegMask.
1441         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1442         CpuRegMask: Delete.
1443         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1444         cpuregzmm, and cpuregmask.
1445         * i386-init.h: Re-generate.
1446         * i386-tbl.h: Re-generate.
1447
1448 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1449
1450         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1451         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1452         * i386-init.h: Re-generate.
1453
1454 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1455
1456         * i386-gen.c (VexImmExt): Delete.
1457         * i386-opc.h (VexImmExt, veximmext): Delete.
1458         * i386-opc.tbl: Drop all VexImmExt uses.
1459         * i386-tlb.h: Re-generate.
1460
1461 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1462
1463         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1464         register-only forms.
1465         * i386-tlb.h: Re-generate.
1466
1467 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1468
1469         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1470
1471 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1472
1473         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1474         PREFIX_0F1C.
1475         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1476         (cpu_flags): Add CpuCLDEMOTE.
1477         * i386-init.h: Regenerate.
1478         * i386-opc.h (enum): Add CpuCLDEMOTE,
1479         (i386_cpu_flags): Add cpucldemote.
1480         * i386-opc.tbl: Add cldemote.
1481         * i386-tbl.h: Regenerate.
1482
1483 2018-04-16  Alan Modra  <amodra@gmail.com>
1484
1485         * Makefile.am: Remove sh5 and sh64 support.
1486         * configure.ac: Likewise.
1487         * disassemble.c: Likewise.
1488         * disassemble.h: Likewise.
1489         * sh-dis.c: Likewise.
1490         * sh64-dis.c: Delete.
1491         * sh64-opc.c: Delete.
1492         * sh64-opc.h: Delete.
1493         * Makefile.in: Regenerate.
1494         * configure: Regenerate.
1495         * po/POTFILES.in: Regenerate.
1496
1497 2018-04-16  Alan Modra  <amodra@gmail.com>
1498
1499         * Makefile.am: Remove w65 support.
1500         * configure.ac: Likewise.
1501         * disassemble.c: Likewise.
1502         * disassemble.h: Likewise.
1503         * w65-dis.c: Delete.
1504         * w65-opc.h: Delete.
1505         * Makefile.in: Regenerate.
1506         * configure: Regenerate.
1507         * po/POTFILES.in: Regenerate.
1508
1509 2018-04-16  Alan Modra  <amodra@gmail.com>
1510
1511         * configure.ac: Remove we32k support.
1512         * configure: Regenerate.
1513
1514 2018-04-16  Alan Modra  <amodra@gmail.com>
1515
1516         * Makefile.am: Remove m88k support.
1517         * configure.ac: Likewise.
1518         * disassemble.c: Likewise.
1519         * disassemble.h: Likewise.
1520         * m88k-dis.c: Delete.
1521         * Makefile.in: Regenerate.
1522         * configure: Regenerate.
1523         * po/POTFILES.in: Regenerate.
1524
1525 2018-04-16  Alan Modra  <amodra@gmail.com>
1526
1527         * Makefile.am: Remove i370 support.
1528         * configure.ac: Likewise.
1529         * disassemble.c: Likewise.
1530         * disassemble.h: Likewise.
1531         * i370-dis.c: Delete.
1532         * i370-opc.c: Delete.
1533         * Makefile.in: Regenerate.
1534         * configure: Regenerate.
1535         * po/POTFILES.in: Regenerate.
1536
1537 2018-04-16  Alan Modra  <amodra@gmail.com>
1538
1539         * Makefile.am: Remove h8500 support.
1540         * configure.ac: Likewise.
1541         * disassemble.c: Likewise.
1542         * disassemble.h: Likewise.
1543         * h8500-dis.c: Delete.
1544         * h8500-opc.h: Delete.
1545         * Makefile.in: Regenerate.
1546         * configure: Regenerate.
1547         * po/POTFILES.in: Regenerate.
1548
1549 2018-04-16  Alan Modra  <amodra@gmail.com>
1550
1551         * configure.ac: Remove tahoe support.
1552         * configure: Regenerate.
1553
1554 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1555
1556         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1557         umwait.
1558         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1559         64-bit mode.
1560         * i386-tbl.h: Regenerated.
1561
1562 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1563
1564         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1565         PREFIX_MOD_1_0FAE_REG_6.
1566         (va_mode): New.
1567         (OP_E_register): Use va_mode.
1568         * i386-dis-evex.h (prefix_table):
1569         New instructions (see prefixes above).
1570         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1571         (cpu_flags): Likewise.
1572         * i386-opc.h (enum): Likewise.
1573         (i386_cpu_flags): Likewise.
1574         * i386-opc.tbl: Add umonitor, umwait, tpause.
1575         * i386-init.h: Regenerate.
1576         * i386-tbl.h: Likewise.
1577
1578 2018-04-11  Alan Modra  <amodra@gmail.com>
1579
1580         * opcodes/i860-dis.c: Delete.
1581         * opcodes/i960-dis.c: Delete.
1582         * Makefile.am: Remove i860 and i960 support.
1583         * configure.ac: Likewise.
1584         * disassemble.c: Likewise.
1585         * disassemble.h: Likewise.
1586         * Makefile.in: Regenerate.
1587         * configure: Regenerate.
1588         * po/POTFILES.in: Regenerate.
1589
1590 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1591
1592         PR binutils/23025
1593         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1594         to 0.
1595         (print_insn): Clear vex instead of vex.evex.
1596
1597 2018-04-04  Nick Clifton  <nickc@redhat.com>
1598
1599         * po/es.po: Updated Spanish translation.
1600
1601 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1602
1603         * i386-gen.c (opcode_modifiers): Delete VecESize.
1604         * i386-opc.h (VecESize): Delete.
1605         (struct i386_opcode_modifier): Delete vecesize.
1606         * i386-opc.tbl: Drop VecESize.
1607         * i386-tlb.h: Re-generate.
1608
1609 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1610
1611         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1612         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1613         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1614         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1615         * i386-tlb.h: Re-generate.
1616
1617 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1618
1619         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1620         Fold AVX512 forms
1621         * i386-tlb.h: Re-generate.
1622
1623 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1624
1625         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1626         (vex_len_table): Drop Y for vcvt*2si.
1627         (putop): Replace plain 'Y' handling by abort().
1628
1629 2018-03-28  Nick Clifton  <nickc@redhat.com>
1630
1631         PR 22988
1632         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1633         instructions with only a base address register.
1634         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1635         handle AARHC64_OPND_SVE_ADDR_R.
1636         (aarch64_print_operand): Likewise.
1637         * aarch64-asm-2.c: Regenerate.
1638         * aarch64_dis-2.c: Regenerate.
1639         * aarch64-opc-2.c: Regenerate.
1640
1641 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1642
1643         * i386-opc.tbl: Drop VecESize from register only insn forms and
1644         memory forms not allowing broadcast.
1645         * i386-tlb.h: Re-generate.
1646
1647 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1648
1649         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1650         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1651         sha256*): Drop Disp<N>.
1652
1653 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1654
1655         * i386-dis.c (EbndS, bnd_swap_mode): New.
1656         (prefix_table): Use EbndS.
1657         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1658         * i386-opc.tbl (bndmov): Move misplaced Load.
1659         * i386-tlb.h: Re-generate.
1660
1661 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1662
1663         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1664         templates allowing memory operands and folded ones for register
1665         only flavors.
1666         * i386-tlb.h: Re-generate.
1667
1668 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1669
1670         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1671         256-bit templates. Drop redundant leftover Disp<N>.
1672         * i386-tlb.h: Re-generate.
1673
1674 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1675
1676         * riscv-opc.c (riscv_insn_types): New.
1677
1678 2018-03-13  Nick Clifton  <nickc@redhat.com>
1679
1680         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1681
1682 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1683
1684         * i386-opc.tbl: Add Optimize to clr.
1685         * i386-tbl.h: Regenerated.
1686
1687 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1688
1689         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1690         * i386-opc.h (OldGcc): Removed.
1691         (i386_opcode_modifier): Remove oldgcc.
1692         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1693         instructions for old (<= 2.8.1) versions of gcc.
1694         * i386-tbl.h: Regenerated.
1695
1696 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1697
1698         * i386-opc.h (EVEXDYN): New.
1699         * i386-opc.tbl: Fold various AVX512VL templates.
1700         * i386-tlb.h: Re-generate.
1701
1702 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1703
1704         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1705         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1706         vpexpandd, vpexpandq): Fold AFX512VF templates.
1707         * i386-tlb.h: Re-generate.
1708
1709 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1710
1711         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1712         Fold 128- and 256-bit VEX-encoded templates.
1713         * i386-tlb.h: Re-generate.
1714
1715 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1716
1717         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1718         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1719         vpexpandd, vpexpandq): Fold AVX512F templates.
1720         * i386-tlb.h: Re-generate.
1721
1722 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1723
1724         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1725         64-bit templates. Drop Disp<N>.
1726         * i386-tlb.h: Re-generate.
1727
1728 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1729
1730         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1731         and 256-bit templates.
1732         * i386-tlb.h: Re-generate.
1733
1734 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1735
1736         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1737         * i386-tlb.h: Re-generate.
1738
1739 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1740
1741         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1742         Drop NoAVX.
1743         * i386-tlb.h: Re-generate.
1744
1745 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1746
1747         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1748         * i386-tlb.h: Re-generate.
1749
1750 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1751
1752         * i386-gen.c (opcode_modifiers): Delete FloatD.
1753         * i386-opc.h (FloatD): Delete.
1754         (struct i386_opcode_modifier): Delete floatd.
1755         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1756         FloatD by D.
1757         * i386-tlb.h: Re-generate.
1758
1759 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1760
1761         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1762
1763 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1764
1765         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1766         * i386-tlb.h: Re-generate.
1767
1768 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1769
1770         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1771         forms.
1772         * i386-tlb.h: Re-generate.
1773
1774 2018-03-07  Alan Modra  <amodra@gmail.com>
1775
1776         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1777         bfd_arch_rs6000.
1778         * disassemble.h (print_insn_rs6000): Delete.
1779         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1780         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1781         (print_insn_rs6000): Delete.
1782
1783 2018-03-03  Alan Modra  <amodra@gmail.com>
1784
1785         * sysdep.h (opcodes_error_handler): Define.
1786         (_bfd_error_handler): Declare.
1787         * Makefile.am: Remove stray #.
1788         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1789         EDIT" comment.
1790         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1791         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1792         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1793         opcodes_error_handler to print errors.  Standardize error messages.
1794         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1795         and include opintl.h.
1796         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1797         * i386-gen.c: Standardize error messages.
1798         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1799         * Makefile.in: Regenerate.
1800         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1801         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1802         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1803         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1804         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1805         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1806         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1807         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1808         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1809         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1810         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1811         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1812         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1813
1814 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1815
1816         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1817         vpsub[bwdq] instructions.
1818         * i386-tbl.h: Regenerated.
1819
1820 2018-03-01  Alan Modra  <amodra@gmail.com>
1821
1822         * configure.ac (ALL_LINGUAS): Sort.
1823         * configure: Regenerate.
1824
1825 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1826
1827         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1828         macro by assignements.
1829
1830 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1831
1832         PR gas/22871
1833         * i386-gen.c (opcode_modifiers): Add Optimize.
1834         * i386-opc.h (Optimize): New enum.
1835         (i386_opcode_modifier): Add optimize.
1836         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1837         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1838         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1839         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1840         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1841         vpxord and vpxorq.
1842         * i386-tbl.h: Regenerated.
1843
1844 2018-02-26  Alan Modra  <amodra@gmail.com>
1845
1846         * crx-dis.c (getregliststring): Allocate a large enough buffer
1847         to silence false positive gcc8 warning.
1848
1849 2018-02-22  Shea Levy <shea@shealevy.com>
1850
1851         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1852
1853 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1854
1855         * i386-opc.tbl: Add {rex},
1856         * i386-tbl.h: Regenerated.
1857
1858 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1859
1860         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1861         (mips16_opcodes): Replace `M' with `m' for "restore".
1862
1863 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1864
1865         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1866
1867 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1868
1869         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1870         variable to `function_index'.
1871
1872 2018-02-13  Nick Clifton  <nickc@redhat.com>
1873
1874         PR 22823
1875         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1876         about truncation of printing.
1877
1878 2018-02-12  Henry Wong <henry@stuffedcow.net>
1879
1880         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1881
1882 2018-02-05  Nick Clifton  <nickc@redhat.com>
1883
1884         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1885
1886 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1887
1888         * i386-dis.c (enum): Add pconfig.
1889         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1890         (cpu_flags): Add CpuPCONFIG.
1891         * i386-opc.h (enum): Add CpuPCONFIG.
1892         (i386_cpu_flags): Add cpupconfig.
1893         * i386-opc.tbl: Add PCONFIG instruction.
1894         * i386-init.h: Regenerate.
1895         * i386-tbl.h: Likewise.
1896
1897 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1898
1899         * i386-dis.c (enum): Add PREFIX_0F09.
1900         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1901         (cpu_flags): Add CpuWBNOINVD.
1902         * i386-opc.h (enum): Add CpuWBNOINVD.
1903         (i386_cpu_flags): Add cpuwbnoinvd.
1904         * i386-opc.tbl: Add WBNOINVD instruction.
1905         * i386-init.h: Regenerate.
1906         * i386-tbl.h: Likewise.
1907
1908 2018-01-17  Jim Wilson  <jimw@sifive.com>
1909
1910         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1911
1912 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1913
1914         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1915         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1916         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1917         (cpu_flags): Add CpuIBT, CpuSHSTK.
1918         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1919         (i386_cpu_flags): Add cpuibt, cpushstk.
1920         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1921         * i386-init.h: Regenerate.
1922         * i386-tbl.h: Likewise.
1923
1924 2018-01-16  Nick Clifton  <nickc@redhat.com>
1925
1926         * po/pt_BR.po: Updated Brazilian Portugese translation.
1927         * po/de.po: Updated German translation.
1928
1929 2018-01-15  Jim Wilson  <jimw@sifive.com>
1930
1931         * riscv-opc.c (match_c_nop): New.
1932         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1933
1934 2018-01-15  Nick Clifton  <nickc@redhat.com>
1935
1936         * po/uk.po: Updated Ukranian translation.
1937
1938 2018-01-13  Nick Clifton  <nickc@redhat.com>
1939
1940         * po/opcodes.pot: Regenerated.
1941
1942 2018-01-13  Nick Clifton  <nickc@redhat.com>
1943
1944         * configure: Regenerate.
1945
1946 2018-01-13  Nick Clifton  <nickc@redhat.com>
1947
1948         2.30 branch created.
1949
1950 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1951
1952         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1953         * i386-tbl.h: Regenerate.
1954
1955 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1956
1957         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1958         * i386-tbl.h: Re-generate.
1959
1960 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1961
1962         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1963         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1964         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1965         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1966         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1967         Disp8MemShift of AVX512VL forms.
1968         * i386-tbl.h: Re-generate.
1969
1970 2018-01-09  Jim Wilson  <jimw@sifive.com>
1971
1972         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1973         then the hi_addr value is zero.
1974
1975 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1976
1977         * arm-dis.c (arm_opcodes): Add csdb.
1978         (thumb32_opcodes): Add csdb.
1979
1980 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1981
1982         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1983         * aarch64-asm-2.c: Regenerate.
1984         * aarch64-dis-2.c: Regenerate.
1985         * aarch64-opc-2.c: Regenerate.
1986
1987 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1988
1989         PR gas/22681
1990         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1991         Remove AVX512 vmovd with 64-bit operands.
1992         * i386-tbl.h: Regenerated.
1993
1994 2018-01-05  Jim Wilson  <jimw@sifive.com>
1995
1996         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1997         jalr.
1998
1999 2018-01-03  Alan Modra  <amodra@gmail.com>
2000
2001         Update year range in copyright notice of all files.
2002
2003 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2004
2005         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2006         and OPERAND_TYPE_REGZMM entries.
2007
2008 For older changes see ChangeLog-2017
2009 \f
2010 Copyright (C) 2018 Free Software Foundation, Inc.
2011
2012 Copying and distribution of this file, with or without modification,
2013 are permitted in any medium without royalty provided the copyright
2014 notice and this notice are preserved.
2015
2016 Local Variables:
2017 mode: change-log
2018 left-margin: 8
2019 fill-column: 74
2020 version-control: never
2021 End: