opcodes/ChangeLog

   1 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
   4         * i386-tbl.h: Regenerated.
   5
   6 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         PR gas/23665
   9         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
  10         VEX_LEN_0FD6_P_2 entries.
  11         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
  12         * i386-tbl.h: Regenerated.
  13
  14 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  15
  16         PR gas/23642
  17         * i386-opc.h (VEXWIG): New.
  18         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
  19         * i386-tbl.h: Regenerated.
  20
  21 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         PR binutils/23655
  24         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
  25         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
  26         * i386-dis.c (EXxEVexR64): New.
  27         (evex_rounding_64_mode): Likewise.
  28         (OP_Rounding): Handle evex_rounding_64_mode.
  29
  30 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  31
  32         PR binutils/23655
  33         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
  34         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
  35         * i386-dis.c (Edqa): New.
  36         (dqa_mode): Likewise.
  37         (intel_operand_size): Handle dqa_mode as m_mode.
  38         (OP_E_register): Handle dqa_mode as dq_mode.
  39         (OP_E_memory): Set shift for dqa_mode based on address_mode.
  40
  41 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  42
  43         * i386-dis.c (OP_E_memory): Reformat.
  44
  45 2018-09-14  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-opc.tbl (crc32): Fold byte and word forms.
  48         * i386-tbl.h: Re-generate.
  49
  50 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
  51
  52         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
  53         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
  54         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
  55         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
  56         * i386-tbl.h: Regenerated.
  57
  58 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
  61         meaningless.
  62         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
  63         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
  64         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
  65         * i386-tbl.h: Re-generate.
  66
  67 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
  70         AVX512_4VNNIW insns.
  71         * i386-tbl.h: Re-generate.
  72
  73 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
  76         meaningless.
  77         * i386-tbl.h: Re-generate.
  78
  79 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
  82         meaningless.
  83         * i386-tbl.h: Re-generate.
  84
  85 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
  88         meaningless.
  89         * i386-tbl.h: Re-generate.
  90
  91 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
  94         meaningless.
  95         * i386-tbl.h: Re-generate.
  96
  97 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 100         meaningless.
 101         * i386-tbl.h: Re-generate.
 102
 103 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 104
 105         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 106         * i386-tbl.h: Re-generate.
 107
 108 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 111         * i386-tbl.h: Re-generate.
 112
 113 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 116         meaningless.
 117         * i386-tbl.h: Re-generate.
 118
 119 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 120
 121         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 122         meaningless.
 123         * i386-tbl.h: Re-generate.
 124
 125 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 128         * i386-tbl.h: Re-generate.
 129
 130 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 133         * i386-tbl.h: Re-generate.
 134
 135 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 138         * i386-tbl.h: Re-generate.
 139
 140 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 143         meaningless.
 144         * i386-tbl.h: Re-generate.
 145
 146 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 149         meaningless.
 150         * i386-tbl.h: Re-generate.
 151
 152 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 155         meaningless.
 156         * i386-tbl.h: Re-generate.
 157
 158 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 159
 160         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 161         * i386-tbl.h: Re-generate.
 162
 163 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 164
 165         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 166         * i386-tbl.h: Re-generate.
 167
 168 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 171         * i386-tbl.h: Re-generate.
 172
 173 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 176         (vpbroadcastw, rdpid): Drop NoRex64.
 177         * i386-tbl.h: Re-generate.
 178
 179 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 182         store templates, adding D.
 183         * i386-tbl.h: Re-generate.
 184
 185 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 188         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 189         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 190         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 191         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 192         Fold load and store templates where possible, adding D. Drop
 193         IgnoreSize where it was pointlessly present. Drop redundant
 194         *word.
 195         * i386-tbl.h: Re-generate.
 196
 197 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 200         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 201         (intel_operand_size): Handle v_bndmk_mode.
 202         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 203
 204 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 205
 206         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 207
 208 2018-08-31  Kito Cheng  <kito@andestech.com>
 209
 210         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 211         compressed floating point instructions.
 212
 213 2018-08-30  Kito Cheng  <kito@andestech.com>
 214
 215         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 216         riscv_opcode.xlen_requirement.
 217         * riscv-opc.c (riscv_opcodes): Update for struct change.
 218
 219 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 220
 221         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 222         psr (PWRPSR) instruction.
 223
 224 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 225
 226         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 227
 228 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 229
 230         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 231
 232 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 233
 234         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 235         loongson3a as an alias of gs464 for compatibility.
 236         * mips-opc.c (mips_opcodes): Change Comments.
 237
 238 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 239
 240         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 241         option.
 242         (print_mips_disassembler_options): Document -M loongson-ext.
 243         * mips-opc.c (LEXT2): New macro.
 244         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 245
 246 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 247
 248          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 249          descriptors.
 250          (parse_mips_ase_option): Handle -M loongson-ext option.
 251          (print_mips_disassembler_options): Document -M loongson-ext.
 252          * mips-opc.c (IL3A): Delete.
 253          * mips-opc.c (LEXT): New macro.
 254          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 255          instructions.
 256
 257 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 258
 259         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 260         descriptors.
 261         (parse_mips_ase_option): Handle -M loongson-cam option.
 262         (print_mips_disassembler_options): Document -M loongson-cam.
 263         * mips-opc.c (LCAM): New macro.
 264         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 265         instructions.
 266
 267 2018-08-21  Alan Modra  <amodra@gmail.com>
 268
 269         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 270         (skip_optional_operands): Count optional operands, and update
 271         ppc_optional_operand_value call.
 272         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 273         (extract_vlensi): Likewise.
 274         (extract_fxm): Return default value for missing optional operand.
 275         (extract_ls, extract_raq, extract_tbr): Likewise.
 276         (insert_sxl, extract_sxl): New functions.
 277         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 278         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 279         flag and extra entry.
 280         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 281         extract_sxl.
 282
 283 2018-08-20  Alan Modra  <amodra@gmail.com>
 284
 285         * sh-opc.h (MASK): Simplify.
 286
 287 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 288
 289         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 290         BM_RESERVED0 or BM_RESERVED1
 291         (bm_rel_decode, bm_n_bytes): Ditto.
 292
 293 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 294
 295         * s12z.h: Delete.
 296
 297 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 298
 299         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 300         address with the addr32 prefix and without base nor index
 301         registers.
 302
 303 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 304
 305         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 306         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 307         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 308         (cpu_flags): Add CpuCMOV and CpuFXSR.
 309         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 310         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 311         * i386-init.h: Regenerated.
 312         * i386-tbl.h: Likewise.
 313
 314 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 315
 316         * arc-regs.h: Update auxiliary registers.
 317
 318 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 321         (RegIP, RegIZ): Define.
 322         * i386-reg.tbl: Adjust comments.
 323         (rip): Use Qword instead of BaseIndex. Use RegIP.
 324         (eip): Use Dword instead of BaseIndex. Use RegIP.
 325         (riz): Add Qword. Use RegIZ.
 326         (eiz): Add Dword. Use RegIZ.
 327         * i386-tbl.h: Re-generate.
 328
 329 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 332         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 333         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 334         * i386-tbl.h: Re-generate.
 335
 336 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-gen.c (operand_types): Remove Mem field.
 339         * i386-opc.h (union i386_operand_type): Remove mem field.
 340         * i386-init.h, i386-tbl.h: Re-generate.
 341
 342 2018-08-01  Alan Modra  <amodra@gmail.com>
 343
 344         * po/POTFILES.in: Regenerate.
 345
 346 2018-07-31  Nick Clifton  <nickc@redhat.com>
 347
 348         * po/sv.po: Updated Swedish translation.
 349
 350 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 351
 352         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 353         * i386-init.h, i386-tbl.h: Re-generate.
 354
 355 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-opc.h (ZEROING_MASKING) Rename to ...
 358         (DYNAMIC_MASKING): ... this. Adjust comment.
 359         * i386-opc.tbl (MaskingMorZ): Define.
 360         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 361         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 362         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 363         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 364         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 365         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 366         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 367         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 368         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 369
 370 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-opc.tbl: Use element rather than vector size for AVX512*
 373         scatter/gather insns.
 374         * i386-tbl.h: Re-generate.
 375
 376 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 379         (cpu_flags): Drop CpuVREX.
 380         * i386-opc.h (CpuVREX): Delete.
 381         (union i386_cpu_flags): Remove cpuvrex.
 382         * i386-init.h, i386-tbl.h: Re-generate.
 383
 384 2018-07-30  Jim Wilson  <jimw@sifive.com>
 385
 386         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 387         fields.
 388         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 389
 390 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 391
 392         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 393         * Makefile.in: Regenerated.
 394         * configure.ac: Add C-SKY.
 395         * configure: Regenerated.
 396         * csky-dis.c: New file.
 397         * csky-opc.h: New file.
 398         * disassemble.c (ARCH_csky): Define.
 399         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 400         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 401
 402 2018-07-27  Alan Modra  <amodra@gmail.com>
 403
 404         * ppc-opc.c (insert_sprbat): Correct function parameter and
 405         return type.
 406         (extract_sprbat): Likewise, variable too.
 407
 408 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 409             Alan Modra  <amodra@gmail.com>
 410
 411         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 412         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 413         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 414         support disjointed BAT.
 415         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 416         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 417         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 418
 419 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 420             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 421
 422         * i386-gen.c (adjust_broadcast_modifier): New function.
 423         (process_i386_opcode_modifier): Add an argument for operands.
 424         Adjust the Broadcast value based on operands.
 425         (output_i386_opcode): Pass operand_types to
 426         process_i386_opcode_modifier.
 427         (process_i386_opcodes): Pass NULL as operands to
 428         process_i386_opcode_modifier.
 429         * i386-opc.h (BYTE_BROADCAST): New.
 430         (WORD_BROADCAST): Likewise.
 431         (DWORD_BROADCAST): Likewise.
 432         (QWORD_BROADCAST): Likewise.
 433         (i386_opcode_modifier): Expand broadcast to 3 bits.
 434         * i386-tbl.h: Regenerated.
 435
 436 2018-07-24  Alan Modra  <amodra@gmail.com>
 437
 438         PR 23430
 439         * or1k-desc.h: Regenerate.
 440
 441 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 442
 443         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 444         vcvtusi2ss, and vcvtusi2sd.
 445         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 446         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 447         * i386-tbl.h: Re-generate.
 448
 449 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 450
 451         * arc-opc.c (extract_w6): Fix extending the sign.
 452
 453 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 454
 455         * arc-tbl.h (vewt): Allow it for ARC EM family.
 456
 457 2018-07-23  Alan Modra  <amodra@gmail.com>
 458
 459         PR 23419
 460         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 461         opcode variants for mtspr/mfspr encodings.
 462
 463 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 464             Maciej W. Rozycki  <macro@mips.com>
 465
 466         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 467         loongson3a descriptors.
 468         (parse_mips_ase_option): Handle -M loongson-mmi option.
 469         (print_mips_disassembler_options): Document -M loongson-mmi.
 470         * mips-opc.c (LMMI): New macro.
 471         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 472         instructions.
 473
 474 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 477         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 478         IgnoreSize and [XYZ]MMword where applicable.
 479         * i386-tbl.h: Re-generate.
 480
 481 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 484         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 485         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 486         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 487         * i386-tbl.h: Re-generate.
 488
 489 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 492         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 493         VPCLMULQDQ templates into their respective AVX512VL counterparts
 494         where possible, using Disp8ShiftVL and CheckRegSize instead of
 495         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 496         * i386-tbl.h: Re-generate.
 497
 498 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 501         AVX512VL counterparts where possible, using Disp8ShiftVL and
 502         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 503         IgnoreSize) as appropriate.
 504         * i386-tbl.h: Re-generate.
 505
 506 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-opc.tbl: Fold AVX512BW templates into their respective
 509         AVX512VL counterparts where possible, using Disp8ShiftVL and
 510         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 511         IgnoreSize) as appropriate.
 512         * i386-tbl.h: Re-generate.
 513
 514 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 515
 516         * i386-opc.tbl: Fold AVX512CD templates into their respective
 517         AVX512VL counterparts where possible, using Disp8ShiftVL and
 518         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 519         IgnoreSize) as appropriate.
 520         * i386-tbl.h: Re-generate.
 521
 522 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 523
 524         * i386-opc.h (DISP8_SHIFT_VL): New.
 525         * i386-opc.tbl (Disp8ShiftVL):  Define.
 526         (various): Fold AVX512VL templates into their respective
 527         AVX512F counterparts where possible, using Disp8ShiftVL and
 528         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 529         IgnoreSize) as appropriate.
 530         * i386-tbl.h: Re-generate.
 531
 532 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 533
 534         * Makefile.am: Change dependencies and rule for
 535         $(srcdir)/i386-init.h.
 536         * Makefile.in: Re-generate.
 537         * i386-gen.c (process_i386_opcodes): New local variable
 538         "marker". Drop opening of input file. Recognize marker and line
 539         number directives.
 540         * i386-opc.tbl (OPCODE_I386_H): Define.
 541         (i386-opc.h): Include it.
 542         (None): Undefine.
 543
 544 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 545
 546         PR gas/23418
 547         * i386-opc.h (Byte): Update comments.
 548         (Word): Likewise.
 549         (Dword): Likewise.
 550         (Fword): Likewise.
 551         (Qword): Likewise.
 552         (Tbyte): Likewise.
 553         (Xmmword): Likewise.
 554         (Ymmword): Likewise.
 555         (Zmmword): Likewise.
 556         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 557         vcvttps2uqq.
 558         * i386-tbl.h: Regenerated.
 559
 560 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 561
 562         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 563         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 564         * aarch64-asm-2.c: Regenerate.
 565         * aarch64-dis-2.c: Regenerate.
 566         * aarch64-opc-2.c: Regenerate.
 567
 568 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 569
 570         PR binutils/23192
 571         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 572         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 573         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 574         sqdmulh, sqrdmulh): Use Em16.
 575
 576 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 577
 578         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 579         csdb together with them.
 580         (thumb32_opcodes): Likewise.
 581
 582 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 585         requiring 32-bit registers as operands 2 and 3. Improve
 586         comments.
 587         (mwait, mwaitx): Fold templates. Improve comments.
 588         OPERAND_TYPE_INOUTPORTREG.
 589         * i386-tbl.h: Re-generate.
 590
 591 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 592
 593         * i386-gen.c (operand_type_init): Remove
 594         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 595         OPERAND_TYPE_INOUTPORTREG.
 596         * i386-init.h: Re-generate.
 597
 598 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 601         (wrssq, wrussq): Add Qword.
 602         * i386-tbl.h: Re-generate.
 603
 604 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 605
 606         * i386-opc.h: Rename OTMax to OTNum.
 607         (OTNumOfUints): Adjust calculation.
 608         (OTUnused): Directly alias to OTNum.
 609
 610 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 611
 612         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 613         `reg_xys'.
 614         (lea_reg_xys): Likewise.
 615         (print_insn_loop_primitive): Rename `reg' local variable to
 616         `reg_dxy'.
 617
 618 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 619
 620         PR binutils/23242
 621         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 622
 623 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 624
 625         PR binutils/23369
 626         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 627         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 628
 629 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 630
 631         PR tdep/8282
 632         * mips-dis.c (mips_option_arg_t): New enumeration.
 633         (mips_options): New variable.
 634         (disassembler_options_mips): New function.
 635         (print_mips_disassembler_options): Reimplement in terms of
 636         `disassembler_options_mips'.
 637         * arm-dis.c (disassembler_options_arm): Adapt to using the
 638         `disasm_options_and_args_t' structure.
 639         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 640         * s390-dis.c (disassembler_options_s390): Likewise.
 641
 642 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 643
 644         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 645         expected result.
 646         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 647         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 648         * testsuite/ld-arm/tls-longplt.d: Likewise.
 649
 650 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 651
 652         PR binutils/23192
 653         * aarch64-asm-2.c: Regenerate.
 654         * aarch64-dis-2.c: Likewise.
 655         * aarch64-opc-2.c: Likewise.
 656         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 657         * aarch64-opc.c (operand_general_constraint_met_p,
 658         aarch64_print_operand): Likewise.
 659         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 660         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 661         fmlal2, fmlsl2.
 662         (AARCH64_OPERANDS): Add Em2.
 663
 664 2018-06-26  Nick Clifton  <nickc@redhat.com>
 665
 666         * po/uk.po: Updated Ukranian translation.
 667         * po/de.po: Updated German translation.
 668         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 669
 670 2018-06-26  Nick Clifton  <nickc@redhat.com>
 671
 672         * nfp-dis.c: Fix spelling mistake.
 673
 674 2018-06-24  Nick Clifton  <nickc@redhat.com>
 675
 676         * configure: Regenerate.
 677         * po/opcodes.pot: Regenerate.
 678
 679 2018-06-24  Nick Clifton  <nickc@redhat.com>
 680
 681         2.31 branch created.
 682
 683 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 684
 685         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 686         * aarch64-asm-2.c: Regenerate.
 687         * aarch64-dis-2.c: Likewise.
 688
 689 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 690
 691         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 692         `-M ginv' option description.
 693
 694 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 695
 696         PR gas/23305
 697         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 698         la and lla.
 699
 700 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 701
 702         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 703         * configure.ac: Remove AC_PREREQ.
 704         * Makefile.in: Re-generate.
 705         * aclocal.m4: Re-generate.
 706         * configure: Re-generate.
 707
 708 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 709
 710         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 711         mips64r6 descriptors.
 712         (parse_mips_ase_option): Handle -Mginv option.
 713         (print_mips_disassembler_options): Document -Mginv.
 714         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 715         (GINV): New macro.
 716         (mips_opcodes): Define ginvi and ginvt.
 717
 718 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 719             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 720
 721         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 722         * mips-opc.c (CRC, CRC64): New macros.
 723         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 724         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 725         crc32cd for CRC64.
 726
 727 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 728
 729         PR 20319
 730         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 731         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 732
 733 2018-06-06  Alan Modra  <amodra@gmail.com>
 734
 735         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 736         setjmp.  Move init for some other vars later too.
 737
 738 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 739
 740         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 741         (dis_private): Add new fields for property section tracking.
 742         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 743         (xtensa_instruction_fits): New functions.
 744         (fetch_data): Bump minimal fetch size to 4.
 745         (print_insn_xtensa): Make struct dis_private static.
 746         Load and prepare property table on section change.
 747         Don't disassemble literals. Don't disassemble instructions that
 748         cross property table boundaries.
 749
 750 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 751
 752         * configure: Regenerated.
 753
 754 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 757         * i386-tbl.h: Re-generate.
 758
 759 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 760
 761         * i386-opc.tbl (sldt, str): Add NoRex64.
 762         * i386-tbl.h: Re-generate.
 763
 764 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 765
 766         * i386-opc.tbl (invpcid): Add Oword.
 767         * i386-tbl.h: Re-generate.
 768
 769 2018-06-01  Alan Modra  <amodra@gmail.com>
 770
 771         * sysdep.h (_bfd_error_handler): Don't declare.
 772         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 773         * rl78-decode.opc: Likewise.
 774         * msp430-decode.c: Regenerate.
 775         * rl78-decode.c: Regenerate.
 776
 777 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 778
 779         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 780         * i386-init.h : Regenerated.
 781
 782 2018-05-25  Alan Modra  <amodra@gmail.com>
 783
 784         * Makefile.in: Regenerate.
 785         * po/POTFILES.in: Regenerate.
 786
 787 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 788
 789         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 790         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 791         (insert_bab, extract_bab, insert_btab, extract_btab,
 792         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 793         (BAT, BBA VBA RBS XB6S): Delete macros.
 794         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 795         (BB, BD, RBX, XC6): Update for new macros.
 796         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 797         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 798         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 799         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 800
 801 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 802
 803         * Makefile.am: Add support for s12z architecture.
 804         * configure.ac: Likewise.
 805         * disassemble.c: Likewise.
 806         * disassemble.h: Likewise.
 807         * Makefile.in: Regenerate.
 808         * configure: Regenerate.
 809         * s12z-dis.c: New file.
 810         * s12z.h: New file.
 811
 812 2018-05-18  Alan Modra  <amodra@gmail.com>
 813
 814         * nfp-dis.c: Don't #include libbfd.h.
 815         (init_nfp3200_priv): Use bfd_get_section_contents.
 816         (nit_nfp6000_mecsr_sec): Likewise.
 817
 818 2018-05-17  Nick Clifton  <nickc@redhat.com>
 819
 820         * po/zh_CN.po: Updated simplified Chinese translation.
 821
 822 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 823
 824         PR binutils/23109
 825         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 826         * aarch64-dis-2.c: Regenerate.
 827
 828 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 829
 830         PR binutils/21446
 831         * aarch64-asm.c (opintl.h): Include.
 832         (aarch64_ins_sysreg): Enforce read/write constraints.
 833         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 834         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 835         (F_REG_READ, F_REG_WRITE): New.
 836         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 837         AARCH64_OPND_SYSREG.
 838         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 839         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 840         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 841         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 842         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 843         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 844         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 845         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 846         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 847         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 848         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 849         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 850         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 851         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 852         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 853         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 854         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 855
 856 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 857
 858         PR binutils/21446
 859         * aarch64-dis.c (no_notes: New.
 860         (parse_aarch64_dis_option): Support notes.
 861         (aarch64_decode_insn, print_operands): Likewise.
 862         (print_aarch64_disassembler_options): Document notes.
 863         * aarch64-opc.c (aarch64_print_operand): Support notes.
 864
 865 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 866
 867         PR binutils/21446
 868         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 869         and take error struct.
 870         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 871         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 872         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 873         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 874         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 875         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 876         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 877         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 878         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 879         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 880         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 881         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 882         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 883         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 884         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 885         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 886         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 887         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 888         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 889         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 890         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 891         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 892         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 893         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 894         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 895         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 896         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 897         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 898         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 899         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 900         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 901         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 902         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 903         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 904         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 905         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 906         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 907         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 908         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 909         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 910         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 911         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 912         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 913         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 914         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 915         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 916         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 917         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 918         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 919         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 920         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 921         (determine_disassembling_preference, aarch64_decode_insn,
 922         print_insn_aarch64_word, print_insn_data): Take errors struct.
 923         (print_insn_aarch64): Use errors.
 924         * aarch64-asm-2.c: Regenerate.
 925         * aarch64-dis-2.c: Regenerate.
 926         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 927         boolean in aarch64_insert_operan.
 928         (print_operand_extractor): Likewise.
 929         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 930
 931 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 932
 933         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 934
 935 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 936
 937         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 938
 939 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 940
 941         * cr16-opc.c (cr16_instruction): Comment typo fix.
 942         * hppa-dis.c (print_insn_hppa): Likewise.
 943
 944 2018-05-08  Jim Wilson  <jimw@sifive.com>
 945
 946         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 947         (match_c_slli64, match_srxi_as_c_srxi): New.
 948         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 949         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 950         <c.slli, c.srli, c.srai>: Use match_s_slli.
 951         <c.slli64, c.srli64, c.srai64>: New.
 952
 953 2018-05-08  Alan Modra  <amodra@gmail.com>
 954
 955         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 956         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 957         partition opcode space for index lookup.
 958
 959 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 960
 961         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 962         <insn_length>: ...with this.  Update usage.
 963         Remove duplicate call to *info->memory_error_func.
 964
 965 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 966             H.J. Lu  <hongjiu.lu@intel.com>
 967
 968         * i386-dis.c (Gva): New.
 969         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 970         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 971         (prefix_table): New instructions (see prefix above).
 972         (mod_table): New instructions (see prefix above).
 973         (OP_G): Handle va_mode.
 974         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 975         CPU_MOVDIR64B_FLAGS.
 976         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 977         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 978         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 979         * i386-opc.tbl: Add movidir{i,64b}.
 980         * i386-init.h: Regenerated.
 981         * i386-tbl.h: Likewise.
 982
 983 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 984
 985         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 986         AddrPrefixOpReg.
 987         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 988         (AddrPrefixOpReg): This.
 989         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 990         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 991
 992 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 993
 994         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 995         (vle_num_opcodes): Likewise.
 996         (spe2_num_opcodes): Likewise.
 997         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 998         initialization loop.
 999         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1000         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1001         only once.
1002
1003 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1004
1005         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1006
1007 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1008
1009         Makefile.am: Added nfp-dis.c.
1010         configure.ac: Added bfd_nfp_arch.
1011         disassemble.h: Added print_insn_nfp prototype.
1012         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1013         nfp-dis.c: New, for NFP support.
1014         po/POTFILES.in: Added nfp-dis.c to the list.
1015         Makefile.in: Regenerate.
1016         configure: Regenerate.
1017
1018 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1019
1020         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1021         templates into their base ones.
1022         * i386-tlb.h: Re-generate.
1023
1024 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1025
1026         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1027         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1028         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1029         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1030         * i386-init.h: Re-generate.
1031
1032 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1035         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1036         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1037         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1038         comment.
1039         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1040         and CpuRegMask.
1041         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1042         CpuRegMask: Delete.
1043         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1044         cpuregzmm, and cpuregmask.
1045         * i386-init.h: Re-generate.
1046         * i386-tbl.h: Re-generate.
1047
1048 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1049
1050         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1051         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1052         * i386-init.h: Re-generate.
1053
1054 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-gen.c (VexImmExt): Delete.
1057         * i386-opc.h (VexImmExt, veximmext): Delete.
1058         * i386-opc.tbl: Drop all VexImmExt uses.
1059         * i386-tlb.h: Re-generate.
1060
1061 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1062
1063         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1064         register-only forms.
1065         * i386-tlb.h: Re-generate.
1066
1067 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1068
1069         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1070
1071 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1072
1073         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1074         PREFIX_0F1C.
1075         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1076         (cpu_flags): Add CpuCLDEMOTE.
1077         * i386-init.h: Regenerate.
1078         * i386-opc.h (enum): Add CpuCLDEMOTE,
1079         (i386_cpu_flags): Add cpucldemote.
1080         * i386-opc.tbl: Add cldemote.
1081         * i386-tbl.h: Regenerate.
1082
1083 2018-04-16  Alan Modra  <amodra@gmail.com>
1084
1085         * Makefile.am: Remove sh5 and sh64 support.
1086         * configure.ac: Likewise.
1087         * disassemble.c: Likewise.
1088         * disassemble.h: Likewise.
1089         * sh-dis.c: Likewise.
1090         * sh64-dis.c: Delete.
1091         * sh64-opc.c: Delete.
1092         * sh64-opc.h: Delete.
1093         * Makefile.in: Regenerate.
1094         * configure: Regenerate.
1095         * po/POTFILES.in: Regenerate.
1096
1097 2018-04-16  Alan Modra  <amodra@gmail.com>
1098
1099         * Makefile.am: Remove w65 support.
1100         * configure.ac: Likewise.
1101         * disassemble.c: Likewise.
1102         * disassemble.h: Likewise.
1103         * w65-dis.c: Delete.
1104         * w65-opc.h: Delete.
1105         * Makefile.in: Regenerate.
1106         * configure: Regenerate.
1107         * po/POTFILES.in: Regenerate.
1108
1109 2018-04-16  Alan Modra  <amodra@gmail.com>
1110
1111         * configure.ac: Remove we32k support.
1112         * configure: Regenerate.
1113
1114 2018-04-16  Alan Modra  <amodra@gmail.com>
1115
1116         * Makefile.am: Remove m88k support.
1117         * configure.ac: Likewise.
1118         * disassemble.c: Likewise.
1119         * disassemble.h: Likewise.
1120         * m88k-dis.c: Delete.
1121         * Makefile.in: Regenerate.
1122         * configure: Regenerate.
1123         * po/POTFILES.in: Regenerate.
1124
1125 2018-04-16  Alan Modra  <amodra@gmail.com>
1126
1127         * Makefile.am: Remove i370 support.
1128         * configure.ac: Likewise.
1129         * disassemble.c: Likewise.
1130         * disassemble.h: Likewise.
1131         * i370-dis.c: Delete.
1132         * i370-opc.c: Delete.
1133         * Makefile.in: Regenerate.
1134         * configure: Regenerate.
1135         * po/POTFILES.in: Regenerate.
1136
1137 2018-04-16  Alan Modra  <amodra@gmail.com>
1138
1139         * Makefile.am: Remove h8500 support.
1140         * configure.ac: Likewise.
1141         * disassemble.c: Likewise.
1142         * disassemble.h: Likewise.
1143         * h8500-dis.c: Delete.
1144         * h8500-opc.h: Delete.
1145         * Makefile.in: Regenerate.
1146         * configure: Regenerate.
1147         * po/POTFILES.in: Regenerate.
1148
1149 2018-04-16  Alan Modra  <amodra@gmail.com>
1150
1151         * configure.ac: Remove tahoe support.
1152         * configure: Regenerate.
1153
1154 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1155
1156         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1157         umwait.
1158         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1159         64-bit mode.
1160         * i386-tbl.h: Regenerated.
1161
1162 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1163
1164         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1165         PREFIX_MOD_1_0FAE_REG_6.
1166         (va_mode): New.
1167         (OP_E_register): Use va_mode.
1168         * i386-dis-evex.h (prefix_table):
1169         New instructions (see prefixes above).
1170         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1171         (cpu_flags): Likewise.
1172         * i386-opc.h (enum): Likewise.
1173         (i386_cpu_flags): Likewise.
1174         * i386-opc.tbl: Add umonitor, umwait, tpause.
1175         * i386-init.h: Regenerate.
1176         * i386-tbl.h: Likewise.
1177
1178 2018-04-11  Alan Modra  <amodra@gmail.com>
1179
1180         * opcodes/i860-dis.c: Delete.
1181         * opcodes/i960-dis.c: Delete.
1182         * Makefile.am: Remove i860 and i960 support.
1183         * configure.ac: Likewise.
1184         * disassemble.c: Likewise.
1185         * disassemble.h: Likewise.
1186         * Makefile.in: Regenerate.
1187         * configure: Regenerate.
1188         * po/POTFILES.in: Regenerate.
1189
1190 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1191
1192         PR binutils/23025
1193         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1194         to 0.
1195         (print_insn): Clear vex instead of vex.evex.
1196
1197 2018-04-04  Nick Clifton  <nickc@redhat.com>
1198
1199         * po/es.po: Updated Spanish translation.
1200
1201 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-gen.c (opcode_modifiers): Delete VecESize.
1204         * i386-opc.h (VecESize): Delete.
1205         (struct i386_opcode_modifier): Delete vecesize.
1206         * i386-opc.tbl: Drop VecESize.
1207         * i386-tlb.h: Re-generate.
1208
1209 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1210
1211         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1212         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1213         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1214         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1215         * i386-tlb.h: Re-generate.
1216
1217 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1218
1219         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1220         Fold AVX512 forms
1221         * i386-tlb.h: Re-generate.
1222
1223 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1224
1225         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1226         (vex_len_table): Drop Y for vcvt*2si.
1227         (putop): Replace plain 'Y' handling by abort().
1228
1229 2018-03-28  Nick Clifton  <nickc@redhat.com>
1230
1231         PR 22988
1232         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1233         instructions with only a base address register.
1234         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1235         handle AARHC64_OPND_SVE_ADDR_R.
1236         (aarch64_print_operand): Likewise.
1237         * aarch64-asm-2.c: Regenerate.
1238         * aarch64_dis-2.c: Regenerate.
1239         * aarch64-opc-2.c: Regenerate.
1240
1241 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1242
1243         * i386-opc.tbl: Drop VecESize from register only insn forms and
1244         memory forms not allowing broadcast.
1245         * i386-tlb.h: Re-generate.
1246
1247 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1248
1249         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1250         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1251         sha256*): Drop Disp<N>.
1252
1253 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-dis.c (EbndS, bnd_swap_mode): New.
1256         (prefix_table): Use EbndS.
1257         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1258         * i386-opc.tbl (bndmov): Move misplaced Load.
1259         * i386-tlb.h: Re-generate.
1260
1261 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1262
1263         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1264         templates allowing memory operands and folded ones for register
1265         only flavors.
1266         * i386-tlb.h: Re-generate.
1267
1268 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1269
1270         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1271         256-bit templates. Drop redundant leftover Disp<N>.
1272         * i386-tlb.h: Re-generate.
1273
1274 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1275
1276         * riscv-opc.c (riscv_insn_types): New.
1277
1278 2018-03-13  Nick Clifton  <nickc@redhat.com>
1279
1280         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1281
1282 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1283
1284         * i386-opc.tbl: Add Optimize to clr.
1285         * i386-tbl.h: Regenerated.
1286
1287 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1288
1289         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1290         * i386-opc.h (OldGcc): Removed.
1291         (i386_opcode_modifier): Remove oldgcc.
1292         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1293         instructions for old (<= 2.8.1) versions of gcc.
1294         * i386-tbl.h: Regenerated.
1295
1296 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1297
1298         * i386-opc.h (EVEXDYN): New.
1299         * i386-opc.tbl: Fold various AVX512VL templates.
1300         * i386-tlb.h: Re-generate.
1301
1302 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1303
1304         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1305         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1306         vpexpandd, vpexpandq): Fold AFX512VF templates.
1307         * i386-tlb.h: Re-generate.
1308
1309 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1310
1311         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1312         Fold 128- and 256-bit VEX-encoded templates.
1313         * i386-tlb.h: Re-generate.
1314
1315 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1316
1317         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1318         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1319         vpexpandd, vpexpandq): Fold AVX512F templates.
1320         * i386-tlb.h: Re-generate.
1321
1322 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1323
1324         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1325         64-bit templates. Drop Disp<N>.
1326         * i386-tlb.h: Re-generate.
1327
1328 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1329
1330         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1331         and 256-bit templates.
1332         * i386-tlb.h: Re-generate.
1333
1334 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1335
1336         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1337         * i386-tlb.h: Re-generate.
1338
1339 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1340
1341         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1342         Drop NoAVX.
1343         * i386-tlb.h: Re-generate.
1344
1345 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1346
1347         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1348         * i386-tlb.h: Re-generate.
1349
1350 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1351
1352         * i386-gen.c (opcode_modifiers): Delete FloatD.
1353         * i386-opc.h (FloatD): Delete.
1354         (struct i386_opcode_modifier): Delete floatd.
1355         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1356         FloatD by D.
1357         * i386-tlb.h: Re-generate.
1358
1359 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1360
1361         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1362
1363 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1364
1365         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1366         * i386-tlb.h: Re-generate.
1367
1368 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1369
1370         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1371         forms.
1372         * i386-tlb.h: Re-generate.
1373
1374 2018-03-07  Alan Modra  <amodra@gmail.com>
1375
1376         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1377         bfd_arch_rs6000.
1378         * disassemble.h (print_insn_rs6000): Delete.
1379         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1380         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1381         (print_insn_rs6000): Delete.
1382
1383 2018-03-03  Alan Modra  <amodra@gmail.com>
1384
1385         * sysdep.h (opcodes_error_handler): Define.
1386         (_bfd_error_handler): Declare.
1387         * Makefile.am: Remove stray #.
1388         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1389         EDIT" comment.
1390         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1391         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1392         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1393         opcodes_error_handler to print errors.  Standardize error messages.
1394         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1395         and include opintl.h.
1396         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1397         * i386-gen.c: Standardize error messages.
1398         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1399         * Makefile.in: Regenerate.
1400         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1401         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1402         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1403         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1404         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1405         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1406         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1407         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1408         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1409         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1410         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1411         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1412         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1413
1414 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1415
1416         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1417         vpsub[bwdq] instructions.
1418         * i386-tbl.h: Regenerated.
1419
1420 2018-03-01  Alan Modra  <amodra@gmail.com>
1421
1422         * configure.ac (ALL_LINGUAS): Sort.
1423         * configure: Regenerate.
1424
1425 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1426
1427         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1428         macro by assignements.
1429
1430 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1431
1432         PR gas/22871
1433         * i386-gen.c (opcode_modifiers): Add Optimize.
1434         * i386-opc.h (Optimize): New enum.
1435         (i386_opcode_modifier): Add optimize.
1436         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1437         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1438         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1439         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1440         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1441         vpxord and vpxorq.
1442         * i386-tbl.h: Regenerated.
1443
1444 2018-02-26  Alan Modra  <amodra@gmail.com>
1445
1446         * crx-dis.c (getregliststring): Allocate a large enough buffer
1447         to silence false positive gcc8 warning.
1448
1449 2018-02-22  Shea Levy <shea@shealevy.com>
1450
1451         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1452
1453 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1454
1455         * i386-opc.tbl: Add {rex},
1456         * i386-tbl.h: Regenerated.
1457
1458 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1459
1460         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1461         (mips16_opcodes): Replace `M' with `m' for "restore".
1462
1463 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1464
1465         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1466
1467 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1468
1469         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1470         variable to `function_index'.
1471
1472 2018-02-13  Nick Clifton  <nickc@redhat.com>
1473
1474         PR 22823
1475         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1476         about truncation of printing.
1477
1478 2018-02-12  Henry Wong <henry@stuffedcow.net>
1479
1480         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1481
1482 2018-02-05  Nick Clifton  <nickc@redhat.com>
1483
1484         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1485
1486 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1487
1488         * i386-dis.c (enum): Add pconfig.
1489         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1490         (cpu_flags): Add CpuPCONFIG.
1491         * i386-opc.h (enum): Add CpuPCONFIG.
1492         (i386_cpu_flags): Add cpupconfig.
1493         * i386-opc.tbl: Add PCONFIG instruction.
1494         * i386-init.h: Regenerate.
1495         * i386-tbl.h: Likewise.
1496
1497 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1498
1499         * i386-dis.c (enum): Add PREFIX_0F09.
1500         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1501         (cpu_flags): Add CpuWBNOINVD.
1502         * i386-opc.h (enum): Add CpuWBNOINVD.
1503         (i386_cpu_flags): Add cpuwbnoinvd.
1504         * i386-opc.tbl: Add WBNOINVD instruction.
1505         * i386-init.h: Regenerate.
1506         * i386-tbl.h: Likewise.
1507
1508 2018-01-17  Jim Wilson  <jimw@sifive.com>
1509
1510         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1511
1512 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1513
1514         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1515         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1516         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1517         (cpu_flags): Add CpuIBT, CpuSHSTK.
1518         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1519         (i386_cpu_flags): Add cpuibt, cpushstk.
1520         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1521         * i386-init.h: Regenerate.
1522         * i386-tbl.h: Likewise.
1523
1524 2018-01-16  Nick Clifton  <nickc@redhat.com>
1525
1526         * po/pt_BR.po: Updated Brazilian Portugese translation.
1527         * po/de.po: Updated German translation.
1528
1529 2018-01-15  Jim Wilson  <jimw@sifive.com>
1530
1531         * riscv-opc.c (match_c_nop): New.
1532         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1533
1534 2018-01-15  Nick Clifton  <nickc@redhat.com>
1535
1536         * po/uk.po: Updated Ukranian translation.
1537
1538 2018-01-13  Nick Clifton  <nickc@redhat.com>
1539
1540         * po/opcodes.pot: Regenerated.
1541
1542 2018-01-13  Nick Clifton  <nickc@redhat.com>
1543
1544         * configure: Regenerate.
1545
1546 2018-01-13  Nick Clifton  <nickc@redhat.com>
1547
1548         2.30 branch created.
1549
1550 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1551
1552         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1553         * i386-tbl.h: Regenerate.
1554
1555 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1556
1557         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1558         * i386-tbl.h: Re-generate.
1559
1560 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1561
1562         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1563         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1564         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1565         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1566         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1567         Disp8MemShift of AVX512VL forms.
1568         * i386-tbl.h: Re-generate.
1569
1570 2018-01-09  Jim Wilson  <jimw@sifive.com>
1571
1572         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1573         then the hi_addr value is zero.
1574
1575 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1576
1577         * arm-dis.c (arm_opcodes): Add csdb.
1578         (thumb32_opcodes): Add csdb.
1579
1580 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1581
1582         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1583         * aarch64-asm-2.c: Regenerate.
1584         * aarch64-dis-2.c: Regenerate.
1585         * aarch64-opc-2.c: Regenerate.
1586
1587 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1588
1589         PR gas/22681
1590         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1591         Remove AVX512 vmovd with 64-bit operands.
1592         * i386-tbl.h: Regenerated.
1593
1594 2018-01-05  Jim Wilson  <jimw@sifive.com>
1595
1596         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1597         jalr.
1598
1599 2018-01-03  Alan Modra  <amodra@gmail.com>
1600
1601         Update year range in copyright notice of all files.
1602
1603 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1604
1605         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1606         and OPERAND_TYPE_REGZMM entries.
1607
1608 For older changes see ChangeLog-2017
1609 \f
1610 Copyright (C) 2018 Free Software Foundation, Inc.
1611
1612 Copying and distribution of this file, with or without modification,
1613 are permitted in any medium without royalty provided the copyright
1614 notice and this notice are preserved.
1615
1616 Local Variables:
1617 mode: change-log
1618 left-margin: 8
1619 fill-column: 74
1620 version-control: never
1621 End: