opcodes/ChangeLog

   1 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
   2
   3         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
   4
   5 2019-06-03  Alan Modra  <amodra@gmail.com>
   6
   7         * ppc-dis.c (prefix_opcd_indices): Correct size.
   8
   9 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
  10
  11         PR gas/24625
  12         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
  13         Disp8ShiftVL.
  14         * i386-tbl.h: Regenerated.
  15
  16 2019-05-24  Alan Modra  <amodra@gmail.com>
  17
  18         * po/POTFILES.in: Regenerate.
  19
  20 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  21             Alan Modra  <amodra@gmail.com>
  22
  23         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
  24         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
  25         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
  26         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
  27         XTOP>): Define and add entries.
  28         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
  29         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
  30         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
  31         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
  32
  33 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  34             Alan Modra  <amodra@gmail.com>
  35
  36         * ppc-dis.c (ppc_opts): Add "future" entry.
  37         (PREFIX_OPCD_SEGS): Define.
  38         (prefix_opcd_indices): New array.
  39         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
  40         (lookup_prefix): New function.
  41         (print_insn_powerpc): Handle 64-bit prefix instructions.
  42         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
  43         (PMRR, POWERXX): Define.
  44         (prefix_opcodes): New instruction table.
  45         (prefix_num_opcodes): New constant.
  46
  47 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  48
  49         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
  50         * configure: Regenerated.
  51         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
  52         and cpu/bpf.opc.
  53         (HFILES): Add bpf-desc.h and bpf-opc.h.
  54         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
  55         bpf-ibld.c and bpf-opc.c.
  56         (BPF_DEPS): Define.
  57         * Makefile.in: Regenerated.
  58         * disassemble.c (ARCH_bpf): Define.
  59         (disassembler): Add case for bfd_arch_bpf.
  60         (disassemble_init_for_target): Likewise.
  61         (enum epbf_isa_attr): Define.
  62         * disassemble.h: extern print_insn_bpf.
  63         * bpf-asm.c: Generated.
  64         * bpf-opc.h: Likewise.
  65         * bpf-opc.c: Likewise.
  66         * bpf-ibld.c: Likewise.
  67         * bpf-dis.c: Likewise.
  68         * bpf-desc.h: Likewise.
  69         * bpf-desc.c: Likewise.
  70
  71 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  72
  73         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
  74         and VMSR with the new operands.
  75
  76 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  77
  78         * arm-dis.c (enum mve_instructions): New enum
  79         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
  80         and cneg.
  81         (mve_opcodes): New instructions as above.
  82         (is_mve_encoding_conflict): Add cases for csinc, csinv,
  83         csneg and csel.
  84         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
  85
  86 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  87
  88         * arm-dis.c (emun mve_instructions): Updated for new instructions.
  89         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
  90         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
  91         uqshl, urshrl and urshr.
  92         (is_mve_okay_in_it): Add new instructions to TRUE list.
  93         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
  94         (print_insn_mve): Updated to accept new %j,
  95         %<bitfield>m and %<bitfield>n patterns.
  96
  97 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
  98
  99         * mips-opc.c (mips_builtin_opcodes): Change source register
 100         constraint for DAUI.
 101
 102 2019-05-20  Nick Clifton  <nickc@redhat.com>
 103
 104         * po/fr.po: Updated French translation.
 105
 106 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 107             Michael Collison <michael.collison@arm.com>
 108
 109         * arm-dis.c (thumb32_opcodes): Add new instructions.
 110         (enum mve_instructions): Likewise.
 111         (enum mve_undefined): Add new reasons.
 112         (is_mve_encoding_conflict): Handle new instructions.
 113         (is_mve_undefined): Likewise.
 114         (is_mve_unpredictable): Likewise.
 115         (print_mve_undefined): Likewise.
 116         (print_mve_size): Likewise.
 117
 118 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 119             Michael Collison <michael.collison@arm.com>
 120
 121         * arm-dis.c (thumb32_opcodes): Add new instructions.
 122         (enum mve_instructions): Likewise.
 123         (is_mve_encoding_conflict): Handle new instructions.
 124         (is_mve_undefined): Likewise.
 125         (is_mve_unpredictable): Likewise.
 126         (print_mve_size): Likewise.
 127
 128 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 129             Michael Collison <michael.collison@arm.com>
 130
 131         * arm-dis.c (thumb32_opcodes): Add new instructions.
 132         (enum mve_instructions): Likewise.
 133         (is_mve_encoding_conflict): Likewise.
 134         (is_mve_unpredictable): Likewise.
 135         (print_mve_size): Likewise.
 136
 137 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 138             Michael Collison <michael.collison@arm.com>
 139
 140         * arm-dis.c (thumb32_opcodes): Add new instructions.
 141         (enum mve_instructions): Likewise.
 142         (is_mve_encoding_conflict): Handle new instructions.
 143         (is_mve_undefined): Likewise.
 144         (is_mve_unpredictable): Likewise.
 145         (print_mve_size): Likewise.
 146
 147 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 148             Michael Collison <michael.collison@arm.com>
 149
 150         * arm-dis.c (thumb32_opcodes): Add new instructions.
 151         (enum mve_instructions): Likewise.
 152         (is_mve_encoding_conflict): Handle new instructions.
 153         (is_mve_undefined): Likewise.
 154         (is_mve_unpredictable): Likewise.
 155         (print_mve_size): Likewise.
 156         (print_insn_mve): Likewise.
 157
 158 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 159             Michael Collison <michael.collison@arm.com>
 160
 161         * arm-dis.c (thumb32_opcodes): Add new instructions.
 162         (print_insn_thumb32): Handle new instructions.
 163
 164 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 165             Michael Collison <michael.collison@arm.com>
 166
 167         * arm-dis.c (enum mve_instructions): Add new instructions.
 168         (enum mve_undefined): Add new reasons.
 169         (is_mve_encoding_conflict): Handle new instructions.
 170         (is_mve_undefined): Likewise.
 171         (is_mve_unpredictable): Likewise.
 172         (print_mve_undefined): Likewise.
 173         (print_mve_size): Likewise.
 174         (print_mve_shift_n): Likewise.
 175         (print_insn_mve): Likewise.
 176
 177 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 178             Michael Collison <michael.collison@arm.com>
 179
 180         * arm-dis.c (enum mve_instructions): Add new instructions.
 181         (is_mve_encoding_conflict): Handle new instructions.
 182         (is_mve_unpredictable): Likewise.
 183         (print_mve_rotate): Likewise.
 184         (print_mve_size): Likewise.
 185         (print_insn_mve): Likewise.
 186
 187 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 188             Michael Collison <michael.collison@arm.com>
 189
 190         * arm-dis.c (enum mve_instructions): Add new instructions.
 191         (is_mve_encoding_conflict): Handle new instructions.
 192         (is_mve_unpredictable): Likewise.
 193         (print_mve_size): Likewise.
 194         (print_insn_mve): Likewise.
 195
 196 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 197             Michael Collison <michael.collison@arm.com>
 198
 199         * arm-dis.c (enum mve_instructions): Add new instructions.
 200         (enum mve_undefined): Add new reasons.
 201         (is_mve_encoding_conflict): Handle new instructions.
 202         (is_mve_undefined): Likewise.
 203         (is_mve_unpredictable): Likewise.
 204         (print_mve_undefined): Likewise.
 205         (print_mve_size): Likewise.
 206         (print_insn_mve): Likewise.
 207
 208 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 209             Michael Collison <michael.collison@arm.com>
 210
 211         * arm-dis.c (enum mve_instructions): Add new instructions.
 212         (is_mve_encoding_conflict): Handle new instructions.
 213         (is_mve_undefined): Likewise.
 214         (is_mve_unpredictable): Likewise.
 215         (print_mve_size): Likewise.
 216         (print_insn_mve): Likewise.
 217
 218 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 219             Michael Collison <michael.collison@arm.com>
 220
 221         * arm-dis.c (enum mve_instructions): Add new instructions.
 222         (enum mve_unpredictable): Add new reasons.
 223         (enum mve_undefined): Likewise.
 224         (is_mve_okay_in_it): Handle new isntructions.
 225         (is_mve_encoding_conflict): Likewise.
 226         (is_mve_undefined): Likewise.
 227         (is_mve_unpredictable): Likewise.
 228         (print_mve_vmov_index): Likewise.
 229         (print_simd_imm8): Likewise.
 230         (print_mve_undefined): Likewise.
 231         (print_mve_unpredictable): Likewise.
 232         (print_mve_size): Likewise.
 233         (print_insn_mve): Likewise.
 234
 235 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 236             Michael Collison <michael.collison@arm.com>
 237
 238         * arm-dis.c (enum mve_instructions): Add new instructions.
 239         (enum mve_unpredictable): Add new reasons.
 240         (enum mve_undefined): Likewise.
 241         (is_mve_encoding_conflict): Handle new instructions.
 242         (is_mve_undefined): Likewise.
 243         (is_mve_unpredictable): Likewise.
 244         (print_mve_undefined): Likewise.
 245         (print_mve_unpredictable): Likewise.
 246         (print_mve_rounding_mode): Likewise.
 247         (print_mve_vcvt_size): Likewise.
 248         (print_mve_size): Likewise.
 249         (print_insn_mve): Likewise.
 250
 251 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 252             Michael Collison <michael.collison@arm.com>
 253
 254         * arm-dis.c (enum mve_instructions): Add new instructions.
 255         (enum mve_unpredictable): Add new reasons.
 256         (enum mve_undefined): Likewise.
 257         (is_mve_undefined): Handle new instructions.
 258         (is_mve_unpredictable): Likewise.
 259         (print_mve_undefined): Likewise.
 260         (print_mve_unpredictable): Likewise.
 261         (print_mve_size): Likewise.
 262         (print_insn_mve): Likewise.
 263
 264 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 265             Michael Collison <michael.collison@arm.com>
 266
 267         * arm-dis.c (enum mve_instructions): Add new instructions.
 268         (enum mve_undefined): Add new reasons.
 269         (insns): Add new instructions.
 270         (is_mve_encoding_conflict):
 271         (print_mve_vld_str_addr): New print function.
 272         (is_mve_undefined): Handle new instructions.
 273         (is_mve_unpredictable): Likewise.
 274         (print_mve_undefined): Likewise.
 275         (print_mve_size): Likewise.
 276         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 277         (print_insn_mve):  Handle new operands.
 278
 279 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 280             Michael Collison <michael.collison@arm.com>
 281
 282         * arm-dis.c (enum mve_instructions): Add new instructions.
 283         (enum mve_unpredictable): Add new reasons.
 284         (is_mve_encoding_conflict): Handle new instructions.
 285         (is_mve_unpredictable): Likewise.
 286         (mve_opcodes): Add new instructions.
 287         (print_mve_unpredictable): Handle new reasons.
 288         (print_mve_register_blocks): New print function.
 289         (print_mve_size): Handle new instructions.
 290         (print_insn_mve): Likewise.
 291
 292 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 293             Michael Collison <michael.collison@arm.com>
 294
 295         * arm-dis.c (enum mve_instructions): Add new instructions.
 296         (enum mve_unpredictable): Add new reasons.
 297         (enum mve_undefined): Likewise.
 298         (is_mve_encoding_conflict): Handle new instructions.
 299         (is_mve_undefined): Likewise.
 300         (is_mve_unpredictable): Likewise.
 301         (coprocessor_opcodes): Move NEON VDUP from here...
 302         (neon_opcodes): ... to here.
 303         (mve_opcodes): Add new instructions.
 304         (print_mve_undefined):  Handle new reasons.
 305         (print_mve_unpredictable): Likewise.
 306         (print_mve_size): Handle new instructions.
 307         (print_insn_neon): Handle vdup.
 308         (print_insn_mve): Handle new operands.
 309
 310 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 311             Michael Collison <michael.collison@arm.com>
 312
 313         * arm-dis.c (enum mve_instructions): Add new instructions.
 314         (enum mve_unpredictable): Add new values.
 315         (mve_opcodes): Add new instructions.
 316         (vec_condnames): New array with vector conditions.
 317         (mve_predicatenames): New array with predicate suffixes.
 318         (mve_vec_sizename): New array with vector sizes.
 319         (enum vpt_pred_state): New enum with vector predication states.
 320         (struct vpt_block): New struct type for vpt blocks.
 321         (vpt_block_state): Global struct to keep track of state.
 322         (mve_extract_pred_mask): New helper function.
 323         (num_instructions_vpt_block): Likewise.
 324         (mark_outside_vpt_block): Likewise.
 325         (mark_inside_vpt_block): Likewise.
 326         (invert_next_predicate_state): Likewise.
 327         (update_next_predicate_state): Likewise.
 328         (update_vpt_block_state): Likewise.
 329         (is_vpt_instruction): Likewise.
 330         (is_mve_encoding_conflict): Add entries for new instructions.
 331         (is_mve_unpredictable): Likewise.
 332         (print_mve_unpredictable): Handle new cases.
 333         (print_instruction_predicate): Likewise.
 334         (print_mve_size): New function.
 335         (print_vec_condition): New function.
 336         (print_insn_mve): Handle vpt blocks and new print operands.
 337
 338 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 339
 340         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 341         8, 14 and 15 for Armv8.1-M Mainline.
 342
 343 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 344             Michael Collison <michael.collison@arm.com>
 345
 346         * arm-dis.c (enum mve_instructions): New enum.
 347         (enum mve_unpredictable): Likewise.
 348         (enum mve_undefined): Likewise.
 349         (struct mopcode32): New struct.
 350         (is_mve_okay_in_it): New function.
 351         (is_mve_architecture): Likewise.
 352         (arm_decode_field): Likewise.
 353         (arm_decode_field_multiple): Likewise.
 354         (is_mve_encoding_conflict): Likewise.
 355         (is_mve_undefined): Likewise.
 356         (is_mve_unpredictable): Likewise.
 357         (print_mve_undefined): Likewise.
 358         (print_mve_unpredictable): Likewise.
 359         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 360         (print_insn_mve): New function.
 361         (print_insn_thumb32): Handle MVE architecture.
 362         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 363
 364 2019-05-10  Nick Clifton  <nickc@redhat.com>
 365
 366         PR 24538
 367         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 368         end of the table prematurely.
 369
 370 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 371
 372         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 373         macros for R6.
 374
 375 2019-05-11  Alan Modra  <amodra@gmail.com>
 376
 377         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 378         when -Mraw is in effect.
 379
 380 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 381
 382         * aarch64-dis-2.c: Regenerate.
 383         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 384         (OP_SVE_BBB): New variant set.
 385         (OP_SVE_DDDD): New variant set.
 386         (OP_SVE_HHH): New variant set.
 387         (OP_SVE_HHHU): New variant set.
 388         (OP_SVE_SSS): New variant set.
 389         (OP_SVE_SSSU): New variant set.
 390         (OP_SVE_SHH): New variant set.
 391         (OP_SVE_SBBU): New variant set.
 392         (OP_SVE_DSS): New variant set.
 393         (OP_SVE_DHHU): New variant set.
 394         (OP_SVE_VMV_HSD_BHS): New variant set.
 395         (OP_SVE_VVU_HSD_BHS): New variant set.
 396         (OP_SVE_VVVU_SD_BH): New variant set.
 397         (OP_SVE_VVVU_BHSD): New variant set.
 398         (OP_SVE_VVV_QHD_DBS): New variant set.
 399         (OP_SVE_VVV_HSD_BHS): New variant set.
 400         (OP_SVE_VVV_HSD_BHS2): New variant set.
 401         (OP_SVE_VVV_BHS_HSD): New variant set.
 402         (OP_SVE_VV_BHS_HSD): New variant set.
 403         (OP_SVE_VVV_SD): New variant set.
 404         (OP_SVE_VVU_BHS_HSD): New variant set.
 405         (OP_SVE_VZVV_SD): New variant set.
 406         (OP_SVE_VZVV_BH): New variant set.
 407         (OP_SVE_VZV_SD): New variant set.
 408         (aarch64_opcode_table): Add sve2 instructions.
 409
 410 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 411
 412         * aarch64-asm-2.c: Regenerated.
 413         * aarch64-dis-2.c: Regenerated.
 414         * aarch64-opc-2.c: Regenerated.
 415         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 416         for SVE_SHLIMM_UNPRED_22.
 417         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 418         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 419         operand.
 420
 421 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 422
 423         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 424         sve_size_tsz_bhs iclass encode.
 425         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 426         sve_size_tsz_bhs iclass decode.
 427
 428 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 429
 430         * aarch64-asm-2.c: Regenerated.
 431         * aarch64-dis-2.c: Regenerated.
 432         * aarch64-opc-2.c: Regenerated.
 433         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 434         for SVE_Zm4_11_INDEX.
 435         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 436         (fields): Handle SVE_i2h field.
 437         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 438         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 439
 440 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 441
 442         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 443         sve_shift_tsz_bhsd iclass encode.
 444         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 445         sve_shift_tsz_bhsd iclass decode.
 446
 447 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 448
 449         * aarch64-asm-2.c: Regenerated.
 450         * aarch64-dis-2.c: Regenerated.
 451         * aarch64-opc-2.c: Regenerated.
 452         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 453         (aarch64_encode_variant_using_iclass): Handle
 454         sve_shift_tsz_hsd iclass encode.
 455         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 456         sve_shift_tsz_hsd iclass decode.
 457         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 458         for SVE_SHRIMM_UNPRED_22.
 459         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 460         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 461         operand.
 462
 463 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 464
 465         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 466         sve_size_013 iclass encode.
 467         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 468         sve_size_013 iclass decode.
 469
 470 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 471
 472         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 473         sve_size_bh iclass encode.
 474         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 475         sve_size_bh iclass decode.
 476
 477 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 478
 479         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 480         sve_size_sd2 iclass encode.
 481         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 482         sve_size_sd2 iclass decode.
 483         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 484         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 485
 486 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 487
 488         * aarch64-asm-2.c: Regenerated.
 489         * aarch64-dis-2.c: Regenerated.
 490         * aarch64-opc-2.c: Regenerated.
 491         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 492         for SVE_ADDR_ZX.
 493         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 494         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 495
 496 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 497
 498         * aarch64-asm-2.c: Regenerated.
 499         * aarch64-dis-2.c: Regenerated.
 500         * aarch64-opc-2.c: Regenerated.
 501         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 502         for SVE_Zm3_11_INDEX.
 503         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 504         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 505         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 506         fields.
 507         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 508
 509 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 510
 511         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 512         sve_size_hsd2 iclass encode.
 513         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 514         sve_size_hsd2 iclass decode.
 515         * aarch64-opc.c (fields): Handle SVE_size field.
 516         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 517
 518 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 519
 520         * aarch64-asm-2.c: Regenerated.
 521         * aarch64-dis-2.c: Regenerated.
 522         * aarch64-opc-2.c: Regenerated.
 523         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 524         for SVE_IMM_ROT3.
 525         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 526         (fields): Handle SVE_rot3 field.
 527         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 528         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 529
 530 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 531
 532         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 533         instructions.
 534
 535 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 536
 537         * aarch64-tbl.h
 538         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 539         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 540         aarch64_feature_sve2bitperm): New feature sets.
 541         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 542         for feature set addresses.
 543         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 544         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 545
 546 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 547             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 548
 549         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 550         argument and set ASE_EVA_R6 appropriately.
 551         (set_default_mips_dis_options): Pass ISA to above.
 552         (parse_mips_dis_option): Likewise.
 553         * mips-opc.c (EVAR6): New macro.
 554         (mips_builtin_opcodes): Add llwpe, scwpe.
 555
 556 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 557
 558         * aarch64-asm-2.c: Regenerated.
 559         * aarch64-dis-2.c: Regenerated.
 560         * aarch64-opc-2.c: Regenerated.
 561         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 562         AARCH64_OPND_TME_UIMM16.
 563         (aarch64_print_operand): Likewise.
 564         * aarch64-tbl.h (QL_IMM_NIL): New.
 565         (TME): New.
 566         (_TME_INSN): New.
 567         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 568
 569 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 570
 571         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 572
 573 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 574             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 575
 576         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 577
 578 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 579
 580         * s12z-opc.h: Add extern "C" bracketing to help
 581         users who wish to use this interface in c++ code.
 582
 583 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 584
 585         * s12z-opc.c (bm_decode): Handle bit map operations with the
 586         "reserved0" mode.
 587
 588 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 589
 590         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 591         specifier.  Add entries for VLDR and VSTR of system registers.
 592         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 593         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 594         of %J and %K format specifier.
 595
 596 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 597
 598         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 599         Add new entries for VSCCLRM instruction.
 600         (print_insn_coprocessor): Handle new %C format control code.
 601
 602 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 603
 604         * arm-dis.c (enum isa): New enum.
 605         (struct sopcode32): New structure.
 606         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 607         set isa field of all current entries to ANY.
 608         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 609         Only match an entry if its isa field allows the current mode.
 610
 611 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 612
 613         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 614         CLRM.
 615         (print_insn_thumb32): Add logic to print %n CLRM register list.
 616
 617 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 618
 619         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 620         and %Q patterns.
 621
 622 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 623
 624         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 625         (print_insn_thumb32): Edit the switch case for %Z.
 626
 627 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 628
 629         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 630
 631 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 632
 633         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 634
 635 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 636
 637         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 638
 639 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 640
 641         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 642         Arm register with r13 and r15 unpredictable.
 643         (thumb32_opcodes): New instructions for bfx and bflx.
 644
 645 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 646
 647         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 648
 649 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 650
 651         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 652
 653 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 654
 655         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 656
 657 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 658
 659         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 660
 661 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 662
 663         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 664         "optr". ("operator" is a reserved word in c++).
 665
 666 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 667
 668         * aarch64-opc.c (aarch64_print_operand): Add case for
 669         AARCH64_OPND_Rt_SP.
 670         (verify_constraints): Likewise.
 671         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 672         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 673         to accept Rt|SP as first operand.
 674         (AARCH64_OPERANDS): Add new Rt_SP.
 675         * aarch64-asm-2.c: Regenerated.
 676         * aarch64-dis-2.c: Regenerated.
 677         * aarch64-opc-2.c: Regenerated.
 678
 679 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 680
 681         * aarch64-asm-2.c: Regenerated.
 682         * aarch64-dis-2.c: Likewise.
 683         * aarch64-opc-2.c: Likewise.
 684         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 685
 686 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 687
 688         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 689
 690 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 691
 692         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 693         * i386-init.h: Regenerated.
 694
 695 2019-04-07  Alan Modra  <amodra@gmail.com>
 696
 697         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 698         op_separator to control printing of spaces, comma and parens
 699         rather than need_comma, need_paren and spaces vars.
 700
 701 2019-04-07  Alan Modra  <amodra@gmail.com>
 702
 703         PR 24421
 704         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 705         (print_insn_neon, print_insn_arm): Likewise.
 706
 707 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 708
 709         * i386-dis-evex.h (evex_table): Updated to support BF16
 710         instructions.
 711         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 712         and EVEX_W_0F3872_P_3.
 713         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 714         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 715         * i386-opc.h (enum): Add CpuAVX512_BF16.
 716         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 717         * i386-opc.tbl: Add AVX512 BF16 instructions.
 718         * i386-init.h: Regenerated.
 719         * i386-tbl.h: Likewise.
 720
 721 2019-04-05  Alan Modra  <amodra@gmail.com>
 722
 723         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 724         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 725         to favour printing of "-" branch hint when using the "y" bit.
 726         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 727
 728 2019-04-05  Alan Modra  <amodra@gmail.com>
 729
 730         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 731         opcode until first operand is output.
 732
 733 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 734
 735         PR gas/24349
 736         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 737         (valid_bo_post_v2): Add support for 'at' branch hints.
 738         (insert_bo): Only error on branch on ctr.
 739         (get_bo_hint_mask): New function.
 740         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 741         for inserting 'at' branch hints.
 742         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 743         for extracting 'at' branch hints.
 744         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 745         (BOE): Delete operand.
 746         (BOM, BOP): New operands.
 747         (RM): Update value.
 748         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 749         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 750         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 751         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 752         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 753         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 754         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 755         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 756         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 757         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 758         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 759         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 760         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 761         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 762         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 763         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 764         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 765         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 766         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 767         bttarl+>: New extended mnemonics.
 768
 769 2019-03-28  Alan Modra  <amodra@gmail.com>
 770
 771         PR 24390
 772         * ppc-opc.c (BTF): Define.
 773         (powerpc_opcodes): Use for mtfsb*.
 774         * ppc-dis.c (print_insn_powerpc): Print fields with both
 775         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 776
 777 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 778
 779         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 780         (mapping_symbol_for_insn): Implement new algorithm.
 781         (print_insn): Remove duplicate code.
 782
 783 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 784
 785         * aarch64-dis.c (print_insn_aarch64):
 786         Implement override.
 787
 788 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 789
 790         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 791         order.
 792
 793 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 794
 795         * aarch64-dis.c (last_stop_offset): New.
 796         (print_insn_aarch64): Use stop_offset.
 797
 798 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 799
 800         PR gas/24359
 801         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 802         CPU_ANY_AVX2_FLAGS.
 803         * i386-init.h: Regenerated.
 804
 805 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 806
 807         PR gas/24348
 808         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 809         vmovdqu16, vmovdqu32 and vmovdqu64.
 810         * i386-tbl.h: Regenerated.
 811
 812 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 813
 814         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 815         from vstrszb, vstrszh, and vstrszf.
 816
 817 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 818
 819         * s390-opc.txt: Add instruction descriptions.
 820
 821 2019-02-08  Jim Wilson  <jimw@sifive.com>
 822
 823         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 824         <bne>: Likewise.
 825
 826 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 827
 828         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 829
 830 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 831
 832         PR binutils/23212
 833         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 834         * aarch64-opc.c (verify_elem_sd): New.
 835         (fields): Add FLD_sz entr.
 836         * aarch64-tbl.h (_SIMD_INSN): New.
 837         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 838         fmulx scalar and vector by element isns.
 839
 840 2019-02-07  Nick Clifton  <nickc@redhat.com>
 841
 842         * po/sv.po: Updated Swedish translation.
 843
 844 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 845
 846         * s390-mkopc.c (main): Accept arch13 as cpu string.
 847         * s390-opc.c: Add new instruction formats and instruction opcode
 848         masks.
 849         * s390-opc.txt: Add new arch13 instructions.
 850
 851 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 852
 853         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 854         (aarch64_opcode): Change encoding for stg, stzg
 855         st2g and st2zg.
 856         * aarch64-asm-2.c: Regenerated.
 857         * aarch64-dis-2.c: Regenerated.
 858         * aarch64-opc-2.c: Regenerated.
 859
 860 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 861
 862         * aarch64-asm-2.c: Regenerated.
 863         * aarch64-dis-2.c: Likewise.
 864         * aarch64-opc-2.c: Likewise.
 865         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 866
 867 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 868             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 869
 870         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 871         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 872         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 873         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 874         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 875         case for ldstgv_indexed.
 876         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 877         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 878         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 879         * aarch64-asm-2.c: Regenerated.
 880         * aarch64-dis-2.c: Regenerated.
 881         * aarch64-opc-2.c: Regenerated.
 882
 883 2019-01-23  Nick Clifton  <nickc@redhat.com>
 884
 885         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 886
 887 2019-01-21  Nick Clifton  <nickc@redhat.com>
 888
 889         * po/de.po: Updated German translation.
 890         * po/uk.po: Updated Ukranian translation.
 891
 892 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 893         * mips-dis.c (mips_arch_choices): Fix typo in
 894         gs464, gs464e and gs264e descriptors.
 895
 896 2019-01-19  Nick Clifton  <nickc@redhat.com>
 897
 898         * configure: Regenerate.
 899         * po/opcodes.pot: Regenerate.
 900
 901 2018-06-24  Nick Clifton  <nickc@redhat.com>
 902
 903         2.32 branch created.
 904
 905 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 906
 907         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 908         if it is null.
 909         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 910         zero.
 911
 912 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 913
 914         * configure: Regenerate.
 915
 916 2019-01-07  Alan Modra  <amodra@gmail.com>
 917
 918         * configure: Regenerate.
 919         * po/POTFILES.in: Regenerate.
 920
 921 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 922
 923         * s12z-opc.c: New file.
 924         * s12z-opc.h: New file.
 925         * s12z-dis.c: Removed all code not directly related to display
 926         of instructions.  Used the interface provided by the new files
 927         instead.
 928         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 929         * Makefile.in: Regenerate.
 930         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 931         * configure: Regenerate.
 932
 933 2019-01-01  Alan Modra  <amodra@gmail.com>
 934
 935         Update year range in copyright notice of all files.
 936
 937 For older changes see ChangeLog-2018
 938 \f
 939 Copyright (C) 2019 Free Software Foundation, Inc.
 940
 941 Copying and distribution of this file, with or without modification,
 942 are permitted in any medium without royalty provided the copyright
 943 notice and this notice are preserved.
 944
 945 Local Variables:
 946 mode: change-log
 947 left-margin: 8
 948 fill-column: 74
 949 version-control: never
 950 End: