opcodes/ChangeLog

   1 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
   4         usage on ISA basis.
   5
   6 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
   7
   8         PR target/20666
   9         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
  10
  11 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
  12
  13         PR target/20667
  14         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
  15         available.
  16
  17 2016-10-07  Alan Modra  <amodra@gmail.com>
  18
  19         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
  20
  21 2016-10-06  Alan Modra  <amodra@gmail.com>
  22
  23         * aarch64-opc.c: Spell fall through comments consistently.
  24         * i386-dis.c: Likewise.
  25         * aarch64-dis.c: Add missing fall through comments.
  26         * aarch64-opc.c: Likewise.
  27         * arc-dis.c: Likewise.
  28         * arm-dis.c: Likewise.
  29         * i386-dis.c: Likewise.
  30         * m68k-dis.c: Likewise.
  31         * mep-asm.c: Likewise.
  32         * ns32k-dis.c: Likewise.
  33         * sh-dis.c: Likewise.
  34         * tic4x-dis.c: Likewise.
  35         * tic6x-dis.c: Likewise.
  36         * vax-dis.c: Likewise.
  37
  38 2016-10-06  Alan Modra  <amodra@gmail.com>
  39
  40         * arc-ext.c (create_map): Add missing break.
  41         * msp430-decode.opc (encode_as): Likewise.
  42         * msp430-decode.c: Regenerate.
  43
  44 2016-10-06  Alan Modra  <amodra@gmail.com>
  45
  46         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
  47         * crx-dis.c (print_insn_crx): Likewise.
  48
  49 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         PR binutils/20657
  52         * i386-dis.c (putop): Don't assign alt twice.
  53
  54 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
  55
  56         PR target/20553
  57         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
  58
  59 2016-09-29  Alan Modra  <amodra@gmail.com>
  60
  61         * ppc-opc.c (L): Make compulsory.
  62         (LOPT): New, optional form of L.
  63         (HTM_R): Define as LOPT.
  64         (L0, L1): Delete.
  65         (L32OPT): New, optional for 32-bit L.
  66         (L2OPT): New, 2-bit L for dcbf.
  67         (SVC_LEC): Update.
  68         (L2): Define.
  69         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
  70         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
  71         <dcbf>: Use L2OPT.
  72         <tlbiel, tlbie>: Use LOPT.
  73         <wclr, wclrall>: Use L2.
  74
  75 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
  76
  77         * Makefile.in: Regenerate.
  78         * configure: Likewise.
  79
  80 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
  81
  82         * arc-ext-tbl.h (EXTINSN2OPF): Define.
  83         (EXTINSN2OP): Use EXTINSN2OPF.
  84         (bspeekm, bspop, modapp): New extension instructions.
  85         * arc-opc.c (F_DNZ_ND): Define.
  86         (F_DNZ_D): Likewise.
  87         (F_SIZEB1): Changed.
  88         (C_DNZ_D): Define.
  89         (C_HARD): Changed.
  90         * arc-tbl.h (dbnz): New instruction.
  91         (prealloc): Allow it for ARC EM.
  92         (xbfu): Likewise.
  93
  94 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  95
  96         * aarch64-opc.c (print_immediate_offset_address): Print spaces
  97         after commas in addresses.
  98         (aarch64_print_operand): Likewise.
  99
 100 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 101
 102         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 103         rather than "should be" or "expected to be" in error messages.
 104
 105 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 106
 107         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 108         (print_mnemonic_name): ...here.
 109         (print_comment): New function.
 110         (print_aarch64_insn): Call it.
 111         * aarch64-opc.c (aarch64_conds): Add SVE names.
 112         (aarch64_print_operand): Print alternative condition names in
 113         a comment.
 114
 115 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 116
 117         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 118         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 119         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 120         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 121         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 122         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 123         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 124         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 125         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 126         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 127         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 128         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 129         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 130         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 131         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 132         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 133         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 134         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 135         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 136         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 137         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 138         (aarch64_feature_sve): New variable.
 139         (SVE): New macro.
 140         (_SVE_INSN): Likewise.
 141         (aarch64_opcode_table): Add SVE instructions.
 142         * aarch64-opc.h (extract_fields): Declare.
 143         * aarch64-opc-2.c: Regenerate.
 144         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 145         * aarch64-asm-2.c: Regenerate.
 146         * aarch64-dis.c (extract_fields): Make global.
 147         (do_misc_decoding): Handle the new SVE aarch64_ops.
 148         * aarch64-dis-2.c: Regenerate.
 149
 150 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 151
 152         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 153         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 154         aarch64_field_kinds.
 155         * aarch64-opc.c (fields): Add corresponding entries.
 156         * aarch64-asm.c (aarch64_get_variant): New function.
 157         (aarch64_encode_variant_using_iclass): Likewise.
 158         (aarch64_opcode_encode): Call it.
 159         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 160         (aarch64_opcode_decode): Call it.
 161
 162 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 163
 164         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 165         and FP register operands.
 166         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 167         (FLD_SVE_Vn): New aarch64_field_kinds.
 168         * aarch64-opc.c (fields): Add corresponding entries.
 169         (aarch64_print_operand): Handle the new SVE core and FP register
 170         operands.
 171         * aarch64-opc-2.c: Regenerate.
 172         * aarch64-asm-2.c: Likewise.
 173         * aarch64-dis-2.c: Likewise.
 174
 175 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 176
 177         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 178         immediate operands.
 179         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 180         * aarch64-opc.c (fields): Add corresponding entry.
 181         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 182         operands.
 183         (aarch64_print_operand): Likewise.
 184         * aarch64-opc-2.c: Regenerate.
 185         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 186         (ins_sve_float_zero_one): New inserters.
 187         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 188         (aarch64_ins_sve_float_half_two): Likewise.
 189         (aarch64_ins_sve_float_zero_one): Likewise.
 190         * aarch64-asm-2.c: Regenerate.
 191         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 192         (ext_sve_float_zero_one): New extractors.
 193         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 194         (aarch64_ext_sve_float_half_two): Likewise.
 195         (aarch64_ext_sve_float_zero_one): Likewise.
 196         * aarch64-dis-2.c: Regenerate.
 197
 198 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 199
 200         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 201         integer immediate operands.
 202         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 203         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 204         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 205         * aarch64-opc.c (fields): Add corresponding entries.
 206         (operand_general_constraint_met_p): Handle the new SVE integer
 207         immediate operands.
 208         (aarch64_print_operand): Likewise.
 209         (aarch64_sve_dupm_mov_immediate_p): New function.
 210         * aarch64-opc-2.c: Regenerate.
 211         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 212         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 213         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 214         (aarch64_ins_limm): ...here.
 215         (aarch64_ins_inv_limm): New function.
 216         (aarch64_ins_sve_aimm): Likewise.
 217         (aarch64_ins_sve_asimm): Likewise.
 218         (aarch64_ins_sve_limm_mov): Likewise.
 219         (aarch64_ins_sve_shlimm): Likewise.
 220         (aarch64_ins_sve_shrimm): Likewise.
 221         * aarch64-asm-2.c: Regenerate.
 222         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 223         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 224         * aarch64-dis.c (decode_limm): New function, split out from...
 225         (aarch64_ext_limm): ...here.
 226         (aarch64_ext_inv_limm): New function.
 227         (decode_sve_aimm): Likewise.
 228         (aarch64_ext_sve_aimm): Likewise.
 229         (aarch64_ext_sve_asimm): Likewise.
 230         (aarch64_ext_sve_limm_mov): Likewise.
 231         (aarch64_top_bit): Likewise.
 232         (aarch64_ext_sve_shlimm): Likewise.
 233         (aarch64_ext_sve_shrimm): Likewise.
 234         * aarch64-dis-2.c: Regenerate.
 235
 236 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 237
 238         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 239         operands.
 240         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 241         the AARCH64_MOD_MUL_VL entry.
 242         (value_aligned_p): Cope with non-power-of-two alignments.
 243         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 244         (print_immediate_offset_address): Likewise.
 245         (aarch64_print_operand): Likewise.
 246         * aarch64-opc-2.c: Regenerate.
 247         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 248         (ins_sve_addr_ri_s9xvl): New inserters.
 249         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 250         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 251         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 252         * aarch64-asm-2.c: Regenerate.
 253         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 254         (ext_sve_addr_ri_s9xvl): New extractors.
 255         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 256         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 257         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 258         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 259         * aarch64-dis-2.c: Regenerate.
 260
 261 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 262
 263         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 264         address operands.
 265         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 266         (FLD_SVE_xs_22): New aarch64_field_kinds.
 267         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 268         (get_operand_specific_data): New function.
 269         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 270         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 271         (operand_general_constraint_met_p): Handle the new SVE address
 272         operands.
 273         (sve_reg): New array.
 274         (get_addr_sve_reg_name): New function.
 275         (aarch64_print_operand): Handle the new SVE address operands.
 276         * aarch64-opc-2.c: Regenerate.
 277         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 278         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 279         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 280         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 281         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 282         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 283         (aarch64_ins_sve_addr_zi_u5): Likewise.
 284         (aarch64_ins_sve_addr_zz): Likewise.
 285         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 286         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 287         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 288         * aarch64-asm-2.c: Regenerate.
 289         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 290         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 291         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 292         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 293         (aarch64_ext_sve_addr_ri_u6): Likewise.
 294         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 295         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 296         (aarch64_ext_sve_addr_zi_u5): Likewise.
 297         (aarch64_ext_sve_addr_zz): Likewise.
 298         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 299         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 300         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 301         * aarch64-dis-2.c: Regenerate.
 302
 303 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 304
 305         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 306         AARCH64_OPND_SVE_PATTERN_SCALED.
 307         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 308         * aarch64-opc.c (fields): Add a corresponding entry.
 309         (set_multiplier_out_of_range_error): New function.
 310         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 311         (operand_general_constraint_met_p): Handle
 312         AARCH64_OPND_SVE_PATTERN_SCALED.
 313         (print_register_offset_address): Use PRIi64 to print the
 314         shift amount.
 315         (aarch64_print_operand): Likewise.  Handle
 316         AARCH64_OPND_SVE_PATTERN_SCALED.
 317         * aarch64-opc-2.c: Regenerate.
 318         * aarch64-asm.h (ins_sve_scale): New inserter.
 319         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 320         * aarch64-asm-2.c: Regenerate.
 321         * aarch64-dis.h (ext_sve_scale): New inserter.
 322         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 323         * aarch64-dis-2.c: Regenerate.
 324
 325 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 326
 327         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 328         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 329         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 330         (FLD_SVE_prfop): Likewise.
 331         * aarch64-opc.c: Include libiberty.h.
 332         (aarch64_sve_pattern_array): New variable.
 333         (aarch64_sve_prfop_array): Likewise.
 334         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 335         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 336         AARCH64_OPND_SVE_PRFOP.
 337         * aarch64-asm-2.c: Regenerate.
 338         * aarch64-dis-2.c: Likewise.
 339         * aarch64-opc-2.c: Likewise.
 340
 341 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 342
 343         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 344         AARCH64_OPND_QLF_P_[ZM].
 345         (aarch64_print_operand): Print /z and /m where appropriate.
 346
 347 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 348
 349         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 350         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 351         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 352         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 353         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 354         * aarch64-opc.c (fields): Add corresponding entries here.
 355         (operand_general_constraint_met_p): Check that SVE register lists
 356         have the correct length.  Check the ranges of SVE index registers.
 357         Check for cases where p8-p15 are used in 3-bit predicate fields.
 358         (aarch64_print_operand): Handle the new SVE operands.
 359         * aarch64-opc-2.c: Regenerate.
 360         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 361         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 362         (aarch64_ins_sve_reglist): Likewise.
 363         * aarch64-asm-2.c: Regenerate.
 364         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 365         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 366         (aarch64_ext_sve_reglist): Likewise.
 367         * aarch64-dis-2.c: Regenerate.
 368
 369 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 370
 371         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 372         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 373         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 374         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 375         tied operands.
 376
 377 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 378
 379         * aarch64-opc.c (get_offset_int_reg_name): New function.
 380         (print_immediate_offset_address): Likewise.
 381         (print_register_offset_address): Take the base and offset
 382         registers as parameters.
 383         (aarch64_print_operand): Update caller accordingly.  Use
 384         print_immediate_offset_address.
 385
 386 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 387
 388         * aarch64-opc.c (BANK): New macro.
 389         (R32, R64): Take a register number as argument
 390         (int_reg): Use BANK.
 391
 392 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 393
 394         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 395         (aarch64_print_operand): Update accordingly.
 396
 397 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 398
 399         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 400         for FPIMM.
 401         * aarch64-asm.h (ins_fpimm): New inserter.
 402         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 403         * aarch64-asm-2.c: Regenerate.
 404         * aarch64-dis.h (ext_fpimm): New extractor.
 405         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 406         (aarch64_ext_fpimm): New function.
 407         * aarch64-dis-2.c: Regenerate.
 408
 409 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 410
 411         * aarch64-asm.c: Include libiberty.h.
 412         (insert_fields): New function.
 413         (aarch64_ins_imm): Use it.
 414         * aarch64-dis.c (extract_fields): New function.
 415         (aarch64_ext_imm): Use it.
 416
 417 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 418
 419         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 420         with an esize parameter.
 421         (operand_general_constraint_met_p): Update accordingly.
 422         Fix misindented code.
 423         * aarch64-asm.c (aarch64_ins_limm): Update call to
 424         aarch64_logical_immediate_p.
 425
 426 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 427
 428         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 429
 430 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 431
 432         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 433
 434 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 435
 436         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 437
 438 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 439
 440         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 441         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 442         xor3>: Delete mnemonics.
 443         <cp_abort>: Rename mnemonic from ...
 444         <cpabort>: ...to this.
 445         <setb>: Change to a X form instruction.
 446         <sync>: Change to 1 operand form.
 447         <copy>: Delete mnemonic.
 448         <copy_first>: Rename mnemonic from ...
 449         <copy>: ...to this.
 450         <paste, paste.>: Delete mnemonics.
 451         <paste_last>: Rename mnemonic from ...
 452         <paste.>: ...to this.
 453
 454 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 455
 456         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 457
 458 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 459
 460         * s390-mkopc.c (main): Support alternate arch strings.
 461
 462 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 463
 464         * s390-opc.txt: Fix kmctr instruction type.
 465
 466 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 467
 468         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 469         * i386-init.h: Regenerated.
 470
 471 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 472
 473         * opcodes/arc-dis.c (print_insn_arc): Changed.
 474
 475 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 476
 477         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 478         camellia_fl.
 479
 480 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 481
 482         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 483         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 484         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 485
 486 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 489         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 490         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 491         PREFIX_MOD_3_0FAE_REG_4.
 492         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 493         PREFIX_MOD_3_0FAE_REG_4.
 494         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 495         (cpu_flags): Add CpuPTWRITE.
 496         * i386-opc.h (CpuPTWRITE): New.
 497         (i386_cpu_flags): Add cpuptwrite.
 498         * i386-opc.tbl: Add ptwrite instruction.
 499         * i386-init.h: Regenerated.
 500         * i386-tbl.h: Likewise.
 501
 502 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 503
 504         * arc-dis.h: Wrap around in extern "C".
 505
 506 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 507
 508         * aarch64-tbl.h (V8_2_INSN): New macro.
 509         (aarch64_opcode_table): Use it.
 510
 511 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 512
 513         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 514         CORE_INSN, __FP_INSN and SIMD_INSN.
 515
 516 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 517
 518         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 519         (aarch64_opcode_table): Update uses accordingly.
 520
 521 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 522         Kwok Cheung Yeung  <kcy@codesourcery.com>
 523
 524         opcodes/
 525         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 526         'e_cmplwi' to 'e_cmpli' instead.
 527         (OPVUPRT, OPVUPRT_MASK): Define.
 528         (powerpc_opcodes): Add E200Z4 insns.
 529         (vle_opcodes): Add context save/restore insns.
 530
 531 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 532
 533         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 534         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 535         "j".
 536
 537 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 538
 539         * arc-nps400-tbl.h: Change block comments to GNU format.
 540         * arc-dis.c: Add new globals addrtypenames,
 541         addrtypenames_max, and addtypeunknown.
 542         (get_addrtype): New function.
 543         (print_insn_arc): Print colons and address types when
 544         required.
 545         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 546         define insert and extract functions for all address types.
 547         (arc_operands): Add operands for colon and all address
 548         types.
 549         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 550         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 551         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 552         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 553         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 554         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 555
 556 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 557
 558         * configure: Regenerated.
 559
 560 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 561
 562         * arc-dis.c (skipclass): New structure.
 563         (decodelist): New variable.
 564         (is_compatible_p): New function.
 565         (new_element): Likewise.
 566         (skip_class_p): Likewise.
 567         (find_format_from_table): Use skip_class_p function.
 568         (find_format): Decode first the extension instructions.
 569         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 570         e_flags.
 571         (parse_option): New function.
 572         (parse_disassembler_options): Likewise.
 573         (print_arc_disassembler_options): Likewise.
 574         (print_insn_arc): Use parse_disassembler_options function.  Proper
 575         select ARCv2 cpu variant.
 576         * disassemble.c (disassembler_usage): Add ARC disassembler
 577         options.
 578
 579 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 580
 581         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 582         annotation from the "nal" entry and reorder it beyond "bltzal".
 583
 584 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 585
 586         * sparc-opc.c (ldtxa): New macro.
 587         (sparc_opcodes): Use the macro defined above to add entries for
 588         the LDTXA instructions.
 589         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 590         instruction.
 591
 592 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 593
 594         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 595         and "jmpc".
 596
 597 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 600         (movzb): Adjust to cover all permitted suffixes.
 601         (movzw): New.
 602         * i386-tbl.h: Re-generate.
 603
 604 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 605
 606         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 607         (lgdt): Remove Tbyte from non-64-bit variant.
 608         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 609         xsaves64, xsavec64): Remove Disp16.
 610         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 611         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 612         64-bit variants.
 613         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 614         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 615         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 616         64-bit variants.
 617         * i386-tbl.h: Re-generate.
 618
 619 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 620
 621         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 622         * i386-tbl.h: Re-generate.
 623
 624 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 625
 626         * arm-dis.c (print_insn): Fix typo in comment.
 627
 628 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 629
 630         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 631         range of ldst_elemlist operands.
 632         (print_register_list): Use PRIi64 to print the index.
 633         (aarch64_print_operand): Likewise.
 634
 635 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 636
 637         * mcore-opc.h: Remove sentinal.
 638         * mcore-dis.c (print_insn_mcore): Adjust.
 639
 640 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 641
 642         * arc-opc.c: Correct description of availability of NPS400
 643         features.
 644
 645 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 646
 647         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 648         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 649         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 650         xor3>: New mnemonics.
 651         <setb>: Change to a VX form instruction.
 652         (insert_sh6): Add support for rldixor.
 653         (extract_sh6): Likewise.
 654
 655 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 656
 657         * arc-ext.h: Wrap in extern C.
 658
 659 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 660
 661         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 662         Use same method for determining instruction length on ARC700 and
 663         NPS-400.
 664         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 665         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 666         with the NPS400 subclass.
 667         * arc-opc.c: Likewise.
 668
 669 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 670
 671         * sparc-opc.c (rdasr): New macro.
 672         (wrasr): Likewise.
 673         (rdpr): Likewise.
 674         (wrpr): Likewise.
 675         (rdhpr): Likewise.
 676         (wrhpr): Likewise.
 677         (sparc_opcodes): Use the macros above to fix and expand the
 678         definition of read/write instructions from/to
 679         asr/privileged/hyperprivileged instructions.
 680         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 681         %hva_mask_nz.  Prefer softint_set and softint_clear over
 682         set_softint and clear_softint.
 683         (print_insn_sparc): Support %ver in Rd.
 684
 685 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 686
 687         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 688         architecture according to the hardware capabilities they require.
 689
 690 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 691
 692         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 693         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 694         bfd_mach_sparc_v9{c,d,e,v,m}.
 695         * sparc-opc.c (MASK_V9C): Define.
 696         (MASK_V9D): Likewise.
 697         (MASK_V9E): Likewise.
 698         (MASK_V9V): Likewise.
 699         (MASK_V9M): Likewise.
 700         (v6): Add MASK_V9{C,D,E,V,M}.
 701         (v6notlet): Likewise.
 702         (v7): Likewise.
 703         (v8): Likewise.
 704         (v9): Likewise.
 705         (v9andleon): Likewise.
 706         (v9a): Likewise.
 707         (v9b): Likewise.
 708         (v9c): Define.
 709         (v9d): Likewise.
 710         (v9e): Likewise.
 711         (v9v): Likewise.
 712         (v9m): Likewise.
 713         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 714
 715 2016-06-15  Nick Clifton  <nickc@redhat.com>
 716
 717         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 718         constants to match expected behaviour.
 719         (nds32_parse_opcode): Likewise.  Also for whitespace.
 720
 721 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 722
 723         * arc-opc.c (extract_rhv1): Extract value from insn.
 724
 725 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 726
 727         * arc-nps400-tbl.h: Add ldbit instruction.
 728         * arc-opc.c: Add flag classes required for ldbit.
 729
 730 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 731
 732         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 733         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 734         support the above instructions.
 735
 736 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 737
 738         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 739         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 740         csma, cbba, zncv, and hofs.
 741         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 742         support the above instructions.
 743
 744 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 745
 746         * arc-nps400-tbl.h: Add andab and orab instructions.
 747
 748 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 749
 750         * arc-nps400-tbl.h: Add addl-like instructions.
 751
 752 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 753
 754         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 755
 756 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 757
 758         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 759         instructions.
 760
 761 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 762
 763         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 764         variable.
 765         (init_disasm): Handle new command line option "insnlength".
 766         (print_s390_disassembler_options): Mention new option in help
 767         output.
 768         (print_insn_s390): Use the encoded insn length when dumping
 769         unknown instructions.
 770
 771 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 772
 773         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 774          to the address and set as symbol address for LDS/ STS immediate operands.
 775
 776 2016-06-07  Alan Modra  <amodra@gmail.com>
 777
 778         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 779         cpu for "vle" to e500.
 780         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 781         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 782         (PPCNONE): Delete, substitute throughout.
 783         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 784         except for major opcode 4 and 31.
 785         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 786
 787 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 788
 789         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 790         ARM_EXT_RAS in relevant entries.
 791
 792 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 793
 794         PR binutils/20196
 795         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 796         opcodes for E6500.
 797
 798 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 799
 800         PR binutis/18386
 801         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 802         (indir_v_mode): New.
 803         Add comments for '&'.
 804         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 805         (putop): Handle '&'.
 806         (intel_operand_size): Handle indir_v_mode.
 807         (OP_E_register): Likewise.
 808         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 809         64-bit indirect call/jmp for AMD64.
 810         * i386-tbl.h: Regenerated
 811
 812 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 813
 814         * arc-dis.c (struct arc_operand_iterator): New structure.
 815         (find_format_from_table): All the old content from find_format,
 816         with some minor adjustments, and parameter renaming.
 817         (find_format_long_instructions): New function.
 818         (find_format): Rewritten.
 819         (arc_insn_length): Add LSB parameter.
 820         (extract_operand_value): New function.
 821         (operand_iterator_next): New function.
 822         (print_insn_arc): Use new functions to find opcode, and iterator
 823         over operands.
 824         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 825         (extract_nps_3bit_dst_short): New function.
 826         (insert_nps_3bit_src2_short): New function.
 827         (extract_nps_3bit_src2_short): New function.
 828         (insert_nps_bitop1_size): New function.
 829         (extract_nps_bitop1_size): New function.
 830         (insert_nps_bitop2_size): New function.
 831         (extract_nps_bitop2_size): New function.
 832         (insert_nps_bitop_mod4_msb): New function.
 833         (extract_nps_bitop_mod4_msb): New function.
 834         (insert_nps_bitop_mod4_lsb): New function.
 835         (extract_nps_bitop_mod4_lsb): New function.
 836         (insert_nps_bitop_dst_pos3_pos4): New function.
 837         (extract_nps_bitop_dst_pos3_pos4): New function.
 838         (insert_nps_bitop_ins_ext): New function.
 839         (extract_nps_bitop_ins_ext): New function.
 840         (arc_operands): Add new operands.
 841         (arc_long_opcodes): New global array.
 842         (arc_num_long_opcodes): New global.
 843         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 844
 845 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 846
 847         * nds32-asm.h: Add extern "C".
 848         * sh-opc.h: Likewise.
 849
 850 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 851
 852         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 853         0,b,limm to the rflt instruction.
 854
 855 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 856
 857         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 858         constant.
 859
 860 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 861
 862         PR gas/20145
 863         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 864         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 865         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 866         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 867         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 868         * i386-init.h: Regenerated.
 869
 870 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         PR gas/20145
 873         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 874         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 875         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 876         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 877         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 878         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 879         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 880         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 881         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 882         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 883         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 884         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 885         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 886         CpuRegMask for AVX512.
 887         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 888         and CpuRegMask.
 889         (set_bitfield_from_cpu_flag_init): New function.
 890         (set_bitfield): Remove const on f.  Call
 891         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 892         * i386-opc.h (CpuRegMMX): New.
 893         (CpuRegXMM): Likewise.
 894         (CpuRegYMM): Likewise.
 895         (CpuRegZMM): Likewise.
 896         (CpuRegMask): Likewise.
 897         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 898         and cpuregmask.
 899         * i386-init.h: Regenerated.
 900         * i386-tbl.h: Likewise.
 901
 902 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 903
 904         PR gas/20154
 905         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 906         (opcode_modifiers): Add AMD64 and Intel64.
 907         (main): Properly verify CpuMax.
 908         * i386-opc.h (CpuAMD64): Removed.
 909         (CpuIntel64): Likewise.
 910         (CpuMax): Set to CpuNo64.
 911         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 912         (AMD64): New.
 913         (Intel64): Likewise.
 914         (i386_opcode_modifier): Add amd64 and intel64.
 915         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 916         on call and jmp.
 917         * i386-init.h: Regenerated.
 918         * i386-tbl.h: Likewise.
 919
 920 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 921
 922         PR gas/20154
 923         * i386-gen.c (main): Fail if CpuMax is incorrect.
 924         * i386-opc.h (CpuMax): Set to CpuIntel64.
 925         * i386-tbl.h: Regenerated.
 926
 927 2016-05-27  Nick Clifton  <nickc@redhat.com>
 928
 929         PR target/20150
 930         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 931         (msp430dis_opcode_unsigned): New function.
 932         (msp430dis_opcode_signed): New function.
 933         (msp430_singleoperand): Use the new opcode reading functions.
 934         Only disassenmble bytes if they were successfully read.
 935         (msp430_doubleoperand): Likewise.
 936         (msp430_branchinstr): Likewise.
 937         (msp430x_callx_instr): Likewise.
 938         (print_insn_msp430): Check that it is safe to read bytes before
 939         attempting disassembly.  Use the new opcode reading functions.
 940
 941 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 942
 943         * ppc-opc.c (CY): New define.  Document it.
 944         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 945
 946 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 947
 948         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 949         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 950         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 951         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 952         CPU_ANY_AVX_FLAGS.
 953         * i386-init.h: Regenerated.
 954
 955 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 956
 957         PR gas/20141
 958         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 959         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 960         * i386-init.h: Regenerated.
 961
 962 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 963
 964         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 965         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 966         * i386-init.h: Regenerated.
 967
 968 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 969
 970         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 971         information.
 972         (print_insn_arc): Set insn_type information.
 973         * arc-opc.c (C_CC): Add F_CLASS_COND.
 974         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 975         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 976         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 977         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 978         (brne, brne_s, jeq_s, jne_s): Likewise.
 979
 980 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 981
 982         * arc-tbl.h (neg): New instruction variant.
 983
 984 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 985
 986         * arc-dis.c (find_format, find_format, get_auxreg)
 987         (print_insn_arc): Changed.
 988         * arc-ext.h (INSERT_XOP): Likewise.
 989
 990 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 991
 992         * tic54x-dis.c (sprint_mmr): Adjust.
 993         * tic54x-opc.c: Likewise.
 994
 995 2016-05-19  Alan Modra  <amodra@gmail.com>
 996
 997         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 998
 999 2016-05-19  Alan Modra  <amodra@gmail.com>
1000
1001         * ppc-opc.c: Formatting.
1002         (NSISIGNOPT): Define.
1003         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1004
1005 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1006
1007         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1008         replacing references to `micromips_ase' throughout.
1009         (_print_insn_mips): Don't use file-level microMIPS annotation to
1010         determine the disassembly mode with the symbol table.
1011
1012 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1013
1014         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1015
1016 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1017
1018         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1019         mips64r6.
1020         * mips-opc.c (D34): New macro.
1021         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1022
1023 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1024
1025         * i386-dis.c (prefix_table): Add RDPID instruction.
1026         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1027         (cpu_flags): Add RDPID bitfield.
1028         * i386-opc.h (enum): Add RDPID element.
1029         (i386_cpu_flags): Add RDPID field.
1030         * i386-opc.tbl: Add RDPID instruction.
1031         * i386-init.h: Regenerate.
1032         * i386-tbl.h: Regenerate.
1033
1034 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1035
1036         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1037         branch type of a symbol.
1038         (print_insn): Likewise.
1039
1040 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1041
1042         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1043         Mainline Security Extensions instructions.
1044         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1045         Extensions instructions.
1046         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1047         instructions.
1048         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1049         special registers.
1050
1051 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1052
1053         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1054
1055 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1056
1057         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1058         (arcExtMap_genOpcode): Likewise.
1059         * arc-opc.c (arg_32bit_rc): Define new variable.
1060         (arg_32bit_u6): Likewise.
1061         (arg_32bit_limm): Likewise.
1062
1063 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1064
1065         * aarch64-gen.c (VERIFIER): Define.
1066         * aarch64-opc.c (VERIFIER): Define.
1067         (verify_ldpsw): Use static linkage.
1068         * aarch64-opc.h (verify_ldpsw): Remove.
1069         * aarch64-tbl.h: Use VERIFIER for verifiers.
1070
1071 2016-04-28  Nick Clifton  <nickc@redhat.com>
1072
1073         PR target/19722
1074         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1075         * aarch64-opc.c (verify_ldpsw): New function.
1076         * aarch64-opc.h (verify_ldpsw): New prototype.
1077         * aarch64-tbl.h: Add initialiser for verifier field.
1078         (LDPSW): Set verifier to verify_ldpsw.
1079
1080 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1081
1082         PR binutils/19983
1083         PR binutils/19984
1084         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1085         smaller than address size.
1086
1087 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1088
1089         * alpha-dis.c: Regenerate.
1090         * crx-dis.c: Likewise.
1091         * disassemble.c: Likewise.
1092         * epiphany-opc.c: Likewise.
1093         * fr30-opc.c: Likewise.
1094         * frv-opc.c: Likewise.
1095         * ip2k-opc.c: Likewise.
1096         * iq2000-opc.c: Likewise.
1097         * lm32-opc.c: Likewise.
1098         * lm32-opinst.c: Likewise.
1099         * m32c-opc.c: Likewise.
1100         * m32r-opc.c: Likewise.
1101         * m32r-opinst.c: Likewise.
1102         * mep-opc.c: Likewise.
1103         * mt-opc.c: Likewise.
1104         * or1k-opc.c: Likewise.
1105         * or1k-opinst.c: Likewise.
1106         * tic80-opc.c: Likewise.
1107         * xc16x-opc.c: Likewise.
1108         * xstormy16-opc.c: Likewise.
1109
1110 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1111
1112         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1113         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1114         calcsd, and calcxd instructions.
1115         * arc-opc.c (insert_nps_bitop_size): Delete.
1116         (extract_nps_bitop_size): Delete.
1117         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1118         (extract_nps_qcmp_m3): Define.
1119         (extract_nps_qcmp_m2): Define.
1120         (extract_nps_qcmp_m1): Define.
1121         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1122         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1123         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1124         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1125         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1126         NPS_QCMP_M3.
1127
1128 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1129
1130         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1131
1132 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1133
1134         * Makefile.in: Regenerated with automake 1.11.6.
1135         * aclocal.m4: Likewise.
1136
1137 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1138
1139         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1140         instructions.
1141         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1142         (extract_nps_cmem_uimm16): New function.
1143         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1144
1145 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1146
1147         * arc-dis.c (arc_insn_length): New function.
1148         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1149         (find_format): Change insnLen parameter to unsigned.
1150
1151 2016-04-13  Nick Clifton  <nickc@redhat.com>
1152
1153         PR target/19937
1154         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1155         the LD.B and LD.BU instructions.
1156
1157 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1158
1159         * arc-dis.c (find_format): Check for extension flags.
1160         (print_flags): New function.
1161         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1162         .extAuxRegister.
1163         * arc-ext.c (arcExtMap_coreRegName): Use
1164         LAST_EXTENSION_CORE_REGISTER.
1165         (arcExtMap_coreReadWrite): Likewise.
1166         (dump_ARC_extmap): Update printing.
1167         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1168         (arc_aux_regs): Add cpu field.
1169         * arc-regs.h: Add cpu field, lower case name aux registers.
1170
1171 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1172
1173         * arc-tbl.h: Add rtsc, sleep with no arguments.
1174
1175 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1176
1177         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1178         Initialize.
1179         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1180         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1181         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1182         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1183         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1184         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1185         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1186         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1187         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1188         (arc_opcode arc_opcodes): Null terminate the array.
1189         (arc_num_opcodes): Remove.
1190         * arc-ext.h (INSERT_XOP): Define.
1191         (extInstruction_t): Likewise.
1192         (arcExtMap_instName): Delete.
1193         (arcExtMap_insn): New function.
1194         (arcExtMap_genOpcode): Likewise.
1195         * arc-ext.c (ExtInstruction): Remove.
1196         (create_map): Zero initialize instruction fields.
1197         (arcExtMap_instName): Remove.
1198         (arcExtMap_insn): New function.
1199         (dump_ARC_extmap): More info while debuging.
1200         (arcExtMap_genOpcode): New function.
1201         * arc-dis.c (find_format): New function.
1202         (print_insn_arc): Use find_format.
1203         (arc_get_disassembler): Enable dump_ARC_extmap only when
1204         debugging.
1205
1206 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1207
1208         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1209         instruction bits out.
1210
1211 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1212
1213         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1214         * arc-opc.c (arc_flag_operands): Add new flags.
1215         (arc_flag_classes): Add new classes.
1216
1217 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1218
1219         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1220
1221 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1222
1223         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1224         encode1, rflt, crc16, and crc32 instructions.
1225         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1226         (arc_flag_classes): Add C_NPS_R.
1227         (insert_nps_bitop_size_2b): New function.
1228         (extract_nps_bitop_size_2b): Likewise.
1229         (insert_nps_bitop_uimm8): Likewise.
1230         (extract_nps_bitop_uimm8): Likewise.
1231         (arc_operands): Add new operand entries.
1232
1233 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1234
1235         * arc-regs.h: Add a new subclass field.  Add double assist
1236         accumulator register values.
1237         * arc-tbl.h: Use DPA subclass to mark the double assist
1238         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1239         * arc-opc.c (RSP): Define instead of SP.
1240         (arc_aux_regs): Add the subclass field.
1241
1242 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1243
1244         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1245
1246 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1247
1248         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1249         NPS_R_SRC1.
1250
1251 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1252
1253         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1254         issues.  No functional changes.
1255
1256 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1257
1258         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1259         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1260         (RTT): Remove duplicate.
1261         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1262         (PCT_CONFIG*): Remove.
1263         (D1L, D1H, D2H, D2L): Define.
1264
1265 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1266
1267         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1268
1269 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1270
1271         * arc-tbl.h (invld07): Remove.
1272         * arc-ext-tbl.h: New file.
1273         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1274         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1275
1276 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1277
1278         Fix -Wstack-usage warnings.
1279         * aarch64-dis.c (print_operands): Substitute size.
1280         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1281
1282 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1283
1284         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1285         to get a proper diagnostic when an invalid ASR register is used.
1286
1287 2016-03-22  Nick Clifton  <nickc@redhat.com>
1288
1289         * configure: Regenerate.
1290
1291 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1292
1293         * arc-nps400-tbl.h: New file.
1294         * arc-opc.c: Add top level comment.
1295         (insert_nps_3bit_dst): New function.
1296         (extract_nps_3bit_dst): New function.
1297         (insert_nps_3bit_src2): New function.
1298         (extract_nps_3bit_src2): New function.
1299         (insert_nps_bitop_size): New function.
1300         (extract_nps_bitop_size): New function.
1301         (arc_flag_operands): Add nps400 entries.
1302         (arc_flag_classes): Add nps400 entries.
1303         (arc_operands): Add nps400 entries.
1304         (arc_opcodes): Add nps400 include.
1305
1306 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1307
1308         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1309         the new class enum values.
1310
1311 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1312
1313         * arc-dis.c (print_insn_arc): Handle nps400.
1314
1315 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1316
1317         * arc-opc.c (BASE): Delete.
1318
1319 2016-03-18  Nick Clifton  <nickc@redhat.com>
1320
1321         PR target/19721
1322         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1323         of MOV insn that aliases an ORR insn.
1324
1325 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1326
1327         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1328
1329 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1330
1331         * mcore-opc.h: Add const qualifiers.
1332         * microblaze-opc.h (struct op_code_struct): Likewise.
1333         * sh-opc.h: Likewise.
1334         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1335         (tic4x_print_op): Likewise.
1336
1337 2016-03-02  Alan Modra  <amodra@gmail.com>
1338
1339         * or1k-desc.h: Regenerate.
1340         * fr30-ibld.c: Regenerate.
1341         * rl78-decode.c: Regenerate.
1342
1343 2016-03-01  Nick Clifton  <nickc@redhat.com>
1344
1345         PR target/19747
1346         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1347
1348 2016-02-24  Renlin Li  <renlin.li@arm.com>
1349
1350         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1351         (print_insn_coprocessor): Support fp16 instructions.
1352
1353 2016-02-24  Renlin Li  <renlin.li@arm.com>
1354
1355         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1356         vminnm, vrint(mpna).
1357
1358 2016-02-24  Renlin Li  <renlin.li@arm.com>
1359
1360         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1361         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1362
1363 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1364
1365         * i386-dis.c (print_insn): Parenthesize expression to prevent
1366         truncated addresses.
1367         (OP_J): Likewise.
1368
1369 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1370             Janek van Oirschot  <jvanoirs@synopsys.com>
1371
1372         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1373         variable.
1374
1375 2016-02-04  Nick Clifton  <nickc@redhat.com>
1376
1377         PR target/19561
1378         * msp430-dis.c (print_insn_msp430): Add a special case for
1379         decoding an RRC instruction with the ZC bit set in the extension
1380         word.
1381
1382 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1383
1384         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1385         * epiphany-ibld.c: Regenerate.
1386         * fr30-ibld.c: Regenerate.
1387         * frv-ibld.c: Regenerate.
1388         * ip2k-ibld.c: Regenerate.
1389         * iq2000-ibld.c: Regenerate.
1390         * lm32-ibld.c: Regenerate.
1391         * m32c-ibld.c: Regenerate.
1392         * m32r-ibld.c: Regenerate.
1393         * mep-ibld.c: Regenerate.
1394         * mt-ibld.c: Regenerate.
1395         * or1k-ibld.c: Regenerate.
1396         * xc16x-ibld.c: Regenerate.
1397         * xstormy16-ibld.c: Regenerate.
1398
1399 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1400
1401         * epiphany-dis.c: Regenerated from latest cpu files.
1402
1403 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1404
1405         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1406         test bit.
1407
1408 2016-01-25  Renlin Li  <renlin.li@arm.com>
1409
1410         * arm-dis.c (mapping_symbol_for_insn): New function.
1411         (find_ifthen_state): Call mapping_symbol_for_insn().
1412
1413 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1414
1415         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1416         of MSR UAO immediate operand.
1417
1418 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1419
1420         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1421         instruction support.
1422
1423 2016-01-17  Alan Modra  <amodra@gmail.com>
1424
1425         * configure: Regenerate.
1426
1427 2016-01-14  Nick Clifton  <nickc@redhat.com>
1428
1429         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1430         instructions that can support stack pointer operations.
1431         * rl78-decode.c: Regenerate.
1432         * rl78-dis.c: Fix display of stack pointer in MOVW based
1433         instructions.
1434
1435 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1436
1437         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1438         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1439         erxtatus_el1 and erxaddr_el1.
1440
1441 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1442
1443         * arm-dis.c (arm_opcodes): Add "esb".
1444         (thumb_opcodes): Likewise.
1445
1446 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1447
1448         * ppc-opc.c <xscmpnedp>: Delete.
1449         <xvcmpnedp>: Likewise.
1450         <xvcmpnedp.>: Likewise.
1451         <xvcmpnesp>: Likewise.
1452         <xvcmpnesp.>: Likewise.
1453
1454 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1455
1456         PR gas/13050
1457         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1458         addition to ISA_A.
1459
1460 2016-01-01  Alan Modra  <amodra@gmail.com>
1461
1462         Update year range in copyright notice of all files.
1463
1464 For older changes see ChangeLog-2015
1465 \f
1466 Copyright (C) 2016 Free Software Foundation, Inc.
1467
1468 Copying and distribution of this file, with or without modification,
1469 are permitted in any medium without royalty provided the copyright
1470 notice and this notice are preserved.
1471
1472 Local Variables:
1473 mode: change-log
1474 left-margin: 8
1475 fill-column: 74
1476 version-control: never
1477 End: