opcodes/ChangeLog

   1 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-tbl.h (QL_LDG): New.
   4         (aarch64_opcode_table): Add ldg.
   5         * aarch64-asm-2.c: Regenerated.
   6         * aarch64-dis-2.c: Regenerated.
   7         * aarch64-opc-2.c: Regenerated.
   8
   9 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  10
  11         * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
  12         for AARCH64_OPND_QLF_imm_tag.
  13         (operand_general_constraint_met_p): Add case for
  14         AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
  15         (aarch64_print_operand): Likewise.
  16         * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
  17         (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
  18         for both offset and pre/post indexed versions.
  19         (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
  20         * aarch64-asm-2.c: Regenerated.
  21         * aarch64-dis-2.c: Regenerated.
  22         * aarch64-opc-2.c: Regenerated.
  23
  24 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  25
  26         * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
  27         * aarch64-asm-2.c: Regenerated.
  28         * aarch64-dis-2.c: Regenerated.
  29         * aarch64-opc-2.c: Regenerated.
  30
  31 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  32
  33         * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
  34         (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
  35         * aarch64-opc.c (fields): Add entry for imm4_3.
  36         (operand_general_constraint_met_p): Add cases for
  37         AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
  38         (aarch64_print_operand): Likewise.
  39         * aarch64-tbl.h (QL_ADDG): New.
  40         (aarch64_opcode_table): Add addg, subg, irg and gmi.
  41         (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
  42         * aarch64-asm.c (aarch64_ins_imm): Add case for
  43         operand_need_shift_by_four.
  44         * aarch64-asm-2.c: Regenerated.
  45         * aarch64-dis-2.c: Regenerated.
  46         * aarch64-opc-2.c: Regenerated.
  47
  48 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
  49
  50         * aarch64-tbl.h (aarch64_feature_memtag): New.
  51         (MEMTAG, MEMTAG_INSN): New.
  52
  53 2018-11-06  Sudakshina Das  <sudi.das@arm.com>
  54
  55         * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
  56         with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
  57
  58 2018-11-06  Alan Modra  <amodra@gmail.com>
  59
  60         * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
  61         (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
  62         (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
  63         (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
  64         Don't return zero on error, insert mask bits instead.
  65         (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
  66         (insert_sh6, extract_sh6): Delete dead code.
  67         (insert_sprbat, insert_sprg): Use unsigned comparisions.
  68         (powerpc_operands <OIMM>): Set shift count rather than using
  69         PPC_OPSHIFT_INV.
  70         <SE_SDH, SE_SDW>: Likewise.  Don't use insert/extract functions.
  71
  72 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
  75         vpbroadcast{d,q} with GPR operand.
  76
  77 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
  80         * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
  81         cases up one level in the hierarchy.
  82
  83 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  84
  85         * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
  86         MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
  87         (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
  88         into MOD_VEX_0F93_P_3_LEN_0.
  89         (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
  90         operand cases up one level in the hierarchy.
  91
  92 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
  95         VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
  96         EVEX_W_0F3A22_P_2): Delete.
  97         (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
  98         entries up one level in the hierarchy.
  99         (OP_E_memory): Handle dq_mode when determining Disp8 shift
 100         value.
 101         * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
 102         entries up one level in the hierarchy.
 103         * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
 104         VexWIG for AVX flavors.
 105         * i386-tbl.h: Re-generate.
 106
 107 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
 110         vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
 111         vcvtusi2ss, kmovd): Drop VexW=1.
 112         * i386-tbl.h: Re-generate.
 113
 114 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
 117         EVex512, EVexLIG, EVexDYN): New.
 118         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
 119         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
 120         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
 121         of EVex=4 (aka EVexLIG).
 122         * i386-tbl.h: Re-generate.
 123
 124 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 125
 126         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
 127         (vpmaxub): Re-order attributes on AVX512BW flavor.
 128         * i386-tbl.h: Re-generate.
 129
 130 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
 133         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
 134         Vex=1 on AVX / AVX2 flavors.
 135         (vpmaxub): Re-order attributes on AVX512BW flavor.
 136         * i386-tbl.h: Re-generate.
 137
 138 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-opc.tbl (VexW0, VexW1): New.
 141         (vphadd*, vphsub*): Use VexW0 on XOP variants.
 142         * i386-tbl.h: Re-generate.
 143
 144 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
 145
 146         * s12z-dis.c (decode_possible_symbol): Add fallback case.
 147         (rel_15_7): Likewise.
 148
 149 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
 150
 151         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
 152         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
 153         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
 154
 155 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
 156
 157         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
 158         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
 159
 160 2018-10-10  Jan Beulich  <jbeulich@suse.com>
 161
 162         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
 163         Size64. Add Size.
 164         * i386-opc.h (Size16, Size32, Size64): Delete.
 165         (Size): New.
 166         (SIZE16, SIZE32, SIZE64): Define.
 167         (struct i386_opcode_modifier): Drop size16, size32, and size64.
 168         Add size.
 169         * i386-opc.tbl (Size16, Size32, Size64): Define.
 170         * i386-tbl.h: Re-generate.
 171
 172 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 173
 174         * aarch64-opc.c (operand_general_constraint_met_p): Add
 175         SSBS in the check for one-bit immediate.
 176         (aarch64_sys_regs): New entry for SSBS.
 177         (aarch64_sys_reg_supported_p): New check for above.
 178         (aarch64_pstatefields): New entry for SSBS.
 179         (aarch64_pstatefield_supported_p): New check for above.
 180
 181 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 182
 183         * aarch64-opc.c (aarch64_sys_regs): New entries for
 184         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
 185         (aarch64_sys_reg_supported_p): New checks for above.
 186
 187 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 188
 189         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
 190         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
 191         with the hint immediate.
 192         * aarch64-opc.c (aarch64_hint_options): New entries for
 193         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
 194         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
 195         while checking for HINT_OPD_F_NOPRINT flag.
 196         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
 197         extract value.
 198         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
 199         (aarch64_opcode_table): Add entry for BTI.
 200         (AARCH64_OPERANDS): Add new description for BTI targets.
 201         * aarch64-asm-2.c: Regenerate.
 202         * aarch64-dis-2.c: Regenerate.
 203         * aarch64-opc-2.c: Regenerate.
 204
 205 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 206
 207         * aarch64-opc.c (aarch64_sys_regs): New entries for
 208         rndr and rndrrs.
 209         (aarch64_sys_reg_supported_p): New check for above.
 210
 211 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 212
 213         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 214         (aarch64_sys_ins_reg_supported_p): New check for above.
 215
 216 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 217
 218         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 219         AARCH64_OPND_SYSREG_SR.
 220         * aarch64-opc.c (aarch64_print_operand): Likewise.
 221         (aarch64_sys_regs_sr): Define table.
 222         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 223         AARCH64_FEATURE_PREDRES.
 224         * aarch64-tbl.h (aarch64_feature_predres): New.
 225         (PREDRES, PREDRES_INSN): New.
 226         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 227         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 228         * aarch64-asm-2.c: Regenerate.
 229         * aarch64-dis-2.c: Regenerate.
 230         * aarch64-opc-2.c: Regenerate.
 231
 232 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 233
 234         * aarch64-tbl.h (aarch64_feature_sb): New.
 235         (SB, SB_INSN): New.
 236         (aarch64_opcode_table): Add entry for sb.
 237         * aarch64-asm-2.c: Regenerate.
 238         * aarch64-dis-2.c: Regenerate.
 239         * aarch64-opc-2.c: Regenerate.
 240
 241 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 242
 243         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 244         (aarch64_feature_frintts): New.
 245         (FLAGMANIP, FRINTTS): New.
 246         (aarch64_opcode_table): Add entries for xaflag, axflag
 247         and frint[32,64][x,z] instructions.
 248         * aarch64-asm-2.c: Regenerate.
 249         * aarch64-dis-2.c: Regenerate.
 250         * aarch64-opc-2.c: Regenerate.
 251
 252 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 253
 254         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 255         (ARMV8_5, V8_5_INSN): New.
 256
 257 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 258
 259         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 260
 261 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 262
 263         * i386-dis.c (rm_table): Add enclv.
 264         * i386-opc.tbl: Add enclv.
 265         * i386-tbl.h: Regenerated.
 266
 267 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 268
 269         * arm-dis.c (arm_opcodes): Add sb.
 270         (thumb32_opcodes): Likewise.
 271
 272 2018-10-05  Richard Henderson  <rth@twiddle.net>
 273             Stafford Horne  <shorne@gmail.com>
 274
 275         * or1k-desc.c: Regenerate.
 276         * or1k-desc.h: Regenerate.
 277         * or1k-opc.c: Regenerate.
 278         * or1k-opc.h: Regenerate.
 279         * or1k-opinst.c: Regenerate.
 280
 281 2018-10-05  Richard Henderson  <rth@twiddle.net>
 282
 283         * or1k-asm.c: Regenerated.
 284         * or1k-desc.c: Regenerated.
 285         * or1k-desc.h: Regenerated.
 286         * or1k-dis.c: Regenerated.
 287         * or1k-ibld.c: Regenerated.
 288         * or1k-opc.c: Regenerated.
 289         * or1k-opc.h: Regenerated.
 290         * or1k-opinst.c: Regenerated.
 291
 292 2018-10-05  Richard Henderson  <rth@twiddle.net>
 293
 294         * or1k-asm.c: Regenerate.
 295
 296 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 297
 298         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 299         * aarch64-dis.c (print_operands): Refactor to take notes.
 300         (print_verifier_notes): New.
 301         (print_aarch64_insn): Apply constraint verifier.
 302         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 303         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 304
 305 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 306
 307         * aarch64-opc.c (init_insn_block): New.
 308         (verify_constraints, aarch64_is_destructive_by_operands): New.
 309         * aarch64-opc.h (verify_constraints): New.
 310
 311 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 312
 313         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 314         * aarch64-opc.c (verify_ldpsw): Update arguments.
 315
 316 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 317
 318         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 319         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 320
 321 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 322
 323         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 324         * aarch64-dis.c (insn_sequence): New.
 325
 326 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 327
 328         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 329         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 330         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 331         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 332         constraints.
 333         (_SVE_INSNC): New.
 334         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 335         constraints.
 336         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 337         F_SCAN flags.
 338         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 339         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 340         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 341         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 342         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 343         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 344         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 345
 346 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 347
 348         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 349
 350 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 351
 352         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 353         are used when extracting signed fields and converting them to
 354         potentially 64-bit types.
 355
 356 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 357
 358         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 359         * Makefile.in: Re-generate.
 360         * aclocal.m4: Re-generate.
 361         * configure: Re-generate.
 362         * configure.ac: Remove check for -Wno-missing-field-initializers.
 363         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 364         (csky_v2_opcodes): Likewise.
 365
 366 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 367
 368         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 369
 370 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 371
 372         * nds32-asm.c (operand_fields): Remove the unused fields.
 373         (nds32_opcodes): Remove the unused instructions.
 374         * nds32-dis.c (nds32_ex9_info): Removed.
 375         (nds32_parse_opcode): Updated.
 376         (print_insn_nds32): Likewise.
 377         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 378         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 379         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 380         build_opcode_hash_table): New functions.
 381         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 382         nds32_opcode_table): New.
 383         (hw_ktabs): Declare it to a pointer rather than an array.
 384         (build_hash_table): Removed.
 385         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 386         SYN_ROPT and upadte HW_GPR and HW_INT.
 387         * nds32-dis.c (keywords): Remove const.
 388         (match_field): New function.
 389         (nds32_parse_opcode): Updated.
 390         * disassemble.c (disassemble_init_for_target):
 391         Add disassemble_init_nds32.
 392         * nds32-dis.c (eum map_type): New.
 393         (nds32_private_data): Likewise.
 394         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 395         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 396         (print_insn_nds32): Updated.
 397         * nds32-asm.c (parse_aext_reg): Add new parameter.
 398         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 399         are allowed to use.
 400         All callers changed.
 401         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 402         (operand_fields): Add new fields.
 403         (nds32_opcodes): Add new instructions.
 404         (keyword_aridxi_mx): New keyword.
 405         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 406         and NASM_ATTR_ZOL.
 407         (ALU2_1, ALU2_2, ALU2_3): New macros.
 408         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 409
 410 2018-09-17  Kito Cheng  <kito@andestech.com>
 411
 412         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 413
 414 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 415
 416         PR gas/23670
 417         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 418         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 419         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 420         (EVEX_LEN_0F7E_P_1): Likewise.
 421         (EVEX_LEN_0F7E_P_2): Likewise.
 422         (EVEX_LEN_0FD6_P_2): Likewise.
 423         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 424         (EVEX_LEN_TABLE): Likewise.
 425         (EVEX_LEN_0F6E_P_2): New enum.
 426         (EVEX_LEN_0F7E_P_1): Likewise.
 427         (EVEX_LEN_0F7E_P_2): Likewise.
 428         (EVEX_LEN_0FD6_P_2): Likewise.
 429         (evex_len_table): New.
 430         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 431         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 432         * i386-tbl.h: Regenerated.
 433
 434 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 435
 436         PR gas/23665
 437         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 438         VEX_LEN_0F7E_P_2 entries.
 439         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 440         * i386-tbl.h: Regenerated.
 441
 442 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * i386-dis.c (VZERO_Fixup): Removed.
 445         (VZERO): Likewise.
 446         (VEX_LEN_0F10_P_1): Likewise.
 447         (VEX_LEN_0F10_P_3): Likewise.
 448         (VEX_LEN_0F11_P_1): Likewise.
 449         (VEX_LEN_0F11_P_3): Likewise.
 450         (VEX_LEN_0F2E_P_0): Likewise.
 451         (VEX_LEN_0F2E_P_2): Likewise.
 452         (VEX_LEN_0F2F_P_0): Likewise.
 453         (VEX_LEN_0F2F_P_2): Likewise.
 454         (VEX_LEN_0F51_P_1): Likewise.
 455         (VEX_LEN_0F51_P_3): Likewise.
 456         (VEX_LEN_0F52_P_1): Likewise.
 457         (VEX_LEN_0F53_P_1): Likewise.
 458         (VEX_LEN_0F58_P_1): Likewise.
 459         (VEX_LEN_0F58_P_3): Likewise.
 460         (VEX_LEN_0F59_P_1): Likewise.
 461         (VEX_LEN_0F59_P_3): Likewise.
 462         (VEX_LEN_0F5A_P_1): Likewise.
 463         (VEX_LEN_0F5A_P_3): Likewise.
 464         (VEX_LEN_0F5C_P_1): Likewise.
 465         (VEX_LEN_0F5C_P_3): Likewise.
 466         (VEX_LEN_0F5D_P_1): Likewise.
 467         (VEX_LEN_0F5D_P_3): Likewise.
 468         (VEX_LEN_0F5E_P_1): Likewise.
 469         (VEX_LEN_0F5E_P_3): Likewise.
 470         (VEX_LEN_0F5F_P_1): Likewise.
 471         (VEX_LEN_0F5F_P_3): Likewise.
 472         (VEX_LEN_0FC2_P_1): Likewise.
 473         (VEX_LEN_0FC2_P_3): Likewise.
 474         (VEX_LEN_0F3A0A_P_2): Likewise.
 475         (VEX_LEN_0F3A0B_P_2): Likewise.
 476         (VEX_W_0F10_P_0): Likewise.
 477         (VEX_W_0F10_P_1): Likewise.
 478         (VEX_W_0F10_P_2): Likewise.
 479         (VEX_W_0F10_P_3): Likewise.
 480         (VEX_W_0F11_P_0): Likewise.
 481         (VEX_W_0F11_P_1): Likewise.
 482         (VEX_W_0F11_P_2): Likewise.
 483         (VEX_W_0F11_P_3): Likewise.
 484         (VEX_W_0F12_P_0_M_0): Likewise.
 485         (VEX_W_0F12_P_0_M_1): Likewise.
 486         (VEX_W_0F12_P_1): Likewise.
 487         (VEX_W_0F12_P_2): Likewise.
 488         (VEX_W_0F12_P_3): Likewise.
 489         (VEX_W_0F13_M_0): Likewise.
 490         (VEX_W_0F14): Likewise.
 491         (VEX_W_0F15): Likewise.
 492         (VEX_W_0F16_P_0_M_0): Likewise.
 493         (VEX_W_0F16_P_0_M_1): Likewise.
 494         (VEX_W_0F16_P_1): Likewise.
 495         (VEX_W_0F16_P_2): Likewise.
 496         (VEX_W_0F17_M_0): Likewise.
 497         (VEX_W_0F28): Likewise.
 498         (VEX_W_0F29): Likewise.
 499         (VEX_W_0F2B_M_0): Likewise.
 500         (VEX_W_0F2E_P_0): Likewise.
 501         (VEX_W_0F2E_P_2): Likewise.
 502         (VEX_W_0F2F_P_0): Likewise.
 503         (VEX_W_0F2F_P_2): Likewise.
 504         (VEX_W_0F50_M_0): Likewise.
 505         (VEX_W_0F51_P_0): Likewise.
 506         (VEX_W_0F51_P_1): Likewise.
 507         (VEX_W_0F51_P_2): Likewise.
 508         (VEX_W_0F51_P_3): Likewise.
 509         (VEX_W_0F52_P_0): Likewise.
 510         (VEX_W_0F52_P_1): Likewise.
 511         (VEX_W_0F53_P_0): Likewise.
 512         (VEX_W_0F53_P_1): Likewise.
 513         (VEX_W_0F58_P_0): Likewise.
 514         (VEX_W_0F58_P_1): Likewise.
 515         (VEX_W_0F58_P_2): Likewise.
 516         (VEX_W_0F58_P_3): Likewise.
 517         (VEX_W_0F59_P_0): Likewise.
 518         (VEX_W_0F59_P_1): Likewise.
 519         (VEX_W_0F59_P_2): Likewise.
 520         (VEX_W_0F59_P_3): Likewise.
 521         (VEX_W_0F5A_P_0): Likewise.
 522         (VEX_W_0F5A_P_1): Likewise.
 523         (VEX_W_0F5A_P_3): Likewise.
 524         (VEX_W_0F5B_P_0): Likewise.
 525         (VEX_W_0F5B_P_1): Likewise.
 526         (VEX_W_0F5B_P_2): Likewise.
 527         (VEX_W_0F5C_P_0): Likewise.
 528         (VEX_W_0F5C_P_1): Likewise.
 529         (VEX_W_0F5C_P_2): Likewise.
 530         (VEX_W_0F5C_P_3): Likewise.
 531         (VEX_W_0F5D_P_0): Likewise.
 532         (VEX_W_0F5D_P_1): Likewise.
 533         (VEX_W_0F5D_P_2): Likewise.
 534         (VEX_W_0F5D_P_3): Likewise.
 535         (VEX_W_0F5E_P_0): Likewise.
 536         (VEX_W_0F5E_P_1): Likewise.
 537         (VEX_W_0F5E_P_2): Likewise.
 538         (VEX_W_0F5E_P_3): Likewise.
 539         (VEX_W_0F5F_P_0): Likewise.
 540         (VEX_W_0F5F_P_1): Likewise.
 541         (VEX_W_0F5F_P_2): Likewise.
 542         (VEX_W_0F5F_P_3): Likewise.
 543         (VEX_W_0F60_P_2): Likewise.
 544         (VEX_W_0F61_P_2): Likewise.
 545         (VEX_W_0F62_P_2): Likewise.
 546         (VEX_W_0F63_P_2): Likewise.
 547         (VEX_W_0F64_P_2): Likewise.
 548         (VEX_W_0F65_P_2): Likewise.
 549         (VEX_W_0F66_P_2): Likewise.
 550         (VEX_W_0F67_P_2): Likewise.
 551         (VEX_W_0F68_P_2): Likewise.
 552         (VEX_W_0F69_P_2): Likewise.
 553         (VEX_W_0F6A_P_2): Likewise.
 554         (VEX_W_0F6B_P_2): Likewise.
 555         (VEX_W_0F6C_P_2): Likewise.
 556         (VEX_W_0F6D_P_2): Likewise.
 557         (VEX_W_0F6F_P_1): Likewise.
 558         (VEX_W_0F6F_P_2): Likewise.
 559         (VEX_W_0F70_P_1): Likewise.
 560         (VEX_W_0F70_P_2): Likewise.
 561         (VEX_W_0F70_P_3): Likewise.
 562         (VEX_W_0F71_R_2_P_2): Likewise.
 563         (VEX_W_0F71_R_4_P_2): Likewise.
 564         (VEX_W_0F71_R_6_P_2): Likewise.
 565         (VEX_W_0F72_R_2_P_2): Likewise.
 566         (VEX_W_0F72_R_4_P_2): Likewise.
 567         (VEX_W_0F72_R_6_P_2): Likewise.
 568         (VEX_W_0F73_R_2_P_2): Likewise.
 569         (VEX_W_0F73_R_3_P_2): Likewise.
 570         (VEX_W_0F73_R_6_P_2): Likewise.
 571         (VEX_W_0F73_R_7_P_2): Likewise.
 572         (VEX_W_0F74_P_2): Likewise.
 573         (VEX_W_0F75_P_2): Likewise.
 574         (VEX_W_0F76_P_2): Likewise.
 575         (VEX_W_0F77_P_0): Likewise.
 576         (VEX_W_0F7C_P_2): Likewise.
 577         (VEX_W_0F7C_P_3): Likewise.
 578         (VEX_W_0F7D_P_2): Likewise.
 579         (VEX_W_0F7D_P_3): Likewise.
 580         (VEX_W_0F7E_P_1): Likewise.
 581         (VEX_W_0F7F_P_1): Likewise.
 582         (VEX_W_0F7F_P_2): Likewise.
 583         (VEX_W_0FAE_R_2_M_0): Likewise.
 584         (VEX_W_0FAE_R_3_M_0): Likewise.
 585         (VEX_W_0FC2_P_0): Likewise.
 586         (VEX_W_0FC2_P_1): Likewise.
 587         (VEX_W_0FC2_P_2): Likewise.
 588         (VEX_W_0FC2_P_3): Likewise.
 589         (VEX_W_0FD0_P_2): Likewise.
 590         (VEX_W_0FD0_P_3): Likewise.
 591         (VEX_W_0FD1_P_2): Likewise.
 592         (VEX_W_0FD2_P_2): Likewise.
 593         (VEX_W_0FD3_P_2): Likewise.
 594         (VEX_W_0FD4_P_2): Likewise.
 595         (VEX_W_0FD5_P_2): Likewise.
 596         (VEX_W_0FD6_P_2): Likewise.
 597         (VEX_W_0FD7_P_2_M_1): Likewise.
 598         (VEX_W_0FD8_P_2): Likewise.
 599         (VEX_W_0FD9_P_2): Likewise.
 600         (VEX_W_0FDA_P_2): Likewise.
 601         (VEX_W_0FDB_P_2): Likewise.
 602         (VEX_W_0FDC_P_2): Likewise.
 603         (VEX_W_0FDD_P_2): Likewise.
 604         (VEX_W_0FDE_P_2): Likewise.
 605         (VEX_W_0FDF_P_2): Likewise.
 606         (VEX_W_0FE0_P_2): Likewise.
 607         (VEX_W_0FE1_P_2): Likewise.
 608         (VEX_W_0FE2_P_2): Likewise.
 609         (VEX_W_0FE3_P_2): Likewise.
 610         (VEX_W_0FE4_P_2): Likewise.
 611         (VEX_W_0FE5_P_2): Likewise.
 612         (VEX_W_0FE6_P_1): Likewise.
 613         (VEX_W_0FE6_P_2): Likewise.
 614         (VEX_W_0FE6_P_3): Likewise.
 615         (VEX_W_0FE7_P_2_M_0): Likewise.
 616         (VEX_W_0FE8_P_2): Likewise.
 617         (VEX_W_0FE9_P_2): Likewise.
 618         (VEX_W_0FEA_P_2): Likewise.
 619         (VEX_W_0FEB_P_2): Likewise.
 620         (VEX_W_0FEC_P_2): Likewise.
 621         (VEX_W_0FED_P_2): Likewise.
 622         (VEX_W_0FEE_P_2): Likewise.
 623         (VEX_W_0FEF_P_2): Likewise.
 624         (VEX_W_0FF0_P_3_M_0): Likewise.
 625         (VEX_W_0FF1_P_2): Likewise.
 626         (VEX_W_0FF2_P_2): Likewise.
 627         (VEX_W_0FF3_P_2): Likewise.
 628         (VEX_W_0FF4_P_2): Likewise.
 629         (VEX_W_0FF5_P_2): Likewise.
 630         (VEX_W_0FF6_P_2): Likewise.
 631         (VEX_W_0FF7_P_2): Likewise.
 632         (VEX_W_0FF8_P_2): Likewise.
 633         (VEX_W_0FF9_P_2): Likewise.
 634         (VEX_W_0FFA_P_2): Likewise.
 635         (VEX_W_0FFB_P_2): Likewise.
 636         (VEX_W_0FFC_P_2): Likewise.
 637         (VEX_W_0FFD_P_2): Likewise.
 638         (VEX_W_0FFE_P_2): Likewise.
 639         (VEX_W_0F3800_P_2): Likewise.
 640         (VEX_W_0F3801_P_2): Likewise.
 641         (VEX_W_0F3802_P_2): Likewise.
 642         (VEX_W_0F3803_P_2): Likewise.
 643         (VEX_W_0F3804_P_2): Likewise.
 644         (VEX_W_0F3805_P_2): Likewise.
 645         (VEX_W_0F3806_P_2): Likewise.
 646         (VEX_W_0F3807_P_2): Likewise.
 647         (VEX_W_0F3808_P_2): Likewise.
 648         (VEX_W_0F3809_P_2): Likewise.
 649         (VEX_W_0F380A_P_2): Likewise.
 650         (VEX_W_0F380B_P_2): Likewise.
 651         (VEX_W_0F3817_P_2): Likewise.
 652         (VEX_W_0F381C_P_2): Likewise.
 653         (VEX_W_0F381D_P_2): Likewise.
 654         (VEX_W_0F381E_P_2): Likewise.
 655         (VEX_W_0F3820_P_2): Likewise.
 656         (VEX_W_0F3821_P_2): Likewise.
 657         (VEX_W_0F3822_P_2): Likewise.
 658         (VEX_W_0F3823_P_2): Likewise.
 659         (VEX_W_0F3824_P_2): Likewise.
 660         (VEX_W_0F3825_P_2): Likewise.
 661         (VEX_W_0F3828_P_2): Likewise.
 662         (VEX_W_0F3829_P_2): Likewise.
 663         (VEX_W_0F382A_P_2_M_0): Likewise.
 664         (VEX_W_0F382B_P_2): Likewise.
 665         (VEX_W_0F3830_P_2): Likewise.
 666         (VEX_W_0F3831_P_2): Likewise.
 667         (VEX_W_0F3832_P_2): Likewise.
 668         (VEX_W_0F3833_P_2): Likewise.
 669         (VEX_W_0F3834_P_2): Likewise.
 670         (VEX_W_0F3835_P_2): Likewise.
 671         (VEX_W_0F3837_P_2): Likewise.
 672         (VEX_W_0F3838_P_2): Likewise.
 673         (VEX_W_0F3839_P_2): Likewise.
 674         (VEX_W_0F383A_P_2): Likewise.
 675         (VEX_W_0F383B_P_2): Likewise.
 676         (VEX_W_0F383C_P_2): Likewise.
 677         (VEX_W_0F383D_P_2): Likewise.
 678         (VEX_W_0F383E_P_2): Likewise.
 679         (VEX_W_0F383F_P_2): Likewise.
 680         (VEX_W_0F3840_P_2): Likewise.
 681         (VEX_W_0F3841_P_2): Likewise.
 682         (VEX_W_0F38DB_P_2): Likewise.
 683         (VEX_W_0F3A08_P_2): Likewise.
 684         (VEX_W_0F3A09_P_2): Likewise.
 685         (VEX_W_0F3A0A_P_2): Likewise.
 686         (VEX_W_0F3A0B_P_2): Likewise.
 687         (VEX_W_0F3A0C_P_2): Likewise.
 688         (VEX_W_0F3A0D_P_2): Likewise.
 689         (VEX_W_0F3A0E_P_2): Likewise.
 690         (VEX_W_0F3A0F_P_2): Likewise.
 691         (VEX_W_0F3A21_P_2): Likewise.
 692         (VEX_W_0F3A40_P_2): Likewise.
 693         (VEX_W_0F3A41_P_2): Likewise.
 694         (VEX_W_0F3A42_P_2): Likewise.
 695         (VEX_W_0F3A62_P_2): Likewise.
 696         (VEX_W_0F3A63_P_2): Likewise.
 697         (VEX_W_0F3ADF_P_2): Likewise.
 698         (VEX_LEN_0F77_P_0): New.
 699         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 700         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 701         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 702         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 703         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 704         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 705         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 706         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 707         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 708         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 709         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 710         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 711         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 712         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 713         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 714         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 715         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 716         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 717         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 718         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 719         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 720         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 721         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 722         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 723         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 724         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 725         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 726         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 727         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 728         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 729         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 730         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 731         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 732         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 733         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 734         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 735         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 736         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 737         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 738         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 739         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 740         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 741         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 742         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 743         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 744         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 745         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 746         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 747         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 748         (vex_table): Update VEX 0F28 and 0F29 entries.
 749         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 750         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 751         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 752         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 753         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 754         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 755         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 756         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 757         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 758         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 759         VEX_LEN_0F3A0B_P_2 entries.
 760         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 761         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 762         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 763         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 764         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 765         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 766         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 767         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 768         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 769         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 770         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 771         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 772         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 773         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 774         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 775         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 776         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 777         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 778         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 779         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 780         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 781         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 782         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 783         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 784         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 785         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 786         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 787         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 788         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 789         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 790         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 791         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 792         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 793         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 794         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 795         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 796         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 797         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 798         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 799         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 800         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 801         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 802         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 803         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 804         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 805         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 806         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 807         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 808         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 809         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 810         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 811         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 812         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 813         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 814         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 815         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 816         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 817         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 818         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 819         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 820         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 821         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 822         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 823         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 824         VEX_W_0F3ADF_P_2 entries.
 825         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 826         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 827         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 828
 829 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 830
 831         * i386-opc.tbl (VexWIG): New.
 832         Replace VexW=3 with VexWIG.
 833
 834 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 835
 836         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 837         * i386-tbl.h: Regenerated.
 838
 839 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 840
 841         PR gas/23665
 842         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 843         VEX_LEN_0FD6_P_2 entries.
 844         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 845         * i386-tbl.h: Regenerated.
 846
 847 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 848
 849         PR gas/23642
 850         * i386-opc.h (VEXWIG): New.
 851         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 852         * i386-tbl.h: Regenerated.
 853
 854 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 855
 856         PR binutils/23655
 857         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 858         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 859         * i386-dis.c (EXxEVexR64): New.
 860         (evex_rounding_64_mode): Likewise.
 861         (OP_Rounding): Handle evex_rounding_64_mode.
 862
 863 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         PR binutils/23655
 866         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 867         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 868         * i386-dis.c (Edqa): New.
 869         (dqa_mode): Likewise.
 870         (intel_operand_size): Handle dqa_mode as m_mode.
 871         (OP_E_register): Handle dqa_mode as dq_mode.
 872         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 873
 874 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 875
 876         * i386-dis.c (OP_E_memory): Reformat.
 877
 878 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-opc.tbl (crc32): Fold byte and word forms.
 881         * i386-tbl.h: Re-generate.
 882
 883 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 884
 885         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 886         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 887         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 888         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 889         * i386-tbl.h: Regenerated.
 890
 891 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 892
 893         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 894         meaningless.
 895         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 896         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 897         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 898         * i386-tbl.h: Re-generate.
 899
 900 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 901
 902         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 903         AVX512_4VNNIW insns.
 904         * i386-tbl.h: Re-generate.
 905
 906 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 907
 908         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 909         meaningless.
 910         * i386-tbl.h: Re-generate.
 911
 912 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 913
 914         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 915         meaningless.
 916         * i386-tbl.h: Re-generate.
 917
 918 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 919
 920         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 921         meaningless.
 922         * i386-tbl.h: Re-generate.
 923
 924 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 925
 926         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 927         meaningless.
 928         * i386-tbl.h: Re-generate.
 929
 930 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 931
 932         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 933         meaningless.
 934         * i386-tbl.h: Re-generate.
 935
 936 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 937
 938         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 939         * i386-tbl.h: Re-generate.
 940
 941 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 942
 943         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 944         * i386-tbl.h: Re-generate.
 945
 946 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 949         meaningless.
 950         * i386-tbl.h: Re-generate.
 951
 952 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 955         meaningless.
 956         * i386-tbl.h: Re-generate.
 957
 958 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 959
 960         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 961         * i386-tbl.h: Re-generate.
 962
 963 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 964
 965         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 966         * i386-tbl.h: Re-generate.
 967
 968 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 969
 970         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 971         * i386-tbl.h: Re-generate.
 972
 973 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 974
 975         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 976         meaningless.
 977         * i386-tbl.h: Re-generate.
 978
 979 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 980
 981         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 982         meaningless.
 983         * i386-tbl.h: Re-generate.
 984
 985 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 986
 987         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 988         meaningless.
 989         * i386-tbl.h: Re-generate.
 990
 991 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 992
 993         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 994         * i386-tbl.h: Re-generate.
 995
 996 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 997
 998         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 999         * i386-tbl.h: Re-generate.
1000
1001 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1002
1003         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1004         * i386-tbl.h: Re-generate.
1005
1006 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1009         (vpbroadcastw, rdpid): Drop NoRex64.
1010         * i386-tbl.h: Re-generate.
1011
1012 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1013
1014         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1015         store templates, adding D.
1016         * i386-tbl.h: Re-generate.
1017
1018 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1019
1020         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1021         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1022         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1023         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1024         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1025         Fold load and store templates where possible, adding D. Drop
1026         IgnoreSize where it was pointlessly present. Drop redundant
1027         *word.
1028         * i386-tbl.h: Re-generate.
1029
1030 2018-09-13  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1033         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1034         (intel_operand_size): Handle v_bndmk_mode.
1035         (OP_E_memory): Likewise. Produce (bad) when also riprel.
1036
1037 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
1038
1039         * disassemble.c (ARCH_s12z): Define if ARCH_all.
1040
1041 2018-08-31  Kito Cheng  <kito@andestech.com>
1042
1043         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1044         compressed floating point instructions.
1045
1046 2018-08-30  Kito Cheng  <kito@andestech.com>
1047
1048         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1049         riscv_opcode.xlen_requirement.
1050         * riscv-opc.c (riscv_opcodes): Update for struct change.
1051
1052 2018-08-29  Martin Aberg  <maberg@gaisler.com>
1053
1054         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1055         psr (PWRPSR) instruction.
1056
1057 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1058
1059         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1060
1061 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1062
1063         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1064
1065 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1066
1067         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1068         loongson3a as an alias of gs464 for compatibility.
1069         * mips-opc.c (mips_opcodes): Change Comments.
1070
1071 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1072
1073         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1074         option.
1075         (print_mips_disassembler_options): Document -M loongson-ext.
1076         * mips-opc.c (LEXT2): New macro.
1077         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1078
1079 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1080
1081          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1082          descriptors.
1083          (parse_mips_ase_option): Handle -M loongson-ext option.
1084          (print_mips_disassembler_options): Document -M loongson-ext.
1085          * mips-opc.c (IL3A): Delete.
1086          * mips-opc.c (LEXT): New macro.
1087          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1088          instructions.
1089
1090 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
1091
1092         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1093         descriptors.
1094         (parse_mips_ase_option): Handle -M loongson-cam option.
1095         (print_mips_disassembler_options): Document -M loongson-cam.
1096         * mips-opc.c (LCAM): New macro.
1097         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1098         instructions.
1099
1100 2018-08-21  Alan Modra  <amodra@gmail.com>
1101
1102         * ppc-dis.c (operand_value_powerpc): Init "invalid".
1103         (skip_optional_operands): Count optional operands, and update
1104         ppc_optional_operand_value call.
1105         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1106         (extract_vlensi): Likewise.
1107         (extract_fxm): Return default value for missing optional operand.
1108         (extract_ls, extract_raq, extract_tbr): Likewise.
1109         (insert_sxl, extract_sxl): New functions.
1110         (insert_esync, extract_esync): Remove Power9 handling and simplify.
1111         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1112         flag and extra entry.
1113         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1114         extract_sxl.
1115
1116 2018-08-20  Alan Modra  <amodra@gmail.com>
1117
1118         * sh-opc.h (MASK): Simplify.
1119
1120 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1121
1122         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1123         BM_RESERVED0 or BM_RESERVED1
1124         (bm_rel_decode, bm_n_bytes): Ditto.
1125
1126 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1127
1128         * s12z.h: Delete.
1129
1130 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1131
1132         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1133         address with the addr32 prefix and without base nor index
1134         registers.
1135
1136 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1137
1138         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1139         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1140         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1141         (cpu_flags): Add CpuCMOV and CpuFXSR.
1142         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1143         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1144         * i386-init.h: Regenerated.
1145         * i386-tbl.h: Likewise.
1146
1147 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1148
1149         * arc-regs.h: Update auxiliary registers.
1150
1151 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1154         (RegIP, RegIZ): Define.
1155         * i386-reg.tbl: Adjust comments.
1156         (rip): Use Qword instead of BaseIndex. Use RegIP.
1157         (eip): Use Dword instead of BaseIndex. Use RegIP.
1158         (riz): Add Qword. Use RegIZ.
1159         (eiz): Add Dword. Use RegIZ.
1160         * i386-tbl.h: Re-generate.
1161
1162 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1163
1164         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1165         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1166         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1167         * i386-tbl.h: Re-generate.
1168
1169 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1170
1171         * i386-gen.c (operand_types): Remove Mem field.
1172         * i386-opc.h (union i386_operand_type): Remove mem field.
1173         * i386-init.h, i386-tbl.h: Re-generate.
1174
1175 2018-08-01  Alan Modra  <amodra@gmail.com>
1176
1177         * po/POTFILES.in: Regenerate.
1178
1179 2018-07-31  Nick Clifton  <nickc@redhat.com>
1180
1181         * po/sv.po: Updated Swedish translation.
1182
1183 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1186         * i386-init.h, i386-tbl.h: Re-generate.
1187
1188 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-opc.h (ZEROING_MASKING) Rename to ...
1191         (DYNAMIC_MASKING): ... this. Adjust comment.
1192         * i386-opc.tbl (MaskingMorZ): Define.
1193         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1194         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1195         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1196         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1197         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1198         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1199         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1200         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1201         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1202
1203 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1204
1205         * i386-opc.tbl: Use element rather than vector size for AVX512*
1206         scatter/gather insns.
1207         * i386-tbl.h: Re-generate.
1208
1209 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1210
1211         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1212         (cpu_flags): Drop CpuVREX.
1213         * i386-opc.h (CpuVREX): Delete.
1214         (union i386_cpu_flags): Remove cpuvrex.
1215         * i386-init.h, i386-tbl.h: Re-generate.
1216
1217 2018-07-30  Jim Wilson  <jimw@sifive.com>
1218
1219         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1220         fields.
1221         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1222
1223 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1224
1225         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1226         * Makefile.in: Regenerated.
1227         * configure.ac: Add C-SKY.
1228         * configure: Regenerated.
1229         * csky-dis.c: New file.
1230         * csky-opc.h: New file.
1231         * disassemble.c (ARCH_csky): Define.
1232         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1233         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1234
1235 2018-07-27  Alan Modra  <amodra@gmail.com>
1236
1237         * ppc-opc.c (insert_sprbat): Correct function parameter and
1238         return type.
1239         (extract_sprbat): Likewise, variable too.
1240
1241 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1242             Alan Modra  <amodra@gmail.com>
1243
1244         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1245         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1246         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1247         support disjointed BAT.
1248         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1249         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1250         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1251
1252 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1253             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1254
1255         * i386-gen.c (adjust_broadcast_modifier): New function.
1256         (process_i386_opcode_modifier): Add an argument for operands.
1257         Adjust the Broadcast value based on operands.
1258         (output_i386_opcode): Pass operand_types to
1259         process_i386_opcode_modifier.
1260         (process_i386_opcodes): Pass NULL as operands to
1261         process_i386_opcode_modifier.
1262         * i386-opc.h (BYTE_BROADCAST): New.
1263         (WORD_BROADCAST): Likewise.
1264         (DWORD_BROADCAST): Likewise.
1265         (QWORD_BROADCAST): Likewise.
1266         (i386_opcode_modifier): Expand broadcast to 3 bits.
1267         * i386-tbl.h: Regenerated.
1268
1269 2018-07-24  Alan Modra  <amodra@gmail.com>
1270
1271         PR 23430
1272         * or1k-desc.h: Regenerate.
1273
1274 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1275
1276         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1277         vcvtusi2ss, and vcvtusi2sd.
1278         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1279         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1280         * i386-tbl.h: Re-generate.
1281
1282 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1283
1284         * arc-opc.c (extract_w6): Fix extending the sign.
1285
1286 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1287
1288         * arc-tbl.h (vewt): Allow it for ARC EM family.
1289
1290 2018-07-23  Alan Modra  <amodra@gmail.com>
1291
1292         PR 23419
1293         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1294         opcode variants for mtspr/mfspr encodings.
1295
1296 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1297             Maciej W. Rozycki  <macro@mips.com>
1298
1299         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1300         loongson3a descriptors.
1301         (parse_mips_ase_option): Handle -M loongson-mmi option.
1302         (print_mips_disassembler_options): Document -M loongson-mmi.
1303         * mips-opc.c (LMMI): New macro.
1304         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1305         instructions.
1306
1307 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1308
1309         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1310         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1311         IgnoreSize and [XYZ]MMword where applicable.
1312         * i386-tbl.h: Re-generate.
1313
1314 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1315
1316         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1317         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1318         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1319         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1320         * i386-tbl.h: Re-generate.
1321
1322 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1323
1324         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1325         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1326         VPCLMULQDQ templates into their respective AVX512VL counterparts
1327         where possible, using Disp8ShiftVL and CheckRegSize instead of
1328         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1329         * i386-tbl.h: Re-generate.
1330
1331 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1332
1333         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1334         AVX512VL counterparts where possible, using Disp8ShiftVL and
1335         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1336         IgnoreSize) as appropriate.
1337         * i386-tbl.h: Re-generate.
1338
1339 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1340
1341         * i386-opc.tbl: Fold AVX512BW templates into their respective
1342         AVX512VL counterparts where possible, using Disp8ShiftVL and
1343         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1344         IgnoreSize) as appropriate.
1345         * i386-tbl.h: Re-generate.
1346
1347 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1348
1349         * i386-opc.tbl: Fold AVX512CD templates into their respective
1350         AVX512VL counterparts where possible, using Disp8ShiftVL and
1351         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1352         IgnoreSize) as appropriate.
1353         * i386-tbl.h: Re-generate.
1354
1355 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1356
1357         * i386-opc.h (DISP8_SHIFT_VL): New.
1358         * i386-opc.tbl (Disp8ShiftVL):  Define.
1359         (various): Fold AVX512VL templates into their respective
1360         AVX512F counterparts where possible, using Disp8ShiftVL and
1361         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1362         IgnoreSize) as appropriate.
1363         * i386-tbl.h: Re-generate.
1364
1365 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1366
1367         * Makefile.am: Change dependencies and rule for
1368         $(srcdir)/i386-init.h.
1369         * Makefile.in: Re-generate.
1370         * i386-gen.c (process_i386_opcodes): New local variable
1371         "marker". Drop opening of input file. Recognize marker and line
1372         number directives.
1373         * i386-opc.tbl (OPCODE_I386_H): Define.
1374         (i386-opc.h): Include it.
1375         (None): Undefine.
1376
1377 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1378
1379         PR gas/23418
1380         * i386-opc.h (Byte): Update comments.
1381         (Word): Likewise.
1382         (Dword): Likewise.
1383         (Fword): Likewise.
1384         (Qword): Likewise.
1385         (Tbyte): Likewise.
1386         (Xmmword): Likewise.
1387         (Ymmword): Likewise.
1388         (Zmmword): Likewise.
1389         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1390         vcvttps2uqq.
1391         * i386-tbl.h: Regenerated.
1392
1393 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1394
1395         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1396         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1397         * aarch64-asm-2.c: Regenerate.
1398         * aarch64-dis-2.c: Regenerate.
1399         * aarch64-opc-2.c: Regenerate.
1400
1401 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1402
1403         PR binutils/23192
1404         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1405         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1406         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1407         sqdmulh, sqrdmulh): Use Em16.
1408
1409 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1410
1411         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1412         csdb together with them.
1413         (thumb32_opcodes): Likewise.
1414
1415 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1416
1417         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1418         requiring 32-bit registers as operands 2 and 3. Improve
1419         comments.
1420         (mwait, mwaitx): Fold templates. Improve comments.
1421         OPERAND_TYPE_INOUTPORTREG.
1422         * i386-tbl.h: Re-generate.
1423
1424 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1425
1426         * i386-gen.c (operand_type_init): Remove
1427         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1428         OPERAND_TYPE_INOUTPORTREG.
1429         * i386-init.h: Re-generate.
1430
1431 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1432
1433         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1434         (wrssq, wrussq): Add Qword.
1435         * i386-tbl.h: Re-generate.
1436
1437 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1438
1439         * i386-opc.h: Rename OTMax to OTNum.
1440         (OTNumOfUints): Adjust calculation.
1441         (OTUnused): Directly alias to OTNum.
1442
1443 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1444
1445         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1446         `reg_xys'.
1447         (lea_reg_xys): Likewise.
1448         (print_insn_loop_primitive): Rename `reg' local variable to
1449         `reg_dxy'.
1450
1451 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1452
1453         PR binutils/23242
1454         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1455
1456 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1457
1458         PR binutils/23369
1459         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1460         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1461
1462 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1463
1464         PR tdep/8282
1465         * mips-dis.c (mips_option_arg_t): New enumeration.
1466         (mips_options): New variable.
1467         (disassembler_options_mips): New function.
1468         (print_mips_disassembler_options): Reimplement in terms of
1469         `disassembler_options_mips'.
1470         * arm-dis.c (disassembler_options_arm): Adapt to using the
1471         `disasm_options_and_args_t' structure.
1472         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1473         * s390-dis.c (disassembler_options_s390): Likewise.
1474
1475 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1476
1477         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1478         expected result.
1479         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1480         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1481         * testsuite/ld-arm/tls-longplt.d: Likewise.
1482
1483 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1484
1485         PR binutils/23192
1486         * aarch64-asm-2.c: Regenerate.
1487         * aarch64-dis-2.c: Likewise.
1488         * aarch64-opc-2.c: Likewise.
1489         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1490         * aarch64-opc.c (operand_general_constraint_met_p,
1491         aarch64_print_operand): Likewise.
1492         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1493         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1494         fmlal2, fmlsl2.
1495         (AARCH64_OPERANDS): Add Em2.
1496
1497 2018-06-26  Nick Clifton  <nickc@redhat.com>
1498
1499         * po/uk.po: Updated Ukranian translation.
1500         * po/de.po: Updated German translation.
1501         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1502
1503 2018-06-26  Nick Clifton  <nickc@redhat.com>
1504
1505         * nfp-dis.c: Fix spelling mistake.
1506
1507 2018-06-24  Nick Clifton  <nickc@redhat.com>
1508
1509         * configure: Regenerate.
1510         * po/opcodes.pot: Regenerate.
1511
1512 2018-06-24  Nick Clifton  <nickc@redhat.com>
1513
1514         2.31 branch created.
1515
1516 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1517
1518         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1519         * aarch64-asm-2.c: Regenerate.
1520         * aarch64-dis-2.c: Likewise.
1521
1522 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1523
1524         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1525         `-M ginv' option description.
1526
1527 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1528
1529         PR gas/23305
1530         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1531         la and lla.
1532
1533 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1534
1535         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1536         * configure.ac: Remove AC_PREREQ.
1537         * Makefile.in: Re-generate.
1538         * aclocal.m4: Re-generate.
1539         * configure: Re-generate.
1540
1541 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1542
1543         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1544         mips64r6 descriptors.
1545         (parse_mips_ase_option): Handle -Mginv option.
1546         (print_mips_disassembler_options): Document -Mginv.
1547         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1548         (GINV): New macro.
1549         (mips_opcodes): Define ginvi and ginvt.
1550
1551 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1552             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1553
1554         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1555         * mips-opc.c (CRC, CRC64): New macros.
1556         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1557         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1558         crc32cd for CRC64.
1559
1560 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1561
1562         PR 20319
1563         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1564         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1565
1566 2018-06-06  Alan Modra  <amodra@gmail.com>
1567
1568         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1569         setjmp.  Move init for some other vars later too.
1570
1571 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1572
1573         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1574         (dis_private): Add new fields for property section tracking.
1575         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1576         (xtensa_instruction_fits): New functions.
1577         (fetch_data): Bump minimal fetch size to 4.
1578         (print_insn_xtensa): Make struct dis_private static.
1579         Load and prepare property table on section change.
1580         Don't disassemble literals. Don't disassemble instructions that
1581         cross property table boundaries.
1582
1583 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1584
1585         * configure: Regenerated.
1586
1587 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1588
1589         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1590         * i386-tbl.h: Re-generate.
1591
1592 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1593
1594         * i386-opc.tbl (sldt, str): Add NoRex64.
1595         * i386-tbl.h: Re-generate.
1596
1597 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1598
1599         * i386-opc.tbl (invpcid): Add Oword.
1600         * i386-tbl.h: Re-generate.
1601
1602 2018-06-01  Alan Modra  <amodra@gmail.com>
1603
1604         * sysdep.h (_bfd_error_handler): Don't declare.
1605         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1606         * rl78-decode.opc: Likewise.
1607         * msp430-decode.c: Regenerate.
1608         * rl78-decode.c: Regenerate.
1609
1610 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1611
1612         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1613         * i386-init.h : Regenerated.
1614
1615 2018-05-25  Alan Modra  <amodra@gmail.com>
1616
1617         * Makefile.in: Regenerate.
1618         * po/POTFILES.in: Regenerate.
1619
1620 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1621
1622         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1623         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1624         (insert_bab, extract_bab, insert_btab, extract_btab,
1625         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1626         (BAT, BBA VBA RBS XB6S): Delete macros.
1627         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1628         (BB, BD, RBX, XC6): Update for new macros.
1629         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1630         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1631         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1632         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1633
1634 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1635
1636         * Makefile.am: Add support for s12z architecture.
1637         * configure.ac: Likewise.
1638         * disassemble.c: Likewise.
1639         * disassemble.h: Likewise.
1640         * Makefile.in: Regenerate.
1641         * configure: Regenerate.
1642         * s12z-dis.c: New file.
1643         * s12z.h: New file.
1644
1645 2018-05-18  Alan Modra  <amodra@gmail.com>
1646
1647         * nfp-dis.c: Don't #include libbfd.h.
1648         (init_nfp3200_priv): Use bfd_get_section_contents.
1649         (nit_nfp6000_mecsr_sec): Likewise.
1650
1651 2018-05-17  Nick Clifton  <nickc@redhat.com>
1652
1653         * po/zh_CN.po: Updated simplified Chinese translation.
1654
1655 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1656
1657         PR binutils/23109
1658         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1659         * aarch64-dis-2.c: Regenerate.
1660
1661 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1662
1663         PR binutils/21446
1664         * aarch64-asm.c (opintl.h): Include.
1665         (aarch64_ins_sysreg): Enforce read/write constraints.
1666         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1667         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1668         (F_REG_READ, F_REG_WRITE): New.
1669         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1670         AARCH64_OPND_SYSREG.
1671         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1672         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1673         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1674         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1675         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1676         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1677         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1678         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1679         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1680         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1681         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1682         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1683         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1684         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1685         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1686         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1687         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1688
1689 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1690
1691         PR binutils/21446
1692         * aarch64-dis.c (no_notes: New.
1693         (parse_aarch64_dis_option): Support notes.
1694         (aarch64_decode_insn, print_operands): Likewise.
1695         (print_aarch64_disassembler_options): Document notes.
1696         * aarch64-opc.c (aarch64_print_operand): Support notes.
1697
1698 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1699
1700         PR binutils/21446
1701         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1702         and take error struct.
1703         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1704         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1705         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1706         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1707         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1708         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1709         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1710         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1711         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1712         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1713         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1714         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1715         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1716         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1717         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1718         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1719         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1720         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1721         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1722         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1723         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1724         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1725         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1726         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1727         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1728         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1729         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1730         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1731         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1732         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1733         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1734         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1735         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1736         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1737         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1738         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1739         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1740         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1741         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1742         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1743         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1744         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1745         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1746         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1747         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1748         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1749         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1750         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1751         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1752         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1753         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1754         (determine_disassembling_preference, aarch64_decode_insn,
1755         print_insn_aarch64_word, print_insn_data): Take errors struct.
1756         (print_insn_aarch64): Use errors.
1757         * aarch64-asm-2.c: Regenerate.
1758         * aarch64-dis-2.c: Regenerate.
1759         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1760         boolean in aarch64_insert_operan.
1761         (print_operand_extractor): Likewise.
1762         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1763
1764 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1765
1766         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1767
1768 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1769
1770         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1771
1772 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1773
1774         * cr16-opc.c (cr16_instruction): Comment typo fix.
1775         * hppa-dis.c (print_insn_hppa): Likewise.
1776
1777 2018-05-08  Jim Wilson  <jimw@sifive.com>
1778
1779         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1780         (match_c_slli64, match_srxi_as_c_srxi): New.
1781         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1782         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1783         <c.slli, c.srli, c.srai>: Use match_s_slli.
1784         <c.slli64, c.srli64, c.srai64>: New.
1785
1786 2018-05-08  Alan Modra  <amodra@gmail.com>
1787
1788         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1789         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1790         partition opcode space for index lookup.
1791
1792 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1793
1794         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1795         <insn_length>: ...with this.  Update usage.
1796         Remove duplicate call to *info->memory_error_func.
1797
1798 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1799             H.J. Lu  <hongjiu.lu@intel.com>
1800
1801         * i386-dis.c (Gva): New.
1802         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1803         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1804         (prefix_table): New instructions (see prefix above).
1805         (mod_table): New instructions (see prefix above).
1806         (OP_G): Handle va_mode.
1807         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1808         CPU_MOVDIR64B_FLAGS.
1809         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1810         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1811         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1812         * i386-opc.tbl: Add movidir{i,64b}.
1813         * i386-init.h: Regenerated.
1814         * i386-tbl.h: Likewise.
1815
1816 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1817
1818         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1819         AddrPrefixOpReg.
1820         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1821         (AddrPrefixOpReg): This.
1822         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1823         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1824
1825 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1826
1827         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1828         (vle_num_opcodes): Likewise.
1829         (spe2_num_opcodes): Likewise.
1830         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1831         initialization loop.
1832         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1833         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1834         only once.
1835
1836 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1837
1838         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1839
1840 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1841
1842         Makefile.am: Added nfp-dis.c.
1843         configure.ac: Added bfd_nfp_arch.
1844         disassemble.h: Added print_insn_nfp prototype.
1845         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1846         nfp-dis.c: New, for NFP support.
1847         po/POTFILES.in: Added nfp-dis.c to the list.
1848         Makefile.in: Regenerate.
1849         configure: Regenerate.
1850
1851 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1852
1853         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1854         templates into their base ones.
1855         * i386-tlb.h: Re-generate.
1856
1857 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1858
1859         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1860         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1861         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1862         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1863         * i386-init.h: Re-generate.
1864
1865 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1866
1867         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1868         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1869         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1870         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1871         comment.
1872         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1873         and CpuRegMask.
1874         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1875         CpuRegMask: Delete.
1876         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1877         cpuregzmm, and cpuregmask.
1878         * i386-init.h: Re-generate.
1879         * i386-tbl.h: Re-generate.
1880
1881 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1882
1883         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1884         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1885         * i386-init.h: Re-generate.
1886
1887 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1888
1889         * i386-gen.c (VexImmExt): Delete.
1890         * i386-opc.h (VexImmExt, veximmext): Delete.
1891         * i386-opc.tbl: Drop all VexImmExt uses.
1892         * i386-tlb.h: Re-generate.
1893
1894 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1895
1896         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1897         register-only forms.
1898         * i386-tlb.h: Re-generate.
1899
1900 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1901
1902         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1903
1904 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1905
1906         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1907         PREFIX_0F1C.
1908         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1909         (cpu_flags): Add CpuCLDEMOTE.
1910         * i386-init.h: Regenerate.
1911         * i386-opc.h (enum): Add CpuCLDEMOTE,
1912         (i386_cpu_flags): Add cpucldemote.
1913         * i386-opc.tbl: Add cldemote.
1914         * i386-tbl.h: Regenerate.
1915
1916 2018-04-16  Alan Modra  <amodra@gmail.com>
1917
1918         * Makefile.am: Remove sh5 and sh64 support.
1919         * configure.ac: Likewise.
1920         * disassemble.c: Likewise.
1921         * disassemble.h: Likewise.
1922         * sh-dis.c: Likewise.
1923         * sh64-dis.c: Delete.
1924         * sh64-opc.c: Delete.
1925         * sh64-opc.h: Delete.
1926         * Makefile.in: Regenerate.
1927         * configure: Regenerate.
1928         * po/POTFILES.in: Regenerate.
1929
1930 2018-04-16  Alan Modra  <amodra@gmail.com>
1931
1932         * Makefile.am: Remove w65 support.
1933         * configure.ac: Likewise.
1934         * disassemble.c: Likewise.
1935         * disassemble.h: Likewise.
1936         * w65-dis.c: Delete.
1937         * w65-opc.h: Delete.
1938         * Makefile.in: Regenerate.
1939         * configure: Regenerate.
1940         * po/POTFILES.in: Regenerate.
1941
1942 2018-04-16  Alan Modra  <amodra@gmail.com>
1943
1944         * configure.ac: Remove we32k support.
1945         * configure: Regenerate.
1946
1947 2018-04-16  Alan Modra  <amodra@gmail.com>
1948
1949         * Makefile.am: Remove m88k support.
1950         * configure.ac: Likewise.
1951         * disassemble.c: Likewise.
1952         * disassemble.h: Likewise.
1953         * m88k-dis.c: Delete.
1954         * Makefile.in: Regenerate.
1955         * configure: Regenerate.
1956         * po/POTFILES.in: Regenerate.
1957
1958 2018-04-16  Alan Modra  <amodra@gmail.com>
1959
1960         * Makefile.am: Remove i370 support.
1961         * configure.ac: Likewise.
1962         * disassemble.c: Likewise.
1963         * disassemble.h: Likewise.
1964         * i370-dis.c: Delete.
1965         * i370-opc.c: Delete.
1966         * Makefile.in: Regenerate.
1967         * configure: Regenerate.
1968         * po/POTFILES.in: Regenerate.
1969
1970 2018-04-16  Alan Modra  <amodra@gmail.com>
1971
1972         * Makefile.am: Remove h8500 support.
1973         * configure.ac: Likewise.
1974         * disassemble.c: Likewise.
1975         * disassemble.h: Likewise.
1976         * h8500-dis.c: Delete.
1977         * h8500-opc.h: Delete.
1978         * Makefile.in: Regenerate.
1979         * configure: Regenerate.
1980         * po/POTFILES.in: Regenerate.
1981
1982 2018-04-16  Alan Modra  <amodra@gmail.com>
1983
1984         * configure.ac: Remove tahoe support.
1985         * configure: Regenerate.
1986
1987 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1988
1989         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1990         umwait.
1991         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1992         64-bit mode.
1993         * i386-tbl.h: Regenerated.
1994
1995 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1996
1997         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1998         PREFIX_MOD_1_0FAE_REG_6.
1999         (va_mode): New.
2000         (OP_E_register): Use va_mode.
2001         * i386-dis-evex.h (prefix_table):
2002         New instructions (see prefixes above).
2003         * i386-gen.c (cpu_flag_init): Add WAITPKG.
2004         (cpu_flags): Likewise.
2005         * i386-opc.h (enum): Likewise.
2006         (i386_cpu_flags): Likewise.
2007         * i386-opc.tbl: Add umonitor, umwait, tpause.
2008         * i386-init.h: Regenerate.
2009         * i386-tbl.h: Likewise.
2010
2011 2018-04-11  Alan Modra  <amodra@gmail.com>
2012
2013         * opcodes/i860-dis.c: Delete.
2014         * opcodes/i960-dis.c: Delete.
2015         * Makefile.am: Remove i860 and i960 support.
2016         * configure.ac: Likewise.
2017         * disassemble.c: Likewise.
2018         * disassemble.h: Likewise.
2019         * Makefile.in: Regenerate.
2020         * configure: Regenerate.
2021         * po/POTFILES.in: Regenerate.
2022
2023 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
2024
2025         PR binutils/23025
2026         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2027         to 0.
2028         (print_insn): Clear vex instead of vex.evex.
2029
2030 2018-04-04  Nick Clifton  <nickc@redhat.com>
2031
2032         * po/es.po: Updated Spanish translation.
2033
2034 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2035
2036         * i386-gen.c (opcode_modifiers): Delete VecESize.
2037         * i386-opc.h (VecESize): Delete.
2038         (struct i386_opcode_modifier): Delete vecesize.
2039         * i386-opc.tbl: Drop VecESize.
2040         * i386-tlb.h: Re-generate.
2041
2042 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2043
2044         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2045         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2046         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2047         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2048         * i386-tlb.h: Re-generate.
2049
2050 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2051
2052         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2053         Fold AVX512 forms
2054         * i386-tlb.h: Re-generate.
2055
2056 2018-03-28  Jan Beulich  <jbeulich@suse.com>
2057
2058         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2059         (vex_len_table): Drop Y for vcvt*2si.
2060         (putop): Replace plain 'Y' handling by abort().
2061
2062 2018-03-28  Nick Clifton  <nickc@redhat.com>
2063
2064         PR 22988
2065         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2066         instructions with only a base address register.
2067         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2068         handle AARHC64_OPND_SVE_ADDR_R.
2069         (aarch64_print_operand): Likewise.
2070         * aarch64-asm-2.c: Regenerate.
2071         * aarch64_dis-2.c: Regenerate.
2072         * aarch64-opc-2.c: Regenerate.
2073
2074 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2075
2076         * i386-opc.tbl: Drop VecESize from register only insn forms and
2077         memory forms not allowing broadcast.
2078         * i386-tlb.h: Re-generate.
2079
2080 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2081
2082         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2083         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2084         sha256*): Drop Disp<N>.
2085
2086 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2087
2088         * i386-dis.c (EbndS, bnd_swap_mode): New.
2089         (prefix_table): Use EbndS.
2090         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2091         * i386-opc.tbl (bndmov): Move misplaced Load.
2092         * i386-tlb.h: Re-generate.
2093
2094 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2095
2096         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2097         templates allowing memory operands and folded ones for register
2098         only flavors.
2099         * i386-tlb.h: Re-generate.
2100
2101 2018-03-22  Jan Beulich  <jbeulich@suse.com>
2102
2103         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2104         256-bit templates. Drop redundant leftover Disp<N>.
2105         * i386-tlb.h: Re-generate.
2106
2107 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
2108
2109         * riscv-opc.c (riscv_insn_types): New.
2110
2111 2018-03-13  Nick Clifton  <nickc@redhat.com>
2112
2113         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2114
2115 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2116
2117         * i386-opc.tbl: Add Optimize to clr.
2118         * i386-tbl.h: Regenerated.
2119
2120 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2121
2122         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2123         * i386-opc.h (OldGcc): Removed.
2124         (i386_opcode_modifier): Remove oldgcc.
2125         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2126         instructions for old (<= 2.8.1) versions of gcc.
2127         * i386-tbl.h: Regenerated.
2128
2129 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2130
2131         * i386-opc.h (EVEXDYN): New.
2132         * i386-opc.tbl: Fold various AVX512VL templates.
2133         * i386-tlb.h: Re-generate.
2134
2135 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2136
2137         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2138         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2139         vpexpandd, vpexpandq): Fold AFX512VF templates.
2140         * i386-tlb.h: Re-generate.
2141
2142 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2143
2144         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2145         Fold 128- and 256-bit VEX-encoded templates.
2146         * i386-tlb.h: Re-generate.
2147
2148 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2149
2150         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2151         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2152         vpexpandd, vpexpandq): Fold AVX512F templates.
2153         * i386-tlb.h: Re-generate.
2154
2155 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2156
2157         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2158         64-bit templates. Drop Disp<N>.
2159         * i386-tlb.h: Re-generate.
2160
2161 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2162
2163         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2164         and 256-bit templates.
2165         * i386-tlb.h: Re-generate.
2166
2167 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2168
2169         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2170         * i386-tlb.h: Re-generate.
2171
2172 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2173
2174         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2175         Drop NoAVX.
2176         * i386-tlb.h: Re-generate.
2177
2178 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2179
2180         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2181         * i386-tlb.h: Re-generate.
2182
2183 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2184
2185         * i386-gen.c (opcode_modifiers): Delete FloatD.
2186         * i386-opc.h (FloatD): Delete.
2187         (struct i386_opcode_modifier): Delete floatd.
2188         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2189         FloatD by D.
2190         * i386-tlb.h: Re-generate.
2191
2192 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2193
2194         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2195
2196 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2197
2198         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2199         * i386-tlb.h: Re-generate.
2200
2201 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2202
2203         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2204         forms.
2205         * i386-tlb.h: Re-generate.
2206
2207 2018-03-07  Alan Modra  <amodra@gmail.com>
2208
2209         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2210         bfd_arch_rs6000.
2211         * disassemble.h (print_insn_rs6000): Delete.
2212         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2213         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2214         (print_insn_rs6000): Delete.
2215
2216 2018-03-03  Alan Modra  <amodra@gmail.com>
2217
2218         * sysdep.h (opcodes_error_handler): Define.
2219         (_bfd_error_handler): Declare.
2220         * Makefile.am: Remove stray #.
2221         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2222         EDIT" comment.
2223         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2224         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2225         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2226         opcodes_error_handler to print errors.  Standardize error messages.
2227         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2228         and include opintl.h.
2229         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2230         * i386-gen.c: Standardize error messages.
2231         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2232         * Makefile.in: Regenerate.
2233         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2234         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2235         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2236         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2237         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2238         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2239         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2240         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2241         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2242         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2243         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2244         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2245         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2246
2247 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2248
2249         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2250         vpsub[bwdq] instructions.
2251         * i386-tbl.h: Regenerated.
2252
2253 2018-03-01  Alan Modra  <amodra@gmail.com>
2254
2255         * configure.ac (ALL_LINGUAS): Sort.
2256         * configure: Regenerate.
2257
2258 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2259
2260         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2261         macro by assignements.
2262
2263 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2264
2265         PR gas/22871
2266         * i386-gen.c (opcode_modifiers): Add Optimize.
2267         * i386-opc.h (Optimize): New enum.
2268         (i386_opcode_modifier): Add optimize.
2269         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2270         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2271         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2272         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2273         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2274         vpxord and vpxorq.
2275         * i386-tbl.h: Regenerated.
2276
2277 2018-02-26  Alan Modra  <amodra@gmail.com>
2278
2279         * crx-dis.c (getregliststring): Allocate a large enough buffer
2280         to silence false positive gcc8 warning.
2281
2282 2018-02-22  Shea Levy <shea@shealevy.com>
2283
2284         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2285
2286 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2287
2288         * i386-opc.tbl: Add {rex},
2289         * i386-tbl.h: Regenerated.
2290
2291 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2292
2293         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2294         (mips16_opcodes): Replace `M' with `m' for "restore".
2295
2296 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2297
2298         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2299
2300 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2301
2302         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2303         variable to `function_index'.
2304
2305 2018-02-13  Nick Clifton  <nickc@redhat.com>
2306
2307         PR 22823
2308         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2309         about truncation of printing.
2310
2311 2018-02-12  Henry Wong <henry@stuffedcow.net>
2312
2313         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2314
2315 2018-02-05  Nick Clifton  <nickc@redhat.com>
2316
2317         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2318
2319 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2320
2321         * i386-dis.c (enum): Add pconfig.
2322         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2323         (cpu_flags): Add CpuPCONFIG.
2324         * i386-opc.h (enum): Add CpuPCONFIG.
2325         (i386_cpu_flags): Add cpupconfig.
2326         * i386-opc.tbl: Add PCONFIG instruction.
2327         * i386-init.h: Regenerate.
2328         * i386-tbl.h: Likewise.
2329
2330 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2331
2332         * i386-dis.c (enum): Add PREFIX_0F09.
2333         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2334         (cpu_flags): Add CpuWBNOINVD.
2335         * i386-opc.h (enum): Add CpuWBNOINVD.
2336         (i386_cpu_flags): Add cpuwbnoinvd.
2337         * i386-opc.tbl: Add WBNOINVD instruction.
2338         * i386-init.h: Regenerate.
2339         * i386-tbl.h: Likewise.
2340
2341 2018-01-17  Jim Wilson  <jimw@sifive.com>
2342
2343         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2344
2345 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2346
2347         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2348         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2349         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2350         (cpu_flags): Add CpuIBT, CpuSHSTK.
2351         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2352         (i386_cpu_flags): Add cpuibt, cpushstk.
2353         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2354         * i386-init.h: Regenerate.
2355         * i386-tbl.h: Likewise.
2356
2357 2018-01-16  Nick Clifton  <nickc@redhat.com>
2358
2359         * po/pt_BR.po: Updated Brazilian Portugese translation.
2360         * po/de.po: Updated German translation.
2361
2362 2018-01-15  Jim Wilson  <jimw@sifive.com>
2363
2364         * riscv-opc.c (match_c_nop): New.
2365         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2366
2367 2018-01-15  Nick Clifton  <nickc@redhat.com>
2368
2369         * po/uk.po: Updated Ukranian translation.
2370
2371 2018-01-13  Nick Clifton  <nickc@redhat.com>
2372
2373         * po/opcodes.pot: Regenerated.
2374
2375 2018-01-13  Nick Clifton  <nickc@redhat.com>
2376
2377         * configure: Regenerate.
2378
2379 2018-01-13  Nick Clifton  <nickc@redhat.com>
2380
2381         2.30 branch created.
2382
2383 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2384
2385         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2386         * i386-tbl.h: Regenerate.
2387
2388 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2389
2390         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2391         * i386-tbl.h: Re-generate.
2392
2393 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2394
2395         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2396         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2397         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2398         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2399         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2400         Disp8MemShift of AVX512VL forms.
2401         * i386-tbl.h: Re-generate.
2402
2403 2018-01-09  Jim Wilson  <jimw@sifive.com>
2404
2405         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2406         then the hi_addr value is zero.
2407
2408 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2409
2410         * arm-dis.c (arm_opcodes): Add csdb.
2411         (thumb32_opcodes): Add csdb.
2412
2413 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2414
2415         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2416         * aarch64-asm-2.c: Regenerate.
2417         * aarch64-dis-2.c: Regenerate.
2418         * aarch64-opc-2.c: Regenerate.
2419
2420 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2421
2422         PR gas/22681
2423         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2424         Remove AVX512 vmovd with 64-bit operands.
2425         * i386-tbl.h: Regenerated.
2426
2427 2018-01-05  Jim Wilson  <jimw@sifive.com>
2428
2429         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2430         jalr.
2431
2432 2018-01-03  Alan Modra  <amodra@gmail.com>
2433
2434         Update year range in copyright notice of all files.
2435
2436 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2437
2438         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2439         and OPERAND_TYPE_REGZMM entries.
2440
2441 For older changes see ChangeLog-2017
2442 \f
2443 Copyright (C) 2018 Free Software Foundation, Inc.
2444
2445 Copying and distribution of this file, with or without modification,
2446 are permitted in any medium without royalty provided the copyright
2447 notice and this notice are preserved.
2448
2449 Local Variables:
2450 mode: change-log
2451 left-margin: 8
2452 fill-column: 74
2453 version-control: never
2454 End: