opcodes/ChangeLog

   1 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (VZERO_Fixup): Removed.
   4         (VZERO): Likewise.
   5         (VEX_LEN_0F10_P_1): Likewise.
   6         (VEX_LEN_0F10_P_3): Likewise.
   7         (VEX_LEN_0F11_P_1): Likewise.
   8         (VEX_LEN_0F11_P_3): Likewise.
   9         (VEX_LEN_0F2E_P_0): Likewise.
  10         (VEX_LEN_0F2E_P_2): Likewise.
  11         (VEX_LEN_0F2F_P_0): Likewise.
  12         (VEX_LEN_0F2F_P_2): Likewise.
  13         (VEX_LEN_0F51_P_1): Likewise.
  14         (VEX_LEN_0F51_P_3): Likewise.
  15         (VEX_LEN_0F52_P_1): Likewise.
  16         (VEX_LEN_0F53_P_1): Likewise.
  17         (VEX_LEN_0F58_P_1): Likewise.
  18         (VEX_LEN_0F58_P_3): Likewise.
  19         (VEX_LEN_0F59_P_1): Likewise.
  20         (VEX_LEN_0F59_P_3): Likewise.
  21         (VEX_LEN_0F5A_P_1): Likewise.
  22         (VEX_LEN_0F5A_P_3): Likewise.
  23         (VEX_LEN_0F5C_P_1): Likewise.
  24         (VEX_LEN_0F5C_P_3): Likewise.
  25         (VEX_LEN_0F5D_P_1): Likewise.
  26         (VEX_LEN_0F5D_P_3): Likewise.
  27         (VEX_LEN_0F5E_P_1): Likewise.
  28         (VEX_LEN_0F5E_P_3): Likewise.
  29         (VEX_LEN_0F5F_P_1): Likewise.
  30         (VEX_LEN_0F5F_P_3): Likewise.
  31         (VEX_LEN_0FC2_P_1): Likewise.
  32         (VEX_LEN_0FC2_P_3): Likewise.
  33         (VEX_LEN_0F3A0A_P_2): Likewise.
  34         (VEX_LEN_0F3A0B_P_2): Likewise.
  35         (VEX_W_0F10_P_0): Likewise.
  36         (VEX_W_0F10_P_1): Likewise.
  37         (VEX_W_0F10_P_2): Likewise.
  38         (VEX_W_0F10_P_3): Likewise.
  39         (VEX_W_0F11_P_0): Likewise.
  40         (VEX_W_0F11_P_1): Likewise.
  41         (VEX_W_0F11_P_2): Likewise.
  42         (VEX_W_0F11_P_3): Likewise.
  43         (VEX_W_0F12_P_0_M_0): Likewise.
  44         (VEX_W_0F12_P_0_M_1): Likewise.
  45         (VEX_W_0F12_P_1): Likewise.
  46         (VEX_W_0F12_P_2): Likewise.
  47         (VEX_W_0F12_P_3): Likewise.
  48         (VEX_W_0F13_M_0): Likewise.
  49         (VEX_W_0F14): Likewise.
  50         (VEX_W_0F15): Likewise.
  51         (VEX_W_0F16_P_0_M_0): Likewise.
  52         (VEX_W_0F16_P_0_M_1): Likewise.
  53         (VEX_W_0F16_P_1): Likewise.
  54         (VEX_W_0F16_P_2): Likewise.
  55         (VEX_W_0F17_M_0): Likewise.
  56         (VEX_W_0F28): Likewise.
  57         (VEX_W_0F29): Likewise.
  58         (VEX_W_0F2B_M_0): Likewise.
  59         (VEX_W_0F2E_P_0): Likewise.
  60         (VEX_W_0F2E_P_2): Likewise.
  61         (VEX_W_0F2F_P_0): Likewise.
  62         (VEX_W_0F2F_P_2): Likewise.
  63         (VEX_W_0F50_M_0): Likewise.
  64         (VEX_W_0F51_P_0): Likewise.
  65         (VEX_W_0F51_P_1): Likewise.
  66         (VEX_W_0F51_P_2): Likewise.
  67         (VEX_W_0F51_P_3): Likewise.
  68         (VEX_W_0F52_P_0): Likewise.
  69         (VEX_W_0F52_P_1): Likewise.
  70         (VEX_W_0F53_P_0): Likewise.
  71         (VEX_W_0F53_P_1): Likewise.
  72         (VEX_W_0F58_P_0): Likewise.
  73         (VEX_W_0F58_P_1): Likewise.
  74         (VEX_W_0F58_P_2): Likewise.
  75         (VEX_W_0F58_P_3): Likewise.
  76         (VEX_W_0F59_P_0): Likewise.
  77         (VEX_W_0F59_P_1): Likewise.
  78         (VEX_W_0F59_P_2): Likewise.
  79         (VEX_W_0F59_P_3): Likewise.
  80         (VEX_W_0F5A_P_0): Likewise.
  81         (VEX_W_0F5A_P_1): Likewise.
  82         (VEX_W_0F5A_P_3): Likewise.
  83         (VEX_W_0F5B_P_0): Likewise.
  84         (VEX_W_0F5B_P_1): Likewise.
  85         (VEX_W_0F5B_P_2): Likewise.
  86         (VEX_W_0F5C_P_0): Likewise.
  87         (VEX_W_0F5C_P_1): Likewise.
  88         (VEX_W_0F5C_P_2): Likewise.
  89         (VEX_W_0F5C_P_3): Likewise.
  90         (VEX_W_0F5D_P_0): Likewise.
  91         (VEX_W_0F5D_P_1): Likewise.
  92         (VEX_W_0F5D_P_2): Likewise.
  93         (VEX_W_0F5D_P_3): Likewise.
  94         (VEX_W_0F5E_P_0): Likewise.
  95         (VEX_W_0F5E_P_1): Likewise.
  96         (VEX_W_0F5E_P_2): Likewise.
  97         (VEX_W_0F5E_P_3): Likewise.
  98         (VEX_W_0F5F_P_0): Likewise.
  99         (VEX_W_0F5F_P_1): Likewise.
 100         (VEX_W_0F5F_P_2): Likewise.
 101         (VEX_W_0F5F_P_3): Likewise.
 102         (VEX_W_0F60_P_2): Likewise.
 103         (VEX_W_0F61_P_2): Likewise.
 104         (VEX_W_0F62_P_2): Likewise.
 105         (VEX_W_0F63_P_2): Likewise.
 106         (VEX_W_0F64_P_2): Likewise.
 107         (VEX_W_0F65_P_2): Likewise.
 108         (VEX_W_0F66_P_2): Likewise.
 109         (VEX_W_0F67_P_2): Likewise.
 110         (VEX_W_0F68_P_2): Likewise.
 111         (VEX_W_0F69_P_2): Likewise.
 112         (VEX_W_0F6A_P_2): Likewise.
 113         (VEX_W_0F6B_P_2): Likewise.
 114         (VEX_W_0F6C_P_2): Likewise.
 115         (VEX_W_0F6D_P_2): Likewise.
 116         (VEX_W_0F6F_P_1): Likewise.
 117         (VEX_W_0F6F_P_2): Likewise.
 118         (VEX_W_0F70_P_1): Likewise.
 119         (VEX_W_0F70_P_2): Likewise.
 120         (VEX_W_0F70_P_3): Likewise.
 121         (VEX_W_0F71_R_2_P_2): Likewise.
 122         (VEX_W_0F71_R_4_P_2): Likewise.
 123         (VEX_W_0F71_R_6_P_2): Likewise.
 124         (VEX_W_0F72_R_2_P_2): Likewise.
 125         (VEX_W_0F72_R_4_P_2): Likewise.
 126         (VEX_W_0F72_R_6_P_2): Likewise.
 127         (VEX_W_0F73_R_2_P_2): Likewise.
 128         (VEX_W_0F73_R_3_P_2): Likewise.
 129         (VEX_W_0F73_R_6_P_2): Likewise.
 130         (VEX_W_0F73_R_7_P_2): Likewise.
 131         (VEX_W_0F74_P_2): Likewise.
 132         (VEX_W_0F75_P_2): Likewise.
 133         (VEX_W_0F76_P_2): Likewise.
 134         (VEX_W_0F77_P_0): Likewise.
 135         (VEX_W_0F7C_P_2): Likewise.
 136         (VEX_W_0F7C_P_3): Likewise.
 137         (VEX_W_0F7D_P_2): Likewise.
 138         (VEX_W_0F7D_P_3): Likewise.
 139         (VEX_W_0F7E_P_1): Likewise.
 140         (VEX_W_0F7F_P_1): Likewise.
 141         (VEX_W_0F7F_P_2): Likewise.
 142         (VEX_W_0FAE_R_2_M_0): Likewise.
 143         (VEX_W_0FAE_R_3_M_0): Likewise.
 144         (VEX_W_0FC2_P_0): Likewise.
 145         (VEX_W_0FC2_P_1): Likewise.
 146         (VEX_W_0FC2_P_2): Likewise.
 147         (VEX_W_0FC2_P_3): Likewise.
 148         (VEX_W_0FD0_P_2): Likewise.
 149         (VEX_W_0FD0_P_3): Likewise.
 150         (VEX_W_0FD1_P_2): Likewise.
 151         (VEX_W_0FD2_P_2): Likewise.
 152         (VEX_W_0FD3_P_2): Likewise.
 153         (VEX_W_0FD4_P_2): Likewise.
 154         (VEX_W_0FD5_P_2): Likewise.
 155         (VEX_W_0FD6_P_2): Likewise.
 156         (VEX_W_0FD7_P_2_M_1): Likewise.
 157         (VEX_W_0FD8_P_2): Likewise.
 158         (VEX_W_0FD9_P_2): Likewise.
 159         (VEX_W_0FDA_P_2): Likewise.
 160         (VEX_W_0FDB_P_2): Likewise.
 161         (VEX_W_0FDC_P_2): Likewise.
 162         (VEX_W_0FDD_P_2): Likewise.
 163         (VEX_W_0FDE_P_2): Likewise.
 164         (VEX_W_0FDF_P_2): Likewise.
 165         (VEX_W_0FE0_P_2): Likewise.
 166         (VEX_W_0FE1_P_2): Likewise.
 167         (VEX_W_0FE2_P_2): Likewise.
 168         (VEX_W_0FE3_P_2): Likewise.
 169         (VEX_W_0FE4_P_2): Likewise.
 170         (VEX_W_0FE5_P_2): Likewise.
 171         (VEX_W_0FE6_P_1): Likewise.
 172         (VEX_W_0FE6_P_2): Likewise.
 173         (VEX_W_0FE6_P_3): Likewise.
 174         (VEX_W_0FE7_P_2_M_0): Likewise.
 175         (VEX_W_0FE8_P_2): Likewise.
 176         (VEX_W_0FE9_P_2): Likewise.
 177         (VEX_W_0FEA_P_2): Likewise.
 178         (VEX_W_0FEB_P_2): Likewise.
 179         (VEX_W_0FEC_P_2): Likewise.
 180         (VEX_W_0FED_P_2): Likewise.
 181         (VEX_W_0FEE_P_2): Likewise.
 182         (VEX_W_0FEF_P_2): Likewise.
 183         (VEX_W_0FF0_P_3_M_0): Likewise.
 184         (VEX_W_0FF1_P_2): Likewise.
 185         (VEX_W_0FF2_P_2): Likewise.
 186         (VEX_W_0FF3_P_2): Likewise.
 187         (VEX_W_0FF4_P_2): Likewise.
 188         (VEX_W_0FF5_P_2): Likewise.
 189         (VEX_W_0FF6_P_2): Likewise.
 190         (VEX_W_0FF7_P_2): Likewise.
 191         (VEX_W_0FF8_P_2): Likewise.
 192         (VEX_W_0FF9_P_2): Likewise.
 193         (VEX_W_0FFA_P_2): Likewise.
 194         (VEX_W_0FFB_P_2): Likewise.
 195         (VEX_W_0FFC_P_2): Likewise.
 196         (VEX_W_0FFD_P_2): Likewise.
 197         (VEX_W_0FFE_P_2): Likewise.
 198         (VEX_W_0F3800_P_2): Likewise.
 199         (VEX_W_0F3801_P_2): Likewise.
 200         (VEX_W_0F3802_P_2): Likewise.
 201         (VEX_W_0F3803_P_2): Likewise.
 202         (VEX_W_0F3804_P_2): Likewise.
 203         (VEX_W_0F3805_P_2): Likewise.
 204         (VEX_W_0F3806_P_2): Likewise.
 205         (VEX_W_0F3807_P_2): Likewise.
 206         (VEX_W_0F3808_P_2): Likewise.
 207         (VEX_W_0F3809_P_2): Likewise.
 208         (VEX_W_0F380A_P_2): Likewise.
 209         (VEX_W_0F380B_P_2): Likewise.
 210         (VEX_W_0F3817_P_2): Likewise.
 211         (VEX_W_0F381C_P_2): Likewise.
 212         (VEX_W_0F381D_P_2): Likewise.
 213         (VEX_W_0F381E_P_2): Likewise.
 214         (VEX_W_0F3820_P_2): Likewise.
 215         (VEX_W_0F3821_P_2): Likewise.
 216         (VEX_W_0F3822_P_2): Likewise.
 217         (VEX_W_0F3823_P_2): Likewise.
 218         (VEX_W_0F3824_P_2): Likewise.
 219         (VEX_W_0F3825_P_2): Likewise.
 220         (VEX_W_0F3828_P_2): Likewise.
 221         (VEX_W_0F3829_P_2): Likewise.
 222         (VEX_W_0F382A_P_2_M_0): Likewise.
 223         (VEX_W_0F382B_P_2): Likewise.
 224         (VEX_W_0F3830_P_2): Likewise.
 225         (VEX_W_0F3831_P_2): Likewise.
 226         (VEX_W_0F3832_P_2): Likewise.
 227         (VEX_W_0F3833_P_2): Likewise.
 228         (VEX_W_0F3834_P_2): Likewise.
 229         (VEX_W_0F3835_P_2): Likewise.
 230         (VEX_W_0F3837_P_2): Likewise.
 231         (VEX_W_0F3838_P_2): Likewise.
 232         (VEX_W_0F3839_P_2): Likewise.
 233         (VEX_W_0F383A_P_2): Likewise.
 234         (VEX_W_0F383B_P_2): Likewise.
 235         (VEX_W_0F383C_P_2): Likewise.
 236         (VEX_W_0F383D_P_2): Likewise.
 237         (VEX_W_0F383E_P_2): Likewise.
 238         (VEX_W_0F383F_P_2): Likewise.
 239         (VEX_W_0F3840_P_2): Likewise.
 240         (VEX_W_0F3841_P_2): Likewise.
 241         (VEX_W_0F38DB_P_2): Likewise.
 242         (VEX_W_0F3A08_P_2): Likewise.
 243         (VEX_W_0F3A09_P_2): Likewise.
 244         (VEX_W_0F3A0A_P_2): Likewise.
 245         (VEX_W_0F3A0B_P_2): Likewise.
 246         (VEX_W_0F3A0C_P_2): Likewise.
 247         (VEX_W_0F3A0D_P_2): Likewise.
 248         (VEX_W_0F3A0E_P_2): Likewise.
 249         (VEX_W_0F3A0F_P_2): Likewise.
 250         (VEX_W_0F3A21_P_2): Likewise.
 251         (VEX_W_0F3A40_P_2): Likewise.
 252         (VEX_W_0F3A41_P_2): Likewise.
 253         (VEX_W_0F3A42_P_2): Likewise.
 254         (VEX_W_0F3A62_P_2): Likewise.
 255         (VEX_W_0F3A63_P_2): Likewise.
 256         (VEX_W_0F3ADF_P_2): Likewise.
 257         (VEX_LEN_0F77_P_0): New.
 258         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 259         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 260         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 261         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 262         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 263         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 264         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 265         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 266         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 267         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 268         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 269         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 270         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 271         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 272         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 273         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 274         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 275         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 276         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 277         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 278         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 279         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 280         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 281         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 282         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 283         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 284         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 285         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 286         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 287         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 288         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 289         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 290         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 291         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 292         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 293         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 294         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 295         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 296         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 297         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 298         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 299         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 300         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 301         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 302         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 303         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 304         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 305         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 306         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 307         (vex_table): Update VEX 0F28 and 0F29 entries.
 308         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 309         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 310         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 311         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 312         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 313         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 314         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 315         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 316         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 317         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 318         VEX_LEN_0F3A0B_P_2 entries.
 319         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 320         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 321         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 322         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 323         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 324         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 325         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 326         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 327         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 328         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 329         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 330         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 331         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 332         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 333         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 334         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 335         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 336         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 337         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 338         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 339         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 340         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 341         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 342         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 343         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 344         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 345         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 346         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 347         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 348         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 349         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 350         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 351         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 352         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 353         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 354         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 355         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 356         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 357         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 358         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 359         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 360         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 361         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 362         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 363         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 364         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 365         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 366         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 367         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 368         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 369         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 370         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 371         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 372         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 373         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 374         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 375         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 376         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 377         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 378         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 379         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 380         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 381         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 382         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 383         VEX_W_0F3ADF_P_2 entries.
 384         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 385         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 386         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 387
 388 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 389
 390         * i386-opc.tbl (VexWIG): New.
 391         Replace VexW=3 with VexWIG.
 392
 393 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 394
 395         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 396         * i386-tbl.h: Regenerated.
 397
 398 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 399
 400         PR gas/23665
 401         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 402         VEX_LEN_0FD6_P_2 entries.
 403         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 404         * i386-tbl.h: Regenerated.
 405
 406 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 407
 408         PR gas/23642
 409         * i386-opc.h (VEXWIG): New.
 410         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 411         * i386-tbl.h: Regenerated.
 412
 413 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         PR binutils/23655
 416         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 417         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 418         * i386-dis.c (EXxEVexR64): New.
 419         (evex_rounding_64_mode): Likewise.
 420         (OP_Rounding): Handle evex_rounding_64_mode.
 421
 422 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 423
 424         PR binutils/23655
 425         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 426         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 427         * i386-dis.c (Edqa): New.
 428         (dqa_mode): Likewise.
 429         (intel_operand_size): Handle dqa_mode as m_mode.
 430         (OP_E_register): Handle dqa_mode as dq_mode.
 431         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 432
 433 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         * i386-dis.c (OP_E_memory): Reformat.
 436
 437 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 438
 439         * i386-opc.tbl (crc32): Fold byte and word forms.
 440         * i386-tbl.h: Re-generate.
 441
 442 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 445         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 446         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 447         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 448         * i386-tbl.h: Regenerated.
 449
 450 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 451
 452         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 453         meaningless.
 454         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 455         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 456         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 457         * i386-tbl.h: Re-generate.
 458
 459 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 462         AVX512_4VNNIW insns.
 463         * i386-tbl.h: Re-generate.
 464
 465 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 466
 467         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 468         meaningless.
 469         * i386-tbl.h: Re-generate.
 470
 471 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 472
 473         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 474         meaningless.
 475         * i386-tbl.h: Re-generate.
 476
 477 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 478
 479         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 480         meaningless.
 481         * i386-tbl.h: Re-generate.
 482
 483 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 484
 485         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 486         meaningless.
 487         * i386-tbl.h: Re-generate.
 488
 489 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 492         meaningless.
 493         * i386-tbl.h: Re-generate.
 494
 495 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 498         * i386-tbl.h: Re-generate.
 499
 500 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 501
 502         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 503         * i386-tbl.h: Re-generate.
 504
 505 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 508         meaningless.
 509         * i386-tbl.h: Re-generate.
 510
 511 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 514         meaningless.
 515         * i386-tbl.h: Re-generate.
 516
 517 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 520         * i386-tbl.h: Re-generate.
 521
 522 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 523
 524         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 525         * i386-tbl.h: Re-generate.
 526
 527 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 528
 529         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 530         * i386-tbl.h: Re-generate.
 531
 532 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 533
 534         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 535         meaningless.
 536         * i386-tbl.h: Re-generate.
 537
 538 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 541         meaningless.
 542         * i386-tbl.h: Re-generate.
 543
 544 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 545
 546         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 547         meaningless.
 548         * i386-tbl.h: Re-generate.
 549
 550 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 551
 552         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 553         * i386-tbl.h: Re-generate.
 554
 555 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 556
 557         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 558         * i386-tbl.h: Re-generate.
 559
 560 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 561
 562         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 563         * i386-tbl.h: Re-generate.
 564
 565 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 566
 567         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 568         (vpbroadcastw, rdpid): Drop NoRex64.
 569         * i386-tbl.h: Re-generate.
 570
 571 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 574         store templates, adding D.
 575         * i386-tbl.h: Re-generate.
 576
 577 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 578
 579         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 580         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 581         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 582         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 583         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 584         Fold load and store templates where possible, adding D. Drop
 585         IgnoreSize where it was pointlessly present. Drop redundant
 586         *word.
 587         * i386-tbl.h: Re-generate.
 588
 589 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 590
 591         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 592         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 593         (intel_operand_size): Handle v_bndmk_mode.
 594         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 595
 596 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 597
 598         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 599
 600 2018-08-31  Kito Cheng  <kito@andestech.com>
 601
 602         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 603         compressed floating point instructions.
 604
 605 2018-08-30  Kito Cheng  <kito@andestech.com>
 606
 607         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 608         riscv_opcode.xlen_requirement.
 609         * riscv-opc.c (riscv_opcodes): Update for struct change.
 610
 611 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 612
 613         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 614         psr (PWRPSR) instruction.
 615
 616 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 617
 618         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 619
 620 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 621
 622         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 623
 624 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 625
 626         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 627         loongson3a as an alias of gs464 for compatibility.
 628         * mips-opc.c (mips_opcodes): Change Comments.
 629
 630 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 631
 632         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 633         option.
 634         (print_mips_disassembler_options): Document -M loongson-ext.
 635         * mips-opc.c (LEXT2): New macro.
 636         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 637
 638 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 639
 640          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 641          descriptors.
 642          (parse_mips_ase_option): Handle -M loongson-ext option.
 643          (print_mips_disassembler_options): Document -M loongson-ext.
 644          * mips-opc.c (IL3A): Delete.
 645          * mips-opc.c (LEXT): New macro.
 646          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 647          instructions.
 648
 649 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 650
 651         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 652         descriptors.
 653         (parse_mips_ase_option): Handle -M loongson-cam option.
 654         (print_mips_disassembler_options): Document -M loongson-cam.
 655         * mips-opc.c (LCAM): New macro.
 656         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 657         instructions.
 658
 659 2018-08-21  Alan Modra  <amodra@gmail.com>
 660
 661         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 662         (skip_optional_operands): Count optional operands, and update
 663         ppc_optional_operand_value call.
 664         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 665         (extract_vlensi): Likewise.
 666         (extract_fxm): Return default value for missing optional operand.
 667         (extract_ls, extract_raq, extract_tbr): Likewise.
 668         (insert_sxl, extract_sxl): New functions.
 669         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 670         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 671         flag and extra entry.
 672         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 673         extract_sxl.
 674
 675 2018-08-20  Alan Modra  <amodra@gmail.com>
 676
 677         * sh-opc.h (MASK): Simplify.
 678
 679 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 680
 681         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 682         BM_RESERVED0 or BM_RESERVED1
 683         (bm_rel_decode, bm_n_bytes): Ditto.
 684
 685 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 686
 687         * s12z.h: Delete.
 688
 689 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 690
 691         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 692         address with the addr32 prefix and without base nor index
 693         registers.
 694
 695 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 696
 697         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 698         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 699         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 700         (cpu_flags): Add CpuCMOV and CpuFXSR.
 701         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 702         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 703         * i386-init.h: Regenerated.
 704         * i386-tbl.h: Likewise.
 705
 706 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 707
 708         * arc-regs.h: Update auxiliary registers.
 709
 710 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 713         (RegIP, RegIZ): Define.
 714         * i386-reg.tbl: Adjust comments.
 715         (rip): Use Qword instead of BaseIndex. Use RegIP.
 716         (eip): Use Dword instead of BaseIndex. Use RegIP.
 717         (riz): Add Qword. Use RegIZ.
 718         (eiz): Add Dword. Use RegIZ.
 719         * i386-tbl.h: Re-generate.
 720
 721 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 722
 723         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 724         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 725         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 726         * i386-tbl.h: Re-generate.
 727
 728 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-gen.c (operand_types): Remove Mem field.
 731         * i386-opc.h (union i386_operand_type): Remove mem field.
 732         * i386-init.h, i386-tbl.h: Re-generate.
 733
 734 2018-08-01  Alan Modra  <amodra@gmail.com>
 735
 736         * po/POTFILES.in: Regenerate.
 737
 738 2018-07-31  Nick Clifton  <nickc@redhat.com>
 739
 740         * po/sv.po: Updated Swedish translation.
 741
 742 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 745         * i386-init.h, i386-tbl.h: Re-generate.
 746
 747 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 748
 749         * i386-opc.h (ZEROING_MASKING) Rename to ...
 750         (DYNAMIC_MASKING): ... this. Adjust comment.
 751         * i386-opc.tbl (MaskingMorZ): Define.
 752         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 753         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 754         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 755         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 756         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 757         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 758         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 759         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 760         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 761
 762 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 763
 764         * i386-opc.tbl: Use element rather than vector size for AVX512*
 765         scatter/gather insns.
 766         * i386-tbl.h: Re-generate.
 767
 768 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 769
 770         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 771         (cpu_flags): Drop CpuVREX.
 772         * i386-opc.h (CpuVREX): Delete.
 773         (union i386_cpu_flags): Remove cpuvrex.
 774         * i386-init.h, i386-tbl.h: Re-generate.
 775
 776 2018-07-30  Jim Wilson  <jimw@sifive.com>
 777
 778         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 779         fields.
 780         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 781
 782 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 783
 784         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 785         * Makefile.in: Regenerated.
 786         * configure.ac: Add C-SKY.
 787         * configure: Regenerated.
 788         * csky-dis.c: New file.
 789         * csky-opc.h: New file.
 790         * disassemble.c (ARCH_csky): Define.
 791         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 792         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 793
 794 2018-07-27  Alan Modra  <amodra@gmail.com>
 795
 796         * ppc-opc.c (insert_sprbat): Correct function parameter and
 797         return type.
 798         (extract_sprbat): Likewise, variable too.
 799
 800 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 801             Alan Modra  <amodra@gmail.com>
 802
 803         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 804         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 805         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 806         support disjointed BAT.
 807         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 808         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 809         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 810
 811 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 812             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 813
 814         * i386-gen.c (adjust_broadcast_modifier): New function.
 815         (process_i386_opcode_modifier): Add an argument for operands.
 816         Adjust the Broadcast value based on operands.
 817         (output_i386_opcode): Pass operand_types to
 818         process_i386_opcode_modifier.
 819         (process_i386_opcodes): Pass NULL as operands to
 820         process_i386_opcode_modifier.
 821         * i386-opc.h (BYTE_BROADCAST): New.
 822         (WORD_BROADCAST): Likewise.
 823         (DWORD_BROADCAST): Likewise.
 824         (QWORD_BROADCAST): Likewise.
 825         (i386_opcode_modifier): Expand broadcast to 3 bits.
 826         * i386-tbl.h: Regenerated.
 827
 828 2018-07-24  Alan Modra  <amodra@gmail.com>
 829
 830         PR 23430
 831         * or1k-desc.h: Regenerate.
 832
 833 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 834
 835         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 836         vcvtusi2ss, and vcvtusi2sd.
 837         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 838         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 839         * i386-tbl.h: Re-generate.
 840
 841 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 842
 843         * arc-opc.c (extract_w6): Fix extending the sign.
 844
 845 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 846
 847         * arc-tbl.h (vewt): Allow it for ARC EM family.
 848
 849 2018-07-23  Alan Modra  <amodra@gmail.com>
 850
 851         PR 23419
 852         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 853         opcode variants for mtspr/mfspr encodings.
 854
 855 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 856             Maciej W. Rozycki  <macro@mips.com>
 857
 858         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 859         loongson3a descriptors.
 860         (parse_mips_ase_option): Handle -M loongson-mmi option.
 861         (print_mips_disassembler_options): Document -M loongson-mmi.
 862         * mips-opc.c (LMMI): New macro.
 863         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 864         instructions.
 865
 866 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 869         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 870         IgnoreSize and [XYZ]MMword where applicable.
 871         * i386-tbl.h: Re-generate.
 872
 873 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 874
 875         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 876         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 877         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 878         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 879         * i386-tbl.h: Re-generate.
 880
 881 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 882
 883         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 884         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 885         VPCLMULQDQ templates into their respective AVX512VL counterparts
 886         where possible, using Disp8ShiftVL and CheckRegSize instead of
 887         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 888         * i386-tbl.h: Re-generate.
 889
 890 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 891
 892         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 893         AVX512VL counterparts where possible, using Disp8ShiftVL and
 894         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 895         IgnoreSize) as appropriate.
 896         * i386-tbl.h: Re-generate.
 897
 898 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 899
 900         * i386-opc.tbl: Fold AVX512BW templates into their respective
 901         AVX512VL counterparts where possible, using Disp8ShiftVL and
 902         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 903         IgnoreSize) as appropriate.
 904         * i386-tbl.h: Re-generate.
 905
 906 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 907
 908         * i386-opc.tbl: Fold AVX512CD templates into their respective
 909         AVX512VL counterparts where possible, using Disp8ShiftVL and
 910         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 911         IgnoreSize) as appropriate.
 912         * i386-tbl.h: Re-generate.
 913
 914 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 915
 916         * i386-opc.h (DISP8_SHIFT_VL): New.
 917         * i386-opc.tbl (Disp8ShiftVL):  Define.
 918         (various): Fold AVX512VL templates into their respective
 919         AVX512F counterparts where possible, using Disp8ShiftVL and
 920         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 921         IgnoreSize) as appropriate.
 922         * i386-tbl.h: Re-generate.
 923
 924 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 925
 926         * Makefile.am: Change dependencies and rule for
 927         $(srcdir)/i386-init.h.
 928         * Makefile.in: Re-generate.
 929         * i386-gen.c (process_i386_opcodes): New local variable
 930         "marker". Drop opening of input file. Recognize marker and line
 931         number directives.
 932         * i386-opc.tbl (OPCODE_I386_H): Define.
 933         (i386-opc.h): Include it.
 934         (None): Undefine.
 935
 936 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 937
 938         PR gas/23418
 939         * i386-opc.h (Byte): Update comments.
 940         (Word): Likewise.
 941         (Dword): Likewise.
 942         (Fword): Likewise.
 943         (Qword): Likewise.
 944         (Tbyte): Likewise.
 945         (Xmmword): Likewise.
 946         (Ymmword): Likewise.
 947         (Zmmword): Likewise.
 948         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 949         vcvttps2uqq.
 950         * i386-tbl.h: Regenerated.
 951
 952 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 953
 954         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 955         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 956         * aarch64-asm-2.c: Regenerate.
 957         * aarch64-dis-2.c: Regenerate.
 958         * aarch64-opc-2.c: Regenerate.
 959
 960 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 961
 962         PR binutils/23192
 963         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 964         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 965         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 966         sqdmulh, sqrdmulh): Use Em16.
 967
 968 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 969
 970         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 971         csdb together with them.
 972         (thumb32_opcodes): Likewise.
 973
 974 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 975
 976         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 977         requiring 32-bit registers as operands 2 and 3. Improve
 978         comments.
 979         (mwait, mwaitx): Fold templates. Improve comments.
 980         OPERAND_TYPE_INOUTPORTREG.
 981         * i386-tbl.h: Re-generate.
 982
 983 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-gen.c (operand_type_init): Remove
 986         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 987         OPERAND_TYPE_INOUTPORTREG.
 988         * i386-init.h: Re-generate.
 989
 990 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 991
 992         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 993         (wrssq, wrussq): Add Qword.
 994         * i386-tbl.h: Re-generate.
 995
 996 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 997
 998         * i386-opc.h: Rename OTMax to OTNum.
 999         (OTNumOfUints): Adjust calculation.
1000         (OTUnused): Directly alias to OTNum.
1001
1002 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1003
1004         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1005         `reg_xys'.
1006         (lea_reg_xys): Likewise.
1007         (print_insn_loop_primitive): Rename `reg' local variable to
1008         `reg_dxy'.
1009
1010 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1011
1012         PR binutils/23242
1013         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1014
1015 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1016
1017         PR binutils/23369
1018         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1019         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1020
1021 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1022
1023         PR tdep/8282
1024         * mips-dis.c (mips_option_arg_t): New enumeration.
1025         (mips_options): New variable.
1026         (disassembler_options_mips): New function.
1027         (print_mips_disassembler_options): Reimplement in terms of
1028         `disassembler_options_mips'.
1029         * arm-dis.c (disassembler_options_arm): Adapt to using the
1030         `disasm_options_and_args_t' structure.
1031         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1032         * s390-dis.c (disassembler_options_s390): Likewise.
1033
1034 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1035
1036         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1037         expected result.
1038         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1039         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1040         * testsuite/ld-arm/tls-longplt.d: Likewise.
1041
1042 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1043
1044         PR binutils/23192
1045         * aarch64-asm-2.c: Regenerate.
1046         * aarch64-dis-2.c: Likewise.
1047         * aarch64-opc-2.c: Likewise.
1048         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1049         * aarch64-opc.c (operand_general_constraint_met_p,
1050         aarch64_print_operand): Likewise.
1051         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1052         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1053         fmlal2, fmlsl2.
1054         (AARCH64_OPERANDS): Add Em2.
1055
1056 2018-06-26  Nick Clifton  <nickc@redhat.com>
1057
1058         * po/uk.po: Updated Ukranian translation.
1059         * po/de.po: Updated German translation.
1060         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1061
1062 2018-06-26  Nick Clifton  <nickc@redhat.com>
1063
1064         * nfp-dis.c: Fix spelling mistake.
1065
1066 2018-06-24  Nick Clifton  <nickc@redhat.com>
1067
1068         * configure: Regenerate.
1069         * po/opcodes.pot: Regenerate.
1070
1071 2018-06-24  Nick Clifton  <nickc@redhat.com>
1072
1073         2.31 branch created.
1074
1075 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1076
1077         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1078         * aarch64-asm-2.c: Regenerate.
1079         * aarch64-dis-2.c: Likewise.
1080
1081 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1082
1083         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1084         `-M ginv' option description.
1085
1086 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1087
1088         PR gas/23305
1089         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1090         la and lla.
1091
1092 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1093
1094         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1095         * configure.ac: Remove AC_PREREQ.
1096         * Makefile.in: Re-generate.
1097         * aclocal.m4: Re-generate.
1098         * configure: Re-generate.
1099
1100 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1101
1102         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1103         mips64r6 descriptors.
1104         (parse_mips_ase_option): Handle -Mginv option.
1105         (print_mips_disassembler_options): Document -Mginv.
1106         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1107         (GINV): New macro.
1108         (mips_opcodes): Define ginvi and ginvt.
1109
1110 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1111             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1112
1113         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1114         * mips-opc.c (CRC, CRC64): New macros.
1115         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1116         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1117         crc32cd for CRC64.
1118
1119 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1120
1121         PR 20319
1122         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1123         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1124
1125 2018-06-06  Alan Modra  <amodra@gmail.com>
1126
1127         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1128         setjmp.  Move init for some other vars later too.
1129
1130 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1131
1132         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1133         (dis_private): Add new fields for property section tracking.
1134         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1135         (xtensa_instruction_fits): New functions.
1136         (fetch_data): Bump minimal fetch size to 4.
1137         (print_insn_xtensa): Make struct dis_private static.
1138         Load and prepare property table on section change.
1139         Don't disassemble literals. Don't disassemble instructions that
1140         cross property table boundaries.
1141
1142 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1143
1144         * configure: Regenerated.
1145
1146 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1147
1148         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1149         * i386-tbl.h: Re-generate.
1150
1151 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-opc.tbl (sldt, str): Add NoRex64.
1154         * i386-tbl.h: Re-generate.
1155
1156 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1157
1158         * i386-opc.tbl (invpcid): Add Oword.
1159         * i386-tbl.h: Re-generate.
1160
1161 2018-06-01  Alan Modra  <amodra@gmail.com>
1162
1163         * sysdep.h (_bfd_error_handler): Don't declare.
1164         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1165         * rl78-decode.opc: Likewise.
1166         * msp430-decode.c: Regenerate.
1167         * rl78-decode.c: Regenerate.
1168
1169 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1170
1171         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1172         * i386-init.h : Regenerated.
1173
1174 2018-05-25  Alan Modra  <amodra@gmail.com>
1175
1176         * Makefile.in: Regenerate.
1177         * po/POTFILES.in: Regenerate.
1178
1179 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1180
1181         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1182         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1183         (insert_bab, extract_bab, insert_btab, extract_btab,
1184         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1185         (BAT, BBA VBA RBS XB6S): Delete macros.
1186         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1187         (BB, BD, RBX, XC6): Update for new macros.
1188         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1189         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1190         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1191         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1192
1193 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1194
1195         * Makefile.am: Add support for s12z architecture.
1196         * configure.ac: Likewise.
1197         * disassemble.c: Likewise.
1198         * disassemble.h: Likewise.
1199         * Makefile.in: Regenerate.
1200         * configure: Regenerate.
1201         * s12z-dis.c: New file.
1202         * s12z.h: New file.
1203
1204 2018-05-18  Alan Modra  <amodra@gmail.com>
1205
1206         * nfp-dis.c: Don't #include libbfd.h.
1207         (init_nfp3200_priv): Use bfd_get_section_contents.
1208         (nit_nfp6000_mecsr_sec): Likewise.
1209
1210 2018-05-17  Nick Clifton  <nickc@redhat.com>
1211
1212         * po/zh_CN.po: Updated simplified Chinese translation.
1213
1214 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1215
1216         PR binutils/23109
1217         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1218         * aarch64-dis-2.c: Regenerate.
1219
1220 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1221
1222         PR binutils/21446
1223         * aarch64-asm.c (opintl.h): Include.
1224         (aarch64_ins_sysreg): Enforce read/write constraints.
1225         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1226         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1227         (F_REG_READ, F_REG_WRITE): New.
1228         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1229         AARCH64_OPND_SYSREG.
1230         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1231         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1232         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1233         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1234         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1235         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1236         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1237         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1238         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1239         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1240         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1241         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1242         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1243         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1244         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1245         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1246         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1247
1248 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1249
1250         PR binutils/21446
1251         * aarch64-dis.c (no_notes: New.
1252         (parse_aarch64_dis_option): Support notes.
1253         (aarch64_decode_insn, print_operands): Likewise.
1254         (print_aarch64_disassembler_options): Document notes.
1255         * aarch64-opc.c (aarch64_print_operand): Support notes.
1256
1257 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1258
1259         PR binutils/21446
1260         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1261         and take error struct.
1262         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1263         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1264         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1265         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1266         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1267         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1268         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1269         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1270         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1271         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1272         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1273         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1274         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1275         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1276         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1277         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1278         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1279         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1280         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1281         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1282         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1283         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1284         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1285         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1286         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1287         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1288         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1289         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1290         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1291         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1292         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1293         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1294         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1295         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1296         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1297         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1298         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1299         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1300         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1301         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1302         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1303         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1304         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1305         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1306         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1307         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1308         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1309         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1310         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1311         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1312         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1313         (determine_disassembling_preference, aarch64_decode_insn,
1314         print_insn_aarch64_word, print_insn_data): Take errors struct.
1315         (print_insn_aarch64): Use errors.
1316         * aarch64-asm-2.c: Regenerate.
1317         * aarch64-dis-2.c: Regenerate.
1318         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1319         boolean in aarch64_insert_operan.
1320         (print_operand_extractor): Likewise.
1321         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1322
1323 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1324
1325         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1326
1327 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1328
1329         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1330
1331 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1332
1333         * cr16-opc.c (cr16_instruction): Comment typo fix.
1334         * hppa-dis.c (print_insn_hppa): Likewise.
1335
1336 2018-05-08  Jim Wilson  <jimw@sifive.com>
1337
1338         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1339         (match_c_slli64, match_srxi_as_c_srxi): New.
1340         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1341         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1342         <c.slli, c.srli, c.srai>: Use match_s_slli.
1343         <c.slli64, c.srli64, c.srai64>: New.
1344
1345 2018-05-08  Alan Modra  <amodra@gmail.com>
1346
1347         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1348         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1349         partition opcode space for index lookup.
1350
1351 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1352
1353         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1354         <insn_length>: ...with this.  Update usage.
1355         Remove duplicate call to *info->memory_error_func.
1356
1357 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1358             H.J. Lu  <hongjiu.lu@intel.com>
1359
1360         * i386-dis.c (Gva): New.
1361         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1362         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1363         (prefix_table): New instructions (see prefix above).
1364         (mod_table): New instructions (see prefix above).
1365         (OP_G): Handle va_mode.
1366         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1367         CPU_MOVDIR64B_FLAGS.
1368         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1369         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1370         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1371         * i386-opc.tbl: Add movidir{i,64b}.
1372         * i386-init.h: Regenerated.
1373         * i386-tbl.h: Likewise.
1374
1375 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1376
1377         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1378         AddrPrefixOpReg.
1379         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1380         (AddrPrefixOpReg): This.
1381         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1382         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1383
1384 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1385
1386         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1387         (vle_num_opcodes): Likewise.
1388         (spe2_num_opcodes): Likewise.
1389         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1390         initialization loop.
1391         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1392         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1393         only once.
1394
1395 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1396
1397         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1398
1399 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1400
1401         Makefile.am: Added nfp-dis.c.
1402         configure.ac: Added bfd_nfp_arch.
1403         disassemble.h: Added print_insn_nfp prototype.
1404         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1405         nfp-dis.c: New, for NFP support.
1406         po/POTFILES.in: Added nfp-dis.c to the list.
1407         Makefile.in: Regenerate.
1408         configure: Regenerate.
1409
1410 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1411
1412         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1413         templates into their base ones.
1414         * i386-tlb.h: Re-generate.
1415
1416 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1417
1418         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1419         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1420         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1421         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1422         * i386-init.h: Re-generate.
1423
1424 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1425
1426         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1427         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1428         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1429         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1430         comment.
1431         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1432         and CpuRegMask.
1433         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1434         CpuRegMask: Delete.
1435         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1436         cpuregzmm, and cpuregmask.
1437         * i386-init.h: Re-generate.
1438         * i386-tbl.h: Re-generate.
1439
1440 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1441
1442         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1443         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1444         * i386-init.h: Re-generate.
1445
1446 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1447
1448         * i386-gen.c (VexImmExt): Delete.
1449         * i386-opc.h (VexImmExt, veximmext): Delete.
1450         * i386-opc.tbl: Drop all VexImmExt uses.
1451         * i386-tlb.h: Re-generate.
1452
1453 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1454
1455         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1456         register-only forms.
1457         * i386-tlb.h: Re-generate.
1458
1459 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1460
1461         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1462
1463 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1464
1465         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1466         PREFIX_0F1C.
1467         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1468         (cpu_flags): Add CpuCLDEMOTE.
1469         * i386-init.h: Regenerate.
1470         * i386-opc.h (enum): Add CpuCLDEMOTE,
1471         (i386_cpu_flags): Add cpucldemote.
1472         * i386-opc.tbl: Add cldemote.
1473         * i386-tbl.h: Regenerate.
1474
1475 2018-04-16  Alan Modra  <amodra@gmail.com>
1476
1477         * Makefile.am: Remove sh5 and sh64 support.
1478         * configure.ac: Likewise.
1479         * disassemble.c: Likewise.
1480         * disassemble.h: Likewise.
1481         * sh-dis.c: Likewise.
1482         * sh64-dis.c: Delete.
1483         * sh64-opc.c: Delete.
1484         * sh64-opc.h: Delete.
1485         * Makefile.in: Regenerate.
1486         * configure: Regenerate.
1487         * po/POTFILES.in: Regenerate.
1488
1489 2018-04-16  Alan Modra  <amodra@gmail.com>
1490
1491         * Makefile.am: Remove w65 support.
1492         * configure.ac: Likewise.
1493         * disassemble.c: Likewise.
1494         * disassemble.h: Likewise.
1495         * w65-dis.c: Delete.
1496         * w65-opc.h: Delete.
1497         * Makefile.in: Regenerate.
1498         * configure: Regenerate.
1499         * po/POTFILES.in: Regenerate.
1500
1501 2018-04-16  Alan Modra  <amodra@gmail.com>
1502
1503         * configure.ac: Remove we32k support.
1504         * configure: Regenerate.
1505
1506 2018-04-16  Alan Modra  <amodra@gmail.com>
1507
1508         * Makefile.am: Remove m88k support.
1509         * configure.ac: Likewise.
1510         * disassemble.c: Likewise.
1511         * disassemble.h: Likewise.
1512         * m88k-dis.c: Delete.
1513         * Makefile.in: Regenerate.
1514         * configure: Regenerate.
1515         * po/POTFILES.in: Regenerate.
1516
1517 2018-04-16  Alan Modra  <amodra@gmail.com>
1518
1519         * Makefile.am: Remove i370 support.
1520         * configure.ac: Likewise.
1521         * disassemble.c: Likewise.
1522         * disassemble.h: Likewise.
1523         * i370-dis.c: Delete.
1524         * i370-opc.c: Delete.
1525         * Makefile.in: Regenerate.
1526         * configure: Regenerate.
1527         * po/POTFILES.in: Regenerate.
1528
1529 2018-04-16  Alan Modra  <amodra@gmail.com>
1530
1531         * Makefile.am: Remove h8500 support.
1532         * configure.ac: Likewise.
1533         * disassemble.c: Likewise.
1534         * disassemble.h: Likewise.
1535         * h8500-dis.c: Delete.
1536         * h8500-opc.h: Delete.
1537         * Makefile.in: Regenerate.
1538         * configure: Regenerate.
1539         * po/POTFILES.in: Regenerate.
1540
1541 2018-04-16  Alan Modra  <amodra@gmail.com>
1542
1543         * configure.ac: Remove tahoe support.
1544         * configure: Regenerate.
1545
1546 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1547
1548         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1549         umwait.
1550         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1551         64-bit mode.
1552         * i386-tbl.h: Regenerated.
1553
1554 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1555
1556         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1557         PREFIX_MOD_1_0FAE_REG_6.
1558         (va_mode): New.
1559         (OP_E_register): Use va_mode.
1560         * i386-dis-evex.h (prefix_table):
1561         New instructions (see prefixes above).
1562         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1563         (cpu_flags): Likewise.
1564         * i386-opc.h (enum): Likewise.
1565         (i386_cpu_flags): Likewise.
1566         * i386-opc.tbl: Add umonitor, umwait, tpause.
1567         * i386-init.h: Regenerate.
1568         * i386-tbl.h: Likewise.
1569
1570 2018-04-11  Alan Modra  <amodra@gmail.com>
1571
1572         * opcodes/i860-dis.c: Delete.
1573         * opcodes/i960-dis.c: Delete.
1574         * Makefile.am: Remove i860 and i960 support.
1575         * configure.ac: Likewise.
1576         * disassemble.c: Likewise.
1577         * disassemble.h: Likewise.
1578         * Makefile.in: Regenerate.
1579         * configure: Regenerate.
1580         * po/POTFILES.in: Regenerate.
1581
1582 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1583
1584         PR binutils/23025
1585         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1586         to 0.
1587         (print_insn): Clear vex instead of vex.evex.
1588
1589 2018-04-04  Nick Clifton  <nickc@redhat.com>
1590
1591         * po/es.po: Updated Spanish translation.
1592
1593 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1594
1595         * i386-gen.c (opcode_modifiers): Delete VecESize.
1596         * i386-opc.h (VecESize): Delete.
1597         (struct i386_opcode_modifier): Delete vecesize.
1598         * i386-opc.tbl: Drop VecESize.
1599         * i386-tlb.h: Re-generate.
1600
1601 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1602
1603         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1604         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1605         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1606         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1607         * i386-tlb.h: Re-generate.
1608
1609 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1610
1611         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1612         Fold AVX512 forms
1613         * i386-tlb.h: Re-generate.
1614
1615 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1616
1617         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1618         (vex_len_table): Drop Y for vcvt*2si.
1619         (putop): Replace plain 'Y' handling by abort().
1620
1621 2018-03-28  Nick Clifton  <nickc@redhat.com>
1622
1623         PR 22988
1624         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1625         instructions with only a base address register.
1626         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1627         handle AARHC64_OPND_SVE_ADDR_R.
1628         (aarch64_print_operand): Likewise.
1629         * aarch64-asm-2.c: Regenerate.
1630         * aarch64_dis-2.c: Regenerate.
1631         * aarch64-opc-2.c: Regenerate.
1632
1633 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1634
1635         * i386-opc.tbl: Drop VecESize from register only insn forms and
1636         memory forms not allowing broadcast.
1637         * i386-tlb.h: Re-generate.
1638
1639 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1640
1641         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1642         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1643         sha256*): Drop Disp<N>.
1644
1645 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1646
1647         * i386-dis.c (EbndS, bnd_swap_mode): New.
1648         (prefix_table): Use EbndS.
1649         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1650         * i386-opc.tbl (bndmov): Move misplaced Load.
1651         * i386-tlb.h: Re-generate.
1652
1653 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1654
1655         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1656         templates allowing memory operands and folded ones for register
1657         only flavors.
1658         * i386-tlb.h: Re-generate.
1659
1660 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1661
1662         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1663         256-bit templates. Drop redundant leftover Disp<N>.
1664         * i386-tlb.h: Re-generate.
1665
1666 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1667
1668         * riscv-opc.c (riscv_insn_types): New.
1669
1670 2018-03-13  Nick Clifton  <nickc@redhat.com>
1671
1672         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1673
1674 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1675
1676         * i386-opc.tbl: Add Optimize to clr.
1677         * i386-tbl.h: Regenerated.
1678
1679 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1680
1681         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1682         * i386-opc.h (OldGcc): Removed.
1683         (i386_opcode_modifier): Remove oldgcc.
1684         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1685         instructions for old (<= 2.8.1) versions of gcc.
1686         * i386-tbl.h: Regenerated.
1687
1688 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1689
1690         * i386-opc.h (EVEXDYN): New.
1691         * i386-opc.tbl: Fold various AVX512VL templates.
1692         * i386-tlb.h: Re-generate.
1693
1694 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1695
1696         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1697         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1698         vpexpandd, vpexpandq): Fold AFX512VF templates.
1699         * i386-tlb.h: Re-generate.
1700
1701 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1702
1703         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1704         Fold 128- and 256-bit VEX-encoded templates.
1705         * i386-tlb.h: Re-generate.
1706
1707 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1708
1709         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1710         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1711         vpexpandd, vpexpandq): Fold AVX512F templates.
1712         * i386-tlb.h: Re-generate.
1713
1714 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1715
1716         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1717         64-bit templates. Drop Disp<N>.
1718         * i386-tlb.h: Re-generate.
1719
1720 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1721
1722         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1723         and 256-bit templates.
1724         * i386-tlb.h: Re-generate.
1725
1726 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1727
1728         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1729         * i386-tlb.h: Re-generate.
1730
1731 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1732
1733         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1734         Drop NoAVX.
1735         * i386-tlb.h: Re-generate.
1736
1737 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1738
1739         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1740         * i386-tlb.h: Re-generate.
1741
1742 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1743
1744         * i386-gen.c (opcode_modifiers): Delete FloatD.
1745         * i386-opc.h (FloatD): Delete.
1746         (struct i386_opcode_modifier): Delete floatd.
1747         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1748         FloatD by D.
1749         * i386-tlb.h: Re-generate.
1750
1751 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1752
1753         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1754
1755 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1756
1757         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1758         * i386-tlb.h: Re-generate.
1759
1760 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1761
1762         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1763         forms.
1764         * i386-tlb.h: Re-generate.
1765
1766 2018-03-07  Alan Modra  <amodra@gmail.com>
1767
1768         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1769         bfd_arch_rs6000.
1770         * disassemble.h (print_insn_rs6000): Delete.
1771         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1772         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1773         (print_insn_rs6000): Delete.
1774
1775 2018-03-03  Alan Modra  <amodra@gmail.com>
1776
1777         * sysdep.h (opcodes_error_handler): Define.
1778         (_bfd_error_handler): Declare.
1779         * Makefile.am: Remove stray #.
1780         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1781         EDIT" comment.
1782         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1783         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1784         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1785         opcodes_error_handler to print errors.  Standardize error messages.
1786         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1787         and include opintl.h.
1788         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1789         * i386-gen.c: Standardize error messages.
1790         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1791         * Makefile.in: Regenerate.
1792         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1793         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1794         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1795         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1796         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1797         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1798         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1799         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1800         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1801         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1802         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1803         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1804         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1805
1806 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1807
1808         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1809         vpsub[bwdq] instructions.
1810         * i386-tbl.h: Regenerated.
1811
1812 2018-03-01  Alan Modra  <amodra@gmail.com>
1813
1814         * configure.ac (ALL_LINGUAS): Sort.
1815         * configure: Regenerate.
1816
1817 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1818
1819         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1820         macro by assignements.
1821
1822 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1823
1824         PR gas/22871
1825         * i386-gen.c (opcode_modifiers): Add Optimize.
1826         * i386-opc.h (Optimize): New enum.
1827         (i386_opcode_modifier): Add optimize.
1828         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1829         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1830         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1831         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1832         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1833         vpxord and vpxorq.
1834         * i386-tbl.h: Regenerated.
1835
1836 2018-02-26  Alan Modra  <amodra@gmail.com>
1837
1838         * crx-dis.c (getregliststring): Allocate a large enough buffer
1839         to silence false positive gcc8 warning.
1840
1841 2018-02-22  Shea Levy <shea@shealevy.com>
1842
1843         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1844
1845 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1846
1847         * i386-opc.tbl: Add {rex},
1848         * i386-tbl.h: Regenerated.
1849
1850 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1851
1852         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1853         (mips16_opcodes): Replace `M' with `m' for "restore".
1854
1855 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1856
1857         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1858
1859 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1860
1861         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1862         variable to `function_index'.
1863
1864 2018-02-13  Nick Clifton  <nickc@redhat.com>
1865
1866         PR 22823
1867         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1868         about truncation of printing.
1869
1870 2018-02-12  Henry Wong <henry@stuffedcow.net>
1871
1872         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1873
1874 2018-02-05  Nick Clifton  <nickc@redhat.com>
1875
1876         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1877
1878 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1879
1880         * i386-dis.c (enum): Add pconfig.
1881         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1882         (cpu_flags): Add CpuPCONFIG.
1883         * i386-opc.h (enum): Add CpuPCONFIG.
1884         (i386_cpu_flags): Add cpupconfig.
1885         * i386-opc.tbl: Add PCONFIG instruction.
1886         * i386-init.h: Regenerate.
1887         * i386-tbl.h: Likewise.
1888
1889 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1890
1891         * i386-dis.c (enum): Add PREFIX_0F09.
1892         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1893         (cpu_flags): Add CpuWBNOINVD.
1894         * i386-opc.h (enum): Add CpuWBNOINVD.
1895         (i386_cpu_flags): Add cpuwbnoinvd.
1896         * i386-opc.tbl: Add WBNOINVD instruction.
1897         * i386-init.h: Regenerate.
1898         * i386-tbl.h: Likewise.
1899
1900 2018-01-17  Jim Wilson  <jimw@sifive.com>
1901
1902         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1903
1904 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1905
1906         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1907         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1908         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1909         (cpu_flags): Add CpuIBT, CpuSHSTK.
1910         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1911         (i386_cpu_flags): Add cpuibt, cpushstk.
1912         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1913         * i386-init.h: Regenerate.
1914         * i386-tbl.h: Likewise.
1915
1916 2018-01-16  Nick Clifton  <nickc@redhat.com>
1917
1918         * po/pt_BR.po: Updated Brazilian Portugese translation.
1919         * po/de.po: Updated German translation.
1920
1921 2018-01-15  Jim Wilson  <jimw@sifive.com>
1922
1923         * riscv-opc.c (match_c_nop): New.
1924         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1925
1926 2018-01-15  Nick Clifton  <nickc@redhat.com>
1927
1928         * po/uk.po: Updated Ukranian translation.
1929
1930 2018-01-13  Nick Clifton  <nickc@redhat.com>
1931
1932         * po/opcodes.pot: Regenerated.
1933
1934 2018-01-13  Nick Clifton  <nickc@redhat.com>
1935
1936         * configure: Regenerate.
1937
1938 2018-01-13  Nick Clifton  <nickc@redhat.com>
1939
1940         2.30 branch created.
1941
1942 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1943
1944         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1945         * i386-tbl.h: Regenerate.
1946
1947 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1948
1949         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1950         * i386-tbl.h: Re-generate.
1951
1952 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1953
1954         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1955         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1956         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1957         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1958         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1959         Disp8MemShift of AVX512VL forms.
1960         * i386-tbl.h: Re-generate.
1961
1962 2018-01-09  Jim Wilson  <jimw@sifive.com>
1963
1964         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1965         then the hi_addr value is zero.
1966
1967 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1968
1969         * arm-dis.c (arm_opcodes): Add csdb.
1970         (thumb32_opcodes): Add csdb.
1971
1972 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1973
1974         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1975         * aarch64-asm-2.c: Regenerate.
1976         * aarch64-dis-2.c: Regenerate.
1977         * aarch64-opc-2.c: Regenerate.
1978
1979 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1980
1981         PR gas/22681
1982         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1983         Remove AVX512 vmovd with 64-bit operands.
1984         * i386-tbl.h: Regenerated.
1985
1986 2018-01-05  Jim Wilson  <jimw@sifive.com>
1987
1988         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1989         jalr.
1990
1991 2018-01-03  Alan Modra  <amodra@gmail.com>
1992
1993         Update year range in copyright notice of all files.
1994
1995 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1996
1997         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1998         and OPERAND_TYPE_REGZMM entries.
1999
2000 For older changes see ChangeLog-2017
2001 \f
2002 Copyright (C) 2018 Free Software Foundation, Inc.
2003
2004 Copying and distribution of this file, with or without modification,
2005 are permitted in any medium without royalty provided the copyright
2006 notice and this notice are preserved.
2007
2008 Local Variables:
2009 mode: change-log
2010 left-margin: 8
2011 fill-column: 74
2012 version-control: never
2013 End: