opcodes/ChangeLog

   1 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-dis.c (is_compatible_p): Remove function.
   4         (skip_this_opcode): Don't add any decoding class to decode list.
   5         Remove warning.
   6         (find_format_from_table): Go through all opcodes, and warn if we
   7         use a guessed mnemonic.
   8
   9 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
  10             Amit Pawar  <amit.pawar@amd.com>
  11
  12         PR binutils/20637
  13         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
  14         instructions.
  15
  16 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
  17
  18         * configure: Regenerate.
  19
  20 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
  21
  22         * sparc-opc.c (HWS_V8): Definition moved from
  23         gas/config/tc-sparc.c.
  24         (HWS_V9): Likewise.
  25         (HWS_VA): Likewise.
  26         (HWS_VB): Likewise.
  27         (HWS_VC): Likewise.
  28         (HWS_VD): Likewise.
  29         (HWS_VE): Likewise.
  30         (HWS_VV): Likewise.
  31         (HWS_VM): Likewise.
  32         (HWS2_VM): Likewise.
  33         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
  34         existing entries.
  35
  36 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  37
  38         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
  39         instructions.
  40
  41 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  42
  43         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
  44         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
  45         (aarch64_opcode_table): Add fcmla and fcadd.
  46         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
  47         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
  48         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
  49         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
  50         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
  51         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
  52         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
  53         (operand_general_constraint_met_p): Rotate and index range check.
  54         (aarch64_print_operand): Handle rotate operand.
  55         * aarch64-asm-2.c: Regenerate.
  56         * aarch64-dis-2.c: Likewise.
  57         * aarch64-opc-2.c: Likewise.
  58
  59 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  60
  61         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
  62         * aarch64-asm-2.c: Regenerate.
  63         * aarch64-dis-2.c: Regenerate.
  64         * aarch64-opc-2.c: Regenerate.
  65
  66 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  67
  68         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
  69         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
  70         * aarch64-asm-2.c: Regenerate.
  71         * aarch64-dis-2.c: Regenerate.
  72         * aarch64-opc-2.c: Regenerate.
  73
  74 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  75
  76         * aarch64-tbl.h (QL_X1NIL): New.
  77         (arch64_opcode_table): Add ldraa, ldrab.
  78         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
  79         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
  80         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
  81         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
  82         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
  83         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
  84         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
  85         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
  86         (aarch64_print_operand): Likewise.
  87         * aarch64-asm-2.c: Regenerate.
  88         * aarch64-dis-2.c: Regenerate.
  89         * aarch64-opc-2.c: Regenerate.
  90
  91 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  92
  93         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
  94         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
  95         * aarch64-asm-2.c: Regenerate.
  96         * aarch64-dis-2.c: Regenerate.
  97         * aarch64-opc-2.c: Regenerate.
  98
  99 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 100
 101         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 102         (AARCH64_OPERANDS): Add Rm_SP.
 103         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 104         * aarch64-asm-2.c: Regenerate.
 105         * aarch64-dis-2.c: Regenerate.
 106         * aarch64-opc-2.c: Regenerate.
 107
 108 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 109
 110         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 111         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 112         autdzb, xpaci, xpacd.
 113         * aarch64-asm-2.c: Regenerate.
 114         * aarch64-dis-2.c: Regenerate.
 115         * aarch64-opc-2.c: Regenerate.
 116
 117 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 118
 119         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 120         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 121         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 122         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 123
 124 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 125
 126         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 127         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 128         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 129         autibsp.
 130         * aarch64-asm-2.c: Regenerate.
 131         * aarch64-dis-2.c: Regenerate.
 132
 133 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 134
 135         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 136
 137 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         PR binutils/20799
 140         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 141         * i386-dis.c (EdqwS): Removed.
 142         (dqw_swap_mode): Likewise.
 143         (intel_operand_size): Don't check dqw_swap_mode.
 144         (OP_E_register): Likewise.
 145         (OP_E_memory): Likewise.
 146         (OP_G): Likewise.
 147         (OP_EX): Likewise.
 148         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 149         * i386-tbl.h: Regerated.
 150
 151 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 152
 153         * i386-opc.tbl: Merge AVX512F vmovq.
 154         * i386-tbl.h: Regerated.
 155
 156 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 157
 158         PR binutils/20701
 159         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 160         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 161         (three_byte_table): Remove THREE_BYTE_0F7A.
 162
 163 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 164
 165         PR binutils/20775
 166         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 167         (FGRPd9_4): Replace 1 with 2.
 168         (FGRPd9_5): Replace 2 with 3.
 169         (FGRPd9_6): Replace 3 with 4.
 170         (FGRPd9_7): Replace 4 with 5.
 171         (FGRPda_5): Replace 5 with 6.
 172         (FGRPdb_4): Replace 6 with 7.
 173         (FGRPde_3): Replace 7 with 8.
 174         (FGRPdf_4): Replace 8 with 9.
 175         (fgrps): Add an entry for Bad_Opcode.
 176
 177 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 178
 179         * arc-opc.c (arc_flag_operands): Add F_DI14.
 180         (arc_flag_classes): Add C_DI14.
 181         * arc-nps400-tbl.h: Add new exc instructions.
 182
 183 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 184
 185         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 186         major opcode 0xa.
 187         * arc-nps-400-tbl.h: Add dcmac instruction.
 188         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 189         (insert_nps_rbdouble_64): Added.
 190         (extract_nps_rbdouble_64): Added.
 191         (insert_nps_proto_size): Added.
 192         (extract_nps_proto_size): Added.
 193
 194 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 195
 196         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 197         relating to long instruction processing, add new limm field.
 198         (OPCODE): Rename to...
 199         (OPCODE_32BIT_INSN): ...this.
 200         (OPCODE_AC): Delete.
 201         (skip_this_opcode): Handle different instruction lengths, update
 202         macro name.
 203         (special_flag_p): Update parameter type.
 204         (find_format_from_table): Update for more instruction lengths.
 205         (find_format_long_instructions): Delete.
 206         (find_format): Update for more instruction lengths.
 207         (arc_insn_length): Likewise.
 208         (extract_operand_value): Update for more instruction lengths.
 209         (operand_iterator_next): Remove code relating to long
 210         instructions.
 211         (arc_opcode_to_insn_type): New function.
 212         (print_insn_arc):Update for more instructions lengths.
 213         * arc-ext.c (extInstruction_t): Change argument type.
 214         * arc-ext.h (extInstruction_t): Change argument type.
 215         * arc-fxi.h: Change type unsigned to unsigned long long
 216         extensively throughout.
 217         * arc-nps400-tbl.h: Add long instructions taken from
 218         arc_long_opcodes table in arc-opc.c.
 219         * arc-opc.c: Update parameter types on insert/extract handlers.
 220         (arc_long_opcodes): Delete.
 221         (arc_num_long_opcodes): Delete.
 222         (arc_opcode_len): Update for more instruction lengths.
 223
 224 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 225
 226         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 227
 228 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 229
 230         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 231         with arc_opcode_len.
 232         (find_format_long_instructions): Likewise.
 233         * arc-opc.c (arc_opcode_len): New function.
 234
 235 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 236
 237         * arc-nps400-tbl.h: Fix some instruction masks.
 238
 239 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 240
 241         * i386-dis.c (REG_82): Removed.
 242         (X86_64_82_REG_0): Likewise.
 243         (X86_64_82_REG_1): Likewise.
 244         (X86_64_82_REG_2): Likewise.
 245         (X86_64_82_REG_3): Likewise.
 246         (X86_64_82_REG_4): Likewise.
 247         (X86_64_82_REG_5): Likewise.
 248         (X86_64_82_REG_6): Likewise.
 249         (X86_64_82_REG_7): Likewise.
 250         (X86_64_82): New.
 251         (dis386): Use X86_64_82 instead of REG_82.
 252         (reg_table): Remove REG_82.
 253         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 254         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 255         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 256         X86_64_82_REG_7.
 257
 258 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 259
 260         PR binutils/20754
 261         * i386-dis.c (REG_82): New.
 262         (X86_64_82_REG_0): Likewise.
 263         (X86_64_82_REG_1): Likewise.
 264         (X86_64_82_REG_2): Likewise.
 265         (X86_64_82_REG_3): Likewise.
 266         (X86_64_82_REG_4): Likewise.
 267         (X86_64_82_REG_5): Likewise.
 268         (X86_64_82_REG_6): Likewise.
 269         (X86_64_82_REG_7): Likewise.
 270         (dis386): Use REG_82.
 271         (reg_table): Add REG_82.
 272         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 273         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 274         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 275
 276 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 277
 278         * i386-dis.c (REG_82): Renamed to ...
 279         (REG_83): This.
 280         (dis386): Updated.
 281         (reg_table): Likewise.
 282
 283 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 284
 285         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 286         * i386-dis-evex.h (evex_table): Updated.
 287         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 288         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 289         (cpu_flags): Add CpuAVX512_4VNNIW.
 290         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 291         (i386_cpu_flags): Add cpuavx512_4vnniw.
 292         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 293         * i386-init.h: Regenerate.
 294         * i386-tbl.h: Ditto.
 295
 296 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 297
 298         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 299         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 300         * i386-dis-evex.h (evex_table): Updated.
 301         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 302         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 303         (cpu_flags): Add CpuAVX512_4FMAPS.
 304         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 305         * i386-opc.h (AVX512_4FMAP): New.
 306         (i386_cpu_flags): Add cpuavx512_4fmaps.
 307         (ImplicitQuadGroup): New.
 308         (i386_opcode_modifier): Add implicitquadgroup.
 309         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 310         * i386-init.h: Regenerate.
 311         * i386-tbl.h: Ditto.
 312
 313 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 314             Andrew Waterman <andrew@sifive.com>
 315
 316         Add support for RISC-V architecture.
 317         * configure.ac: Add entry for bfd_riscv_arch.
 318         * configure: Regenerate.
 319         * disassemble.c (disassembler): Add support for riscv.
 320         (disassembler_usage): Likewise.
 321         * riscv-dis.c: New file.
 322         * riscv-opc.c: New file.
 323
 324 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 325
 326         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 327         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 328         (rm_table): Update the RM_0FAE_REG_7 entry.
 329         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 330         (cpu_flags): Remove CpuPCOMMIT.
 331         * i386-opc.h (CpuPCOMMIT): Removed.
 332         (i386_cpu_flags): Remove cpupcommit.
 333         * i386-opc.tbl: Remove pcommit.
 334         * i386-init.h: Regenerated.
 335         * i386-tbl.h: Likewise.
 336
 337 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 338
 339         PR binutis/20705
 340         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 341         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 342         32-bit mode.  Don't check vex.register_specifier in 32-bit
 343         mode.
 344         (OP_VEX): Check for invalid mask registers.
 345
 346 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 347
 348         PR binutis/20699
 349         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 350         sizeflag.
 351
 352 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 353
 354         PR binutis/20704
 355         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 356
 357 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 358
 359         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 360         local variable to `index_regno'.
 361
 362 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 363
 364         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 365
 366 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 367
 368         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 369         usage on ISA basis.
 370
 371 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 372
 373         PR target/20666
 374         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 375
 376 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 377
 378         PR target/20667
 379         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 380         available.
 381
 382 2016-10-07  Alan Modra  <amodra@gmail.com>
 383
 384         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 385
 386 2016-10-06  Alan Modra  <amodra@gmail.com>
 387
 388         * aarch64-opc.c: Spell fall through comments consistently.
 389         * i386-dis.c: Likewise.
 390         * aarch64-dis.c: Add missing fall through comments.
 391         * aarch64-opc.c: Likewise.
 392         * arc-dis.c: Likewise.
 393         * arm-dis.c: Likewise.
 394         * i386-dis.c: Likewise.
 395         * m68k-dis.c: Likewise.
 396         * mep-asm.c: Likewise.
 397         * ns32k-dis.c: Likewise.
 398         * sh-dis.c: Likewise.
 399         * tic4x-dis.c: Likewise.
 400         * tic6x-dis.c: Likewise.
 401         * vax-dis.c: Likewise.
 402
 403 2016-10-06  Alan Modra  <amodra@gmail.com>
 404
 405         * arc-ext.c (create_map): Add missing break.
 406         * msp430-decode.opc (encode_as): Likewise.
 407         * msp430-decode.c: Regenerate.
 408
 409 2016-10-06  Alan Modra  <amodra@gmail.com>
 410
 411         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 412         * crx-dis.c (print_insn_crx): Likewise.
 413
 414 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 415
 416         PR binutils/20657
 417         * i386-dis.c (putop): Don't assign alt twice.
 418
 419 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 420
 421         PR target/20553
 422         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 423
 424 2016-09-29  Alan Modra  <amodra@gmail.com>
 425
 426         * ppc-opc.c (L): Make compulsory.
 427         (LOPT): New, optional form of L.
 428         (HTM_R): Define as LOPT.
 429         (L0, L1): Delete.
 430         (L32OPT): New, optional for 32-bit L.
 431         (L2OPT): New, 2-bit L for dcbf.
 432         (SVC_LEC): Update.
 433         (L2): Define.
 434         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 435         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 436         <dcbf>: Use L2OPT.
 437         <tlbiel, tlbie>: Use LOPT.
 438         <wclr, wclrall>: Use L2.
 439
 440 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 441
 442         * Makefile.in: Regenerate.
 443         * configure: Likewise.
 444
 445 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 446
 447         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 448         (EXTINSN2OP): Use EXTINSN2OPF.
 449         (bspeekm, bspop, modapp): New extension instructions.
 450         * arc-opc.c (F_DNZ_ND): Define.
 451         (F_DNZ_D): Likewise.
 452         (F_SIZEB1): Changed.
 453         (C_DNZ_D): Define.
 454         (C_HARD): Changed.
 455         * arc-tbl.h (dbnz): New instruction.
 456         (prealloc): Allow it for ARC EM.
 457         (xbfu): Likewise.
 458
 459 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 460
 461         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 462         after commas in addresses.
 463         (aarch64_print_operand): Likewise.
 464
 465 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 466
 467         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 468         rather than "should be" or "expected to be" in error messages.
 469
 470 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 471
 472         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 473         (print_mnemonic_name): ...here.
 474         (print_comment): New function.
 475         (print_aarch64_insn): Call it.
 476         * aarch64-opc.c (aarch64_conds): Add SVE names.
 477         (aarch64_print_operand): Print alternative condition names in
 478         a comment.
 479
 480 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 481
 482         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 483         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 484         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 485         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 486         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 487         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 488         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 489         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 490         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 491         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 492         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 493         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 494         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 495         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 496         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 497         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 498         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 499         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 500         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 501         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 502         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 503         (aarch64_feature_sve): New variable.
 504         (SVE): New macro.
 505         (_SVE_INSN): Likewise.
 506         (aarch64_opcode_table): Add SVE instructions.
 507         * aarch64-opc.h (extract_fields): Declare.
 508         * aarch64-opc-2.c: Regenerate.
 509         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 510         * aarch64-asm-2.c: Regenerate.
 511         * aarch64-dis.c (extract_fields): Make global.
 512         (do_misc_decoding): Handle the new SVE aarch64_ops.
 513         * aarch64-dis-2.c: Regenerate.
 514
 515 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 516
 517         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 518         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 519         aarch64_field_kinds.
 520         * aarch64-opc.c (fields): Add corresponding entries.
 521         * aarch64-asm.c (aarch64_get_variant): New function.
 522         (aarch64_encode_variant_using_iclass): Likewise.
 523         (aarch64_opcode_encode): Call it.
 524         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 525         (aarch64_opcode_decode): Call it.
 526
 527 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 528
 529         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 530         and FP register operands.
 531         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 532         (FLD_SVE_Vn): New aarch64_field_kinds.
 533         * aarch64-opc.c (fields): Add corresponding entries.
 534         (aarch64_print_operand): Handle the new SVE core and FP register
 535         operands.
 536         * aarch64-opc-2.c: Regenerate.
 537         * aarch64-asm-2.c: Likewise.
 538         * aarch64-dis-2.c: Likewise.
 539
 540 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 541
 542         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 543         immediate operands.
 544         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 545         * aarch64-opc.c (fields): Add corresponding entry.
 546         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 547         operands.
 548         (aarch64_print_operand): Likewise.
 549         * aarch64-opc-2.c: Regenerate.
 550         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 551         (ins_sve_float_zero_one): New inserters.
 552         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 553         (aarch64_ins_sve_float_half_two): Likewise.
 554         (aarch64_ins_sve_float_zero_one): Likewise.
 555         * aarch64-asm-2.c: Regenerate.
 556         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 557         (ext_sve_float_zero_one): New extractors.
 558         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 559         (aarch64_ext_sve_float_half_two): Likewise.
 560         (aarch64_ext_sve_float_zero_one): Likewise.
 561         * aarch64-dis-2.c: Regenerate.
 562
 563 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 564
 565         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 566         integer immediate operands.
 567         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 568         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 569         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 570         * aarch64-opc.c (fields): Add corresponding entries.
 571         (operand_general_constraint_met_p): Handle the new SVE integer
 572         immediate operands.
 573         (aarch64_print_operand): Likewise.
 574         (aarch64_sve_dupm_mov_immediate_p): New function.
 575         * aarch64-opc-2.c: Regenerate.
 576         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 577         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 578         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 579         (aarch64_ins_limm): ...here.
 580         (aarch64_ins_inv_limm): New function.
 581         (aarch64_ins_sve_aimm): Likewise.
 582         (aarch64_ins_sve_asimm): Likewise.
 583         (aarch64_ins_sve_limm_mov): Likewise.
 584         (aarch64_ins_sve_shlimm): Likewise.
 585         (aarch64_ins_sve_shrimm): Likewise.
 586         * aarch64-asm-2.c: Regenerate.
 587         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 588         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 589         * aarch64-dis.c (decode_limm): New function, split out from...
 590         (aarch64_ext_limm): ...here.
 591         (aarch64_ext_inv_limm): New function.
 592         (decode_sve_aimm): Likewise.
 593         (aarch64_ext_sve_aimm): Likewise.
 594         (aarch64_ext_sve_asimm): Likewise.
 595         (aarch64_ext_sve_limm_mov): Likewise.
 596         (aarch64_top_bit): Likewise.
 597         (aarch64_ext_sve_shlimm): Likewise.
 598         (aarch64_ext_sve_shrimm): Likewise.
 599         * aarch64-dis-2.c: Regenerate.
 600
 601 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 602
 603         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 604         operands.
 605         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 606         the AARCH64_MOD_MUL_VL entry.
 607         (value_aligned_p): Cope with non-power-of-two alignments.
 608         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 609         (print_immediate_offset_address): Likewise.
 610         (aarch64_print_operand): Likewise.
 611         * aarch64-opc-2.c: Regenerate.
 612         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 613         (ins_sve_addr_ri_s9xvl): New inserters.
 614         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 615         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 616         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 617         * aarch64-asm-2.c: Regenerate.
 618         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 619         (ext_sve_addr_ri_s9xvl): New extractors.
 620         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 621         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 622         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 623         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 624         * aarch64-dis-2.c: Regenerate.
 625
 626 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 627
 628         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 629         address operands.
 630         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 631         (FLD_SVE_xs_22): New aarch64_field_kinds.
 632         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 633         (get_operand_specific_data): New function.
 634         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 635         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 636         (operand_general_constraint_met_p): Handle the new SVE address
 637         operands.
 638         (sve_reg): New array.
 639         (get_addr_sve_reg_name): New function.
 640         (aarch64_print_operand): Handle the new SVE address operands.
 641         * aarch64-opc-2.c: Regenerate.
 642         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 643         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 644         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 645         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 646         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 647         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 648         (aarch64_ins_sve_addr_zi_u5): Likewise.
 649         (aarch64_ins_sve_addr_zz): Likewise.
 650         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 651         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 652         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 653         * aarch64-asm-2.c: Regenerate.
 654         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 655         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 656         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 657         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 658         (aarch64_ext_sve_addr_ri_u6): Likewise.
 659         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 660         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 661         (aarch64_ext_sve_addr_zi_u5): Likewise.
 662         (aarch64_ext_sve_addr_zz): Likewise.
 663         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 664         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 665         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 666         * aarch64-dis-2.c: Regenerate.
 667
 668 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 669
 670         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 671         AARCH64_OPND_SVE_PATTERN_SCALED.
 672         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 673         * aarch64-opc.c (fields): Add a corresponding entry.
 674         (set_multiplier_out_of_range_error): New function.
 675         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 676         (operand_general_constraint_met_p): Handle
 677         AARCH64_OPND_SVE_PATTERN_SCALED.
 678         (print_register_offset_address): Use PRIi64 to print the
 679         shift amount.
 680         (aarch64_print_operand): Likewise.  Handle
 681         AARCH64_OPND_SVE_PATTERN_SCALED.
 682         * aarch64-opc-2.c: Regenerate.
 683         * aarch64-asm.h (ins_sve_scale): New inserter.
 684         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 685         * aarch64-asm-2.c: Regenerate.
 686         * aarch64-dis.h (ext_sve_scale): New inserter.
 687         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 688         * aarch64-dis-2.c: Regenerate.
 689
 690 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 691
 692         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 693         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 694         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 695         (FLD_SVE_prfop): Likewise.
 696         * aarch64-opc.c: Include libiberty.h.
 697         (aarch64_sve_pattern_array): New variable.
 698         (aarch64_sve_prfop_array): Likewise.
 699         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 700         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 701         AARCH64_OPND_SVE_PRFOP.
 702         * aarch64-asm-2.c: Regenerate.
 703         * aarch64-dis-2.c: Likewise.
 704         * aarch64-opc-2.c: Likewise.
 705
 706 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 707
 708         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 709         AARCH64_OPND_QLF_P_[ZM].
 710         (aarch64_print_operand): Print /z and /m where appropriate.
 711
 712 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 713
 714         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 715         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 716         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 717         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 718         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 719         * aarch64-opc.c (fields): Add corresponding entries here.
 720         (operand_general_constraint_met_p): Check that SVE register lists
 721         have the correct length.  Check the ranges of SVE index registers.
 722         Check for cases where p8-p15 are used in 3-bit predicate fields.
 723         (aarch64_print_operand): Handle the new SVE operands.
 724         * aarch64-opc-2.c: Regenerate.
 725         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 726         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 727         (aarch64_ins_sve_reglist): Likewise.
 728         * aarch64-asm-2.c: Regenerate.
 729         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 730         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 731         (aarch64_ext_sve_reglist): Likewise.
 732         * aarch64-dis-2.c: Regenerate.
 733
 734 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 735
 736         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 737         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 738         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 739         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 740         tied operands.
 741
 742 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 743
 744         * aarch64-opc.c (get_offset_int_reg_name): New function.
 745         (print_immediate_offset_address): Likewise.
 746         (print_register_offset_address): Take the base and offset
 747         registers as parameters.
 748         (aarch64_print_operand): Update caller accordingly.  Use
 749         print_immediate_offset_address.
 750
 751 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 752
 753         * aarch64-opc.c (BANK): New macro.
 754         (R32, R64): Take a register number as argument
 755         (int_reg): Use BANK.
 756
 757 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 758
 759         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 760         (aarch64_print_operand): Update accordingly.
 761
 762 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 763
 764         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 765         for FPIMM.
 766         * aarch64-asm.h (ins_fpimm): New inserter.
 767         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 768         * aarch64-asm-2.c: Regenerate.
 769         * aarch64-dis.h (ext_fpimm): New extractor.
 770         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 771         (aarch64_ext_fpimm): New function.
 772         * aarch64-dis-2.c: Regenerate.
 773
 774 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 775
 776         * aarch64-asm.c: Include libiberty.h.
 777         (insert_fields): New function.
 778         (aarch64_ins_imm): Use it.
 779         * aarch64-dis.c (extract_fields): New function.
 780         (aarch64_ext_imm): Use it.
 781
 782 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 783
 784         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 785         with an esize parameter.
 786         (operand_general_constraint_met_p): Update accordingly.
 787         Fix misindented code.
 788         * aarch64-asm.c (aarch64_ins_limm): Update call to
 789         aarch64_logical_immediate_p.
 790
 791 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 792
 793         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 794
 795 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 796
 797         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 798
 799 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 800
 801         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 802
 803 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 804
 805         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 806         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 807         xor3>: Delete mnemonics.
 808         <cp_abort>: Rename mnemonic from ...
 809         <cpabort>: ...to this.
 810         <setb>: Change to a X form instruction.
 811         <sync>: Change to 1 operand form.
 812         <copy>: Delete mnemonic.
 813         <copy_first>: Rename mnemonic from ...
 814         <copy>: ...to this.
 815         <paste, paste.>: Delete mnemonics.
 816         <paste_last>: Rename mnemonic from ...
 817         <paste.>: ...to this.
 818
 819 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 820
 821         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 822
 823 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 824
 825         * s390-mkopc.c (main): Support alternate arch strings.
 826
 827 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 828
 829         * s390-opc.txt: Fix kmctr instruction type.
 830
 831 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 832
 833         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 834         * i386-init.h: Regenerated.
 835
 836 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 837
 838         * opcodes/arc-dis.c (print_insn_arc): Changed.
 839
 840 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 841
 842         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 843         camellia_fl.
 844
 845 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 846
 847         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 848         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 849         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 850
 851 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 852
 853         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 854         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 855         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 856         PREFIX_MOD_3_0FAE_REG_4.
 857         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 858         PREFIX_MOD_3_0FAE_REG_4.
 859         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 860         (cpu_flags): Add CpuPTWRITE.
 861         * i386-opc.h (CpuPTWRITE): New.
 862         (i386_cpu_flags): Add cpuptwrite.
 863         * i386-opc.tbl: Add ptwrite instruction.
 864         * i386-init.h: Regenerated.
 865         * i386-tbl.h: Likewise.
 866
 867 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 868
 869         * arc-dis.h: Wrap around in extern "C".
 870
 871 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 872
 873         * aarch64-tbl.h (V8_2_INSN): New macro.
 874         (aarch64_opcode_table): Use it.
 875
 876 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 877
 878         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 879         CORE_INSN, __FP_INSN and SIMD_INSN.
 880
 881 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 882
 883         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 884         (aarch64_opcode_table): Update uses accordingly.
 885
 886 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 887         Kwok Cheung Yeung  <kcy@codesourcery.com>
 888
 889         opcodes/
 890         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 891         'e_cmplwi' to 'e_cmpli' instead.
 892         (OPVUPRT, OPVUPRT_MASK): Define.
 893         (powerpc_opcodes): Add E200Z4 insns.
 894         (vle_opcodes): Add context save/restore insns.
 895
 896 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 897
 898         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 899         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 900         "j".
 901
 902 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 903
 904         * arc-nps400-tbl.h: Change block comments to GNU format.
 905         * arc-dis.c: Add new globals addrtypenames,
 906         addrtypenames_max, and addtypeunknown.
 907         (get_addrtype): New function.
 908         (print_insn_arc): Print colons and address types when
 909         required.
 910         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 911         define insert and extract functions for all address types.
 912         (arc_operands): Add operands for colon and all address
 913         types.
 914         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 915         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 916         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 917         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 918         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 919         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 920
 921 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         * configure: Regenerated.
 924
 925 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 926
 927         * arc-dis.c (skipclass): New structure.
 928         (decodelist): New variable.
 929         (is_compatible_p): New function.
 930         (new_element): Likewise.
 931         (skip_class_p): Likewise.
 932         (find_format_from_table): Use skip_class_p function.
 933         (find_format): Decode first the extension instructions.
 934         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 935         e_flags.
 936         (parse_option): New function.
 937         (parse_disassembler_options): Likewise.
 938         (print_arc_disassembler_options): Likewise.
 939         (print_insn_arc): Use parse_disassembler_options function.  Proper
 940         select ARCv2 cpu variant.
 941         * disassemble.c (disassembler_usage): Add ARC disassembler
 942         options.
 943
 944 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 945
 946         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 947         annotation from the "nal" entry and reorder it beyond "bltzal".
 948
 949 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 950
 951         * sparc-opc.c (ldtxa): New macro.
 952         (sparc_opcodes): Use the macro defined above to add entries for
 953         the LDTXA instructions.
 954         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 955         instruction.
 956
 957 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 958
 959         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 960         and "jmpc".
 961
 962 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 963
 964         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 965         (movzb): Adjust to cover all permitted suffixes.
 966         (movzw): New.
 967         * i386-tbl.h: Re-generate.
 968
 969 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 972         (lgdt): Remove Tbyte from non-64-bit variant.
 973         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 974         xsaves64, xsavec64): Remove Disp16.
 975         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 976         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 977         64-bit variants.
 978         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 979         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 980         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 981         64-bit variants.
 982         * i386-tbl.h: Re-generate.
 983
 984 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 985
 986         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 987         * i386-tbl.h: Re-generate.
 988
 989 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 990
 991         * arm-dis.c (print_insn): Fix typo in comment.
 992
 993 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 994
 995         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 996         range of ldst_elemlist operands.
 997         (print_register_list): Use PRIi64 to print the index.
 998         (aarch64_print_operand): Likewise.
 999
1000 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1001
1002         * mcore-opc.h: Remove sentinal.
1003         * mcore-dis.c (print_insn_mcore): Adjust.
1004
1005 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1006
1007         * arc-opc.c: Correct description of availability of NPS400
1008         features.
1009
1010 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1011
1012         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1013         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1014         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1015         xor3>: New mnemonics.
1016         <setb>: Change to a VX form instruction.
1017         (insert_sh6): Add support for rldixor.
1018         (extract_sh6): Likewise.
1019
1020 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1021
1022         * arc-ext.h: Wrap in extern C.
1023
1024 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1025
1026         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1027         Use same method for determining instruction length on ARC700 and
1028         NPS-400.
1029         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1030         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1031         with the NPS400 subclass.
1032         * arc-opc.c: Likewise.
1033
1034 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1035
1036         * sparc-opc.c (rdasr): New macro.
1037         (wrasr): Likewise.
1038         (rdpr): Likewise.
1039         (wrpr): Likewise.
1040         (rdhpr): Likewise.
1041         (wrhpr): Likewise.
1042         (sparc_opcodes): Use the macros above to fix and expand the
1043         definition of read/write instructions from/to
1044         asr/privileged/hyperprivileged instructions.
1045         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1046         %hva_mask_nz.  Prefer softint_set and softint_clear over
1047         set_softint and clear_softint.
1048         (print_insn_sparc): Support %ver in Rd.
1049
1050 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1051
1052         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1053         architecture according to the hardware capabilities they require.
1054
1055 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1056
1057         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1058         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1059         bfd_mach_sparc_v9{c,d,e,v,m}.
1060         * sparc-opc.c (MASK_V9C): Define.
1061         (MASK_V9D): Likewise.
1062         (MASK_V9E): Likewise.
1063         (MASK_V9V): Likewise.
1064         (MASK_V9M): Likewise.
1065         (v6): Add MASK_V9{C,D,E,V,M}.
1066         (v6notlet): Likewise.
1067         (v7): Likewise.
1068         (v8): Likewise.
1069         (v9): Likewise.
1070         (v9andleon): Likewise.
1071         (v9a): Likewise.
1072         (v9b): Likewise.
1073         (v9c): Define.
1074         (v9d): Likewise.
1075         (v9e): Likewise.
1076         (v9v): Likewise.
1077         (v9m): Likewise.
1078         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1079
1080 2016-06-15  Nick Clifton  <nickc@redhat.com>
1081
1082         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1083         constants to match expected behaviour.
1084         (nds32_parse_opcode): Likewise.  Also for whitespace.
1085
1086 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1087
1088         * arc-opc.c (extract_rhv1): Extract value from insn.
1089
1090 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1091
1092         * arc-nps400-tbl.h: Add ldbit instruction.
1093         * arc-opc.c: Add flag classes required for ldbit.
1094
1095 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1096
1097         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1098         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1099         support the above instructions.
1100
1101 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1102
1103         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1104         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1105         csma, cbba, zncv, and hofs.
1106         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1107         support the above instructions.
1108
1109 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1110
1111         * arc-nps400-tbl.h: Add andab and orab instructions.
1112
1113 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1114
1115         * arc-nps400-tbl.h: Add addl-like instructions.
1116
1117 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1118
1119         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1120
1121 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1122
1123         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1124         instructions.
1125
1126 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1127
1128         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1129         variable.
1130         (init_disasm): Handle new command line option "insnlength".
1131         (print_s390_disassembler_options): Mention new option in help
1132         output.
1133         (print_insn_s390): Use the encoded insn length when dumping
1134         unknown instructions.
1135
1136 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1137
1138         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1139          to the address and set as symbol address for LDS/ STS immediate operands.
1140
1141 2016-06-07  Alan Modra  <amodra@gmail.com>
1142
1143         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1144         cpu for "vle" to e500.
1145         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1146         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1147         (PPCNONE): Delete, substitute throughout.
1148         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1149         except for major opcode 4 and 31.
1150         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1151
1152 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1153
1154         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1155         ARM_EXT_RAS in relevant entries.
1156
1157 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1158
1159         PR binutils/20196
1160         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1161         opcodes for E6500.
1162
1163 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1164
1165         PR binutis/18386
1166         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1167         (indir_v_mode): New.
1168         Add comments for '&'.
1169         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1170         (putop): Handle '&'.
1171         (intel_operand_size): Handle indir_v_mode.
1172         (OP_E_register): Likewise.
1173         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1174         64-bit indirect call/jmp for AMD64.
1175         * i386-tbl.h: Regenerated
1176
1177 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1178
1179         * arc-dis.c (struct arc_operand_iterator): New structure.
1180         (find_format_from_table): All the old content from find_format,
1181         with some minor adjustments, and parameter renaming.
1182         (find_format_long_instructions): New function.
1183         (find_format): Rewritten.
1184         (arc_insn_length): Add LSB parameter.
1185         (extract_operand_value): New function.
1186         (operand_iterator_next): New function.
1187         (print_insn_arc): Use new functions to find opcode, and iterator
1188         over operands.
1189         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1190         (extract_nps_3bit_dst_short): New function.
1191         (insert_nps_3bit_src2_short): New function.
1192         (extract_nps_3bit_src2_short): New function.
1193         (insert_nps_bitop1_size): New function.
1194         (extract_nps_bitop1_size): New function.
1195         (insert_nps_bitop2_size): New function.
1196         (extract_nps_bitop2_size): New function.
1197         (insert_nps_bitop_mod4_msb): New function.
1198         (extract_nps_bitop_mod4_msb): New function.
1199         (insert_nps_bitop_mod4_lsb): New function.
1200         (extract_nps_bitop_mod4_lsb): New function.
1201         (insert_nps_bitop_dst_pos3_pos4): New function.
1202         (extract_nps_bitop_dst_pos3_pos4): New function.
1203         (insert_nps_bitop_ins_ext): New function.
1204         (extract_nps_bitop_ins_ext): New function.
1205         (arc_operands): Add new operands.
1206         (arc_long_opcodes): New global array.
1207         (arc_num_long_opcodes): New global.
1208         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1209
1210 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1211
1212         * nds32-asm.h: Add extern "C".
1213         * sh-opc.h: Likewise.
1214
1215 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1216
1217         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1218         0,b,limm to the rflt instruction.
1219
1220 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1221
1222         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1223         constant.
1224
1225 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1226
1227         PR gas/20145
1228         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1229         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1230         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1231         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1232         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1233         * i386-init.h: Regenerated.
1234
1235 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1236
1237         PR gas/20145
1238         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1239         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1240         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1241         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1242         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1243         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1244         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1245         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1246         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1247         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1248         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1249         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1250         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1251         CpuRegMask for AVX512.
1252         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1253         and CpuRegMask.
1254         (set_bitfield_from_cpu_flag_init): New function.
1255         (set_bitfield): Remove const on f.  Call
1256         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1257         * i386-opc.h (CpuRegMMX): New.
1258         (CpuRegXMM): Likewise.
1259         (CpuRegYMM): Likewise.
1260         (CpuRegZMM): Likewise.
1261         (CpuRegMask): Likewise.
1262         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1263         and cpuregmask.
1264         * i386-init.h: Regenerated.
1265         * i386-tbl.h: Likewise.
1266
1267 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1268
1269         PR gas/20154
1270         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1271         (opcode_modifiers): Add AMD64 and Intel64.
1272         (main): Properly verify CpuMax.
1273         * i386-opc.h (CpuAMD64): Removed.
1274         (CpuIntel64): Likewise.
1275         (CpuMax): Set to CpuNo64.
1276         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1277         (AMD64): New.
1278         (Intel64): Likewise.
1279         (i386_opcode_modifier): Add amd64 and intel64.
1280         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1281         on call and jmp.
1282         * i386-init.h: Regenerated.
1283         * i386-tbl.h: Likewise.
1284
1285 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1286
1287         PR gas/20154
1288         * i386-gen.c (main): Fail if CpuMax is incorrect.
1289         * i386-opc.h (CpuMax): Set to CpuIntel64.
1290         * i386-tbl.h: Regenerated.
1291
1292 2016-05-27  Nick Clifton  <nickc@redhat.com>
1293
1294         PR target/20150
1295         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1296         (msp430dis_opcode_unsigned): New function.
1297         (msp430dis_opcode_signed): New function.
1298         (msp430_singleoperand): Use the new opcode reading functions.
1299         Only disassenmble bytes if they were successfully read.
1300         (msp430_doubleoperand): Likewise.
1301         (msp430_branchinstr): Likewise.
1302         (msp430x_callx_instr): Likewise.
1303         (print_insn_msp430): Check that it is safe to read bytes before
1304         attempting disassembly.  Use the new opcode reading functions.
1305
1306 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1307
1308         * ppc-opc.c (CY): New define.  Document it.
1309         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1310
1311 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1312
1313         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1314         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1315         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1316         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1317         CPU_ANY_AVX_FLAGS.
1318         * i386-init.h: Regenerated.
1319
1320 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1321
1322         PR gas/20141
1323         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1324         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1325         * i386-init.h: Regenerated.
1326
1327 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1328
1329         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1330         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1331         * i386-init.h: Regenerated.
1332
1333 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1334
1335         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1336         information.
1337         (print_insn_arc): Set insn_type information.
1338         * arc-opc.c (C_CC): Add F_CLASS_COND.
1339         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1340         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1341         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1342         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1343         (brne, brne_s, jeq_s, jne_s): Likewise.
1344
1345 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1346
1347         * arc-tbl.h (neg): New instruction variant.
1348
1349 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1350
1351         * arc-dis.c (find_format, find_format, get_auxreg)
1352         (print_insn_arc): Changed.
1353         * arc-ext.h (INSERT_XOP): Likewise.
1354
1355 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1356
1357         * tic54x-dis.c (sprint_mmr): Adjust.
1358         * tic54x-opc.c: Likewise.
1359
1360 2016-05-19  Alan Modra  <amodra@gmail.com>
1361
1362         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1363
1364 2016-05-19  Alan Modra  <amodra@gmail.com>
1365
1366         * ppc-opc.c: Formatting.
1367         (NSISIGNOPT): Define.
1368         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1369
1370 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1371
1372         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1373         replacing references to `micromips_ase' throughout.
1374         (_print_insn_mips): Don't use file-level microMIPS annotation to
1375         determine the disassembly mode with the symbol table.
1376
1377 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1378
1379         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1380
1381 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1382
1383         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1384         mips64r6.
1385         * mips-opc.c (D34): New macro.
1386         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1387
1388 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1389
1390         * i386-dis.c (prefix_table): Add RDPID instruction.
1391         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1392         (cpu_flags): Add RDPID bitfield.
1393         * i386-opc.h (enum): Add RDPID element.
1394         (i386_cpu_flags): Add RDPID field.
1395         * i386-opc.tbl: Add RDPID instruction.
1396         * i386-init.h: Regenerate.
1397         * i386-tbl.h: Regenerate.
1398
1399 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1400
1401         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1402         branch type of a symbol.
1403         (print_insn): Likewise.
1404
1405 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1406
1407         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1408         Mainline Security Extensions instructions.
1409         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1410         Extensions instructions.
1411         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1412         instructions.
1413         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1414         special registers.
1415
1416 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1417
1418         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1419
1420 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1421
1422         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1423         (arcExtMap_genOpcode): Likewise.
1424         * arc-opc.c (arg_32bit_rc): Define new variable.
1425         (arg_32bit_u6): Likewise.
1426         (arg_32bit_limm): Likewise.
1427
1428 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1429
1430         * aarch64-gen.c (VERIFIER): Define.
1431         * aarch64-opc.c (VERIFIER): Define.
1432         (verify_ldpsw): Use static linkage.
1433         * aarch64-opc.h (verify_ldpsw): Remove.
1434         * aarch64-tbl.h: Use VERIFIER for verifiers.
1435
1436 2016-04-28  Nick Clifton  <nickc@redhat.com>
1437
1438         PR target/19722
1439         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1440         * aarch64-opc.c (verify_ldpsw): New function.
1441         * aarch64-opc.h (verify_ldpsw): New prototype.
1442         * aarch64-tbl.h: Add initialiser for verifier field.
1443         (LDPSW): Set verifier to verify_ldpsw.
1444
1445 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1446
1447         PR binutils/19983
1448         PR binutils/19984
1449         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1450         smaller than address size.
1451
1452 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1453
1454         * alpha-dis.c: Regenerate.
1455         * crx-dis.c: Likewise.
1456         * disassemble.c: Likewise.
1457         * epiphany-opc.c: Likewise.
1458         * fr30-opc.c: Likewise.
1459         * frv-opc.c: Likewise.
1460         * ip2k-opc.c: Likewise.
1461         * iq2000-opc.c: Likewise.
1462         * lm32-opc.c: Likewise.
1463         * lm32-opinst.c: Likewise.
1464         * m32c-opc.c: Likewise.
1465         * m32r-opc.c: Likewise.
1466         * m32r-opinst.c: Likewise.
1467         * mep-opc.c: Likewise.
1468         * mt-opc.c: Likewise.
1469         * or1k-opc.c: Likewise.
1470         * or1k-opinst.c: Likewise.
1471         * tic80-opc.c: Likewise.
1472         * xc16x-opc.c: Likewise.
1473         * xstormy16-opc.c: Likewise.
1474
1475 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1476
1477         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1478         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1479         calcsd, and calcxd instructions.
1480         * arc-opc.c (insert_nps_bitop_size): Delete.
1481         (extract_nps_bitop_size): Delete.
1482         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1483         (extract_nps_qcmp_m3): Define.
1484         (extract_nps_qcmp_m2): Define.
1485         (extract_nps_qcmp_m1): Define.
1486         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1487         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1488         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1489         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1490         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1491         NPS_QCMP_M3.
1492
1493 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1494
1495         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1496
1497 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1498
1499         * Makefile.in: Regenerated with automake 1.11.6.
1500         * aclocal.m4: Likewise.
1501
1502 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1503
1504         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1505         instructions.
1506         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1507         (extract_nps_cmem_uimm16): New function.
1508         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1509
1510 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1511
1512         * arc-dis.c (arc_insn_length): New function.
1513         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1514         (find_format): Change insnLen parameter to unsigned.
1515
1516 2016-04-13  Nick Clifton  <nickc@redhat.com>
1517
1518         PR target/19937
1519         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1520         the LD.B and LD.BU instructions.
1521
1522 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1523
1524         * arc-dis.c (find_format): Check for extension flags.
1525         (print_flags): New function.
1526         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1527         .extAuxRegister.
1528         * arc-ext.c (arcExtMap_coreRegName): Use
1529         LAST_EXTENSION_CORE_REGISTER.
1530         (arcExtMap_coreReadWrite): Likewise.
1531         (dump_ARC_extmap): Update printing.
1532         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1533         (arc_aux_regs): Add cpu field.
1534         * arc-regs.h: Add cpu field, lower case name aux registers.
1535
1536 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1537
1538         * arc-tbl.h: Add rtsc, sleep with no arguments.
1539
1540 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1541
1542         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1543         Initialize.
1544         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1545         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1546         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1547         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1548         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1549         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1550         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1551         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1552         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1553         (arc_opcode arc_opcodes): Null terminate the array.
1554         (arc_num_opcodes): Remove.
1555         * arc-ext.h (INSERT_XOP): Define.
1556         (extInstruction_t): Likewise.
1557         (arcExtMap_instName): Delete.
1558         (arcExtMap_insn): New function.
1559         (arcExtMap_genOpcode): Likewise.
1560         * arc-ext.c (ExtInstruction): Remove.
1561         (create_map): Zero initialize instruction fields.
1562         (arcExtMap_instName): Remove.
1563         (arcExtMap_insn): New function.
1564         (dump_ARC_extmap): More info while debuging.
1565         (arcExtMap_genOpcode): New function.
1566         * arc-dis.c (find_format): New function.
1567         (print_insn_arc): Use find_format.
1568         (arc_get_disassembler): Enable dump_ARC_extmap only when
1569         debugging.
1570
1571 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1572
1573         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1574         instruction bits out.
1575
1576 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1577
1578         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1579         * arc-opc.c (arc_flag_operands): Add new flags.
1580         (arc_flag_classes): Add new classes.
1581
1582 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1583
1584         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1585
1586 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1587
1588         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1589         encode1, rflt, crc16, and crc32 instructions.
1590         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1591         (arc_flag_classes): Add C_NPS_R.
1592         (insert_nps_bitop_size_2b): New function.
1593         (extract_nps_bitop_size_2b): Likewise.
1594         (insert_nps_bitop_uimm8): Likewise.
1595         (extract_nps_bitop_uimm8): Likewise.
1596         (arc_operands): Add new operand entries.
1597
1598 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1599
1600         * arc-regs.h: Add a new subclass field.  Add double assist
1601         accumulator register values.
1602         * arc-tbl.h: Use DPA subclass to mark the double assist
1603         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1604         * arc-opc.c (RSP): Define instead of SP.
1605         (arc_aux_regs): Add the subclass field.
1606
1607 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1608
1609         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1610
1611 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1612
1613         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1614         NPS_R_SRC1.
1615
1616 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1617
1618         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1619         issues.  No functional changes.
1620
1621 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1622
1623         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1624         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1625         (RTT): Remove duplicate.
1626         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1627         (PCT_CONFIG*): Remove.
1628         (D1L, D1H, D2H, D2L): Define.
1629
1630 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1631
1632         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1633
1634 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1635
1636         * arc-tbl.h (invld07): Remove.
1637         * arc-ext-tbl.h: New file.
1638         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1639         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1640
1641 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1642
1643         Fix -Wstack-usage warnings.
1644         * aarch64-dis.c (print_operands): Substitute size.
1645         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1646
1647 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1648
1649         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1650         to get a proper diagnostic when an invalid ASR register is used.
1651
1652 2016-03-22  Nick Clifton  <nickc@redhat.com>
1653
1654         * configure: Regenerate.
1655
1656 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1657
1658         * arc-nps400-tbl.h: New file.
1659         * arc-opc.c: Add top level comment.
1660         (insert_nps_3bit_dst): New function.
1661         (extract_nps_3bit_dst): New function.
1662         (insert_nps_3bit_src2): New function.
1663         (extract_nps_3bit_src2): New function.
1664         (insert_nps_bitop_size): New function.
1665         (extract_nps_bitop_size): New function.
1666         (arc_flag_operands): Add nps400 entries.
1667         (arc_flag_classes): Add nps400 entries.
1668         (arc_operands): Add nps400 entries.
1669         (arc_opcodes): Add nps400 include.
1670
1671 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1672
1673         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1674         the new class enum values.
1675
1676 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1677
1678         * arc-dis.c (print_insn_arc): Handle nps400.
1679
1680 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1681
1682         * arc-opc.c (BASE): Delete.
1683
1684 2016-03-18  Nick Clifton  <nickc@redhat.com>
1685
1686         PR target/19721
1687         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1688         of MOV insn that aliases an ORR insn.
1689
1690 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1691
1692         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1693
1694 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1695
1696         * mcore-opc.h: Add const qualifiers.
1697         * microblaze-opc.h (struct op_code_struct): Likewise.
1698         * sh-opc.h: Likewise.
1699         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1700         (tic4x_print_op): Likewise.
1701
1702 2016-03-02  Alan Modra  <amodra@gmail.com>
1703
1704         * or1k-desc.h: Regenerate.
1705         * fr30-ibld.c: Regenerate.
1706         * rl78-decode.c: Regenerate.
1707
1708 2016-03-01  Nick Clifton  <nickc@redhat.com>
1709
1710         PR target/19747
1711         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1712
1713 2016-02-24  Renlin Li  <renlin.li@arm.com>
1714
1715         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1716         (print_insn_coprocessor): Support fp16 instructions.
1717
1718 2016-02-24  Renlin Li  <renlin.li@arm.com>
1719
1720         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1721         vminnm, vrint(mpna).
1722
1723 2016-02-24  Renlin Li  <renlin.li@arm.com>
1724
1725         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1726         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1727
1728 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1729
1730         * i386-dis.c (print_insn): Parenthesize expression to prevent
1731         truncated addresses.
1732         (OP_J): Likewise.
1733
1734 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1735             Janek van Oirschot  <jvanoirs@synopsys.com>
1736
1737         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1738         variable.
1739
1740 2016-02-04  Nick Clifton  <nickc@redhat.com>
1741
1742         PR target/19561
1743         * msp430-dis.c (print_insn_msp430): Add a special case for
1744         decoding an RRC instruction with the ZC bit set in the extension
1745         word.
1746
1747 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1748
1749         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1750         * epiphany-ibld.c: Regenerate.
1751         * fr30-ibld.c: Regenerate.
1752         * frv-ibld.c: Regenerate.
1753         * ip2k-ibld.c: Regenerate.
1754         * iq2000-ibld.c: Regenerate.
1755         * lm32-ibld.c: Regenerate.
1756         * m32c-ibld.c: Regenerate.
1757         * m32r-ibld.c: Regenerate.
1758         * mep-ibld.c: Regenerate.
1759         * mt-ibld.c: Regenerate.
1760         * or1k-ibld.c: Regenerate.
1761         * xc16x-ibld.c: Regenerate.
1762         * xstormy16-ibld.c: Regenerate.
1763
1764 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1765
1766         * epiphany-dis.c: Regenerated from latest cpu files.
1767
1768 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1769
1770         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1771         test bit.
1772
1773 2016-01-25  Renlin Li  <renlin.li@arm.com>
1774
1775         * arm-dis.c (mapping_symbol_for_insn): New function.
1776         (find_ifthen_state): Call mapping_symbol_for_insn().
1777
1778 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1779
1780         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1781         of MSR UAO immediate operand.
1782
1783 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1784
1785         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1786         instruction support.
1787
1788 2016-01-17  Alan Modra  <amodra@gmail.com>
1789
1790         * configure: Regenerate.
1791
1792 2016-01-14  Nick Clifton  <nickc@redhat.com>
1793
1794         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1795         instructions that can support stack pointer operations.
1796         * rl78-decode.c: Regenerate.
1797         * rl78-dis.c: Fix display of stack pointer in MOVW based
1798         instructions.
1799
1800 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1801
1802         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1803         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1804         erxtatus_el1 and erxaddr_el1.
1805
1806 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1807
1808         * arm-dis.c (arm_opcodes): Add "esb".
1809         (thumb_opcodes): Likewise.
1810
1811 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1812
1813         * ppc-opc.c <xscmpnedp>: Delete.
1814         <xvcmpnedp>: Likewise.
1815         <xvcmpnedp.>: Likewise.
1816         <xvcmpnesp>: Likewise.
1817         <xvcmpnesp.>: Likewise.
1818
1819 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1820
1821         PR gas/13050
1822         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1823         addition to ISA_A.
1824
1825 2016-01-01  Alan Modra  <amodra@gmail.com>
1826
1827         Update year range in copyright notice of all files.
1828
1829 For older changes see ChangeLog-2015
1830 \f
1831 Copyright (C) 2016 Free Software Foundation, Inc.
1832
1833 Copying and distribution of this file, with or without modification,
1834 are permitted in any medium without royalty provided the copyright
1835 notice and this notice are preserved.
1836
1837 Local Variables:
1838 mode: change-log
1839 left-margin: 8
1840 fill-column: 74
1841 version-control: never
1842 End: