opcodes/ChangeLog

   1 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-opc.c (insert_rbd): New function.
   4         (RBD): Define.
   5         (RBDdup): Likewise.
   6         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
   7         instructions.
   8
   9 2020-07-07  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
  12         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
  13         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
  14         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
  15         Delete.
  16         (putop): Handle "BW".
  17         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
  18         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
  19         and 0F3A3F ...
  20         * i386-dis-evex-prefix.h: ... here.
  21
  22 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
  25         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
  26         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
  27         VEX_W_0FXOP_09_83): New enumerators.
  28         (xop_table): Reference the above.
  29         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
  30         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
  31         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
  32         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
  33
  34 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-dis.c (EVEX_W_0F3838_P_1,
  37         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
  38         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
  39         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
  40         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
  41         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
  42         (putop): Centralize management of last[]. Delete SAVE_LAST.
  43         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
  44         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
  45         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
  46         * i386-dis-evex-prefix.h: here.
  47
  48 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
  51         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
  52         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
  53         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
  54         enumerators.
  55         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
  56         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
  57         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
  58         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
  59         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
  60         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
  61         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
  62         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
  63         these, respectively.
  64         * i386-dis-evex-len.h: Adjust comments.
  65         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
  66         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
  67         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
  68         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
  69         MOD_EVEX_0F385B_P_2_W_1 table entries.
  70         * i386-dis-evex-w.h: Reference mod_table[] for
  71         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
  72         EVEX_W_0F385B_P_2.
  73
  74 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
  77         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
  78         EXymm.
  79         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
  80         Likewise. Mark 256-bit entries invalid.
  81
  82 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
  85         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
  86         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
  87         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
  88         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
  89         PREFIX_EVEX_0F382B): Delete.
  90         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
  91         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
  92         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
  93         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
  94         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
  95         to ...
  96         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
  97         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
  98         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
  99         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
 100         respectively.
 101         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
 102         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
 103         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
 104         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
 105         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
 106         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
 107         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
 108         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
 109         PREFIX_EVEX_0F382B): Remove table entries.
 110         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
 111         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
 112         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
 113
 114 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
 117         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
 118         enumerators.
 119         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
 120         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
 121         EVEX_LEN_0F3A01_P_2_W_1 table entries.
 122         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
 123         entries.
 124
 125 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
 128         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
 129         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
 130         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
 131         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
 132         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
 133         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
 134         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
 135         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
 136         entries.
 137
 138 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
 141         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
 142         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
 143         respectively.
 144         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
 145         entries.
 146         * i386-dis-evex.h (evex_table): Reference VEX table entry for
 147         opcode 0F3A1D.
 148         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
 149         entry.
 150         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
 151
 152 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 155         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 156         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 157         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 158         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 159         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 160         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 161         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 162         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 163         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 164         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 165         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 166         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 167         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 168         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 169         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 170         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 171         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 172         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 173         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 174         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 175         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 176         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 177         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 178         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 179         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 180         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
 181         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
 182         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
 183         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
 184         (prefix_table): Add EXxEVexR to FMA table entries.
 185         (OP_Rounding): Move abort() invocation.
 186         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
 187         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
 188         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
 189         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
 190         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
 191         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
 192         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
 193         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
 194         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
 195         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
 196         0F3ACE, 0F3ACF.
 197         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
 198         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 199         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
 200         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
 201         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 202         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
 203         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
 204         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
 205         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 206         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
 207         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
 208         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
 209         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
 210         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
 211         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
 212         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
 213         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
 214         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
 215         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
 216         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
 217         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
 218         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
 219         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
 220         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
 221         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
 222         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
 223         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
 224         Delete table entries.
 225         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
 226         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
 227         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
 228         Likewise.
 229
 230 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 231
 232         * i386-dis.c (EXqScalarS): Delete.
 233         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
 234         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
 235
 236 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 237
 238         * i386-dis.c (safe-ctype.h): Include.
 239         (EXdScalar, EXqScalar): Delete.
 240         (d_scalar_mode, q_scalar_mode): Delete.
 241         (prefix_table, vex_len_table): Use EXxmm_md in place of
 242         EXdScalar and EXxmm_mq in place of EXqScalar.
 243         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
 244         d_scalar_mode and q_scalar_mode.
 245         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
 246         (vmovsd): Use EXxmm_mq.
 247
 248 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
 249
 250         PR 26204
 251         * arc-dis.c: Fix spelling mistake.
 252         * po/opcodes.pot: Regenerate.
 253
 254 2020-07-06  Nick Clifton  <nickc@redhat.com>
 255
 256         * po/pt_BR.po: Updated Brazilian Portugugese translation.
 257         * po/uk.po: Updated Ukranian translation.
 258
 259 2020-07-04  Nick Clifton  <nickc@redhat.com>
 260
 261         * configure: Regenerate.
 262         * po/opcodes.pot: Regenerate.
 263
 264 2020-07-04  Nick Clifton  <nickc@redhat.com>
 265
 266         Binutils 2.35 branch created.
 267
 268 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
 269
 270         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
 271         * i386-opc.h (VexSwapSources): New.
 272         (i386_opcode_modifier): Add vexswapsources.
 273         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
 274         with two source operands swapped.
 275         * i386-tbl.h: Regenerated.
 276
 277 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
 278
 279         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
 280         unprivileged CSR can also be initialized.
 281
 282 2020-06-29  Alan Modra  <amodra@gmail.com>
 283
 284         * arm-dis.c: Use C style comments.
 285         * cr16-opc.c: Likewise.
 286         * ft32-dis.c: Likewise.
 287         * moxie-opc.c: Likewise.
 288         * tic54x-dis.c: Likewise.
 289         * s12z-opc.c: Remove useless comment.
 290         * xgate-dis.c: Likewise.
 291
 292 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * i386-opc.tbl: Add a blank line.
 295
 296 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 297
 298         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
 299         (VecSIB128): Renamed to ...
 300         (VECSIB128): This.
 301         (VecSIB256): Renamed to ...
 302         (VECSIB256): This.
 303         (VecSIB512): Renamed to ...
 304         (VECSIB512): This.
 305         (VecSIB): Renamed to ...
 306         (SIB): This.
 307         (i386_opcode_modifier): Replace vecsib with sib.
 308         * i386-opc.tbl (VecSIB128): New.
 309         (VecSIB256): Likewise.
 310         (VecSIB512): Likewise.
 311         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
 312         and VecSIB512, respectively.
 313
 314 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-dis.c: Adjust description of I macro.
 317         (x86_64_table): Drop use of I.
 318         (float_mem): Replace use of I.
 319         (putop): Remove handling of I. Adjust setting/clearing of "alt".
 320
 321 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-dis.c: (print_insn): Avoid straight assignment to
 324         priv.orig_sizeflag when processing -M sub-options.
 325
 326 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-dis.c: Adjust description of J macro.
 329         (dis386, x86_64_table, mod_table): Replace J.
 330         (putop): Remove handling of J.
 331
 332 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 335
 336 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-dis.c: Adjust description of "LQ" macro.
 339         (dis386_twobyte): Use LQ for sysret.
 340         (putop): Adjust handling of LQ.
 341
 342 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 343
 344         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 345         * riscv-dis.c: Include elfxx-riscv.h.
 346
 347 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 348
 349         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 350
 351 2020-06-17  Lili Cui  <lili.cui@intel.com>
 352
 353         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 354
 355 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 356
 357         PR gas/26115
 358         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 359         * i386-opc.tbl: Likewise.
 360         * i386-tbl.h: Regenerated.
 361
 362 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 363
 364         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 365
 366 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 367
 368         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 369         (SR_CORE): Likewise.
 370         (SR_FEAT): Likewise.
 371         (SR_RNG): Likewise.
 372         (SR_V8_1): Likewise.
 373         (SR_V8_2): Likewise.
 374         (SR_V8_3): Likewise.
 375         (SR_V8_4): Likewise.
 376         (SR_PAN): Likewise.
 377         (SR_RAS): Likewise.
 378         (SR_SSBS): Likewise.
 379         (SR_SVE): Likewise.
 380         (SR_ID_PFR2): Likewise.
 381         (SR_PROFILE): Likewise.
 382         (SR_MEMTAG): Likewise.
 383         (SR_SCXTNUM): Likewise.
 384         (aarch64_sys_regs): Refactor to store feature information in the table.
 385         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 386         that now describe their own features.
 387         (aarch64_pstatefield_supported_p): Likewise.
 388
 389 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 390
 391         * i386-dis.c (prefix_table): Fix a typo in comments.
 392
 393 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 394
 395         * i386-dis.c (rex_ignored): Delete.
 396         (ckprefix): Drop rex_ignored initialization.
 397         (get_valid_dis386): Drop setting of rex_ignored.
 398         (print_insn): Drop checking of rex_ignored. Don't record data
 399         size prefix as used with VEX-and-alike encodings.
 400
 401 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 402
 403         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 404         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 405         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 406         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 407         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 408         VEX_0F12, and VEX_0F16.
 409         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 410         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 411         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 412         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 413         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 414         MOD_VEX_0F16_PREFIX_2 entries.
 415
 416 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 417
 418         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 419         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 420         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 421         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 422         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 423         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 424         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 425         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 426         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 427         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 428         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 429         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 430         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 431         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 432         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 433         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 434         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 435         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 436         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 437         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 438         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 439         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 440         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 441         EVEX_W_0FC6_P_2): Delete.
 442         (print_insn): Add EVEX.W vs embedded prefix consistency check
 443         to prefix validation.
 444         * i386-dis-evex.h (evex_table): Don't further descend for
 445         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 446         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 447         and 0F2B.
 448         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 449         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 450         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 451         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 452         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 453         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 454         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 455         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 456         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 457         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 458         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 459         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 460         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 461         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 462         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 463         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 464         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 465         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 466         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 467         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 468         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 469         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 470         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 471         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 472         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 473         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 474         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 475
 476 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 479         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 480         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 481         vmovmskpX.
 482         (print_insn): Drop pointless check against bad_opcode. Split
 483         prefix validation into legacy and VEX-and-alike parts.
 484         (putop): Re-work 'X' macro handling.
 485
 486 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-dis.c (MOD_0F51): Rename to ...
 489         (MOD_0F50): ... this.
 490
 491 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 492
 493         * arm-dis.c (arm_opcodes): Add dfb.
 494         (thumb32_opcodes): Add dfb.
 495
 496 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 497
 498         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 499
 500 2020-06-06  Alan Modra  <amodra@gmail.com>
 501
 502         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 503
 504 2020-06-05  Alan Modra  <amodra@gmail.com>
 505
 506         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 507         size is large enough.
 508
 509 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 510
 511         * disassemble.c (disassemble_init_for_target): Set endian_code for
 512         bpf targets.
 513         * bpf-desc.c: Regenerate.
 514         * bpf-opc.c: Likewise.
 515         * bpf-dis.c: Likewise.
 516
 517 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 518
 519         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 520         (cgen_put_insn_value): Likewise.
 521         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 522         * cgen-dis.in (print_insn): Likewise.
 523         * cgen-ibld.in (insert_1): Likewise.
 524         (insert_1): Likewise.
 525         (insert_insn_normal): Likewise.
 526         (extract_1): Likewise.
 527         * bpf-dis.c: Regenerate.
 528         * bpf-ibld.c: Likewise.
 529         * bpf-ibld.c: Likewise.
 530         * cgen-dis.in: Likewise.
 531         * cgen-ibld.in: Likewise.
 532         * cgen-opc.c: Likewise.
 533         * epiphany-dis.c: Likewise.
 534         * epiphany-ibld.c: Likewise.
 535         * fr30-dis.c: Likewise.
 536         * fr30-ibld.c: Likewise.
 537         * frv-dis.c: Likewise.
 538         * frv-ibld.c: Likewise.
 539         * ip2k-dis.c: Likewise.
 540         * ip2k-ibld.c: Likewise.
 541         * iq2000-dis.c: Likewise.
 542         * iq2000-ibld.c: Likewise.
 543         * lm32-dis.c: Likewise.
 544         * lm32-ibld.c: Likewise.
 545         * m32c-dis.c: Likewise.
 546         * m32c-ibld.c: Likewise.
 547         * m32r-dis.c: Likewise.
 548         * m32r-ibld.c: Likewise.
 549         * mep-dis.c: Likewise.
 550         * mep-ibld.c: Likewise.
 551         * mt-dis.c: Likewise.
 552         * mt-ibld.c: Likewise.
 553         * or1k-dis.c: Likewise.
 554         * or1k-ibld.c: Likewise.
 555         * xc16x-dis.c: Likewise.
 556         * xc16x-ibld.c: Likewise.
 557         * xstormy16-dis.c: Likewise.
 558         * xstormy16-ibld.c: Likewise.
 559
 560 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 561
 562         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 563         (print_insn_): Handle instruction endian.
 564         * bpf-dis.c: Regenerate.
 565         * bpf-desc.c: Regenerate.
 566         * epiphany-dis.c: Likewise.
 567         * epiphany-desc.c: Likewise.
 568         * fr30-dis.c: Likewise.
 569         * fr30-desc.c: Likewise.
 570         * frv-dis.c: Likewise.
 571         * frv-desc.c: Likewise.
 572         * ip2k-dis.c: Likewise.
 573         * ip2k-desc.c: Likewise.
 574         * iq2000-dis.c: Likewise.
 575         * iq2000-desc.c: Likewise.
 576         * lm32-dis.c: Likewise.
 577         * lm32-desc.c: Likewise.
 578         * m32c-dis.c: Likewise.
 579         * m32c-desc.c: Likewise.
 580         * m32r-dis.c: Likewise.
 581         * m32r-desc.c: Likewise.
 582         * mep-dis.c: Likewise.
 583         * mep-desc.c: Likewise.
 584         * mt-dis.c: Likewise.
 585         * mt-desc.c: Likewise.
 586         * or1k-dis.c: Likewise.
 587         * or1k-desc.c: Likewise.
 588         * xc16x-dis.c: Likewise.
 589         * xc16x-desc.c: Likewise.
 590         * xstormy16-dis.c: Likewise.
 591         * xstormy16-desc.c: Likewise.
 592
 593 2020-06-03  Nick Clifton  <nickc@redhat.com>
 594
 595         * po/sr.po: Updated Serbian translation.
 596
 597 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 598
 599         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 600         (riscv_get_priv_spec_class): Likewise.
 601
 602 2020-06-01  Alan Modra  <amodra@gmail.com>
 603
 604         * bpf-desc.c: Regenerate.
 605
 606 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 607             David Faust <david.faust@oracle.com>
 608
 609         * bpf-desc.c: Regenerate.
 610         * bpf-opc.h: Likewise.
 611         * bpf-opc.c: Likewise.
 612         * bpf-dis.c: Likewise.
 613
 614 2020-05-28  Alan Modra  <amodra@gmail.com>
 615
 616         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 617         values.
 618
 619 2020-05-28  Alan Modra  <amodra@gmail.com>
 620
 621         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 622         immediates.
 623         (print_insn_ns32k): Revert last change.
 624
 625 2020-05-28  Nick Clifton  <nickc@redhat.com>
 626
 627         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 628         static.
 629
 630 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 631
 632         Fix extraction of signed constants in nios2 disassembler (again).
 633
 634         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 635         extractions of signed fields.
 636
 637 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 638
 639         * s390-opc.txt: Relocate vector load/store instructions with
 640         additional alignment parameter and change architecture level
 641         constraint from z14 to z13.
 642
 643 2020-05-21  Alan Modra  <amodra@gmail.com>
 644
 645         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 646         * sparc-dis.c: Likewise.
 647         * tic4x-dis.c: Likewise.
 648         * xtensa-dis.c: Likewise.
 649         * bpf-desc.c: Regenerate.
 650         * epiphany-desc.c: Regenerate.
 651         * fr30-desc.c: Regenerate.
 652         * frv-desc.c: Regenerate.
 653         * ip2k-desc.c: Regenerate.
 654         * iq2000-desc.c: Regenerate.
 655         * lm32-desc.c: Regenerate.
 656         * m32c-desc.c: Regenerate.
 657         * m32r-desc.c: Regenerate.
 658         * mep-asm.c: Regenerate.
 659         * mep-desc.c: Regenerate.
 660         * mt-desc.c: Regenerate.
 661         * or1k-desc.c: Regenerate.
 662         * xc16x-desc.c: Regenerate.
 663         * xstormy16-desc.c: Regenerate.
 664
 665 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 666
 667         * riscv-opc.c (riscv_ext_version_table): The table used to store
 668         all information about the supported spec and the corresponding ISA
 669         versions.  Currently, only Zicsr is supported to verify the
 670         correctness of Z sub extension settings.  Others will be supported
 671         in the future patches.
 672         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 673         classes and the corresponding strings.
 674         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 675         spec class by giving a ISA spec string.
 676         * riscv-opc.c (struct priv_spec_t): New structure.
 677         (struct priv_spec_t priv_specs): List for all supported privilege spec
 678         classes and the corresponding strings.
 679         (riscv_get_priv_spec_class): New function.  Get the corresponding
 680         privilege spec class by giving a spec string.
 681         (riscv_get_priv_spec_name): New function.  Get the corresponding
 682         privilege spec string by giving a CSR version class.
 683         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 684         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 685         according to the chosen version.  Build a hash table riscv_csr_hash to
 686         store the valid CSR for the chosen pirv verison.  Dump the direct
 687         CSR address rather than it's name if it is invalid.
 688         (parse_riscv_dis_option_without_args): New function.  Parse the options
 689         without arguments.
 690         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 691         parse the options without arguments first, and then handle the options
 692         with arguments.  Add the new option -Mpriv-spec, which has argument.
 693         * riscv-dis.c (print_riscv_disassembler_options): Add description
 694         about the new OBJDUMP option.
 695
 696 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 697
 698         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 699         WC values on POWER10 sync, dcbf  and wait instructions.
 700         (insert_pl, extract_pl): New functions.
 701         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 702         (LS3): New , 3-bit L for sync.
 703         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 704         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 705         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 706         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 707         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 708         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 709         <wait>: Enable PL operand on POWER10.
 710         <dcbf>: Enable L3OPT operand on POWER10.
 711         <sync>: Enable SC2 operand on POWER10.
 712
 713 2020-05-19  Stafford Horne  <shorne@gmail.com>
 714
 715         PR 25184
 716         * or1k-asm.c: Regenerate.
 717         * or1k-desc.c: Regenerate.
 718         * or1k-desc.h: Regenerate.
 719         * or1k-dis.c: Regenerate.
 720         * or1k-ibld.c: Regenerate.
 721         * or1k-opc.c: Regenerate.
 722         * or1k-opc.h: Regenerate.
 723         * or1k-opinst.c: Regenerate.
 724
 725 2020-05-11  Alan Modra  <amodra@gmail.com>
 726
 727         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 728         xsmaxcqp, xsmincqp.
 729
 730 2020-05-11  Alan Modra  <amodra@gmail.com>
 731
 732         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 733         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 734
 735 2020-05-11  Alan Modra  <amodra@gmail.com>
 736
 737         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 738
 739 2020-05-11  Alan Modra  <amodra@gmail.com>
 740
 741         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 742         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 743
 744 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 745
 746         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 747         mnemonics.
 748
 749 2020-05-11  Alan Modra  <amodra@gmail.com>
 750
 751         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 752         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 753         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 754         (prefix_opcodes): Add xxeval.
 755
 756 2020-05-11  Alan Modra  <amodra@gmail.com>
 757
 758         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 759         xxgenpcvwm, xxgenpcvdm.
 760
 761 2020-05-11  Alan Modra  <amodra@gmail.com>
 762
 763         * ppc-opc.c (MP, VXVAM_MASK): Define.
 764         (VXVAPS_MASK): Use VXVA_MASK.
 765         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 766         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 767         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 768         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 769
 770 2020-05-11  Alan Modra  <amodra@gmail.com>
 771             Peter Bergner  <bergner@linux.ibm.com>
 772
 773         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 774         New functions.
 775         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 776         YMSK2, XA6a, XA6ap, XB6a entries.
 777         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 778         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 779         (PPCVSX4): Define.
 780         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 781         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 782         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 783         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 784         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 785         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 786         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 787         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 788         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 789         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 790         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 791         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 792         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 793         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 794
 795 2020-05-11  Alan Modra  <amodra@gmail.com>
 796
 797         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 798         (insert_xts, extract_xts): New functions.
 799         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 800         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 801         (VXRC_MASK, VXSH_MASK): Define.
 802         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 803         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 804         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 805         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 806         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 807         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 808         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 809
 810 2020-05-11  Alan Modra  <amodra@gmail.com>
 811
 812         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 813         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 814         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 815         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 816         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 817
 818 2020-05-11  Alan Modra  <amodra@gmail.com>
 819
 820         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 821         (XTP, DQXP, DQXP_MASK): Define.
 822         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 823         (prefix_opcodes): Add plxvp and pstxvp.
 824
 825 2020-05-11  Alan Modra  <amodra@gmail.com>
 826
 827         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 828         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 829         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 830
 831 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 832
 833         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 834
 835 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 836
 837         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 838         (L1OPT): Define.
 839         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 840
 841 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 842
 843         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 844
 845 2020-05-11  Alan Modra  <amodra@gmail.com>
 846
 847         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 848
 849 2020-05-11  Alan Modra  <amodra@gmail.com>
 850
 851         * ppc-dis.c (ppc_opts): Add "power10" entry.
 852         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 853         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 854
 855 2020-05-11  Nick Clifton  <nickc@redhat.com>
 856
 857         * po/fr.po: Updated French translation.
 858
 859 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 860
 861         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 862         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 863         (operand_general_constraint_met_p): validate
 864         AARCH64_OPND_UNDEFINED.
 865         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 866         for FLD_imm16_2.
 867         * aarch64-asm-2.c: Regenerated.
 868         * aarch64-dis-2.c: Regenerated.
 869         * aarch64-opc-2.c: Regenerated.
 870
 871 2020-04-29  Nick Clifton  <nickc@redhat.com>
 872
 873         PR 22699
 874         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 875         and SETRC insns.
 876
 877 2020-04-29  Nick Clifton  <nickc@redhat.com>
 878
 879         * po/sv.po: Updated Swedish translation.
 880
 881 2020-04-29  Nick Clifton  <nickc@redhat.com>
 882
 883         PR 22699
 884         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 885         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 886         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 887         IMM0_8U case.
 888
 889 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 890
 891         PR 25848
 892         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 893         cmpi only on m68020up and cpu32.
 894
 895 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 896
 897         * aarch64-asm.c (aarch64_ins_none): New.
 898         * aarch64-asm.h (ins_none): New declaration.
 899         * aarch64-dis.c (aarch64_ext_none): New.
 900         * aarch64-dis.h (ext_none): New declaration.
 901         * aarch64-opc.c (aarch64_print_operand): Update case for
 902         AARCH64_OPND_BARRIER_PSB.
 903         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 904         (AARCH64_OPERANDS): Update inserter/extracter for
 905         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 906         * aarch64-asm-2.c: Regenerated.
 907         * aarch64-dis-2.c: Regenerated.
 908         * aarch64-opc-2.c: Regenerated.
 909
 910 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 911
 912         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 913         (aarch64_feature_ras, RAS): Likewise.
 914         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 915         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 916         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 917         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 918         * aarch64-asm-2.c: Regenerated.
 919         * aarch64-dis-2.c: Regenerated.
 920         * aarch64-opc-2.c: Regenerated.
 921
 922 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 923
 924         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 925         (print_insn_neon): Support disassembly of conditional
 926         instructions.
 927
 928 2020-02-16  David Faust  <david.faust@oracle.com>
 929
 930         * bpf-desc.c: Regenerate.
 931         * bpf-desc.h: Likewise.
 932         * bpf-opc.c: Regenerate.
 933         * bpf-opc.h: Likewise.
 934
 935 2020-04-07  Lili Cui  <lili.cui@intel.com>
 936
 937         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 938         (prefix_table): New instructions (see prefixes above).
 939         (rm_table): Likewise
 940         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 941         CPU_ANY_TSXLDTRK_FLAGS.
 942         (cpu_flags): Add CpuTSXLDTRK.
 943         * i386-opc.h (enum): Add CpuTSXLDTRK.
 944         (i386_cpu_flags): Add cputsxldtrk.
 945         * i386-opc.tbl: Add XSUSPLDTRK insns.
 946         * i386-init.h: Regenerate.
 947         * i386-tbl.h: Likewise.
 948
 949 2020-04-02  Lili Cui  <lili.cui@intel.com>
 950
 951         * i386-dis.c (prefix_table): New instructions serialize.
 952         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 953         CPU_ANY_SERIALIZE_FLAGS.
 954         (cpu_flags): Add CpuSERIALIZE.
 955         * i386-opc.h (enum): Add CpuSERIALIZE.
 956         (i386_cpu_flags): Add cpuserialize.
 957         * i386-opc.tbl: Add SERIALIZE insns.
 958         * i386-init.h: Regenerate.
 959         * i386-tbl.h: Likewise.
 960
 961 2020-03-26  Alan Modra  <amodra@gmail.com>
 962
 963         * disassemble.h (opcodes_assert): Declare.
 964         (OPCODES_ASSERT): Define.
 965         * disassemble.c: Don't include assert.h.  Include opintl.h.
 966         (opcodes_assert): New function.
 967         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 968         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 969         calculate maxlen.  Omit insn decoding when insn length exceeds
 970         maxlen.  Exit from nibble loop when looking for E, before
 971         accessing next data byte.  Move processing of E outside loop.
 972         Replace tests of maxlen in loop with assertions.
 973
 974 2020-03-26  Alan Modra  <amodra@gmail.com>
 975
 976         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 977
 978 2020-03-25  Alan Modra  <amodra@gmail.com>
 979
 980         * z80-dis.c (suffix): Init mybuf.
 981
 982 2020-03-22  Alan Modra  <amodra@gmail.com>
 983
 984         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 985         successflly read from section.
 986
 987 2020-03-22  Alan Modra  <amodra@gmail.com>
 988
 989         * arc-dis.c (find_format): Use ISO C string concatenation rather
 990         than line continuation within a string.  Don't access needs_limm
 991         before testing opcode != NULL.
 992
 993 2020-03-22  Alan Modra  <amodra@gmail.com>
 994
 995         * ns32k-dis.c (print_insn_arg): Update comment.
 996         (print_insn_ns32k): Reduce size of index_offset array, and
 997         initialize, passing -1 to print_insn_arg for args that are not
 998         an index.  Don't exit arg loop early.  Abort on bad arg number.
 999
1000 2020-03-22  Alan Modra  <amodra@gmail.com>
1001
1002         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1003         * s12z-opc.c: Formatting.
1004         (operands_f): Return an int.
1005         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1006         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1007         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1008         (exg_sex_discrim): Likewise.
1009         (create_immediate_operand, create_bitfield_operand),
1010         (create_register_operand_with_size, create_register_all_operand),
1011         (create_register_all16_operand, create_simple_memory_operand),
1012         (create_memory_operand, create_memory_auto_operand): Don't
1013         segfault on malloc failure.
1014         (z_ext24_decode): Return an int status, negative on fail, zero
1015         on success.
1016         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1017         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1018         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1019         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1020         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1021         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1022         (loop_primitive_decode, shift_decode, psh_pul_decode),
1023         (bit_field_decode): Similarly.
1024         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
1025         to return value, update callers.
1026         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1027         Don't segfault on NULL operand.
1028         (decode_operation): Return OP_INVALID on first fail.
1029         (decode_s12z): Check all reads, returning -1 on fail.
1030
1031 2020-03-20  Alan Modra  <amodra@gmail.com>
1032
1033         * metag-dis.c (print_insn_metag): Don't ignore status from
1034         read_memory_func.
1035
1036 2020-03-20  Alan Modra  <amodra@gmail.com>
1037
1038         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1039         Initialize parts of buffer not written when handling a possible
1040         2-byte insn at end of section.  Don't attempt decoding of such
1041         an insn by the 4-byte machinery.
1042
1043 2020-03-20  Alan Modra  <amodra@gmail.com>
1044
1045         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1046         partially filled buffer.  Prevent lookup of 4-byte insns when
1047         only VLE 2-byte insns are possible due to section size.  Print
1048         ".word" rather than ".long" for 2-byte leftovers.
1049
1050 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
1051
1052         PR 25641
1053         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1054
1055 2020-03-13  Jan Beulich  <jbeulich@suse.com>
1056
1057         * i386-dis.c (X86_64_0D): Rename to ...
1058         (X86_64_0E): ... this.
1059
1060 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1061
1062         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1063         * Makefile.in: Regenerated.
1064
1065 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1066
1067         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1068         3-operand pseudos.
1069         * i386-tbl.h: Re-generate.
1070
1071 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1072
1073         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1074         vprot*, vpsha*, and vpshl*.
1075         * i386-tbl.h: Re-generate.
1076
1077 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1078
1079         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1080         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1081         * i386-tbl.h: Re-generate.
1082
1083 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1084
1085         * i386-gen.c (set_bitfield): Ignore zero-length field names.
1086         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1087         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1088         * i386-tbl.h: Re-generate.
1089
1090 2020-03-09  Jan Beulich  <jbeulich@suse.com>
1091
1092         * i386-gen.c (struct template_arg, struct template_instance,
1093         struct template_param, struct template, templates,
1094         parse_template, expand_templates): New.
1095         (process_i386_opcodes): Various local variables moved to
1096         expand_templates. Call parse_template and expand_templates.
1097         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1098         * i386-tbl.h: Re-generate.
1099
1100 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1101
1102         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1103         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1104         register and memory source templates. Replace VexW= by VexW*
1105         where applicable.
1106         * i386-tbl.h: Re-generate.
1107
1108 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1109
1110         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1111         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1112         * i386-tbl.h: Re-generate.
1113
1114 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1115
1116         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1117         * i386-tbl.h: Re-generate.
1118
1119 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1120
1121         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1122         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1123         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1124         VexW0 on SSE2AVX variants.
1125         (vmovq): Drop NoRex64 from XMM/XMM variants.
1126         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1127         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1128         applicable use VexW0.
1129         * i386-tbl.h: Re-generate.
1130
1131 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1132
1133         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1134         * i386-opc.h (Rex64): Delete.
1135         (struct i386_opcode_modifier): Remove rex64 field.
1136         * i386-opc.tbl (crc32): Drop Rex64.
1137         Replace Rex64 with Size64 everywhere else.
1138         * i386-tbl.h: Re-generate.
1139
1140 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1141
1142         * i386-dis.c (OP_E_memory): Exclude recording of used address
1143         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1144         addressed memory operands for MPX insns.
1145
1146 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1147
1148         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1149         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1150         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1151         (ptwrite): Split into non-64-bit and 64-bit forms.
1152         * i386-tbl.h: Re-generate.
1153
1154 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1155
1156         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1157         template.
1158         * i386-tbl.h: Re-generate.
1159
1160 2020-03-04  Jan Beulich  <jbeulich@suse.com>
1161
1162         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1163         (prefix_table): Move vmmcall here. Add vmgexit.
1164         (rm_table): Replace vmmcall entry by prefix_table[] escape.
1165         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1166         (cpu_flags): Add CpuSEV_ES entry.
1167         * i386-opc.h (CpuSEV_ES): New.
1168         (union i386_cpu_flags): Add cpusev_es field.
1169         * i386-opc.tbl (vmgexit): New.
1170         * i386-init.h, i386-tbl.h: Re-generate.
1171
1172 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1173
1174         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1175         with MnemonicSize.
1176         * i386-opc.h (IGNORESIZE): New.
1177         (DEFAULTSIZE): Likewise.
1178         (IgnoreSize): Removed.
1179         (DefaultSize): Likewise.
1180         (MnemonicSize): New.
1181         (i386_opcode_modifier): Replace ignoresize/defaultsize with
1182         mnemonicsize.
1183         * i386-opc.tbl (IgnoreSize): New.
1184         (DefaultSize): Likewise.
1185         * i386-tbl.h: Regenerated.
1186
1187 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1188
1189         PR 25627
1190         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1191         instructions.
1192
1193 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1194
1195         PR gas/25622
1196         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1197         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1198         * i386-tbl.h: Regenerated.
1199
1200 2020-02-26  Alan Modra  <amodra@gmail.com>
1201
1202         * aarch64-asm.c: Indent labels correctly.
1203         * aarch64-dis.c: Likewise.
1204         * aarch64-gen.c: Likewise.
1205         * aarch64-opc.c: Likewise.
1206         * alpha-dis.c: Likewise.
1207         * i386-dis.c: Likewise.
1208         * nds32-asm.c: Likewise.
1209         * nfp-dis.c: Likewise.
1210         * visium-dis.c: Likewise.
1211
1212 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
1213
1214         * arc-regs.h (int_vector_base): Make it available for all ARC
1215         CPUs.
1216
1217 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
1218
1219         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1220         changed.
1221
1222 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
1223
1224         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1225         c.mv/c.li if rs1 is zero.
1226
1227 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
1228
1229         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1230         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1231         CPU_POPCNT_FLAGS.
1232         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1233         * i386-opc.h (CpuABM): Removed.
1234         (CpuPOPCNT): New.
1235         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1236         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1237         popcnt.  Remove CpuABM from lzcnt.
1238         * i386-init.h: Regenerated.
1239         * i386-tbl.h: Likewise.
1240
1241 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1242
1243         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1244         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1245         VexW1 instead of open-coding them.
1246         * i386-tbl.h: Re-generate.
1247
1248 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1249
1250         * i386-opc.tbl (AddrPrefixOpReg): Define.
1251         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1252         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1253         templates. Drop NoRex64.
1254         * i386-tbl.h: Re-generate.
1255
1256 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1257
1258         PR gas/6518
1259         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1260         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1261         into Intel syntax instance (with Unpsecified) and AT&T one
1262         (without).
1263         (vcvtneps2bf16): Likewise, along with folding the two so far
1264         separate ones.
1265         * i386-tbl.h: Re-generate.
1266
1267 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1268
1269         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1270         CPU_ANY_SSE4A_FLAGS.
1271
1272 2020-02-17  Alan Modra  <amodra@gmail.com>
1273
1274         * i386-gen.c (cpu_flag_init): Correct last change.
1275
1276 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1277
1278         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1279         CPU_ANY_SSE4_FLAGS.
1280
1281 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1282
1283         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1284         (movzx): Likewise.
1285
1286 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1287
1288         PR gas/25438
1289         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1290         destination for Cpu64-only variant.
1291         (movzx): Fold patterns.
1292         * i386-tbl.h: Re-generate.
1293
1294 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1295
1296         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1297         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1298         CPU_ANY_SSE4_FLAGS entry.
1299         * i386-init.h: Re-generate.
1300
1301 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1302
1303         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1304         with Unspecified, making the present one AT&T syntax only.
1305         * i386-tbl.h: Re-generate.
1306
1307 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1308
1309         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1310         * i386-tbl.h: Re-generate.
1311
1312 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1313
1314         PR gas/24546
1315         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1316         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1317         Amd64 and Intel64 templates.
1318         (call, jmp): Likewise for far indirect variants. Dro
1319         Unspecified.
1320         * i386-tbl.h: Re-generate.
1321
1322 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1323
1324         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1325         * i386-opc.h (ShortForm): Delete.
1326         (struct i386_opcode_modifier): Remove shortform field.
1327         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1328         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1329         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1330         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1331         Drop ShortForm.
1332         * i386-tbl.h: Re-generate.
1333
1334 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1335
1336         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1337         fucompi): Drop ShortForm from operand-less templates.
1338         * i386-tbl.h: Re-generate.
1339
1340 2020-02-11  Alan Modra  <amodra@gmail.com>
1341
1342         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1343         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1344         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1345         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1346         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1347
1348 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1349
1350         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1351         (cde_opcodes): Add VCX* instructions.
1352
1353 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1354             Matthew Malcomson  <matthew.malcomson@arm.com>
1355
1356         * arm-dis.c (struct cdeopcode32): New.
1357         (CDE_OPCODE): New macro.
1358         (cde_opcodes): New disassembly table.
1359         (regnames): New option to table.
1360         (cde_coprocs): New global variable.
1361         (print_insn_cde): New
1362         (print_insn_thumb32): Use print_insn_cde.
1363         (parse_arm_disassembler_options): Parse coprocN args.
1364
1365 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1366
1367         PR gas/25516
1368         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1369         with ISA64.
1370         * i386-opc.h (AMD64): Removed.
1371         (Intel64): Likewose.
1372         (AMD64): New.
1373         (INTEL64): Likewise.
1374         (INTEL64ONLY): Likewise.
1375         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1376         * i386-opc.tbl (Amd64): New.
1377         (Intel64): Likewise.
1378         (Intel64Only): Likewise.
1379         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1380         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1381         * i386-tbl.h: Regenerated.
1382
1383 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1384
1385         PR 25469
1386         * z80-dis.c: Add support for GBZ80 opcodes.
1387
1388 2020-02-04  Alan Modra  <amodra@gmail.com>
1389
1390         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1391
1392 2020-02-03  Alan Modra  <amodra@gmail.com>
1393
1394         * m32c-ibld.c: Regenerate.
1395
1396 2020-02-01  Alan Modra  <amodra@gmail.com>
1397
1398         * frv-ibld.c: Regenerate.
1399
1400 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1401
1402         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1403         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1404         (OP_E_memory): Replace xmm_mdq_mode case label by
1405         vex_scalar_w_dq_mode one.
1406         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1407
1408 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1409
1410         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1411         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1412         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1413         (intel_operand_size): Drop vex_w_dq_mode case label.
1414
1415 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1416
1417         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1418         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1419
1420 2020-01-30  Alan Modra  <amodra@gmail.com>
1421
1422         * m32c-ibld.c: Regenerate.
1423
1424 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1425
1426         * bpf-opc.c: Regenerate.
1427
1428 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1429
1430         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1431         (dis386): Use them to replace C2/C3 table entries.
1432         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1433         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1434         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1435         * i386-tbl.h: Re-generate.
1436
1437 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1438
1439         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1440         forms.
1441         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1442         DefaultSize.
1443         * i386-tbl.h: Re-generate.
1444
1445 2020-01-30  Alan Modra  <amodra@gmail.com>
1446
1447         * tic4x-dis.c (tic4x_dp): Make unsigned.
1448
1449 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1450             Jan Beulich  <jbeulich@suse.com>
1451
1452         PR binutils/25445
1453         * i386-dis.c (MOVSXD_Fixup): New function.
1454         (movsxd_mode): New enum.
1455         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1456         (intel_operand_size): Handle movsxd_mode.
1457         (OP_E_register): Likewise.
1458         (OP_G): Likewise.
1459         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1460         register on movsxd.  Add movsxd with 16-bit destination register
1461         for AMD64 and Intel64 ISAs.
1462         * i386-tbl.h: Regenerated.
1463
1464 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1465
1466         PR 25403
1467         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1468         * aarch64-asm-2.c: Regenerate
1469         * aarch64-dis-2.c: Likewise.
1470         * aarch64-opc-2.c: Likewise.
1471
1472 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1473
1474         * i386-opc.tbl (sysret): Drop DefaultSize.
1475         * i386-tbl.h: Re-generate.
1476
1477 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1478
1479         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1480         Dword.
1481         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1482         * i386-tbl.h: Re-generate.
1483
1484 2020-01-20  Nick Clifton  <nickc@redhat.com>
1485
1486         * po/de.po: Updated German translation.
1487         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1488         * po/uk.po: Updated Ukranian translation.
1489
1490 2020-01-20  Alan Modra  <amodra@gmail.com>
1491
1492         * hppa-dis.c (fput_const): Remove useless cast.
1493
1494 2020-01-20  Alan Modra  <amodra@gmail.com>
1495
1496         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1497
1498 2020-01-18  Nick Clifton  <nickc@redhat.com>
1499
1500         * configure: Regenerate.
1501         * po/opcodes.pot: Regenerate.
1502
1503 2020-01-18  Nick Clifton  <nickc@redhat.com>
1504
1505         Binutils 2.34 branch created.
1506
1507 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1508
1509         * opintl.h: Fix spelling error (seperate).
1510
1511 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1512
1513         * i386-opc.tbl: Add {vex} pseudo prefix.
1514         * i386-tbl.h: Regenerated.
1515
1516 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1517
1518         PR 25376
1519         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1520         (neon_opcodes): Likewise.
1521         (select_arm_features): Make sure we enable MVE bits when selecting
1522         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1523         any architecture.
1524
1525 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1526
1527         * i386-opc.tbl: Drop stale comment from XOP section.
1528
1529 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1530
1531         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1532         (extractps): Add VexWIG to SSE2AVX forms.
1533         * i386-tbl.h: Re-generate.
1534
1535 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1536
1537         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1538         Size64 from and use VexW1 on SSE2AVX forms.
1539         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1540         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1541         * i386-tbl.h: Re-generate.
1542
1543 2020-01-15  Alan Modra  <amodra@gmail.com>
1544
1545         * tic4x-dis.c (tic4x_version): Make unsigned long.
1546         (optab, optab_special, registernames): New file scope vars.
1547         (tic4x_print_register): Set up registernames rather than
1548         malloc'd registertable.
1549         (tic4x_disassemble): Delete optable and optable_special.  Use
1550         optab and optab_special instead.  Throw away old optab,
1551         optab_special and registernames when info->mach changes.
1552
1553 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1554
1555         PR 25377
1556         * z80-dis.c (suffix): Use .db instruction to generate double
1557         prefix.
1558
1559 2020-01-14  Alan Modra  <amodra@gmail.com>
1560
1561         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1562         values to unsigned before shifting.
1563
1564 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1565
1566         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1567         flow instructions.
1568         (print_insn_thumb16, print_insn_thumb32): Likewise.
1569         (print_insn): Initialize the insn info.
1570         * i386-dis.c (print_insn): Initialize the insn info fields, and
1571         detect jumps.
1572
1573 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1574
1575         * arc-opc.c (C_NE): Make it required.
1576
1577 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1578
1579         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1580         reserved register name.
1581
1582 2020-01-13  Alan Modra  <amodra@gmail.com>
1583
1584         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1585         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1586
1587 2020-01-13  Alan Modra  <amodra@gmail.com>
1588
1589         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1590         result of wasm_read_leb128 in a uint64_t and check that bits
1591         are not lost when copying to other locals.  Use uint32_t for
1592         most locals.  Use PRId64 when printing int64_t.
1593
1594 2020-01-13  Alan Modra  <amodra@gmail.com>
1595
1596         * score-dis.c: Formatting.
1597         * score7-dis.c: Formatting.
1598
1599 2020-01-13  Alan Modra  <amodra@gmail.com>
1600
1601         * score-dis.c (print_insn_score48): Use unsigned variables for
1602         unsigned values.  Don't left shift negative values.
1603         (print_insn_score32): Likewise.
1604         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1605
1606 2020-01-13  Alan Modra  <amodra@gmail.com>
1607
1608         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1609
1610 2020-01-13  Alan Modra  <amodra@gmail.com>
1611
1612         * fr30-ibld.c: Regenerate.
1613
1614 2020-01-13  Alan Modra  <amodra@gmail.com>
1615
1616         * xgate-dis.c (print_insn): Don't left shift signed value.
1617         (ripBits): Formatting, use 1u.
1618
1619 2020-01-10  Alan Modra  <amodra@gmail.com>
1620
1621         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1622         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1623
1624 2020-01-10  Alan Modra  <amodra@gmail.com>
1625
1626         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1627         and XRREG value earlier to avoid a shift with negative exponent.
1628         * m10200-dis.c (disassemble): Similarly.
1629
1630 2020-01-09  Nick Clifton  <nickc@redhat.com>
1631
1632         PR 25224
1633         * z80-dis.c (ld_ii_ii): Use correct cast.
1634
1635 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1636
1637         PR 25224
1638         * z80-dis.c (ld_ii_ii): Use character constant when checking
1639         opcode byte value.
1640
1641 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1642
1643         * i386-dis.c (SEP_Fixup): New.
1644         (SEP): Define.
1645         (dis386_twobyte): Use it for sysenter/sysexit.
1646         (enum x86_64_isa): Change amd64 enumerator to value 1.
1647         (OP_J): Compare isa64 against intel64 instead of amd64.
1648         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1649         forms.
1650         * i386-tbl.h: Re-generate.
1651
1652 2020-01-08  Alan Modra  <amodra@gmail.com>
1653
1654         * z8k-dis.c: Include libiberty.h
1655         (instr_data_s): Make max_fetched unsigned.
1656         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1657         Don't exceed byte_info bounds.
1658         (output_instr): Make num_bytes unsigned.
1659         (unpack_instr): Likewise for nibl_count and loop.
1660         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1661         idx unsigned.
1662         * z8k-opc.h: Regenerate.
1663
1664 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1665
1666         * arc-tbl.h (llock): Use 'LLOCK' as class.
1667         (llockd): Likewise.
1668         (scond): Use 'SCOND' as class.
1669         (scondd): Likewise.
1670         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1671         (scondd): Likewise.
1672
1673 2020-01-06  Alan Modra  <amodra@gmail.com>
1674
1675         * m32c-ibld.c: Regenerate.
1676
1677 2020-01-06  Alan Modra  <amodra@gmail.com>
1678
1679         PR 25344
1680         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1681         Peek at next byte to prevent recursion on repeated prefix bytes.
1682         Ensure uninitialised "mybuf" is not accessed.
1683         (print_insn_z80): Don't zero n_fetch and n_used here,..
1684         (print_insn_z80_buf): ..do it here instead.
1685
1686 2020-01-04  Alan Modra  <amodra@gmail.com>
1687
1688         * m32r-ibld.c: Regenerate.
1689
1690 2020-01-04  Alan Modra  <amodra@gmail.com>
1691
1692         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1693
1694 2020-01-04  Alan Modra  <amodra@gmail.com>
1695
1696         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1697
1698 2020-01-04  Alan Modra  <amodra@gmail.com>
1699
1700         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1701
1702 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1703
1704         * aarch64-tbl.h (aarch64_opcode_table): Use
1705         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1706
1707 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1708
1709         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1710         forms of SUDOT and USDOT.
1711
1712 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1713
1714         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1715         uzip{1,2}.
1716         * opcodes/aarch64-dis-2.c: Re-generate.
1717
1718 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1719
1720         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1721         FMMLA encoding.
1722         * opcodes/aarch64-dis-2.c: Re-generate.
1723
1724 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1725
1726         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1727
1728 2020-01-01  Alan Modra  <amodra@gmail.com>
1729
1730         Update year range in copyright notice of all files.
1731
1732 For older changes see ChangeLog-2019
1733 \f
1734 Copyright (C) 2020 Free Software Foundation, Inc.
1735
1736 Copying and distribution of this file, with or without modification,
1737 are permitted in any medium without royalty provided the copyright
1738 notice and this notice are preserved.
1739
1740 Local Variables:
1741 mode: change-log
1742 left-margin: 8
1743 fill-column: 74
1744 version-control: never
1745 End: