opcodes/ChangeLog

   1 2020-05-11  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
   4         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
   5         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
   6
   7 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
   8
   9         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
  10
  11 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  12
  13         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
  14         (L1OPT): Define.
  15         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
  16
  17 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  18
  19         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
  20
  21 2020-05-11  Alan Modra  <amodra@gmail.com>
  22
  23         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
  24
  25 2020-05-11  Alan Modra  <amodra@gmail.com>
  26
  27         * ppc-dis.c (ppc_opts): Add "power10" entry.
  28         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
  29         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
  30
  31 2020-05-11  Nick Clifton  <nickc@redhat.com>
  32
  33         * po/fr.po: Updated French translation.
  34
  35 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
  36
  37         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
  38         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
  39         (operand_general_constraint_met_p): validate
  40         AARCH64_OPND_UNDEFINED.
  41         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
  42         for FLD_imm16_2.
  43         * aarch64-asm-2.c: Regenerated.
  44         * aarch64-dis-2.c: Regenerated.
  45         * aarch64-opc-2.c: Regenerated.
  46
  47 2020-04-29  Nick Clifton  <nickc@redhat.com>
  48
  49         PR 22699
  50         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
  51         and SETRC insns.
  52
  53 2020-04-29  Nick Clifton  <nickc@redhat.com>
  54
  55         * po/sv.po: Updated Swedish translation.
  56
  57 2020-04-29  Nick Clifton  <nickc@redhat.com>
  58
  59         PR 22699
  60         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
  61         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
  62         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
  63         IMM0_8U case.
  64
  65 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
  66
  67         PR 25848
  68         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
  69         cmpi only on m68020up and cpu32.
  70
  71 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  72
  73         * aarch64-asm.c (aarch64_ins_none): New.
  74         * aarch64-asm.h (ins_none): New declaration.
  75         * aarch64-dis.c (aarch64_ext_none): New.
  76         * aarch64-dis.h (ext_none): New declaration.
  77         * aarch64-opc.c (aarch64_print_operand): Update case for
  78         AARCH64_OPND_BARRIER_PSB.
  79         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  80         (AARCH64_OPERANDS): Update inserter/extracter for
  81         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  82         * aarch64-asm-2.c: Regenerated.
  83         * aarch64-dis-2.c: Regenerated.
  84         * aarch64-opc-2.c: Regenerated.
  85
  86 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  87
  88         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  89         (aarch64_feature_ras, RAS): Likewise.
  90         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  91         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  92         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
  93         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
  94         * aarch64-asm-2.c: Regenerated.
  95         * aarch64-dis-2.c: Regenerated.
  96         * aarch64-opc-2.c: Regenerated.
  97
  98 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  99
 100         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 101         (print_insn_neon): Support disassembly of conditional
 102         instructions.
 103
 104 2020-02-16  David Faust  <david.faust@oracle.com>
 105
 106         * bpf-desc.c: Regenerate.
 107         * bpf-desc.h: Likewise.
 108         * bpf-opc.c: Regenerate.
 109         * bpf-opc.h: Likewise.
 110
 111 2020-04-07  Lili Cui  <lili.cui@intel.com>
 112
 113         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 114         (prefix_table): New instructions (see prefixes above).
 115         (rm_table): Likewise
 116         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 117         CPU_ANY_TSXLDTRK_FLAGS.
 118         (cpu_flags): Add CpuTSXLDTRK.
 119         * i386-opc.h (enum): Add CpuTSXLDTRK.
 120         (i386_cpu_flags): Add cputsxldtrk.
 121         * i386-opc.tbl: Add XSUSPLDTRK insns.
 122         * i386-init.h: Regenerate.
 123         * i386-tbl.h: Likewise.
 124
 125 2020-04-02  Lili Cui  <lili.cui@intel.com>
 126
 127         * i386-dis.c (prefix_table): New instructions serialize.
 128         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 129         CPU_ANY_SERIALIZE_FLAGS.
 130         (cpu_flags): Add CpuSERIALIZE.
 131         * i386-opc.h (enum): Add CpuSERIALIZE.
 132         (i386_cpu_flags): Add cpuserialize.
 133         * i386-opc.tbl: Add SERIALIZE insns.
 134         * i386-init.h: Regenerate.
 135         * i386-tbl.h: Likewise.
 136
 137 2020-03-26  Alan Modra  <amodra@gmail.com>
 138
 139         * disassemble.h (opcodes_assert): Declare.
 140         (OPCODES_ASSERT): Define.
 141         * disassemble.c: Don't include assert.h.  Include opintl.h.
 142         (opcodes_assert): New function.
 143         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 144         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 145         calculate maxlen.  Omit insn decoding when insn length exceeds
 146         maxlen.  Exit from nibble loop when looking for E, before
 147         accessing next data byte.  Move processing of E outside loop.
 148         Replace tests of maxlen in loop with assertions.
 149
 150 2020-03-26  Alan Modra  <amodra@gmail.com>
 151
 152         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 153
 154 2020-03-25  Alan Modra  <amodra@gmail.com>
 155
 156         * z80-dis.c (suffix): Init mybuf.
 157
 158 2020-03-22  Alan Modra  <amodra@gmail.com>
 159
 160         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 161         successflly read from section.
 162
 163 2020-03-22  Alan Modra  <amodra@gmail.com>
 164
 165         * arc-dis.c (find_format): Use ISO C string concatenation rather
 166         than line continuation within a string.  Don't access needs_limm
 167         before testing opcode != NULL.
 168
 169 2020-03-22  Alan Modra  <amodra@gmail.com>
 170
 171         * ns32k-dis.c (print_insn_arg): Update comment.
 172         (print_insn_ns32k): Reduce size of index_offset array, and
 173         initialize, passing -1 to print_insn_arg for args that are not
 174         an index.  Don't exit arg loop early.  Abort on bad arg number.
 175
 176 2020-03-22  Alan Modra  <amodra@gmail.com>
 177
 178         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 179         * s12z-opc.c: Formatting.
 180         (operands_f): Return an int.
 181         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 182         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 183         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 184         (exg_sex_discrim): Likewise.
 185         (create_immediate_operand, create_bitfield_operand),
 186         (create_register_operand_with_size, create_register_all_operand),
 187         (create_register_all16_operand, create_simple_memory_operand),
 188         (create_memory_operand, create_memory_auto_operand): Don't
 189         segfault on malloc failure.
 190         (z_ext24_decode): Return an int status, negative on fail, zero
 191         on success.
 192         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 193         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 194         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 195         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 196         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 197         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 198         (loop_primitive_decode, shift_decode, psh_pul_decode),
 199         (bit_field_decode): Similarly.
 200         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 201         to return value, update callers.
 202         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 203         Don't segfault on NULL operand.
 204         (decode_operation): Return OP_INVALID on first fail.
 205         (decode_s12z): Check all reads, returning -1 on fail.
 206
 207 2020-03-20  Alan Modra  <amodra@gmail.com>
 208
 209         * metag-dis.c (print_insn_metag): Don't ignore status from
 210         read_memory_func.
 211
 212 2020-03-20  Alan Modra  <amodra@gmail.com>
 213
 214         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 215         Initialize parts of buffer not written when handling a possible
 216         2-byte insn at end of section.  Don't attempt decoding of such
 217         an insn by the 4-byte machinery.
 218
 219 2020-03-20  Alan Modra  <amodra@gmail.com>
 220
 221         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 222         partially filled buffer.  Prevent lookup of 4-byte insns when
 223         only VLE 2-byte insns are possible due to section size.  Print
 224         ".word" rather than ".long" for 2-byte leftovers.
 225
 226 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 227
 228         PR 25641
 229         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 230
 231 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-dis.c (X86_64_0D): Rename to ...
 234         (X86_64_0E): ... this.
 235
 236 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 237
 238         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 239         * Makefile.in: Regenerated.
 240
 241 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 244         3-operand pseudos.
 245         * i386-tbl.h: Re-generate.
 246
 247 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 250         vprot*, vpsha*, and vpshl*.
 251         * i386-tbl.h: Re-generate.
 252
 253 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 254
 255         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 256         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 257         * i386-tbl.h: Re-generate.
 258
 259 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 262         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 263         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 264         * i386-tbl.h: Re-generate.
 265
 266 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-gen.c (struct template_arg, struct template_instance,
 269         struct template_param, struct template, templates,
 270         parse_template, expand_templates): New.
 271         (process_i386_opcodes): Various local variables moved to
 272         expand_templates. Call parse_template and expand_templates.
 273         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 274         * i386-tbl.h: Re-generate.
 275
 276 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 279         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 280         register and memory source templates. Replace VexW= by VexW*
 281         where applicable.
 282         * i386-tbl.h: Re-generate.
 283
 284 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 285
 286         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 287         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 288         * i386-tbl.h: Re-generate.
 289
 290 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 293         * i386-tbl.h: Re-generate.
 294
 295 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 296
 297         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 298         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 299         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 300         VexW0 on SSE2AVX variants.
 301         (vmovq): Drop NoRex64 from XMM/XMM variants.
 302         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 303         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 304         applicable use VexW0.
 305         * i386-tbl.h: Re-generate.
 306
 307 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 310         * i386-opc.h (Rex64): Delete.
 311         (struct i386_opcode_modifier): Remove rex64 field.
 312         * i386-opc.tbl (crc32): Drop Rex64.
 313         Replace Rex64 with Size64 everywhere else.
 314         * i386-tbl.h: Re-generate.
 315
 316 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-dis.c (OP_E_memory): Exclude recording of used address
 319         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 320         addressed memory operands for MPX insns.
 321
 322 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 323
 324         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 325         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 326         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 327         (ptwrite): Split into non-64-bit and 64-bit forms.
 328         * i386-tbl.h: Re-generate.
 329
 330 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 333         template.
 334         * i386-tbl.h: Re-generate.
 335
 336 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 339         (prefix_table): Move vmmcall here. Add vmgexit.
 340         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 341         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 342         (cpu_flags): Add CpuSEV_ES entry.
 343         * i386-opc.h (CpuSEV_ES): New.
 344         (union i386_cpu_flags): Add cpusev_es field.
 345         * i386-opc.tbl (vmgexit): New.
 346         * i386-init.h, i386-tbl.h: Re-generate.
 347
 348 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 349
 350         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 351         with MnemonicSize.
 352         * i386-opc.h (IGNORESIZE): New.
 353         (DEFAULTSIZE): Likewise.
 354         (IgnoreSize): Removed.
 355         (DefaultSize): Likewise.
 356         (MnemonicSize): New.
 357         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 358         mnemonicsize.
 359         * i386-opc.tbl (IgnoreSize): New.
 360         (DefaultSize): Likewise.
 361         * i386-tbl.h: Regenerated.
 362
 363 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 364
 365         PR 25627
 366         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 367         instructions.
 368
 369 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 370
 371         PR gas/25622
 372         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 373         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 374         * i386-tbl.h: Regenerated.
 375
 376 2020-02-26  Alan Modra  <amodra@gmail.com>
 377
 378         * aarch64-asm.c: Indent labels correctly.
 379         * aarch64-dis.c: Likewise.
 380         * aarch64-gen.c: Likewise.
 381         * aarch64-opc.c: Likewise.
 382         * alpha-dis.c: Likewise.
 383         * i386-dis.c: Likewise.
 384         * nds32-asm.c: Likewise.
 385         * nfp-dis.c: Likewise.
 386         * visium-dis.c: Likewise.
 387
 388 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 389
 390         * arc-regs.h (int_vector_base): Make it available for all ARC
 391         CPUs.
 392
 393 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 394
 395         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 396         changed.
 397
 398 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 399
 400         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 401         c.mv/c.li if rs1 is zero.
 402
 403 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 404
 405         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 406         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 407         CPU_POPCNT_FLAGS.
 408         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 409         * i386-opc.h (CpuABM): Removed.
 410         (CpuPOPCNT): New.
 411         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 412         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 413         popcnt.  Remove CpuABM from lzcnt.
 414         * i386-init.h: Regenerated.
 415         * i386-tbl.h: Likewise.
 416
 417 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 418
 419         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 420         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 421         VexW1 instead of open-coding them.
 422         * i386-tbl.h: Re-generate.
 423
 424 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 425
 426         * i386-opc.tbl (AddrPrefixOpReg): Define.
 427         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 428         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 429         templates. Drop NoRex64.
 430         * i386-tbl.h: Re-generate.
 431
 432 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 433
 434         PR gas/6518
 435         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 436         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 437         into Intel syntax instance (with Unpsecified) and AT&T one
 438         (without).
 439         (vcvtneps2bf16): Likewise, along with folding the two so far
 440         separate ones.
 441         * i386-tbl.h: Re-generate.
 442
 443 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 444
 445         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 446         CPU_ANY_SSE4A_FLAGS.
 447
 448 2020-02-17  Alan Modra  <amodra@gmail.com>
 449
 450         * i386-gen.c (cpu_flag_init): Correct last change.
 451
 452 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 453
 454         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 455         CPU_ANY_SSE4_FLAGS.
 456
 457 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 458
 459         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 460         (movzx): Likewise.
 461
 462 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 463
 464         PR gas/25438
 465         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 466         destination for Cpu64-only variant.
 467         (movzx): Fold patterns.
 468         * i386-tbl.h: Re-generate.
 469
 470 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 473         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 474         CPU_ANY_SSE4_FLAGS entry.
 475         * i386-init.h: Re-generate.
 476
 477 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 478
 479         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 480         with Unspecified, making the present one AT&T syntax only.
 481         * i386-tbl.h: Re-generate.
 482
 483 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 484
 485         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 486         * i386-tbl.h: Re-generate.
 487
 488 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 489
 490         PR gas/24546
 491         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 492         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 493         Amd64 and Intel64 templates.
 494         (call, jmp): Likewise for far indirect variants. Dro
 495         Unspecified.
 496         * i386-tbl.h: Re-generate.
 497
 498 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 501         * i386-opc.h (ShortForm): Delete.
 502         (struct i386_opcode_modifier): Remove shortform field.
 503         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 504         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 505         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 506         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 507         Drop ShortForm.
 508         * i386-tbl.h: Re-generate.
 509
 510 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 513         fucompi): Drop ShortForm from operand-less templates.
 514         * i386-tbl.h: Re-generate.
 515
 516 2020-02-11  Alan Modra  <amodra@gmail.com>
 517
 518         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 519         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 520         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 521         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 522         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 523
 524 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 525
 526         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 527         (cde_opcodes): Add VCX* instructions.
 528
 529 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 530             Matthew Malcomson  <matthew.malcomson@arm.com>
 531
 532         * arm-dis.c (struct cdeopcode32): New.
 533         (CDE_OPCODE): New macro.
 534         (cde_opcodes): New disassembly table.
 535         (regnames): New option to table.
 536         (cde_coprocs): New global variable.
 537         (print_insn_cde): New
 538         (print_insn_thumb32): Use print_insn_cde.
 539         (parse_arm_disassembler_options): Parse coprocN args.
 540
 541 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 542
 543         PR gas/25516
 544         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 545         with ISA64.
 546         * i386-opc.h (AMD64): Removed.
 547         (Intel64): Likewose.
 548         (AMD64): New.
 549         (INTEL64): Likewise.
 550         (INTEL64ONLY): Likewise.
 551         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 552         * i386-opc.tbl (Amd64): New.
 553         (Intel64): Likewise.
 554         (Intel64Only): Likewise.
 555         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 556         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 557         * i386-tbl.h: Regenerated.
 558
 559 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 560
 561         PR 25469
 562         * z80-dis.c: Add support for GBZ80 opcodes.
 563
 564 2020-02-04  Alan Modra  <amodra@gmail.com>
 565
 566         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 567
 568 2020-02-03  Alan Modra  <amodra@gmail.com>
 569
 570         * m32c-ibld.c: Regenerate.
 571
 572 2020-02-01  Alan Modra  <amodra@gmail.com>
 573
 574         * frv-ibld.c: Regenerate.
 575
 576 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 577
 578         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 579         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 580         (OP_E_memory): Replace xmm_mdq_mode case label by
 581         vex_scalar_w_dq_mode one.
 582         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 583
 584 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 587         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 588         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 589         (intel_operand_size): Drop vex_w_dq_mode case label.
 590
 591 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 592
 593         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 594         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 595
 596 2020-01-30  Alan Modra  <amodra@gmail.com>
 597
 598         * m32c-ibld.c: Regenerate.
 599
 600 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 601
 602         * bpf-opc.c: Regenerate.
 603
 604 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 605
 606         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 607         (dis386): Use them to replace C2/C3 table entries.
 608         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 609         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 610         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 611         * i386-tbl.h: Re-generate.
 612
 613 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 614
 615         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 616         forms.
 617         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 618         DefaultSize.
 619         * i386-tbl.h: Re-generate.
 620
 621 2020-01-30  Alan Modra  <amodra@gmail.com>
 622
 623         * tic4x-dis.c (tic4x_dp): Make unsigned.
 624
 625 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 626             Jan Beulich  <jbeulich@suse.com>
 627
 628         PR binutils/25445
 629         * i386-dis.c (MOVSXD_Fixup): New function.
 630         (movsxd_mode): New enum.
 631         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 632         (intel_operand_size): Handle movsxd_mode.
 633         (OP_E_register): Likewise.
 634         (OP_G): Likewise.
 635         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 636         register on movsxd.  Add movsxd with 16-bit destination register
 637         for AMD64 and Intel64 ISAs.
 638         * i386-tbl.h: Regenerated.
 639
 640 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 641
 642         PR 25403
 643         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 644         * aarch64-asm-2.c: Regenerate
 645         * aarch64-dis-2.c: Likewise.
 646         * aarch64-opc-2.c: Likewise.
 647
 648 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 649
 650         * i386-opc.tbl (sysret): Drop DefaultSize.
 651         * i386-tbl.h: Re-generate.
 652
 653 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 654
 655         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 656         Dword.
 657         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 658         * i386-tbl.h: Re-generate.
 659
 660 2020-01-20  Nick Clifton  <nickc@redhat.com>
 661
 662         * po/de.po: Updated German translation.
 663         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 664         * po/uk.po: Updated Ukranian translation.
 665
 666 2020-01-20  Alan Modra  <amodra@gmail.com>
 667
 668         * hppa-dis.c (fput_const): Remove useless cast.
 669
 670 2020-01-20  Alan Modra  <amodra@gmail.com>
 671
 672         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 673
 674 2020-01-18  Nick Clifton  <nickc@redhat.com>
 675
 676         * configure: Regenerate.
 677         * po/opcodes.pot: Regenerate.
 678
 679 2020-01-18  Nick Clifton  <nickc@redhat.com>
 680
 681         Binutils 2.34 branch created.
 682
 683 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 684
 685         * opintl.h: Fix spelling error (seperate).
 686
 687 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 688
 689         * i386-opc.tbl: Add {vex} pseudo prefix.
 690         * i386-tbl.h: Regenerated.
 691
 692 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 693
 694         PR 25376
 695         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 696         (neon_opcodes): Likewise.
 697         (select_arm_features): Make sure we enable MVE bits when selecting
 698         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 699         any architecture.
 700
 701 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 702
 703         * i386-opc.tbl: Drop stale comment from XOP section.
 704
 705 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 708         (extractps): Add VexWIG to SSE2AVX forms.
 709         * i386-tbl.h: Re-generate.
 710
 711 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 712
 713         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 714         Size64 from and use VexW1 on SSE2AVX forms.
 715         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 716         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 717         * i386-tbl.h: Re-generate.
 718
 719 2020-01-15  Alan Modra  <amodra@gmail.com>
 720
 721         * tic4x-dis.c (tic4x_version): Make unsigned long.
 722         (optab, optab_special, registernames): New file scope vars.
 723         (tic4x_print_register): Set up registernames rather than
 724         malloc'd registertable.
 725         (tic4x_disassemble): Delete optable and optable_special.  Use
 726         optab and optab_special instead.  Throw away old optab,
 727         optab_special and registernames when info->mach changes.
 728
 729 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 730
 731         PR 25377
 732         * z80-dis.c (suffix): Use .db instruction to generate double
 733         prefix.
 734
 735 2020-01-14  Alan Modra  <amodra@gmail.com>
 736
 737         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 738         values to unsigned before shifting.
 739
 740 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 741
 742         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 743         flow instructions.
 744         (print_insn_thumb16, print_insn_thumb32): Likewise.
 745         (print_insn): Initialize the insn info.
 746         * i386-dis.c (print_insn): Initialize the insn info fields, and
 747         detect jumps.
 748
 749 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 750
 751         * arc-opc.c (C_NE): Make it required.
 752
 753 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 754
 755         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 756         reserved register name.
 757
 758 2020-01-13  Alan Modra  <amodra@gmail.com>
 759
 760         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 761         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 762
 763 2020-01-13  Alan Modra  <amodra@gmail.com>
 764
 765         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 766         result of wasm_read_leb128 in a uint64_t and check that bits
 767         are not lost when copying to other locals.  Use uint32_t for
 768         most locals.  Use PRId64 when printing int64_t.
 769
 770 2020-01-13  Alan Modra  <amodra@gmail.com>
 771
 772         * score-dis.c: Formatting.
 773         * score7-dis.c: Formatting.
 774
 775 2020-01-13  Alan Modra  <amodra@gmail.com>
 776
 777         * score-dis.c (print_insn_score48): Use unsigned variables for
 778         unsigned values.  Don't left shift negative values.
 779         (print_insn_score32): Likewise.
 780         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 781
 782 2020-01-13  Alan Modra  <amodra@gmail.com>
 783
 784         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 785
 786 2020-01-13  Alan Modra  <amodra@gmail.com>
 787
 788         * fr30-ibld.c: Regenerate.
 789
 790 2020-01-13  Alan Modra  <amodra@gmail.com>
 791
 792         * xgate-dis.c (print_insn): Don't left shift signed value.
 793         (ripBits): Formatting, use 1u.
 794
 795 2020-01-10  Alan Modra  <amodra@gmail.com>
 796
 797         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 798         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 799
 800 2020-01-10  Alan Modra  <amodra@gmail.com>
 801
 802         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 803         and XRREG value earlier to avoid a shift with negative exponent.
 804         * m10200-dis.c (disassemble): Similarly.
 805
 806 2020-01-09  Nick Clifton  <nickc@redhat.com>
 807
 808         PR 25224
 809         * z80-dis.c (ld_ii_ii): Use correct cast.
 810
 811 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 812
 813         PR 25224
 814         * z80-dis.c (ld_ii_ii): Use character constant when checking
 815         opcode byte value.
 816
 817 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 818
 819         * i386-dis.c (SEP_Fixup): New.
 820         (SEP): Define.
 821         (dis386_twobyte): Use it for sysenter/sysexit.
 822         (enum x86_64_isa): Change amd64 enumerator to value 1.
 823         (OP_J): Compare isa64 against intel64 instead of amd64.
 824         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 825         forms.
 826         * i386-tbl.h: Re-generate.
 827
 828 2020-01-08  Alan Modra  <amodra@gmail.com>
 829
 830         * z8k-dis.c: Include libiberty.h
 831         (instr_data_s): Make max_fetched unsigned.
 832         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 833         Don't exceed byte_info bounds.
 834         (output_instr): Make num_bytes unsigned.
 835         (unpack_instr): Likewise for nibl_count and loop.
 836         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 837         idx unsigned.
 838         * z8k-opc.h: Regenerate.
 839
 840 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 841
 842         * arc-tbl.h (llock): Use 'LLOCK' as class.
 843         (llockd): Likewise.
 844         (scond): Use 'SCOND' as class.
 845         (scondd): Likewise.
 846         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 847         (scondd): Likewise.
 848
 849 2020-01-06  Alan Modra  <amodra@gmail.com>
 850
 851         * m32c-ibld.c: Regenerate.
 852
 853 2020-01-06  Alan Modra  <amodra@gmail.com>
 854
 855         PR 25344
 856         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 857         Peek at next byte to prevent recursion on repeated prefix bytes.
 858         Ensure uninitialised "mybuf" is not accessed.
 859         (print_insn_z80): Don't zero n_fetch and n_used here,..
 860         (print_insn_z80_buf): ..do it here instead.
 861
 862 2020-01-04  Alan Modra  <amodra@gmail.com>
 863
 864         * m32r-ibld.c: Regenerate.
 865
 866 2020-01-04  Alan Modra  <amodra@gmail.com>
 867
 868         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 869
 870 2020-01-04  Alan Modra  <amodra@gmail.com>
 871
 872         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 873
 874 2020-01-04  Alan Modra  <amodra@gmail.com>
 875
 876         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 877
 878 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 879
 880         * aarch64-tbl.h (aarch64_opcode_table): Use
 881         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 882
 883 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 884
 885         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 886         forms of SUDOT and USDOT.
 887
 888 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 889
 890         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 891         uzip{1,2}.
 892         * opcodes/aarch64-dis-2.c: Re-generate.
 893
 894 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 895
 896         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 897         FMMLA encoding.
 898         * opcodes/aarch64-dis-2.c: Re-generate.
 899
 900 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 901
 902         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 903
 904 2020-01-01  Alan Modra  <amodra@gmail.com>
 905
 906         Update year range in copyright notice of all files.
 907
 908 For older changes see ChangeLog-2019
 909 \f
 910 Copyright (C) 2020 Free Software Foundation, Inc.
 911
 912 Copying and distribution of this file, with or without modification,
 913 are permitted in any medium without royalty provided the copyright
 914 notice and this notice are preserved.
 915
 916 Local Variables:
 917 mode: change-log
 918 left-margin: 8
 919 fill-column: 74
 920 version-control: never
 921 End: