opcodes/ChangeLog

   1 2018-11-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
   4         EVex512, EVexLIG, EVexDYN): New.
   5         (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
   6         insns): Use Vex128 instead of Vex=3 (aka VexLIG).
   7         (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
   8         of EVex=4 (aka EVexLIG).
   9         * i386-tbl.h: Re-generate.
  10
  11 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
  14         (vpmaxub): Re-order attributes on AVX512BW flavor.
  15         * i386-tbl.h: Re-generate.
  16
  17 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
  20         vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
  21         Vex=1 on AVX / AVX2 flavors.
  22         (vpmaxub): Re-order attributes on AVX512BW flavor.
  23         * i386-tbl.h: Re-generate.
  24
  25 2018-11-06  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl (VexW0, VexW1): New.
  28         (vphadd*, vphsub*): Use VexW0 on XOP variants.
  29         * i386-tbl.h: Re-generate.
  30
  31 2018-10-22  John Darrington  <john@darrington.wattle.id.au>
  32
  33         * s12z-dis.c (decode_possible_symbol): Add fallback case.
  34         (rel_15_7): Likewise.
  35
  36 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
  37
  38         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
  39         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
  40         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
  41
  42 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
  43
  44         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
  45         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
  46
  47 2018-10-10  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
  50         Size64. Add Size.
  51         * i386-opc.h (Size16, Size32, Size64): Delete.
  52         (Size): New.
  53         (SIZE16, SIZE32, SIZE64): Define.
  54         (struct i386_opcode_modifier): Drop size16, size32, and size64.
  55         Add size.
  56         * i386-opc.tbl (Size16, Size32, Size64): Define.
  57         * i386-tbl.h: Re-generate.
  58
  59 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  60
  61         * aarch64-opc.c (operand_general_constraint_met_p): Add
  62         SSBS in the check for one-bit immediate.
  63         (aarch64_sys_regs): New entry for SSBS.
  64         (aarch64_sys_reg_supported_p): New check for above.
  65         (aarch64_pstatefields): New entry for SSBS.
  66         (aarch64_pstatefield_supported_p): New check for above.
  67
  68 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  69
  70         * aarch64-opc.c (aarch64_sys_regs): New entries for
  71         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
  72         (aarch64_sys_reg_supported_p): New checks for above.
  73
  74 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  75
  76         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
  77         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
  78         with the hint immediate.
  79         * aarch64-opc.c (aarch64_hint_options): New entries for
  80         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
  81         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
  82         while checking for HINT_OPD_F_NOPRINT flag.
  83         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
  84         extract value.
  85         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
  86         (aarch64_opcode_table): Add entry for BTI.
  87         (AARCH64_OPERANDS): Add new description for BTI targets.
  88         * aarch64-asm-2.c: Regenerate.
  89         * aarch64-dis-2.c: Regenerate.
  90         * aarch64-opc-2.c: Regenerate.
  91
  92 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  93
  94         * aarch64-opc.c (aarch64_sys_regs): New entries for
  95         rndr and rndrrs.
  96         (aarch64_sys_reg_supported_p): New check for above.
  97
  98 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  99
 100         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
 101         (aarch64_sys_ins_reg_supported_p): New check for above.
 102
 103 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 104
 105         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
 106         AARCH64_OPND_SYSREG_SR.
 107         * aarch64-opc.c (aarch64_print_operand): Likewise.
 108         (aarch64_sys_regs_sr): Define table.
 109         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
 110         AARCH64_FEATURE_PREDRES.
 111         * aarch64-tbl.h (aarch64_feature_predres): New.
 112         (PREDRES, PREDRES_INSN): New.
 113         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
 114         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
 115         * aarch64-asm-2.c: Regenerate.
 116         * aarch64-dis-2.c: Regenerate.
 117         * aarch64-opc-2.c: Regenerate.
 118
 119 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 120
 121         * aarch64-tbl.h (aarch64_feature_sb): New.
 122         (SB, SB_INSN): New.
 123         (aarch64_opcode_table): Add entry for sb.
 124         * aarch64-asm-2.c: Regenerate.
 125         * aarch64-dis-2.c: Regenerate.
 126         * aarch64-opc-2.c: Regenerate.
 127
 128 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 129
 130         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
 131         (aarch64_feature_frintts): New.
 132         (FLAGMANIP, FRINTTS): New.
 133         (aarch64_opcode_table): Add entries for xaflag, axflag
 134         and frint[32,64][x,z] instructions.
 135         * aarch64-asm-2.c: Regenerate.
 136         * aarch64-dis-2.c: Regenerate.
 137         * aarch64-opc-2.c: Regenerate.
 138
 139 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 140
 141         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 142         (ARMV8_5, V8_5_INSN): New.
 143
 144 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 145
 146         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 147
 148 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 149
 150         * i386-dis.c (rm_table): Add enclv.
 151         * i386-opc.tbl: Add enclv.
 152         * i386-tbl.h: Regenerated.
 153
 154 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 155
 156         * arm-dis.c (arm_opcodes): Add sb.
 157         (thumb32_opcodes): Likewise.
 158
 159 2018-10-05  Richard Henderson  <rth@twiddle.net>
 160             Stafford Horne  <shorne@gmail.com>
 161
 162         * or1k-desc.c: Regenerate.
 163         * or1k-desc.h: Regenerate.
 164         * or1k-opc.c: Regenerate.
 165         * or1k-opc.h: Regenerate.
 166         * or1k-opinst.c: Regenerate.
 167
 168 2018-10-05  Richard Henderson  <rth@twiddle.net>
 169
 170         * or1k-asm.c: Regenerated.
 171         * or1k-desc.c: Regenerated.
 172         * or1k-desc.h: Regenerated.
 173         * or1k-dis.c: Regenerated.
 174         * or1k-ibld.c: Regenerated.
 175         * or1k-opc.c: Regenerated.
 176         * or1k-opc.h: Regenerated.
 177         * or1k-opinst.c: Regenerated.
 178
 179 2018-10-05  Richard Henderson  <rth@twiddle.net>
 180
 181         * or1k-asm.c: Regenerate.
 182
 183 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 184
 185         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 186         * aarch64-dis.c (print_operands): Refactor to take notes.
 187         (print_verifier_notes): New.
 188         (print_aarch64_insn): Apply constraint verifier.
 189         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 190         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 191
 192 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 193
 194         * aarch64-opc.c (init_insn_block): New.
 195         (verify_constraints, aarch64_is_destructive_by_operands): New.
 196         * aarch64-opc.h (verify_constraints): New.
 197
 198 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 199
 200         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 201         * aarch64-opc.c (verify_ldpsw): Update arguments.
 202
 203 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 204
 205         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 206         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 207
 208 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 209
 210         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 211         * aarch64-dis.c (insn_sequence): New.
 212
 213 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 214
 215         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 216         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 217         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 218         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 219         constraints.
 220         (_SVE_INSNC): New.
 221         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 222         constraints.
 223         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 224         F_SCAN flags.
 225         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 226         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 227         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 228         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 229         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 230         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 231         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 232
 233 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 234
 235         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 236
 237 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 238
 239         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 240         are used when extracting signed fields and converting them to
 241         potentially 64-bit types.
 242
 243 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 244
 245         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 246         * Makefile.in: Re-generate.
 247         * aclocal.m4: Re-generate.
 248         * configure: Re-generate.
 249         * configure.ac: Remove check for -Wno-missing-field-initializers.
 250         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 251         (csky_v2_opcodes): Likewise.
 252
 253 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 254
 255         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 256
 257 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 258
 259         * nds32-asm.c (operand_fields): Remove the unused fields.
 260         (nds32_opcodes): Remove the unused instructions.
 261         * nds32-dis.c (nds32_ex9_info): Removed.
 262         (nds32_parse_opcode): Updated.
 263         (print_insn_nds32): Likewise.
 264         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 265         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 266         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 267         build_opcode_hash_table): New functions.
 268         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 269         nds32_opcode_table): New.
 270         (hw_ktabs): Declare it to a pointer rather than an array.
 271         (build_hash_table): Removed.
 272         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 273         SYN_ROPT and upadte HW_GPR and HW_INT.
 274         * nds32-dis.c (keywords): Remove const.
 275         (match_field): New function.
 276         (nds32_parse_opcode): Updated.
 277         * disassemble.c (disassemble_init_for_target):
 278         Add disassemble_init_nds32.
 279         * nds32-dis.c (eum map_type): New.
 280         (nds32_private_data): Likewise.
 281         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 282         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 283         (print_insn_nds32): Updated.
 284         * nds32-asm.c (parse_aext_reg): Add new parameter.
 285         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 286         are allowed to use.
 287         All callers changed.
 288         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 289         (operand_fields): Add new fields.
 290         (nds32_opcodes): Add new instructions.
 291         (keyword_aridxi_mx): New keyword.
 292         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 293         and NASM_ATTR_ZOL.
 294         (ALU2_1, ALU2_2, ALU2_3): New macros.
 295         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 296
 297 2018-09-17  Kito Cheng  <kito@andestech.com>
 298
 299         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 300
 301 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 302
 303         PR gas/23670
 304         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 305         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 306         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 307         (EVEX_LEN_0F7E_P_1): Likewise.
 308         (EVEX_LEN_0F7E_P_2): Likewise.
 309         (EVEX_LEN_0FD6_P_2): Likewise.
 310         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 311         (EVEX_LEN_TABLE): Likewise.
 312         (EVEX_LEN_0F6E_P_2): New enum.
 313         (EVEX_LEN_0F7E_P_1): Likewise.
 314         (EVEX_LEN_0F7E_P_2): Likewise.
 315         (EVEX_LEN_0FD6_P_2): Likewise.
 316         (evex_len_table): New.
 317         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 318         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 319         * i386-tbl.h: Regenerated.
 320
 321 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 322
 323         PR gas/23665
 324         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 325         VEX_LEN_0F7E_P_2 entries.
 326         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 327         * i386-tbl.h: Regenerated.
 328
 329 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 330
 331         * i386-dis.c (VZERO_Fixup): Removed.
 332         (VZERO): Likewise.
 333         (VEX_LEN_0F10_P_1): Likewise.
 334         (VEX_LEN_0F10_P_3): Likewise.
 335         (VEX_LEN_0F11_P_1): Likewise.
 336         (VEX_LEN_0F11_P_3): Likewise.
 337         (VEX_LEN_0F2E_P_0): Likewise.
 338         (VEX_LEN_0F2E_P_2): Likewise.
 339         (VEX_LEN_0F2F_P_0): Likewise.
 340         (VEX_LEN_0F2F_P_2): Likewise.
 341         (VEX_LEN_0F51_P_1): Likewise.
 342         (VEX_LEN_0F51_P_3): Likewise.
 343         (VEX_LEN_0F52_P_1): Likewise.
 344         (VEX_LEN_0F53_P_1): Likewise.
 345         (VEX_LEN_0F58_P_1): Likewise.
 346         (VEX_LEN_0F58_P_3): Likewise.
 347         (VEX_LEN_0F59_P_1): Likewise.
 348         (VEX_LEN_0F59_P_3): Likewise.
 349         (VEX_LEN_0F5A_P_1): Likewise.
 350         (VEX_LEN_0F5A_P_3): Likewise.
 351         (VEX_LEN_0F5C_P_1): Likewise.
 352         (VEX_LEN_0F5C_P_3): Likewise.
 353         (VEX_LEN_0F5D_P_1): Likewise.
 354         (VEX_LEN_0F5D_P_3): Likewise.
 355         (VEX_LEN_0F5E_P_1): Likewise.
 356         (VEX_LEN_0F5E_P_3): Likewise.
 357         (VEX_LEN_0F5F_P_1): Likewise.
 358         (VEX_LEN_0F5F_P_3): Likewise.
 359         (VEX_LEN_0FC2_P_1): Likewise.
 360         (VEX_LEN_0FC2_P_3): Likewise.
 361         (VEX_LEN_0F3A0A_P_2): Likewise.
 362         (VEX_LEN_0F3A0B_P_2): Likewise.
 363         (VEX_W_0F10_P_0): Likewise.
 364         (VEX_W_0F10_P_1): Likewise.
 365         (VEX_W_0F10_P_2): Likewise.
 366         (VEX_W_0F10_P_3): Likewise.
 367         (VEX_W_0F11_P_0): Likewise.
 368         (VEX_W_0F11_P_1): Likewise.
 369         (VEX_W_0F11_P_2): Likewise.
 370         (VEX_W_0F11_P_3): Likewise.
 371         (VEX_W_0F12_P_0_M_0): Likewise.
 372         (VEX_W_0F12_P_0_M_1): Likewise.
 373         (VEX_W_0F12_P_1): Likewise.
 374         (VEX_W_0F12_P_2): Likewise.
 375         (VEX_W_0F12_P_3): Likewise.
 376         (VEX_W_0F13_M_0): Likewise.
 377         (VEX_W_0F14): Likewise.
 378         (VEX_W_0F15): Likewise.
 379         (VEX_W_0F16_P_0_M_0): Likewise.
 380         (VEX_W_0F16_P_0_M_1): Likewise.
 381         (VEX_W_0F16_P_1): Likewise.
 382         (VEX_W_0F16_P_2): Likewise.
 383         (VEX_W_0F17_M_0): Likewise.
 384         (VEX_W_0F28): Likewise.
 385         (VEX_W_0F29): Likewise.
 386         (VEX_W_0F2B_M_0): Likewise.
 387         (VEX_W_0F2E_P_0): Likewise.
 388         (VEX_W_0F2E_P_2): Likewise.
 389         (VEX_W_0F2F_P_0): Likewise.
 390         (VEX_W_0F2F_P_2): Likewise.
 391         (VEX_W_0F50_M_0): Likewise.
 392         (VEX_W_0F51_P_0): Likewise.
 393         (VEX_W_0F51_P_1): Likewise.
 394         (VEX_W_0F51_P_2): Likewise.
 395         (VEX_W_0F51_P_3): Likewise.
 396         (VEX_W_0F52_P_0): Likewise.
 397         (VEX_W_0F52_P_1): Likewise.
 398         (VEX_W_0F53_P_0): Likewise.
 399         (VEX_W_0F53_P_1): Likewise.
 400         (VEX_W_0F58_P_0): Likewise.
 401         (VEX_W_0F58_P_1): Likewise.
 402         (VEX_W_0F58_P_2): Likewise.
 403         (VEX_W_0F58_P_3): Likewise.
 404         (VEX_W_0F59_P_0): Likewise.
 405         (VEX_W_0F59_P_1): Likewise.
 406         (VEX_W_0F59_P_2): Likewise.
 407         (VEX_W_0F59_P_3): Likewise.
 408         (VEX_W_0F5A_P_0): Likewise.
 409         (VEX_W_0F5A_P_1): Likewise.
 410         (VEX_W_0F5A_P_3): Likewise.
 411         (VEX_W_0F5B_P_0): Likewise.
 412         (VEX_W_0F5B_P_1): Likewise.
 413         (VEX_W_0F5B_P_2): Likewise.
 414         (VEX_W_0F5C_P_0): Likewise.
 415         (VEX_W_0F5C_P_1): Likewise.
 416         (VEX_W_0F5C_P_2): Likewise.
 417         (VEX_W_0F5C_P_3): Likewise.
 418         (VEX_W_0F5D_P_0): Likewise.
 419         (VEX_W_0F5D_P_1): Likewise.
 420         (VEX_W_0F5D_P_2): Likewise.
 421         (VEX_W_0F5D_P_3): Likewise.
 422         (VEX_W_0F5E_P_0): Likewise.
 423         (VEX_W_0F5E_P_1): Likewise.
 424         (VEX_W_0F5E_P_2): Likewise.
 425         (VEX_W_0F5E_P_3): Likewise.
 426         (VEX_W_0F5F_P_0): Likewise.
 427         (VEX_W_0F5F_P_1): Likewise.
 428         (VEX_W_0F5F_P_2): Likewise.
 429         (VEX_W_0F5F_P_3): Likewise.
 430         (VEX_W_0F60_P_2): Likewise.
 431         (VEX_W_0F61_P_2): Likewise.
 432         (VEX_W_0F62_P_2): Likewise.
 433         (VEX_W_0F63_P_2): Likewise.
 434         (VEX_W_0F64_P_2): Likewise.
 435         (VEX_W_0F65_P_2): Likewise.
 436         (VEX_W_0F66_P_2): Likewise.
 437         (VEX_W_0F67_P_2): Likewise.
 438         (VEX_W_0F68_P_2): Likewise.
 439         (VEX_W_0F69_P_2): Likewise.
 440         (VEX_W_0F6A_P_2): Likewise.
 441         (VEX_W_0F6B_P_2): Likewise.
 442         (VEX_W_0F6C_P_2): Likewise.
 443         (VEX_W_0F6D_P_2): Likewise.
 444         (VEX_W_0F6F_P_1): Likewise.
 445         (VEX_W_0F6F_P_2): Likewise.
 446         (VEX_W_0F70_P_1): Likewise.
 447         (VEX_W_0F70_P_2): Likewise.
 448         (VEX_W_0F70_P_3): Likewise.
 449         (VEX_W_0F71_R_2_P_2): Likewise.
 450         (VEX_W_0F71_R_4_P_2): Likewise.
 451         (VEX_W_0F71_R_6_P_2): Likewise.
 452         (VEX_W_0F72_R_2_P_2): Likewise.
 453         (VEX_W_0F72_R_4_P_2): Likewise.
 454         (VEX_W_0F72_R_6_P_2): Likewise.
 455         (VEX_W_0F73_R_2_P_2): Likewise.
 456         (VEX_W_0F73_R_3_P_2): Likewise.
 457         (VEX_W_0F73_R_6_P_2): Likewise.
 458         (VEX_W_0F73_R_7_P_2): Likewise.
 459         (VEX_W_0F74_P_2): Likewise.
 460         (VEX_W_0F75_P_2): Likewise.
 461         (VEX_W_0F76_P_2): Likewise.
 462         (VEX_W_0F77_P_0): Likewise.
 463         (VEX_W_0F7C_P_2): Likewise.
 464         (VEX_W_0F7C_P_3): Likewise.
 465         (VEX_W_0F7D_P_2): Likewise.
 466         (VEX_W_0F7D_P_3): Likewise.
 467         (VEX_W_0F7E_P_1): Likewise.
 468         (VEX_W_0F7F_P_1): Likewise.
 469         (VEX_W_0F7F_P_2): Likewise.
 470         (VEX_W_0FAE_R_2_M_0): Likewise.
 471         (VEX_W_0FAE_R_3_M_0): Likewise.
 472         (VEX_W_0FC2_P_0): Likewise.
 473         (VEX_W_0FC2_P_1): Likewise.
 474         (VEX_W_0FC2_P_2): Likewise.
 475         (VEX_W_0FC2_P_3): Likewise.
 476         (VEX_W_0FD0_P_2): Likewise.
 477         (VEX_W_0FD0_P_3): Likewise.
 478         (VEX_W_0FD1_P_2): Likewise.
 479         (VEX_W_0FD2_P_2): Likewise.
 480         (VEX_W_0FD3_P_2): Likewise.
 481         (VEX_W_0FD4_P_2): Likewise.
 482         (VEX_W_0FD5_P_2): Likewise.
 483         (VEX_W_0FD6_P_2): Likewise.
 484         (VEX_W_0FD7_P_2_M_1): Likewise.
 485         (VEX_W_0FD8_P_2): Likewise.
 486         (VEX_W_0FD9_P_2): Likewise.
 487         (VEX_W_0FDA_P_2): Likewise.
 488         (VEX_W_0FDB_P_2): Likewise.
 489         (VEX_W_0FDC_P_2): Likewise.
 490         (VEX_W_0FDD_P_2): Likewise.
 491         (VEX_W_0FDE_P_2): Likewise.
 492         (VEX_W_0FDF_P_2): Likewise.
 493         (VEX_W_0FE0_P_2): Likewise.
 494         (VEX_W_0FE1_P_2): Likewise.
 495         (VEX_W_0FE2_P_2): Likewise.
 496         (VEX_W_0FE3_P_2): Likewise.
 497         (VEX_W_0FE4_P_2): Likewise.
 498         (VEX_W_0FE5_P_2): Likewise.
 499         (VEX_W_0FE6_P_1): Likewise.
 500         (VEX_W_0FE6_P_2): Likewise.
 501         (VEX_W_0FE6_P_3): Likewise.
 502         (VEX_W_0FE7_P_2_M_0): Likewise.
 503         (VEX_W_0FE8_P_2): Likewise.
 504         (VEX_W_0FE9_P_2): Likewise.
 505         (VEX_W_0FEA_P_2): Likewise.
 506         (VEX_W_0FEB_P_2): Likewise.
 507         (VEX_W_0FEC_P_2): Likewise.
 508         (VEX_W_0FED_P_2): Likewise.
 509         (VEX_W_0FEE_P_2): Likewise.
 510         (VEX_W_0FEF_P_2): Likewise.
 511         (VEX_W_0FF0_P_3_M_0): Likewise.
 512         (VEX_W_0FF1_P_2): Likewise.
 513         (VEX_W_0FF2_P_2): Likewise.
 514         (VEX_W_0FF3_P_2): Likewise.
 515         (VEX_W_0FF4_P_2): Likewise.
 516         (VEX_W_0FF5_P_2): Likewise.
 517         (VEX_W_0FF6_P_2): Likewise.
 518         (VEX_W_0FF7_P_2): Likewise.
 519         (VEX_W_0FF8_P_2): Likewise.
 520         (VEX_W_0FF9_P_2): Likewise.
 521         (VEX_W_0FFA_P_2): Likewise.
 522         (VEX_W_0FFB_P_2): Likewise.
 523         (VEX_W_0FFC_P_2): Likewise.
 524         (VEX_W_0FFD_P_2): Likewise.
 525         (VEX_W_0FFE_P_2): Likewise.
 526         (VEX_W_0F3800_P_2): Likewise.
 527         (VEX_W_0F3801_P_2): Likewise.
 528         (VEX_W_0F3802_P_2): Likewise.
 529         (VEX_W_0F3803_P_2): Likewise.
 530         (VEX_W_0F3804_P_2): Likewise.
 531         (VEX_W_0F3805_P_2): Likewise.
 532         (VEX_W_0F3806_P_2): Likewise.
 533         (VEX_W_0F3807_P_2): Likewise.
 534         (VEX_W_0F3808_P_2): Likewise.
 535         (VEX_W_0F3809_P_2): Likewise.
 536         (VEX_W_0F380A_P_2): Likewise.
 537         (VEX_W_0F380B_P_2): Likewise.
 538         (VEX_W_0F3817_P_2): Likewise.
 539         (VEX_W_0F381C_P_2): Likewise.
 540         (VEX_W_0F381D_P_2): Likewise.
 541         (VEX_W_0F381E_P_2): Likewise.
 542         (VEX_W_0F3820_P_2): Likewise.
 543         (VEX_W_0F3821_P_2): Likewise.
 544         (VEX_W_0F3822_P_2): Likewise.
 545         (VEX_W_0F3823_P_2): Likewise.
 546         (VEX_W_0F3824_P_2): Likewise.
 547         (VEX_W_0F3825_P_2): Likewise.
 548         (VEX_W_0F3828_P_2): Likewise.
 549         (VEX_W_0F3829_P_2): Likewise.
 550         (VEX_W_0F382A_P_2_M_0): Likewise.
 551         (VEX_W_0F382B_P_2): Likewise.
 552         (VEX_W_0F3830_P_2): Likewise.
 553         (VEX_W_0F3831_P_2): Likewise.
 554         (VEX_W_0F3832_P_2): Likewise.
 555         (VEX_W_0F3833_P_2): Likewise.
 556         (VEX_W_0F3834_P_2): Likewise.
 557         (VEX_W_0F3835_P_2): Likewise.
 558         (VEX_W_0F3837_P_2): Likewise.
 559         (VEX_W_0F3838_P_2): Likewise.
 560         (VEX_W_0F3839_P_2): Likewise.
 561         (VEX_W_0F383A_P_2): Likewise.
 562         (VEX_W_0F383B_P_2): Likewise.
 563         (VEX_W_0F383C_P_2): Likewise.
 564         (VEX_W_0F383D_P_2): Likewise.
 565         (VEX_W_0F383E_P_2): Likewise.
 566         (VEX_W_0F383F_P_2): Likewise.
 567         (VEX_W_0F3840_P_2): Likewise.
 568         (VEX_W_0F3841_P_2): Likewise.
 569         (VEX_W_0F38DB_P_2): Likewise.
 570         (VEX_W_0F3A08_P_2): Likewise.
 571         (VEX_W_0F3A09_P_2): Likewise.
 572         (VEX_W_0F3A0A_P_2): Likewise.
 573         (VEX_W_0F3A0B_P_2): Likewise.
 574         (VEX_W_0F3A0C_P_2): Likewise.
 575         (VEX_W_0F3A0D_P_2): Likewise.
 576         (VEX_W_0F3A0E_P_2): Likewise.
 577         (VEX_W_0F3A0F_P_2): Likewise.
 578         (VEX_W_0F3A21_P_2): Likewise.
 579         (VEX_W_0F3A40_P_2): Likewise.
 580         (VEX_W_0F3A41_P_2): Likewise.
 581         (VEX_W_0F3A42_P_2): Likewise.
 582         (VEX_W_0F3A62_P_2): Likewise.
 583         (VEX_W_0F3A63_P_2): Likewise.
 584         (VEX_W_0F3ADF_P_2): Likewise.
 585         (VEX_LEN_0F77_P_0): New.
 586         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 587         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 588         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 589         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 590         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 591         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 592         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 593         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 594         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 595         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 596         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 597         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 598         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 599         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 600         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 601         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 602         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 603         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 604         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 605         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 606         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 607         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 608         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 609         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 610         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 611         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 612         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 613         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 614         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 615         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 616         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 617         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 618         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 619         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 620         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 621         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 622         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 623         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 624         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 625         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 626         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 627         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 628         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 629         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 630         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 631         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 632         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 633         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 634         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 635         (vex_table): Update VEX 0F28 and 0F29 entries.
 636         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 637         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 638         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 639         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 640         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 641         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 642         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 643         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 644         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 645         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 646         VEX_LEN_0F3A0B_P_2 entries.
 647         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 648         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 649         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 650         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 651         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 652         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 653         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 654         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 655         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 656         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 657         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 658         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 659         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 660         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 661         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 662         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 663         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 664         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 665         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 666         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 667         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 668         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 669         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 670         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 671         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 672         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 673         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 674         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 675         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 676         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 677         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 678         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 679         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 680         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 681         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 682         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 683         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 684         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 685         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 686         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 687         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 688         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 689         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 690         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 691         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 692         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 693         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 694         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 695         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 696         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 697         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 698         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 699         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 700         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 701         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 702         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 703         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 704         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 705         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 706         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 707         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 708         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 709         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 710         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 711         VEX_W_0F3ADF_P_2 entries.
 712         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 713         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 714         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 715
 716 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 717
 718         * i386-opc.tbl (VexWIG): New.
 719         Replace VexW=3 with VexWIG.
 720
 721 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 722
 723         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 724         * i386-tbl.h: Regenerated.
 725
 726 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 727
 728         PR gas/23665
 729         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 730         VEX_LEN_0FD6_P_2 entries.
 731         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 732         * i386-tbl.h: Regenerated.
 733
 734 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 735
 736         PR gas/23642
 737         * i386-opc.h (VEXWIG): New.
 738         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 739         * i386-tbl.h: Regenerated.
 740
 741 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 742
 743         PR binutils/23655
 744         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 745         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 746         * i386-dis.c (EXxEVexR64): New.
 747         (evex_rounding_64_mode): Likewise.
 748         (OP_Rounding): Handle evex_rounding_64_mode.
 749
 750 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 751
 752         PR binutils/23655
 753         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 754         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 755         * i386-dis.c (Edqa): New.
 756         (dqa_mode): Likewise.
 757         (intel_operand_size): Handle dqa_mode as m_mode.
 758         (OP_E_register): Handle dqa_mode as dq_mode.
 759         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 760
 761 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 762
 763         * i386-dis.c (OP_E_memory): Reformat.
 764
 765 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-opc.tbl (crc32): Fold byte and word forms.
 768         * i386-tbl.h: Re-generate.
 769
 770 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 771
 772         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 773         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 774         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 775         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 776         * i386-tbl.h: Regenerated.
 777
 778 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 779
 780         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 781         meaningless.
 782         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 783         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 784         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 785         * i386-tbl.h: Re-generate.
 786
 787 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 790         AVX512_4VNNIW insns.
 791         * i386-tbl.h: Re-generate.
 792
 793 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 796         meaningless.
 797         * i386-tbl.h: Re-generate.
 798
 799 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 802         meaningless.
 803         * i386-tbl.h: Re-generate.
 804
 805 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 808         meaningless.
 809         * i386-tbl.h: Re-generate.
 810
 811 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 812
 813         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 814         meaningless.
 815         * i386-tbl.h: Re-generate.
 816
 817 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 818
 819         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 820         meaningless.
 821         * i386-tbl.h: Re-generate.
 822
 823 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 824
 825         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 826         * i386-tbl.h: Re-generate.
 827
 828 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 829
 830         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 831         * i386-tbl.h: Re-generate.
 832
 833 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 834
 835         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 836         meaningless.
 837         * i386-tbl.h: Re-generate.
 838
 839 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 840
 841         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 842         meaningless.
 843         * i386-tbl.h: Re-generate.
 844
 845 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 846
 847         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 848         * i386-tbl.h: Re-generate.
 849
 850 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 853         * i386-tbl.h: Re-generate.
 854
 855 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 856
 857         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 858         * i386-tbl.h: Re-generate.
 859
 860 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 861
 862         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 863         meaningless.
 864         * i386-tbl.h: Re-generate.
 865
 866 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 869         meaningless.
 870         * i386-tbl.h: Re-generate.
 871
 872 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 875         meaningless.
 876         * i386-tbl.h: Re-generate.
 877
 878 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 881         * i386-tbl.h: Re-generate.
 882
 883 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 884
 885         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 886         * i386-tbl.h: Re-generate.
 887
 888 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 889
 890         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 891         * i386-tbl.h: Re-generate.
 892
 893 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 896         (vpbroadcastw, rdpid): Drop NoRex64.
 897         * i386-tbl.h: Re-generate.
 898
 899 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 900
 901         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 902         store templates, adding D.
 903         * i386-tbl.h: Re-generate.
 904
 905 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 906
 907         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 908         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 909         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 910         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 911         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 912         Fold load and store templates where possible, adding D. Drop
 913         IgnoreSize where it was pointlessly present. Drop redundant
 914         *word.
 915         * i386-tbl.h: Re-generate.
 916
 917 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 918
 919         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 920         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 921         (intel_operand_size): Handle v_bndmk_mode.
 922         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 923
 924 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 925
 926         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 927
 928 2018-08-31  Kito Cheng  <kito@andestech.com>
 929
 930         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 931         compressed floating point instructions.
 932
 933 2018-08-30  Kito Cheng  <kito@andestech.com>
 934
 935         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 936         riscv_opcode.xlen_requirement.
 937         * riscv-opc.c (riscv_opcodes): Update for struct change.
 938
 939 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 940
 941         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 942         psr (PWRPSR) instruction.
 943
 944 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 945
 946         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 947
 948 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 949
 950         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 951
 952 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 953
 954         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 955         loongson3a as an alias of gs464 for compatibility.
 956         * mips-opc.c (mips_opcodes): Change Comments.
 957
 958 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 959
 960         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 961         option.
 962         (print_mips_disassembler_options): Document -M loongson-ext.
 963         * mips-opc.c (LEXT2): New macro.
 964         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 965
 966 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 967
 968          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 969          descriptors.
 970          (parse_mips_ase_option): Handle -M loongson-ext option.
 971          (print_mips_disassembler_options): Document -M loongson-ext.
 972          * mips-opc.c (IL3A): Delete.
 973          * mips-opc.c (LEXT): New macro.
 974          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 975          instructions.
 976
 977 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 978
 979         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 980         descriptors.
 981         (parse_mips_ase_option): Handle -M loongson-cam option.
 982         (print_mips_disassembler_options): Document -M loongson-cam.
 983         * mips-opc.c (LCAM): New macro.
 984         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 985         instructions.
 986
 987 2018-08-21  Alan Modra  <amodra@gmail.com>
 988
 989         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 990         (skip_optional_operands): Count optional operands, and update
 991         ppc_optional_operand_value call.
 992         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 993         (extract_vlensi): Likewise.
 994         (extract_fxm): Return default value for missing optional operand.
 995         (extract_ls, extract_raq, extract_tbr): Likewise.
 996         (insert_sxl, extract_sxl): New functions.
 997         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 998         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 999         flag and extra entry.
1000         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1001         extract_sxl.
1002
1003 2018-08-20  Alan Modra  <amodra@gmail.com>
1004
1005         * sh-opc.h (MASK): Simplify.
1006
1007 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1008
1009         * s12z-dis.c (bm_decode): Deal with cases where the mode is
1010         BM_RESERVED0 or BM_RESERVED1
1011         (bm_rel_decode, bm_n_bytes): Ditto.
1012
1013 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
1014
1015         * s12z.h: Delete.
1016
1017 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
1018
1019         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1020         address with the addr32 prefix and without base nor index
1021         registers.
1022
1023 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
1024
1025         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1026         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1027         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1028         (cpu_flags): Add CpuCMOV and CpuFXSR.
1029         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1030         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
1031         * i386-init.h: Regenerated.
1032         * i386-tbl.h: Likewise.
1033
1034 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1035
1036         * arc-regs.h: Update auxiliary registers.
1037
1038 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1039
1040         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1041         (RegIP, RegIZ): Define.
1042         * i386-reg.tbl: Adjust comments.
1043         (rip): Use Qword instead of BaseIndex. Use RegIP.
1044         (eip): Use Dword instead of BaseIndex. Use RegIP.
1045         (riz): Add Qword. Use RegIZ.
1046         (eiz): Add Dword. Use RegIZ.
1047         * i386-tbl.h: Re-generate.
1048
1049 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1050
1051         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1052         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1053         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1054         * i386-tbl.h: Re-generate.
1055
1056 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1057
1058         * i386-gen.c (operand_types): Remove Mem field.
1059         * i386-opc.h (union i386_operand_type): Remove mem field.
1060         * i386-init.h, i386-tbl.h: Re-generate.
1061
1062 2018-08-01  Alan Modra  <amodra@gmail.com>
1063
1064         * po/POTFILES.in: Regenerate.
1065
1066 2018-07-31  Nick Clifton  <nickc@redhat.com>
1067
1068         * po/sv.po: Updated Swedish translation.
1069
1070 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1071
1072         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1073         * i386-init.h, i386-tbl.h: Re-generate.
1074
1075 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1076
1077         * i386-opc.h (ZEROING_MASKING) Rename to ...
1078         (DYNAMIC_MASKING): ... this. Adjust comment.
1079         * i386-opc.tbl (MaskingMorZ): Define.
1080         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1081         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1082         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1083         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1084         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1085         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1086         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1087         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1088         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1089
1090 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1091
1092         * i386-opc.tbl: Use element rather than vector size for AVX512*
1093         scatter/gather insns.
1094         * i386-tbl.h: Re-generate.
1095
1096 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1097
1098         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1099         (cpu_flags): Drop CpuVREX.
1100         * i386-opc.h (CpuVREX): Delete.
1101         (union i386_cpu_flags): Remove cpuvrex.
1102         * i386-init.h, i386-tbl.h: Re-generate.
1103
1104 2018-07-30  Jim Wilson  <jimw@sifive.com>
1105
1106         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1107         fields.
1108         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1109
1110 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1111
1112         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1113         * Makefile.in: Regenerated.
1114         * configure.ac: Add C-SKY.
1115         * configure: Regenerated.
1116         * csky-dis.c: New file.
1117         * csky-opc.h: New file.
1118         * disassemble.c (ARCH_csky): Define.
1119         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1120         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1121
1122 2018-07-27  Alan Modra  <amodra@gmail.com>
1123
1124         * ppc-opc.c (insert_sprbat): Correct function parameter and
1125         return type.
1126         (extract_sprbat): Likewise, variable too.
1127
1128 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1129             Alan Modra  <amodra@gmail.com>
1130
1131         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1132         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1133         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1134         support disjointed BAT.
1135         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1136         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1137         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1138
1139 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1140             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1141
1142         * i386-gen.c (adjust_broadcast_modifier): New function.
1143         (process_i386_opcode_modifier): Add an argument for operands.
1144         Adjust the Broadcast value based on operands.
1145         (output_i386_opcode): Pass operand_types to
1146         process_i386_opcode_modifier.
1147         (process_i386_opcodes): Pass NULL as operands to
1148         process_i386_opcode_modifier.
1149         * i386-opc.h (BYTE_BROADCAST): New.
1150         (WORD_BROADCAST): Likewise.
1151         (DWORD_BROADCAST): Likewise.
1152         (QWORD_BROADCAST): Likewise.
1153         (i386_opcode_modifier): Expand broadcast to 3 bits.
1154         * i386-tbl.h: Regenerated.
1155
1156 2018-07-24  Alan Modra  <amodra@gmail.com>
1157
1158         PR 23430
1159         * or1k-desc.h: Regenerate.
1160
1161 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1162
1163         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1164         vcvtusi2ss, and vcvtusi2sd.
1165         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1166         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1167         * i386-tbl.h: Re-generate.
1168
1169 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1170
1171         * arc-opc.c (extract_w6): Fix extending the sign.
1172
1173 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1174
1175         * arc-tbl.h (vewt): Allow it for ARC EM family.
1176
1177 2018-07-23  Alan Modra  <amodra@gmail.com>
1178
1179         PR 23419
1180         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1181         opcode variants for mtspr/mfspr encodings.
1182
1183 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1184             Maciej W. Rozycki  <macro@mips.com>
1185
1186         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1187         loongson3a descriptors.
1188         (parse_mips_ase_option): Handle -M loongson-mmi option.
1189         (print_mips_disassembler_options): Document -M loongson-mmi.
1190         * mips-opc.c (LMMI): New macro.
1191         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1192         instructions.
1193
1194 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1195
1196         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1197         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1198         IgnoreSize and [XYZ]MMword where applicable.
1199         * i386-tbl.h: Re-generate.
1200
1201 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1204         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1205         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1206         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1207         * i386-tbl.h: Re-generate.
1208
1209 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1210
1211         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1212         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1213         VPCLMULQDQ templates into their respective AVX512VL counterparts
1214         where possible, using Disp8ShiftVL and CheckRegSize instead of
1215         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1216         * i386-tbl.h: Re-generate.
1217
1218 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1219
1220         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1221         AVX512VL counterparts where possible, using Disp8ShiftVL and
1222         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1223         IgnoreSize) as appropriate.
1224         * i386-tbl.h: Re-generate.
1225
1226 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1227
1228         * i386-opc.tbl: Fold AVX512BW templates into their respective
1229         AVX512VL counterparts where possible, using Disp8ShiftVL and
1230         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1231         IgnoreSize) as appropriate.
1232         * i386-tbl.h: Re-generate.
1233
1234 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1235
1236         * i386-opc.tbl: Fold AVX512CD templates into their respective
1237         AVX512VL counterparts where possible, using Disp8ShiftVL and
1238         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1239         IgnoreSize) as appropriate.
1240         * i386-tbl.h: Re-generate.
1241
1242 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1243
1244         * i386-opc.h (DISP8_SHIFT_VL): New.
1245         * i386-opc.tbl (Disp8ShiftVL):  Define.
1246         (various): Fold AVX512VL templates into their respective
1247         AVX512F counterparts where possible, using Disp8ShiftVL and
1248         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1249         IgnoreSize) as appropriate.
1250         * i386-tbl.h: Re-generate.
1251
1252 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1253
1254         * Makefile.am: Change dependencies and rule for
1255         $(srcdir)/i386-init.h.
1256         * Makefile.in: Re-generate.
1257         * i386-gen.c (process_i386_opcodes): New local variable
1258         "marker". Drop opening of input file. Recognize marker and line
1259         number directives.
1260         * i386-opc.tbl (OPCODE_I386_H): Define.
1261         (i386-opc.h): Include it.
1262         (None): Undefine.
1263
1264 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1265
1266         PR gas/23418
1267         * i386-opc.h (Byte): Update comments.
1268         (Word): Likewise.
1269         (Dword): Likewise.
1270         (Fword): Likewise.
1271         (Qword): Likewise.
1272         (Tbyte): Likewise.
1273         (Xmmword): Likewise.
1274         (Ymmword): Likewise.
1275         (Zmmword): Likewise.
1276         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1277         vcvttps2uqq.
1278         * i386-tbl.h: Regenerated.
1279
1280 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1281
1282         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1283         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1284         * aarch64-asm-2.c: Regenerate.
1285         * aarch64-dis-2.c: Regenerate.
1286         * aarch64-opc-2.c: Regenerate.
1287
1288 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1289
1290         PR binutils/23192
1291         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1292         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1293         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1294         sqdmulh, sqrdmulh): Use Em16.
1295
1296 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1297
1298         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1299         csdb together with them.
1300         (thumb32_opcodes): Likewise.
1301
1302 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1303
1304         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1305         requiring 32-bit registers as operands 2 and 3. Improve
1306         comments.
1307         (mwait, mwaitx): Fold templates. Improve comments.
1308         OPERAND_TYPE_INOUTPORTREG.
1309         * i386-tbl.h: Re-generate.
1310
1311 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1312
1313         * i386-gen.c (operand_type_init): Remove
1314         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1315         OPERAND_TYPE_INOUTPORTREG.
1316         * i386-init.h: Re-generate.
1317
1318 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1319
1320         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1321         (wrssq, wrussq): Add Qword.
1322         * i386-tbl.h: Re-generate.
1323
1324 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1325
1326         * i386-opc.h: Rename OTMax to OTNum.
1327         (OTNumOfUints): Adjust calculation.
1328         (OTUnused): Directly alias to OTNum.
1329
1330 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1331
1332         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1333         `reg_xys'.
1334         (lea_reg_xys): Likewise.
1335         (print_insn_loop_primitive): Rename `reg' local variable to
1336         `reg_dxy'.
1337
1338 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1339
1340         PR binutils/23242
1341         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1342
1343 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1344
1345         PR binutils/23369
1346         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1347         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1348
1349 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1350
1351         PR tdep/8282
1352         * mips-dis.c (mips_option_arg_t): New enumeration.
1353         (mips_options): New variable.
1354         (disassembler_options_mips): New function.
1355         (print_mips_disassembler_options): Reimplement in terms of
1356         `disassembler_options_mips'.
1357         * arm-dis.c (disassembler_options_arm): Adapt to using the
1358         `disasm_options_and_args_t' structure.
1359         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1360         * s390-dis.c (disassembler_options_s390): Likewise.
1361
1362 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1363
1364         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1365         expected result.
1366         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1367         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1368         * testsuite/ld-arm/tls-longplt.d: Likewise.
1369
1370 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1371
1372         PR binutils/23192
1373         * aarch64-asm-2.c: Regenerate.
1374         * aarch64-dis-2.c: Likewise.
1375         * aarch64-opc-2.c: Likewise.
1376         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1377         * aarch64-opc.c (operand_general_constraint_met_p,
1378         aarch64_print_operand): Likewise.
1379         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1380         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1381         fmlal2, fmlsl2.
1382         (AARCH64_OPERANDS): Add Em2.
1383
1384 2018-06-26  Nick Clifton  <nickc@redhat.com>
1385
1386         * po/uk.po: Updated Ukranian translation.
1387         * po/de.po: Updated German translation.
1388         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1389
1390 2018-06-26  Nick Clifton  <nickc@redhat.com>
1391
1392         * nfp-dis.c: Fix spelling mistake.
1393
1394 2018-06-24  Nick Clifton  <nickc@redhat.com>
1395
1396         * configure: Regenerate.
1397         * po/opcodes.pot: Regenerate.
1398
1399 2018-06-24  Nick Clifton  <nickc@redhat.com>
1400
1401         2.31 branch created.
1402
1403 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1404
1405         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1406         * aarch64-asm-2.c: Regenerate.
1407         * aarch64-dis-2.c: Likewise.
1408
1409 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1410
1411         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1412         `-M ginv' option description.
1413
1414 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1415
1416         PR gas/23305
1417         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1418         la and lla.
1419
1420 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1421
1422         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1423         * configure.ac: Remove AC_PREREQ.
1424         * Makefile.in: Re-generate.
1425         * aclocal.m4: Re-generate.
1426         * configure: Re-generate.
1427
1428 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1429
1430         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1431         mips64r6 descriptors.
1432         (parse_mips_ase_option): Handle -Mginv option.
1433         (print_mips_disassembler_options): Document -Mginv.
1434         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1435         (GINV): New macro.
1436         (mips_opcodes): Define ginvi and ginvt.
1437
1438 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1439             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1440
1441         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1442         * mips-opc.c (CRC, CRC64): New macros.
1443         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1444         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1445         crc32cd for CRC64.
1446
1447 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1448
1449         PR 20319
1450         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1451         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1452
1453 2018-06-06  Alan Modra  <amodra@gmail.com>
1454
1455         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1456         setjmp.  Move init for some other vars later too.
1457
1458 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1459
1460         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1461         (dis_private): Add new fields for property section tracking.
1462         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1463         (xtensa_instruction_fits): New functions.
1464         (fetch_data): Bump minimal fetch size to 4.
1465         (print_insn_xtensa): Make struct dis_private static.
1466         Load and prepare property table on section change.
1467         Don't disassemble literals. Don't disassemble instructions that
1468         cross property table boundaries.
1469
1470 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1471
1472         * configure: Regenerated.
1473
1474 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1475
1476         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1477         * i386-tbl.h: Re-generate.
1478
1479 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1480
1481         * i386-opc.tbl (sldt, str): Add NoRex64.
1482         * i386-tbl.h: Re-generate.
1483
1484 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1485
1486         * i386-opc.tbl (invpcid): Add Oword.
1487         * i386-tbl.h: Re-generate.
1488
1489 2018-06-01  Alan Modra  <amodra@gmail.com>
1490
1491         * sysdep.h (_bfd_error_handler): Don't declare.
1492         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1493         * rl78-decode.opc: Likewise.
1494         * msp430-decode.c: Regenerate.
1495         * rl78-decode.c: Regenerate.
1496
1497 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1498
1499         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1500         * i386-init.h : Regenerated.
1501
1502 2018-05-25  Alan Modra  <amodra@gmail.com>
1503
1504         * Makefile.in: Regenerate.
1505         * po/POTFILES.in: Regenerate.
1506
1507 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1508
1509         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1510         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1511         (insert_bab, extract_bab, insert_btab, extract_btab,
1512         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1513         (BAT, BBA VBA RBS XB6S): Delete macros.
1514         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1515         (BB, BD, RBX, XC6): Update for new macros.
1516         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1517         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1518         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1519         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1520
1521 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1522
1523         * Makefile.am: Add support for s12z architecture.
1524         * configure.ac: Likewise.
1525         * disassemble.c: Likewise.
1526         * disassemble.h: Likewise.
1527         * Makefile.in: Regenerate.
1528         * configure: Regenerate.
1529         * s12z-dis.c: New file.
1530         * s12z.h: New file.
1531
1532 2018-05-18  Alan Modra  <amodra@gmail.com>
1533
1534         * nfp-dis.c: Don't #include libbfd.h.
1535         (init_nfp3200_priv): Use bfd_get_section_contents.
1536         (nit_nfp6000_mecsr_sec): Likewise.
1537
1538 2018-05-17  Nick Clifton  <nickc@redhat.com>
1539
1540         * po/zh_CN.po: Updated simplified Chinese translation.
1541
1542 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1543
1544         PR binutils/23109
1545         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1546         * aarch64-dis-2.c: Regenerate.
1547
1548 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1549
1550         PR binutils/21446
1551         * aarch64-asm.c (opintl.h): Include.
1552         (aarch64_ins_sysreg): Enforce read/write constraints.
1553         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1554         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1555         (F_REG_READ, F_REG_WRITE): New.
1556         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1557         AARCH64_OPND_SYSREG.
1558         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1559         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1560         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1561         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1562         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1563         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1564         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1565         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1566         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1567         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1568         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1569         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1570         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1571         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1572         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1573         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1574         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1575
1576 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1577
1578         PR binutils/21446
1579         * aarch64-dis.c (no_notes: New.
1580         (parse_aarch64_dis_option): Support notes.
1581         (aarch64_decode_insn, print_operands): Likewise.
1582         (print_aarch64_disassembler_options): Document notes.
1583         * aarch64-opc.c (aarch64_print_operand): Support notes.
1584
1585 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1586
1587         PR binutils/21446
1588         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1589         and take error struct.
1590         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1591         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1592         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1593         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1594         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1595         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1596         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1597         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1598         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1599         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1600         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1601         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1602         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1603         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1604         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1605         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1606         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1607         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1608         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1609         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1610         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1611         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1612         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1613         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1614         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1615         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1616         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1617         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1618         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1619         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1620         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1621         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1622         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1623         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1624         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1625         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1626         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1627         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1628         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1629         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1630         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1631         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1632         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1633         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1634         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1635         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1636         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1637         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1638         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1639         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1640         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1641         (determine_disassembling_preference, aarch64_decode_insn,
1642         print_insn_aarch64_word, print_insn_data): Take errors struct.
1643         (print_insn_aarch64): Use errors.
1644         * aarch64-asm-2.c: Regenerate.
1645         * aarch64-dis-2.c: Regenerate.
1646         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1647         boolean in aarch64_insert_operan.
1648         (print_operand_extractor): Likewise.
1649         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1650
1651 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1652
1653         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1654
1655 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1656
1657         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1658
1659 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1660
1661         * cr16-opc.c (cr16_instruction): Comment typo fix.
1662         * hppa-dis.c (print_insn_hppa): Likewise.
1663
1664 2018-05-08  Jim Wilson  <jimw@sifive.com>
1665
1666         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1667         (match_c_slli64, match_srxi_as_c_srxi): New.
1668         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1669         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1670         <c.slli, c.srli, c.srai>: Use match_s_slli.
1671         <c.slli64, c.srli64, c.srai64>: New.
1672
1673 2018-05-08  Alan Modra  <amodra@gmail.com>
1674
1675         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1676         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1677         partition opcode space for index lookup.
1678
1679 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1680
1681         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1682         <insn_length>: ...with this.  Update usage.
1683         Remove duplicate call to *info->memory_error_func.
1684
1685 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1686             H.J. Lu  <hongjiu.lu@intel.com>
1687
1688         * i386-dis.c (Gva): New.
1689         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1690         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1691         (prefix_table): New instructions (see prefix above).
1692         (mod_table): New instructions (see prefix above).
1693         (OP_G): Handle va_mode.
1694         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1695         CPU_MOVDIR64B_FLAGS.
1696         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1697         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1698         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1699         * i386-opc.tbl: Add movidir{i,64b}.
1700         * i386-init.h: Regenerated.
1701         * i386-tbl.h: Likewise.
1702
1703 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1704
1705         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1706         AddrPrefixOpReg.
1707         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1708         (AddrPrefixOpReg): This.
1709         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1710         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1711
1712 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1713
1714         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1715         (vle_num_opcodes): Likewise.
1716         (spe2_num_opcodes): Likewise.
1717         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1718         initialization loop.
1719         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1720         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1721         only once.
1722
1723 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1724
1725         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1726
1727 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1728
1729         Makefile.am: Added nfp-dis.c.
1730         configure.ac: Added bfd_nfp_arch.
1731         disassemble.h: Added print_insn_nfp prototype.
1732         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1733         nfp-dis.c: New, for NFP support.
1734         po/POTFILES.in: Added nfp-dis.c to the list.
1735         Makefile.in: Regenerate.
1736         configure: Regenerate.
1737
1738 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1739
1740         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1741         templates into their base ones.
1742         * i386-tlb.h: Re-generate.
1743
1744 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1745
1746         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1747         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1748         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1749         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1750         * i386-init.h: Re-generate.
1751
1752 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1753
1754         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1755         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1756         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1757         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1758         comment.
1759         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1760         and CpuRegMask.
1761         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1762         CpuRegMask: Delete.
1763         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1764         cpuregzmm, and cpuregmask.
1765         * i386-init.h: Re-generate.
1766         * i386-tbl.h: Re-generate.
1767
1768 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1769
1770         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1771         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1772         * i386-init.h: Re-generate.
1773
1774 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1775
1776         * i386-gen.c (VexImmExt): Delete.
1777         * i386-opc.h (VexImmExt, veximmext): Delete.
1778         * i386-opc.tbl: Drop all VexImmExt uses.
1779         * i386-tlb.h: Re-generate.
1780
1781 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1782
1783         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1784         register-only forms.
1785         * i386-tlb.h: Re-generate.
1786
1787 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1788
1789         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1790
1791 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1792
1793         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1794         PREFIX_0F1C.
1795         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1796         (cpu_flags): Add CpuCLDEMOTE.
1797         * i386-init.h: Regenerate.
1798         * i386-opc.h (enum): Add CpuCLDEMOTE,
1799         (i386_cpu_flags): Add cpucldemote.
1800         * i386-opc.tbl: Add cldemote.
1801         * i386-tbl.h: Regenerate.
1802
1803 2018-04-16  Alan Modra  <amodra@gmail.com>
1804
1805         * Makefile.am: Remove sh5 and sh64 support.
1806         * configure.ac: Likewise.
1807         * disassemble.c: Likewise.
1808         * disassemble.h: Likewise.
1809         * sh-dis.c: Likewise.
1810         * sh64-dis.c: Delete.
1811         * sh64-opc.c: Delete.
1812         * sh64-opc.h: Delete.
1813         * Makefile.in: Regenerate.
1814         * configure: Regenerate.
1815         * po/POTFILES.in: Regenerate.
1816
1817 2018-04-16  Alan Modra  <amodra@gmail.com>
1818
1819         * Makefile.am: Remove w65 support.
1820         * configure.ac: Likewise.
1821         * disassemble.c: Likewise.
1822         * disassemble.h: Likewise.
1823         * w65-dis.c: Delete.
1824         * w65-opc.h: Delete.
1825         * Makefile.in: Regenerate.
1826         * configure: Regenerate.
1827         * po/POTFILES.in: Regenerate.
1828
1829 2018-04-16  Alan Modra  <amodra@gmail.com>
1830
1831         * configure.ac: Remove we32k support.
1832         * configure: Regenerate.
1833
1834 2018-04-16  Alan Modra  <amodra@gmail.com>
1835
1836         * Makefile.am: Remove m88k support.
1837         * configure.ac: Likewise.
1838         * disassemble.c: Likewise.
1839         * disassemble.h: Likewise.
1840         * m88k-dis.c: Delete.
1841         * Makefile.in: Regenerate.
1842         * configure: Regenerate.
1843         * po/POTFILES.in: Regenerate.
1844
1845 2018-04-16  Alan Modra  <amodra@gmail.com>
1846
1847         * Makefile.am: Remove i370 support.
1848         * configure.ac: Likewise.
1849         * disassemble.c: Likewise.
1850         * disassemble.h: Likewise.
1851         * i370-dis.c: Delete.
1852         * i370-opc.c: Delete.
1853         * Makefile.in: Regenerate.
1854         * configure: Regenerate.
1855         * po/POTFILES.in: Regenerate.
1856
1857 2018-04-16  Alan Modra  <amodra@gmail.com>
1858
1859         * Makefile.am: Remove h8500 support.
1860         * configure.ac: Likewise.
1861         * disassemble.c: Likewise.
1862         * disassemble.h: Likewise.
1863         * h8500-dis.c: Delete.
1864         * h8500-opc.h: Delete.
1865         * Makefile.in: Regenerate.
1866         * configure: Regenerate.
1867         * po/POTFILES.in: Regenerate.
1868
1869 2018-04-16  Alan Modra  <amodra@gmail.com>
1870
1871         * configure.ac: Remove tahoe support.
1872         * configure: Regenerate.
1873
1874 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1875
1876         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1877         umwait.
1878         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1879         64-bit mode.
1880         * i386-tbl.h: Regenerated.
1881
1882 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1883
1884         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1885         PREFIX_MOD_1_0FAE_REG_6.
1886         (va_mode): New.
1887         (OP_E_register): Use va_mode.
1888         * i386-dis-evex.h (prefix_table):
1889         New instructions (see prefixes above).
1890         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1891         (cpu_flags): Likewise.
1892         * i386-opc.h (enum): Likewise.
1893         (i386_cpu_flags): Likewise.
1894         * i386-opc.tbl: Add umonitor, umwait, tpause.
1895         * i386-init.h: Regenerate.
1896         * i386-tbl.h: Likewise.
1897
1898 2018-04-11  Alan Modra  <amodra@gmail.com>
1899
1900         * opcodes/i860-dis.c: Delete.
1901         * opcodes/i960-dis.c: Delete.
1902         * Makefile.am: Remove i860 and i960 support.
1903         * configure.ac: Likewise.
1904         * disassemble.c: Likewise.
1905         * disassemble.h: Likewise.
1906         * Makefile.in: Regenerate.
1907         * configure: Regenerate.
1908         * po/POTFILES.in: Regenerate.
1909
1910 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1911
1912         PR binutils/23025
1913         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1914         to 0.
1915         (print_insn): Clear vex instead of vex.evex.
1916
1917 2018-04-04  Nick Clifton  <nickc@redhat.com>
1918
1919         * po/es.po: Updated Spanish translation.
1920
1921 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1922
1923         * i386-gen.c (opcode_modifiers): Delete VecESize.
1924         * i386-opc.h (VecESize): Delete.
1925         (struct i386_opcode_modifier): Delete vecesize.
1926         * i386-opc.tbl: Drop VecESize.
1927         * i386-tlb.h: Re-generate.
1928
1929 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1930
1931         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1932         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1933         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1934         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1935         * i386-tlb.h: Re-generate.
1936
1937 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1938
1939         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1940         Fold AVX512 forms
1941         * i386-tlb.h: Re-generate.
1942
1943 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1944
1945         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1946         (vex_len_table): Drop Y for vcvt*2si.
1947         (putop): Replace plain 'Y' handling by abort().
1948
1949 2018-03-28  Nick Clifton  <nickc@redhat.com>
1950
1951         PR 22988
1952         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1953         instructions with only a base address register.
1954         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1955         handle AARHC64_OPND_SVE_ADDR_R.
1956         (aarch64_print_operand): Likewise.
1957         * aarch64-asm-2.c: Regenerate.
1958         * aarch64_dis-2.c: Regenerate.
1959         * aarch64-opc-2.c: Regenerate.
1960
1961 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1962
1963         * i386-opc.tbl: Drop VecESize from register only insn forms and
1964         memory forms not allowing broadcast.
1965         * i386-tlb.h: Re-generate.
1966
1967 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1968
1969         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1970         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1971         sha256*): Drop Disp<N>.
1972
1973 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1974
1975         * i386-dis.c (EbndS, bnd_swap_mode): New.
1976         (prefix_table): Use EbndS.
1977         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1978         * i386-opc.tbl (bndmov): Move misplaced Load.
1979         * i386-tlb.h: Re-generate.
1980
1981 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1982
1983         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1984         templates allowing memory operands and folded ones for register
1985         only flavors.
1986         * i386-tlb.h: Re-generate.
1987
1988 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1989
1990         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1991         256-bit templates. Drop redundant leftover Disp<N>.
1992         * i386-tlb.h: Re-generate.
1993
1994 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1995
1996         * riscv-opc.c (riscv_insn_types): New.
1997
1998 2018-03-13  Nick Clifton  <nickc@redhat.com>
1999
2000         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2001
2002 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2003
2004         * i386-opc.tbl: Add Optimize to clr.
2005         * i386-tbl.h: Regenerated.
2006
2007 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
2008
2009         * i386-gen.c (opcode_modifiers): Remove OldGcc.
2010         * i386-opc.h (OldGcc): Removed.
2011         (i386_opcode_modifier): Remove oldgcc.
2012         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2013         instructions for old (<= 2.8.1) versions of gcc.
2014         * i386-tbl.h: Regenerated.
2015
2016 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2017
2018         * i386-opc.h (EVEXDYN): New.
2019         * i386-opc.tbl: Fold various AVX512VL templates.
2020         * i386-tlb.h: Re-generate.
2021
2022 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2023
2024         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2025         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2026         vpexpandd, vpexpandq): Fold AFX512VF templates.
2027         * i386-tlb.h: Re-generate.
2028
2029 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2030
2031         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2032         Fold 128- and 256-bit VEX-encoded templates.
2033         * i386-tlb.h: Re-generate.
2034
2035 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2036
2037         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2038         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2039         vpexpandd, vpexpandq): Fold AVX512F templates.
2040         * i386-tlb.h: Re-generate.
2041
2042 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2043
2044         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2045         64-bit templates. Drop Disp<N>.
2046         * i386-tlb.h: Re-generate.
2047
2048 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2049
2050         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2051         and 256-bit templates.
2052         * i386-tlb.h: Re-generate.
2053
2054 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2055
2056         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2057         * i386-tlb.h: Re-generate.
2058
2059 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2060
2061         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2062         Drop NoAVX.
2063         * i386-tlb.h: Re-generate.
2064
2065 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2066
2067         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2068         * i386-tlb.h: Re-generate.
2069
2070 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2071
2072         * i386-gen.c (opcode_modifiers): Delete FloatD.
2073         * i386-opc.h (FloatD): Delete.
2074         (struct i386_opcode_modifier): Delete floatd.
2075         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2076         FloatD by D.
2077         * i386-tlb.h: Re-generate.
2078
2079 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2080
2081         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2082
2083 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2084
2085         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2086         * i386-tlb.h: Re-generate.
2087
2088 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2089
2090         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2091         forms.
2092         * i386-tlb.h: Re-generate.
2093
2094 2018-03-07  Alan Modra  <amodra@gmail.com>
2095
2096         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2097         bfd_arch_rs6000.
2098         * disassemble.h (print_insn_rs6000): Delete.
2099         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2100         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2101         (print_insn_rs6000): Delete.
2102
2103 2018-03-03  Alan Modra  <amodra@gmail.com>
2104
2105         * sysdep.h (opcodes_error_handler): Define.
2106         (_bfd_error_handler): Declare.
2107         * Makefile.am: Remove stray #.
2108         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2109         EDIT" comment.
2110         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2111         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2112         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2113         opcodes_error_handler to print errors.  Standardize error messages.
2114         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2115         and include opintl.h.
2116         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2117         * i386-gen.c: Standardize error messages.
2118         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2119         * Makefile.in: Regenerate.
2120         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2121         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2122         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2123         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2124         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2125         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2126         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2127         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2128         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2129         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2130         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2131         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2132         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2133
2134 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2135
2136         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2137         vpsub[bwdq] instructions.
2138         * i386-tbl.h: Regenerated.
2139
2140 2018-03-01  Alan Modra  <amodra@gmail.com>
2141
2142         * configure.ac (ALL_LINGUAS): Sort.
2143         * configure: Regenerate.
2144
2145 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2146
2147         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2148         macro by assignements.
2149
2150 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2151
2152         PR gas/22871
2153         * i386-gen.c (opcode_modifiers): Add Optimize.
2154         * i386-opc.h (Optimize): New enum.
2155         (i386_opcode_modifier): Add optimize.
2156         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2157         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2158         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2159         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2160         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2161         vpxord and vpxorq.
2162         * i386-tbl.h: Regenerated.
2163
2164 2018-02-26  Alan Modra  <amodra@gmail.com>
2165
2166         * crx-dis.c (getregliststring): Allocate a large enough buffer
2167         to silence false positive gcc8 warning.
2168
2169 2018-02-22  Shea Levy <shea@shealevy.com>
2170
2171         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2172
2173 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2174
2175         * i386-opc.tbl: Add {rex},
2176         * i386-tbl.h: Regenerated.
2177
2178 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2179
2180         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2181         (mips16_opcodes): Replace `M' with `m' for "restore".
2182
2183 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2184
2185         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2186
2187 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2188
2189         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2190         variable to `function_index'.
2191
2192 2018-02-13  Nick Clifton  <nickc@redhat.com>
2193
2194         PR 22823
2195         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2196         about truncation of printing.
2197
2198 2018-02-12  Henry Wong <henry@stuffedcow.net>
2199
2200         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2201
2202 2018-02-05  Nick Clifton  <nickc@redhat.com>
2203
2204         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2205
2206 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2207
2208         * i386-dis.c (enum): Add pconfig.
2209         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2210         (cpu_flags): Add CpuPCONFIG.
2211         * i386-opc.h (enum): Add CpuPCONFIG.
2212         (i386_cpu_flags): Add cpupconfig.
2213         * i386-opc.tbl: Add PCONFIG instruction.
2214         * i386-init.h: Regenerate.
2215         * i386-tbl.h: Likewise.
2216
2217 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2218
2219         * i386-dis.c (enum): Add PREFIX_0F09.
2220         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2221         (cpu_flags): Add CpuWBNOINVD.
2222         * i386-opc.h (enum): Add CpuWBNOINVD.
2223         (i386_cpu_flags): Add cpuwbnoinvd.
2224         * i386-opc.tbl: Add WBNOINVD instruction.
2225         * i386-init.h: Regenerate.
2226         * i386-tbl.h: Likewise.
2227
2228 2018-01-17  Jim Wilson  <jimw@sifive.com>
2229
2230         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2231
2232 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2233
2234         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2235         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2236         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2237         (cpu_flags): Add CpuIBT, CpuSHSTK.
2238         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2239         (i386_cpu_flags): Add cpuibt, cpushstk.
2240         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2241         * i386-init.h: Regenerate.
2242         * i386-tbl.h: Likewise.
2243
2244 2018-01-16  Nick Clifton  <nickc@redhat.com>
2245
2246         * po/pt_BR.po: Updated Brazilian Portugese translation.
2247         * po/de.po: Updated German translation.
2248
2249 2018-01-15  Jim Wilson  <jimw@sifive.com>
2250
2251         * riscv-opc.c (match_c_nop): New.
2252         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2253
2254 2018-01-15  Nick Clifton  <nickc@redhat.com>
2255
2256         * po/uk.po: Updated Ukranian translation.
2257
2258 2018-01-13  Nick Clifton  <nickc@redhat.com>
2259
2260         * po/opcodes.pot: Regenerated.
2261
2262 2018-01-13  Nick Clifton  <nickc@redhat.com>
2263
2264         * configure: Regenerate.
2265
2266 2018-01-13  Nick Clifton  <nickc@redhat.com>
2267
2268         2.30 branch created.
2269
2270 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2271
2272         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2273         * i386-tbl.h: Regenerate.
2274
2275 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2276
2277         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2278         * i386-tbl.h: Re-generate.
2279
2280 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2281
2282         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2283         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2284         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2285         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2286         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2287         Disp8MemShift of AVX512VL forms.
2288         * i386-tbl.h: Re-generate.
2289
2290 2018-01-09  Jim Wilson  <jimw@sifive.com>
2291
2292         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2293         then the hi_addr value is zero.
2294
2295 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2296
2297         * arm-dis.c (arm_opcodes): Add csdb.
2298         (thumb32_opcodes): Add csdb.
2299
2300 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2301
2302         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2303         * aarch64-asm-2.c: Regenerate.
2304         * aarch64-dis-2.c: Regenerate.
2305         * aarch64-opc-2.c: Regenerate.
2306
2307 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2308
2309         PR gas/22681
2310         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2311         Remove AVX512 vmovd with 64-bit operands.
2312         * i386-tbl.h: Regenerated.
2313
2314 2018-01-05  Jim Wilson  <jimw@sifive.com>
2315
2316         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2317         jalr.
2318
2319 2018-01-03  Alan Modra  <amodra@gmail.com>
2320
2321         Update year range in copyright notice of all files.
2322
2323 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2324
2325         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2326         and OPERAND_TYPE_REGZMM entries.
2327
2328 For older changes see ChangeLog-2017
2329 \f
2330 Copyright (C) 2018 Free Software Foundation, Inc.
2331
2332 Copying and distribution of this file, with or without modification,
2333 are permitted in any medium without royalty provided the copyright
2334 notice and this notice are preserved.
2335
2336 Local Variables:
2337 mode: change-log
2338 left-margin: 8
2339 fill-column: 74
2340 version-control: never
2341 End: