opcodes/ChangeLog

   1 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
   4         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
   5         with the hint immediate.
   6         * aarch64-opc.c (aarch64_hint_options): New entries for
   7         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
   8         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
   9         while checking for HINT_OPD_F_NOPRINT flag.
  10         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
  11         extract value.
  12         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
  13         (aarch64_opcode_table): Add entry for BTI.
  14         (AARCH64_OPERANDS): Add new description for BTI targets.
  15         * aarch64-asm-2.c: Regenerate.
  16         * aarch64-dis-2.c: Regenerate.
  17         * aarch64-opc-2.c: Regenerate.
  18
  19 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  20
  21         * aarch64-opc.c (aarch64_sys_regs): New entries for
  22         rndr and rndrrs.
  23         (aarch64_sys_reg_supported_p): New check for above.
  24
  25 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  26
  27         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
  28         (aarch64_sys_ins_reg_supported_p): New check for above.
  29
  30 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  31
  32         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
  33         AARCH64_OPND_SYSREG_SR.
  34         * aarch64-opc.c (aarch64_print_operand): Likewise.
  35         (aarch64_sys_regs_sr): Define table.
  36         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
  37         AARCH64_FEATURE_PREDRES.
  38         * aarch64-tbl.h (aarch64_feature_predres): New.
  39         (PREDRES, PREDRES_INSN): New.
  40         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
  41         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
  42         * aarch64-asm-2.c: Regenerate.
  43         * aarch64-dis-2.c: Regenerate.
  44         * aarch64-opc-2.c: Regenerate.
  45
  46 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  47
  48         * aarch64-tbl.h (aarch64_feature_sb): New.
  49         (SB, SB_INSN): New.
  50         (aarch64_opcode_table): Add entry for sb.
  51         * aarch64-asm-2.c: Regenerate.
  52         * aarch64-dis-2.c: Regenerate.
  53         * aarch64-opc-2.c: Regenerate.
  54
  55 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  56
  57         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
  58         (aarch64_feature_frintts): New.
  59         (FLAGMANIP, FRINTTS): New.
  60         (aarch64_opcode_table): Add entries for xaflag, axflag
  61         and frint[32,64][x,z] instructions.
  62         * aarch64-asm-2.c: Regenerate.
  63         * aarch64-dis-2.c: Regenerate.
  64         * aarch64-opc-2.c: Regenerate.
  65
  66 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  67
  68         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
  69         (ARMV8_5, V8_5_INSN): New.
  70
  71 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
  72
  73         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
  74
  75 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
  76
  77         * i386-dis.c (rm_table): Add enclv.
  78         * i386-opc.tbl: Add enclv.
  79         * i386-tbl.h: Regenerated.
  80
  81 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
  82
  83         * arm-dis.c (arm_opcodes): Add sb.
  84         (thumb32_opcodes): Likewise.
  85
  86 2018-10-05  Richard Henderson  <rth@twiddle.net>
  87             Stafford Horne  <shorne@gmail.com>
  88
  89         * or1k-desc.c: Regenerate.
  90         * or1k-desc.h: Regenerate.
  91         * or1k-opc.c: Regenerate.
  92         * or1k-opc.h: Regenerate.
  93         * or1k-opinst.c: Regenerate.
  94
  95 2018-10-05  Richard Henderson  <rth@twiddle.net>
  96
  97         * or1k-asm.c: Regenerated.
  98         * or1k-desc.c: Regenerated.
  99         * or1k-desc.h: Regenerated.
 100         * or1k-dis.c: Regenerated.
 101         * or1k-ibld.c: Regenerated.
 102         * or1k-opc.c: Regenerated.
 103         * or1k-opc.h: Regenerated.
 104         * or1k-opinst.c: Regenerated.
 105
 106 2018-10-05  Richard Henderson  <rth@twiddle.net>
 107
 108         * or1k-asm.c: Regenerate.
 109
 110 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 111
 112         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 113         * aarch64-dis.c (print_operands): Refactor to take notes.
 114         (print_verifier_notes): New.
 115         (print_aarch64_insn): Apply constraint verifier.
 116         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 117         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 118
 119 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 120
 121         * aarch64-opc.c (init_insn_block): New.
 122         (verify_constraints, aarch64_is_destructive_by_operands): New.
 123         * aarch64-opc.h (verify_constraints): New.
 124
 125 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 126
 127         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 128         * aarch64-opc.c (verify_ldpsw): Update arguments.
 129
 130 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 131
 132         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 133         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 134
 135 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 136
 137         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 138         * aarch64-dis.c (insn_sequence): New.
 139
 140 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 141
 142         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 143         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 144         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 145         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 146         constraints.
 147         (_SVE_INSNC): New.
 148         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 149         constraints.
 150         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 151         F_SCAN flags.
 152         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 153         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 154         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 155         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 156         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 157         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 158         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 159
 160 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 161
 162         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 163
 164 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 165
 166         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 167         are used when extracting signed fields and converting them to
 168         potentially 64-bit types.
 169
 170 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 171
 172         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 173         * Makefile.in: Re-generate.
 174         * aclocal.m4: Re-generate.
 175         * configure: Re-generate.
 176         * configure.ac: Remove check for -Wno-missing-field-initializers.
 177         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 178         (csky_v2_opcodes): Likewise.
 179
 180 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 181
 182         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 183
 184 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 185
 186         * nds32-asm.c (operand_fields): Remove the unused fields.
 187         (nds32_opcodes): Remove the unused instructions.
 188         * nds32-dis.c (nds32_ex9_info): Removed.
 189         (nds32_parse_opcode): Updated.
 190         (print_insn_nds32): Likewise.
 191         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 192         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 193         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 194         build_opcode_hash_table): New functions.
 195         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 196         nds32_opcode_table): New.
 197         (hw_ktabs): Declare it to a pointer rather than an array.
 198         (build_hash_table): Removed.
 199         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 200         SYN_ROPT and upadte HW_GPR and HW_INT.
 201         * nds32-dis.c (keywords): Remove const.
 202         (match_field): New function.
 203         (nds32_parse_opcode): Updated.
 204         * disassemble.c (disassemble_init_for_target):
 205         Add disassemble_init_nds32.
 206         * nds32-dis.c (eum map_type): New.
 207         (nds32_private_data): Likewise.
 208         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 209         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 210         (print_insn_nds32): Updated.
 211         * nds32-asm.c (parse_aext_reg): Add new parameter.
 212         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 213         are allowed to use.
 214         All callers changed.
 215         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 216         (operand_fields): Add new fields.
 217         (nds32_opcodes): Add new instructions.
 218         (keyword_aridxi_mx): New keyword.
 219         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 220         and NASM_ATTR_ZOL.
 221         (ALU2_1, ALU2_2, ALU2_3): New macros.
 222         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 223
 224 2018-09-17  Kito Cheng  <kito@andestech.com>
 225
 226         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 227
 228 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 229
 230         PR gas/23670
 231         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 232         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 233         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 234         (EVEX_LEN_0F7E_P_1): Likewise.
 235         (EVEX_LEN_0F7E_P_2): Likewise.
 236         (EVEX_LEN_0FD6_P_2): Likewise.
 237         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 238         (EVEX_LEN_TABLE): Likewise.
 239         (EVEX_LEN_0F6E_P_2): New enum.
 240         (EVEX_LEN_0F7E_P_1): Likewise.
 241         (EVEX_LEN_0F7E_P_2): Likewise.
 242         (EVEX_LEN_0FD6_P_2): Likewise.
 243         (evex_len_table): New.
 244         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 245         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 246         * i386-tbl.h: Regenerated.
 247
 248 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 249
 250         PR gas/23665
 251         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 252         VEX_LEN_0F7E_P_2 entries.
 253         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 254         * i386-tbl.h: Regenerated.
 255
 256 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 257
 258         * i386-dis.c (VZERO_Fixup): Removed.
 259         (VZERO): Likewise.
 260         (VEX_LEN_0F10_P_1): Likewise.
 261         (VEX_LEN_0F10_P_3): Likewise.
 262         (VEX_LEN_0F11_P_1): Likewise.
 263         (VEX_LEN_0F11_P_3): Likewise.
 264         (VEX_LEN_0F2E_P_0): Likewise.
 265         (VEX_LEN_0F2E_P_2): Likewise.
 266         (VEX_LEN_0F2F_P_0): Likewise.
 267         (VEX_LEN_0F2F_P_2): Likewise.
 268         (VEX_LEN_0F51_P_1): Likewise.
 269         (VEX_LEN_0F51_P_3): Likewise.
 270         (VEX_LEN_0F52_P_1): Likewise.
 271         (VEX_LEN_0F53_P_1): Likewise.
 272         (VEX_LEN_0F58_P_1): Likewise.
 273         (VEX_LEN_0F58_P_3): Likewise.
 274         (VEX_LEN_0F59_P_1): Likewise.
 275         (VEX_LEN_0F59_P_3): Likewise.
 276         (VEX_LEN_0F5A_P_1): Likewise.
 277         (VEX_LEN_0F5A_P_3): Likewise.
 278         (VEX_LEN_0F5C_P_1): Likewise.
 279         (VEX_LEN_0F5C_P_3): Likewise.
 280         (VEX_LEN_0F5D_P_1): Likewise.
 281         (VEX_LEN_0F5D_P_3): Likewise.
 282         (VEX_LEN_0F5E_P_1): Likewise.
 283         (VEX_LEN_0F5E_P_3): Likewise.
 284         (VEX_LEN_0F5F_P_1): Likewise.
 285         (VEX_LEN_0F5F_P_3): Likewise.
 286         (VEX_LEN_0FC2_P_1): Likewise.
 287         (VEX_LEN_0FC2_P_3): Likewise.
 288         (VEX_LEN_0F3A0A_P_2): Likewise.
 289         (VEX_LEN_0F3A0B_P_2): Likewise.
 290         (VEX_W_0F10_P_0): Likewise.
 291         (VEX_W_0F10_P_1): Likewise.
 292         (VEX_W_0F10_P_2): Likewise.
 293         (VEX_W_0F10_P_3): Likewise.
 294         (VEX_W_0F11_P_0): Likewise.
 295         (VEX_W_0F11_P_1): Likewise.
 296         (VEX_W_0F11_P_2): Likewise.
 297         (VEX_W_0F11_P_3): Likewise.
 298         (VEX_W_0F12_P_0_M_0): Likewise.
 299         (VEX_W_0F12_P_0_M_1): Likewise.
 300         (VEX_W_0F12_P_1): Likewise.
 301         (VEX_W_0F12_P_2): Likewise.
 302         (VEX_W_0F12_P_3): Likewise.
 303         (VEX_W_0F13_M_0): Likewise.
 304         (VEX_W_0F14): Likewise.
 305         (VEX_W_0F15): Likewise.
 306         (VEX_W_0F16_P_0_M_0): Likewise.
 307         (VEX_W_0F16_P_0_M_1): Likewise.
 308         (VEX_W_0F16_P_1): Likewise.
 309         (VEX_W_0F16_P_2): Likewise.
 310         (VEX_W_0F17_M_0): Likewise.
 311         (VEX_W_0F28): Likewise.
 312         (VEX_W_0F29): Likewise.
 313         (VEX_W_0F2B_M_0): Likewise.
 314         (VEX_W_0F2E_P_0): Likewise.
 315         (VEX_W_0F2E_P_2): Likewise.
 316         (VEX_W_0F2F_P_0): Likewise.
 317         (VEX_W_0F2F_P_2): Likewise.
 318         (VEX_W_0F50_M_0): Likewise.
 319         (VEX_W_0F51_P_0): Likewise.
 320         (VEX_W_0F51_P_1): Likewise.
 321         (VEX_W_0F51_P_2): Likewise.
 322         (VEX_W_0F51_P_3): Likewise.
 323         (VEX_W_0F52_P_0): Likewise.
 324         (VEX_W_0F52_P_1): Likewise.
 325         (VEX_W_0F53_P_0): Likewise.
 326         (VEX_W_0F53_P_1): Likewise.
 327         (VEX_W_0F58_P_0): Likewise.
 328         (VEX_W_0F58_P_1): Likewise.
 329         (VEX_W_0F58_P_2): Likewise.
 330         (VEX_W_0F58_P_3): Likewise.
 331         (VEX_W_0F59_P_0): Likewise.
 332         (VEX_W_0F59_P_1): Likewise.
 333         (VEX_W_0F59_P_2): Likewise.
 334         (VEX_W_0F59_P_3): Likewise.
 335         (VEX_W_0F5A_P_0): Likewise.
 336         (VEX_W_0F5A_P_1): Likewise.
 337         (VEX_W_0F5A_P_3): Likewise.
 338         (VEX_W_0F5B_P_0): Likewise.
 339         (VEX_W_0F5B_P_1): Likewise.
 340         (VEX_W_0F5B_P_2): Likewise.
 341         (VEX_W_0F5C_P_0): Likewise.
 342         (VEX_W_0F5C_P_1): Likewise.
 343         (VEX_W_0F5C_P_2): Likewise.
 344         (VEX_W_0F5C_P_3): Likewise.
 345         (VEX_W_0F5D_P_0): Likewise.
 346         (VEX_W_0F5D_P_1): Likewise.
 347         (VEX_W_0F5D_P_2): Likewise.
 348         (VEX_W_0F5D_P_3): Likewise.
 349         (VEX_W_0F5E_P_0): Likewise.
 350         (VEX_W_0F5E_P_1): Likewise.
 351         (VEX_W_0F5E_P_2): Likewise.
 352         (VEX_W_0F5E_P_3): Likewise.
 353         (VEX_W_0F5F_P_0): Likewise.
 354         (VEX_W_0F5F_P_1): Likewise.
 355         (VEX_W_0F5F_P_2): Likewise.
 356         (VEX_W_0F5F_P_3): Likewise.
 357         (VEX_W_0F60_P_2): Likewise.
 358         (VEX_W_0F61_P_2): Likewise.
 359         (VEX_W_0F62_P_2): Likewise.
 360         (VEX_W_0F63_P_2): Likewise.
 361         (VEX_W_0F64_P_2): Likewise.
 362         (VEX_W_0F65_P_2): Likewise.
 363         (VEX_W_0F66_P_2): Likewise.
 364         (VEX_W_0F67_P_2): Likewise.
 365         (VEX_W_0F68_P_2): Likewise.
 366         (VEX_W_0F69_P_2): Likewise.
 367         (VEX_W_0F6A_P_2): Likewise.
 368         (VEX_W_0F6B_P_2): Likewise.
 369         (VEX_W_0F6C_P_2): Likewise.
 370         (VEX_W_0F6D_P_2): Likewise.
 371         (VEX_W_0F6F_P_1): Likewise.
 372         (VEX_W_0F6F_P_2): Likewise.
 373         (VEX_W_0F70_P_1): Likewise.
 374         (VEX_W_0F70_P_2): Likewise.
 375         (VEX_W_0F70_P_3): Likewise.
 376         (VEX_W_0F71_R_2_P_2): Likewise.
 377         (VEX_W_0F71_R_4_P_2): Likewise.
 378         (VEX_W_0F71_R_6_P_2): Likewise.
 379         (VEX_W_0F72_R_2_P_2): Likewise.
 380         (VEX_W_0F72_R_4_P_2): Likewise.
 381         (VEX_W_0F72_R_6_P_2): Likewise.
 382         (VEX_W_0F73_R_2_P_2): Likewise.
 383         (VEX_W_0F73_R_3_P_2): Likewise.
 384         (VEX_W_0F73_R_6_P_2): Likewise.
 385         (VEX_W_0F73_R_7_P_2): Likewise.
 386         (VEX_W_0F74_P_2): Likewise.
 387         (VEX_W_0F75_P_2): Likewise.
 388         (VEX_W_0F76_P_2): Likewise.
 389         (VEX_W_0F77_P_0): Likewise.
 390         (VEX_W_0F7C_P_2): Likewise.
 391         (VEX_W_0F7C_P_3): Likewise.
 392         (VEX_W_0F7D_P_2): Likewise.
 393         (VEX_W_0F7D_P_3): Likewise.
 394         (VEX_W_0F7E_P_1): Likewise.
 395         (VEX_W_0F7F_P_1): Likewise.
 396         (VEX_W_0F7F_P_2): Likewise.
 397         (VEX_W_0FAE_R_2_M_0): Likewise.
 398         (VEX_W_0FAE_R_3_M_0): Likewise.
 399         (VEX_W_0FC2_P_0): Likewise.
 400         (VEX_W_0FC2_P_1): Likewise.
 401         (VEX_W_0FC2_P_2): Likewise.
 402         (VEX_W_0FC2_P_3): Likewise.
 403         (VEX_W_0FD0_P_2): Likewise.
 404         (VEX_W_0FD0_P_3): Likewise.
 405         (VEX_W_0FD1_P_2): Likewise.
 406         (VEX_W_0FD2_P_2): Likewise.
 407         (VEX_W_0FD3_P_2): Likewise.
 408         (VEX_W_0FD4_P_2): Likewise.
 409         (VEX_W_0FD5_P_2): Likewise.
 410         (VEX_W_0FD6_P_2): Likewise.
 411         (VEX_W_0FD7_P_2_M_1): Likewise.
 412         (VEX_W_0FD8_P_2): Likewise.
 413         (VEX_W_0FD9_P_2): Likewise.
 414         (VEX_W_0FDA_P_2): Likewise.
 415         (VEX_W_0FDB_P_2): Likewise.
 416         (VEX_W_0FDC_P_2): Likewise.
 417         (VEX_W_0FDD_P_2): Likewise.
 418         (VEX_W_0FDE_P_2): Likewise.
 419         (VEX_W_0FDF_P_2): Likewise.
 420         (VEX_W_0FE0_P_2): Likewise.
 421         (VEX_W_0FE1_P_2): Likewise.
 422         (VEX_W_0FE2_P_2): Likewise.
 423         (VEX_W_0FE3_P_2): Likewise.
 424         (VEX_W_0FE4_P_2): Likewise.
 425         (VEX_W_0FE5_P_2): Likewise.
 426         (VEX_W_0FE6_P_1): Likewise.
 427         (VEX_W_0FE6_P_2): Likewise.
 428         (VEX_W_0FE6_P_3): Likewise.
 429         (VEX_W_0FE7_P_2_M_0): Likewise.
 430         (VEX_W_0FE8_P_2): Likewise.
 431         (VEX_W_0FE9_P_2): Likewise.
 432         (VEX_W_0FEA_P_2): Likewise.
 433         (VEX_W_0FEB_P_2): Likewise.
 434         (VEX_W_0FEC_P_2): Likewise.
 435         (VEX_W_0FED_P_2): Likewise.
 436         (VEX_W_0FEE_P_2): Likewise.
 437         (VEX_W_0FEF_P_2): Likewise.
 438         (VEX_W_0FF0_P_3_M_0): Likewise.
 439         (VEX_W_0FF1_P_2): Likewise.
 440         (VEX_W_0FF2_P_2): Likewise.
 441         (VEX_W_0FF3_P_2): Likewise.
 442         (VEX_W_0FF4_P_2): Likewise.
 443         (VEX_W_0FF5_P_2): Likewise.
 444         (VEX_W_0FF6_P_2): Likewise.
 445         (VEX_W_0FF7_P_2): Likewise.
 446         (VEX_W_0FF8_P_2): Likewise.
 447         (VEX_W_0FF9_P_2): Likewise.
 448         (VEX_W_0FFA_P_2): Likewise.
 449         (VEX_W_0FFB_P_2): Likewise.
 450         (VEX_W_0FFC_P_2): Likewise.
 451         (VEX_W_0FFD_P_2): Likewise.
 452         (VEX_W_0FFE_P_2): Likewise.
 453         (VEX_W_0F3800_P_2): Likewise.
 454         (VEX_W_0F3801_P_2): Likewise.
 455         (VEX_W_0F3802_P_2): Likewise.
 456         (VEX_W_0F3803_P_2): Likewise.
 457         (VEX_W_0F3804_P_2): Likewise.
 458         (VEX_W_0F3805_P_2): Likewise.
 459         (VEX_W_0F3806_P_2): Likewise.
 460         (VEX_W_0F3807_P_2): Likewise.
 461         (VEX_W_0F3808_P_2): Likewise.
 462         (VEX_W_0F3809_P_2): Likewise.
 463         (VEX_W_0F380A_P_2): Likewise.
 464         (VEX_W_0F380B_P_2): Likewise.
 465         (VEX_W_0F3817_P_2): Likewise.
 466         (VEX_W_0F381C_P_2): Likewise.
 467         (VEX_W_0F381D_P_2): Likewise.
 468         (VEX_W_0F381E_P_2): Likewise.
 469         (VEX_W_0F3820_P_2): Likewise.
 470         (VEX_W_0F3821_P_2): Likewise.
 471         (VEX_W_0F3822_P_2): Likewise.
 472         (VEX_W_0F3823_P_2): Likewise.
 473         (VEX_W_0F3824_P_2): Likewise.
 474         (VEX_W_0F3825_P_2): Likewise.
 475         (VEX_W_0F3828_P_2): Likewise.
 476         (VEX_W_0F3829_P_2): Likewise.
 477         (VEX_W_0F382A_P_2_M_0): Likewise.
 478         (VEX_W_0F382B_P_2): Likewise.
 479         (VEX_W_0F3830_P_2): Likewise.
 480         (VEX_W_0F3831_P_2): Likewise.
 481         (VEX_W_0F3832_P_2): Likewise.
 482         (VEX_W_0F3833_P_2): Likewise.
 483         (VEX_W_0F3834_P_2): Likewise.
 484         (VEX_W_0F3835_P_2): Likewise.
 485         (VEX_W_0F3837_P_2): Likewise.
 486         (VEX_W_0F3838_P_2): Likewise.
 487         (VEX_W_0F3839_P_2): Likewise.
 488         (VEX_W_0F383A_P_2): Likewise.
 489         (VEX_W_0F383B_P_2): Likewise.
 490         (VEX_W_0F383C_P_2): Likewise.
 491         (VEX_W_0F383D_P_2): Likewise.
 492         (VEX_W_0F383E_P_2): Likewise.
 493         (VEX_W_0F383F_P_2): Likewise.
 494         (VEX_W_0F3840_P_2): Likewise.
 495         (VEX_W_0F3841_P_2): Likewise.
 496         (VEX_W_0F38DB_P_2): Likewise.
 497         (VEX_W_0F3A08_P_2): Likewise.
 498         (VEX_W_0F3A09_P_2): Likewise.
 499         (VEX_W_0F3A0A_P_2): Likewise.
 500         (VEX_W_0F3A0B_P_2): Likewise.
 501         (VEX_W_0F3A0C_P_2): Likewise.
 502         (VEX_W_0F3A0D_P_2): Likewise.
 503         (VEX_W_0F3A0E_P_2): Likewise.
 504         (VEX_W_0F3A0F_P_2): Likewise.
 505         (VEX_W_0F3A21_P_2): Likewise.
 506         (VEX_W_0F3A40_P_2): Likewise.
 507         (VEX_W_0F3A41_P_2): Likewise.
 508         (VEX_W_0F3A42_P_2): Likewise.
 509         (VEX_W_0F3A62_P_2): Likewise.
 510         (VEX_W_0F3A63_P_2): Likewise.
 511         (VEX_W_0F3ADF_P_2): Likewise.
 512         (VEX_LEN_0F77_P_0): New.
 513         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 514         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 515         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 516         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 517         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 518         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 519         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 520         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 521         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 522         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 523         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 524         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 525         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 526         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 527         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 528         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 529         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 530         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 531         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 532         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 533         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 534         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 535         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 536         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 537         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 538         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 539         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 540         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 541         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 542         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 543         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 544         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 545         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 546         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 547         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 548         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 549         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 550         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 551         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 552         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 553         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 554         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 555         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 556         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 557         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 558         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 559         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 560         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 561         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 562         (vex_table): Update VEX 0F28 and 0F29 entries.
 563         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 564         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 565         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 566         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 567         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 568         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 569         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 570         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 571         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 572         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 573         VEX_LEN_0F3A0B_P_2 entries.
 574         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 575         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 576         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 577         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 578         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 579         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 580         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 581         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 582         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 583         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 584         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 585         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 586         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 587         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 588         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 589         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 590         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 591         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 592         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 593         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 594         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 595         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 596         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 597         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 598         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 599         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 600         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 601         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 602         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 603         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 604         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 605         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 606         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 607         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 608         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 609         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 610         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 611         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 612         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 613         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 614         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 615         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 616         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 617         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 618         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 619         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 620         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 621         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 622         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 623         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 624         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 625         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 626         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 627         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 628         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 629         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 630         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 631         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 632         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 633         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 634         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 635         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 636         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 637         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 638         VEX_W_0F3ADF_P_2 entries.
 639         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 640         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 641         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 642
 643 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         * i386-opc.tbl (VexWIG): New.
 646         Replace VexW=3 with VexWIG.
 647
 648 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 649
 650         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 651         * i386-tbl.h: Regenerated.
 652
 653 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 654
 655         PR gas/23665
 656         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 657         VEX_LEN_0FD6_P_2 entries.
 658         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 659         * i386-tbl.h: Regenerated.
 660
 661 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 662
 663         PR gas/23642
 664         * i386-opc.h (VEXWIG): New.
 665         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 666         * i386-tbl.h: Regenerated.
 667
 668 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 669
 670         PR binutils/23655
 671         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 672         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 673         * i386-dis.c (EXxEVexR64): New.
 674         (evex_rounding_64_mode): Likewise.
 675         (OP_Rounding): Handle evex_rounding_64_mode.
 676
 677 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 678
 679         PR binutils/23655
 680         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 681         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 682         * i386-dis.c (Edqa): New.
 683         (dqa_mode): Likewise.
 684         (intel_operand_size): Handle dqa_mode as m_mode.
 685         (OP_E_register): Handle dqa_mode as dq_mode.
 686         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 687
 688 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 689
 690         * i386-dis.c (OP_E_memory): Reformat.
 691
 692 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-opc.tbl (crc32): Fold byte and word forms.
 695         * i386-tbl.h: Re-generate.
 696
 697 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 698
 699         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 700         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 701         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 702         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 703         * i386-tbl.h: Regenerated.
 704
 705 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 708         meaningless.
 709         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 710         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 711         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 712         * i386-tbl.h: Re-generate.
 713
 714 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 715
 716         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 717         AVX512_4VNNIW insns.
 718         * i386-tbl.h: Re-generate.
 719
 720 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 721
 722         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 723         meaningless.
 724         * i386-tbl.h: Re-generate.
 725
 726 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 729         meaningless.
 730         * i386-tbl.h: Re-generate.
 731
 732 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 733
 734         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 735         meaningless.
 736         * i386-tbl.h: Re-generate.
 737
 738 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 739
 740         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 741         meaningless.
 742         * i386-tbl.h: Re-generate.
 743
 744 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 745
 746         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 747         meaningless.
 748         * i386-tbl.h: Re-generate.
 749
 750 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 753         * i386-tbl.h: Re-generate.
 754
 755 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 756
 757         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 758         * i386-tbl.h: Re-generate.
 759
 760 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 763         meaningless.
 764         * i386-tbl.h: Re-generate.
 765
 766 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 767
 768         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 769         meaningless.
 770         * i386-tbl.h: Re-generate.
 771
 772 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 773
 774         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 775         * i386-tbl.h: Re-generate.
 776
 777 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 778
 779         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 780         * i386-tbl.h: Re-generate.
 781
 782 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 783
 784         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 785         * i386-tbl.h: Re-generate.
 786
 787 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 790         meaningless.
 791         * i386-tbl.h: Re-generate.
 792
 793 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 796         meaningless.
 797         * i386-tbl.h: Re-generate.
 798
 799 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 802         meaningless.
 803         * i386-tbl.h: Re-generate.
 804
 805 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 808         * i386-tbl.h: Re-generate.
 809
 810 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 811
 812         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 813         * i386-tbl.h: Re-generate.
 814
 815 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 816
 817         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 818         * i386-tbl.h: Re-generate.
 819
 820 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 821
 822         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 823         (vpbroadcastw, rdpid): Drop NoRex64.
 824         * i386-tbl.h: Re-generate.
 825
 826 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 829         store templates, adding D.
 830         * i386-tbl.h: Re-generate.
 831
 832 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 833
 834         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 835         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 836         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 837         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 838         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 839         Fold load and store templates where possible, adding D. Drop
 840         IgnoreSize where it was pointlessly present. Drop redundant
 841         *word.
 842         * i386-tbl.h: Re-generate.
 843
 844 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 845
 846         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 847         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 848         (intel_operand_size): Handle v_bndmk_mode.
 849         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 850
 851 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 852
 853         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 854
 855 2018-08-31  Kito Cheng  <kito@andestech.com>
 856
 857         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 858         compressed floating point instructions.
 859
 860 2018-08-30  Kito Cheng  <kito@andestech.com>
 861
 862         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 863         riscv_opcode.xlen_requirement.
 864         * riscv-opc.c (riscv_opcodes): Update for struct change.
 865
 866 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 867
 868         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 869         psr (PWRPSR) instruction.
 870
 871 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 872
 873         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 874
 875 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 876
 877         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 878
 879 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 880
 881         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 882         loongson3a as an alias of gs464 for compatibility.
 883         * mips-opc.c (mips_opcodes): Change Comments.
 884
 885 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 886
 887         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 888         option.
 889         (print_mips_disassembler_options): Document -M loongson-ext.
 890         * mips-opc.c (LEXT2): New macro.
 891         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 892
 893 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 894
 895          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 896          descriptors.
 897          (parse_mips_ase_option): Handle -M loongson-ext option.
 898          (print_mips_disassembler_options): Document -M loongson-ext.
 899          * mips-opc.c (IL3A): Delete.
 900          * mips-opc.c (LEXT): New macro.
 901          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 902          instructions.
 903
 904 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 905
 906         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 907         descriptors.
 908         (parse_mips_ase_option): Handle -M loongson-cam option.
 909         (print_mips_disassembler_options): Document -M loongson-cam.
 910         * mips-opc.c (LCAM): New macro.
 911         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 912         instructions.
 913
 914 2018-08-21  Alan Modra  <amodra@gmail.com>
 915
 916         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 917         (skip_optional_operands): Count optional operands, and update
 918         ppc_optional_operand_value call.
 919         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 920         (extract_vlensi): Likewise.
 921         (extract_fxm): Return default value for missing optional operand.
 922         (extract_ls, extract_raq, extract_tbr): Likewise.
 923         (insert_sxl, extract_sxl): New functions.
 924         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 925         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 926         flag and extra entry.
 927         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 928         extract_sxl.
 929
 930 2018-08-20  Alan Modra  <amodra@gmail.com>
 931
 932         * sh-opc.h (MASK): Simplify.
 933
 934 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 935
 936         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 937         BM_RESERVED0 or BM_RESERVED1
 938         (bm_rel_decode, bm_n_bytes): Ditto.
 939
 940 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 941
 942         * s12z.h: Delete.
 943
 944 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 945
 946         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 947         address with the addr32 prefix and without base nor index
 948         registers.
 949
 950 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 951
 952         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 953         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 954         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 955         (cpu_flags): Add CpuCMOV and CpuFXSR.
 956         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 957         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 958         * i386-init.h: Regenerated.
 959         * i386-tbl.h: Likewise.
 960
 961 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 962
 963         * arc-regs.h: Update auxiliary registers.
 964
 965 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 968         (RegIP, RegIZ): Define.
 969         * i386-reg.tbl: Adjust comments.
 970         (rip): Use Qword instead of BaseIndex. Use RegIP.
 971         (eip): Use Dword instead of BaseIndex. Use RegIP.
 972         (riz): Add Qword. Use RegIZ.
 973         (eiz): Add Dword. Use RegIZ.
 974         * i386-tbl.h: Re-generate.
 975
 976 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 979         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 980         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 981         * i386-tbl.h: Re-generate.
 982
 983 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 984
 985         * i386-gen.c (operand_types): Remove Mem field.
 986         * i386-opc.h (union i386_operand_type): Remove mem field.
 987         * i386-init.h, i386-tbl.h: Re-generate.
 988
 989 2018-08-01  Alan Modra  <amodra@gmail.com>
 990
 991         * po/POTFILES.in: Regenerate.
 992
 993 2018-07-31  Nick Clifton  <nickc@redhat.com>
 994
 995         * po/sv.po: Updated Swedish translation.
 996
 997 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 998
 999         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1000         * i386-init.h, i386-tbl.h: Re-generate.
1001
1002 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1003
1004         * i386-opc.h (ZEROING_MASKING) Rename to ...
1005         (DYNAMIC_MASKING): ... this. Adjust comment.
1006         * i386-opc.tbl (MaskingMorZ): Define.
1007         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1008         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1009         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1010         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1011         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1012         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1013         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1014         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1015         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1016
1017 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-opc.tbl: Use element rather than vector size for AVX512*
1020         scatter/gather insns.
1021         * i386-tbl.h: Re-generate.
1022
1023 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1024
1025         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1026         (cpu_flags): Drop CpuVREX.
1027         * i386-opc.h (CpuVREX): Delete.
1028         (union i386_cpu_flags): Remove cpuvrex.
1029         * i386-init.h, i386-tbl.h: Re-generate.
1030
1031 2018-07-30  Jim Wilson  <jimw@sifive.com>
1032
1033         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1034         fields.
1035         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1036
1037 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1038
1039         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1040         * Makefile.in: Regenerated.
1041         * configure.ac: Add C-SKY.
1042         * configure: Regenerated.
1043         * csky-dis.c: New file.
1044         * csky-opc.h: New file.
1045         * disassemble.c (ARCH_csky): Define.
1046         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1047         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1048
1049 2018-07-27  Alan Modra  <amodra@gmail.com>
1050
1051         * ppc-opc.c (insert_sprbat): Correct function parameter and
1052         return type.
1053         (extract_sprbat): Likewise, variable too.
1054
1055 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1056             Alan Modra  <amodra@gmail.com>
1057
1058         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1059         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1060         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1061         support disjointed BAT.
1062         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1063         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1064         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1065
1066 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1067             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1068
1069         * i386-gen.c (adjust_broadcast_modifier): New function.
1070         (process_i386_opcode_modifier): Add an argument for operands.
1071         Adjust the Broadcast value based on operands.
1072         (output_i386_opcode): Pass operand_types to
1073         process_i386_opcode_modifier.
1074         (process_i386_opcodes): Pass NULL as operands to
1075         process_i386_opcode_modifier.
1076         * i386-opc.h (BYTE_BROADCAST): New.
1077         (WORD_BROADCAST): Likewise.
1078         (DWORD_BROADCAST): Likewise.
1079         (QWORD_BROADCAST): Likewise.
1080         (i386_opcode_modifier): Expand broadcast to 3 bits.
1081         * i386-tbl.h: Regenerated.
1082
1083 2018-07-24  Alan Modra  <amodra@gmail.com>
1084
1085         PR 23430
1086         * or1k-desc.h: Regenerate.
1087
1088 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1089
1090         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1091         vcvtusi2ss, and vcvtusi2sd.
1092         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1093         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1094         * i386-tbl.h: Re-generate.
1095
1096 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1097
1098         * arc-opc.c (extract_w6): Fix extending the sign.
1099
1100 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1101
1102         * arc-tbl.h (vewt): Allow it for ARC EM family.
1103
1104 2018-07-23  Alan Modra  <amodra@gmail.com>
1105
1106         PR 23419
1107         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1108         opcode variants for mtspr/mfspr encodings.
1109
1110 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1111             Maciej W. Rozycki  <macro@mips.com>
1112
1113         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1114         loongson3a descriptors.
1115         (parse_mips_ase_option): Handle -M loongson-mmi option.
1116         (print_mips_disassembler_options): Document -M loongson-mmi.
1117         * mips-opc.c (LMMI): New macro.
1118         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1119         instructions.
1120
1121 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1122
1123         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1124         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1125         IgnoreSize and [XYZ]MMword where applicable.
1126         * i386-tbl.h: Re-generate.
1127
1128 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1129
1130         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1131         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1132         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1133         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1134         * i386-tbl.h: Re-generate.
1135
1136 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1137
1138         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1139         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1140         VPCLMULQDQ templates into their respective AVX512VL counterparts
1141         where possible, using Disp8ShiftVL and CheckRegSize instead of
1142         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1143         * i386-tbl.h: Re-generate.
1144
1145 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1148         AVX512VL counterparts where possible, using Disp8ShiftVL and
1149         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1150         IgnoreSize) as appropriate.
1151         * i386-tbl.h: Re-generate.
1152
1153 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1154
1155         * i386-opc.tbl: Fold AVX512BW templates into their respective
1156         AVX512VL counterparts where possible, using Disp8ShiftVL and
1157         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1158         IgnoreSize) as appropriate.
1159         * i386-tbl.h: Re-generate.
1160
1161 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1162
1163         * i386-opc.tbl: Fold AVX512CD templates into their respective
1164         AVX512VL counterparts where possible, using Disp8ShiftVL and
1165         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1166         IgnoreSize) as appropriate.
1167         * i386-tbl.h: Re-generate.
1168
1169 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1170
1171         * i386-opc.h (DISP8_SHIFT_VL): New.
1172         * i386-opc.tbl (Disp8ShiftVL):  Define.
1173         (various): Fold AVX512VL templates into their respective
1174         AVX512F counterparts where possible, using Disp8ShiftVL and
1175         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1176         IgnoreSize) as appropriate.
1177         * i386-tbl.h: Re-generate.
1178
1179 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1180
1181         * Makefile.am: Change dependencies and rule for
1182         $(srcdir)/i386-init.h.
1183         * Makefile.in: Re-generate.
1184         * i386-gen.c (process_i386_opcodes): New local variable
1185         "marker". Drop opening of input file. Recognize marker and line
1186         number directives.
1187         * i386-opc.tbl (OPCODE_I386_H): Define.
1188         (i386-opc.h): Include it.
1189         (None): Undefine.
1190
1191 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1192
1193         PR gas/23418
1194         * i386-opc.h (Byte): Update comments.
1195         (Word): Likewise.
1196         (Dword): Likewise.
1197         (Fword): Likewise.
1198         (Qword): Likewise.
1199         (Tbyte): Likewise.
1200         (Xmmword): Likewise.
1201         (Ymmword): Likewise.
1202         (Zmmword): Likewise.
1203         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1204         vcvttps2uqq.
1205         * i386-tbl.h: Regenerated.
1206
1207 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1208
1209         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1210         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1211         * aarch64-asm-2.c: Regenerate.
1212         * aarch64-dis-2.c: Regenerate.
1213         * aarch64-opc-2.c: Regenerate.
1214
1215 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1216
1217         PR binutils/23192
1218         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1219         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1220         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1221         sqdmulh, sqrdmulh): Use Em16.
1222
1223 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1224
1225         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1226         csdb together with them.
1227         (thumb32_opcodes): Likewise.
1228
1229 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1230
1231         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1232         requiring 32-bit registers as operands 2 and 3. Improve
1233         comments.
1234         (mwait, mwaitx): Fold templates. Improve comments.
1235         OPERAND_TYPE_INOUTPORTREG.
1236         * i386-tbl.h: Re-generate.
1237
1238 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1239
1240         * i386-gen.c (operand_type_init): Remove
1241         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1242         OPERAND_TYPE_INOUTPORTREG.
1243         * i386-init.h: Re-generate.
1244
1245 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1246
1247         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1248         (wrssq, wrussq): Add Qword.
1249         * i386-tbl.h: Re-generate.
1250
1251 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1252
1253         * i386-opc.h: Rename OTMax to OTNum.
1254         (OTNumOfUints): Adjust calculation.
1255         (OTUnused): Directly alias to OTNum.
1256
1257 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1258
1259         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1260         `reg_xys'.
1261         (lea_reg_xys): Likewise.
1262         (print_insn_loop_primitive): Rename `reg' local variable to
1263         `reg_dxy'.
1264
1265 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1266
1267         PR binutils/23242
1268         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1269
1270 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1271
1272         PR binutils/23369
1273         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1274         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1275
1276 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1277
1278         PR tdep/8282
1279         * mips-dis.c (mips_option_arg_t): New enumeration.
1280         (mips_options): New variable.
1281         (disassembler_options_mips): New function.
1282         (print_mips_disassembler_options): Reimplement in terms of
1283         `disassembler_options_mips'.
1284         * arm-dis.c (disassembler_options_arm): Adapt to using the
1285         `disasm_options_and_args_t' structure.
1286         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1287         * s390-dis.c (disassembler_options_s390): Likewise.
1288
1289 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1290
1291         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1292         expected result.
1293         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1294         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1295         * testsuite/ld-arm/tls-longplt.d: Likewise.
1296
1297 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1298
1299         PR binutils/23192
1300         * aarch64-asm-2.c: Regenerate.
1301         * aarch64-dis-2.c: Likewise.
1302         * aarch64-opc-2.c: Likewise.
1303         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1304         * aarch64-opc.c (operand_general_constraint_met_p,
1305         aarch64_print_operand): Likewise.
1306         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1307         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1308         fmlal2, fmlsl2.
1309         (AARCH64_OPERANDS): Add Em2.
1310
1311 2018-06-26  Nick Clifton  <nickc@redhat.com>
1312
1313         * po/uk.po: Updated Ukranian translation.
1314         * po/de.po: Updated German translation.
1315         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1316
1317 2018-06-26  Nick Clifton  <nickc@redhat.com>
1318
1319         * nfp-dis.c: Fix spelling mistake.
1320
1321 2018-06-24  Nick Clifton  <nickc@redhat.com>
1322
1323         * configure: Regenerate.
1324         * po/opcodes.pot: Regenerate.
1325
1326 2018-06-24  Nick Clifton  <nickc@redhat.com>
1327
1328         2.31 branch created.
1329
1330 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1331
1332         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1333         * aarch64-asm-2.c: Regenerate.
1334         * aarch64-dis-2.c: Likewise.
1335
1336 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1337
1338         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1339         `-M ginv' option description.
1340
1341 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1342
1343         PR gas/23305
1344         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1345         la and lla.
1346
1347 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1348
1349         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1350         * configure.ac: Remove AC_PREREQ.
1351         * Makefile.in: Re-generate.
1352         * aclocal.m4: Re-generate.
1353         * configure: Re-generate.
1354
1355 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1356
1357         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1358         mips64r6 descriptors.
1359         (parse_mips_ase_option): Handle -Mginv option.
1360         (print_mips_disassembler_options): Document -Mginv.
1361         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1362         (GINV): New macro.
1363         (mips_opcodes): Define ginvi and ginvt.
1364
1365 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1366             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1367
1368         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1369         * mips-opc.c (CRC, CRC64): New macros.
1370         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1371         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1372         crc32cd for CRC64.
1373
1374 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1375
1376         PR 20319
1377         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1378         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1379
1380 2018-06-06  Alan Modra  <amodra@gmail.com>
1381
1382         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1383         setjmp.  Move init for some other vars later too.
1384
1385 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1386
1387         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1388         (dis_private): Add new fields for property section tracking.
1389         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1390         (xtensa_instruction_fits): New functions.
1391         (fetch_data): Bump minimal fetch size to 4.
1392         (print_insn_xtensa): Make struct dis_private static.
1393         Load and prepare property table on section change.
1394         Don't disassemble literals. Don't disassemble instructions that
1395         cross property table boundaries.
1396
1397 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1398
1399         * configure: Regenerated.
1400
1401 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1402
1403         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1404         * i386-tbl.h: Re-generate.
1405
1406 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1407
1408         * i386-opc.tbl (sldt, str): Add NoRex64.
1409         * i386-tbl.h: Re-generate.
1410
1411 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1412
1413         * i386-opc.tbl (invpcid): Add Oword.
1414         * i386-tbl.h: Re-generate.
1415
1416 2018-06-01  Alan Modra  <amodra@gmail.com>
1417
1418         * sysdep.h (_bfd_error_handler): Don't declare.
1419         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1420         * rl78-decode.opc: Likewise.
1421         * msp430-decode.c: Regenerate.
1422         * rl78-decode.c: Regenerate.
1423
1424 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1425
1426         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1427         * i386-init.h : Regenerated.
1428
1429 2018-05-25  Alan Modra  <amodra@gmail.com>
1430
1431         * Makefile.in: Regenerate.
1432         * po/POTFILES.in: Regenerate.
1433
1434 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1435
1436         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1437         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1438         (insert_bab, extract_bab, insert_btab, extract_btab,
1439         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1440         (BAT, BBA VBA RBS XB6S): Delete macros.
1441         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1442         (BB, BD, RBX, XC6): Update for new macros.
1443         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1444         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1445         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1446         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1447
1448 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1449
1450         * Makefile.am: Add support for s12z architecture.
1451         * configure.ac: Likewise.
1452         * disassemble.c: Likewise.
1453         * disassemble.h: Likewise.
1454         * Makefile.in: Regenerate.
1455         * configure: Regenerate.
1456         * s12z-dis.c: New file.
1457         * s12z.h: New file.
1458
1459 2018-05-18  Alan Modra  <amodra@gmail.com>
1460
1461         * nfp-dis.c: Don't #include libbfd.h.
1462         (init_nfp3200_priv): Use bfd_get_section_contents.
1463         (nit_nfp6000_mecsr_sec): Likewise.
1464
1465 2018-05-17  Nick Clifton  <nickc@redhat.com>
1466
1467         * po/zh_CN.po: Updated simplified Chinese translation.
1468
1469 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1470
1471         PR binutils/23109
1472         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1473         * aarch64-dis-2.c: Regenerate.
1474
1475 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1476
1477         PR binutils/21446
1478         * aarch64-asm.c (opintl.h): Include.
1479         (aarch64_ins_sysreg): Enforce read/write constraints.
1480         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1481         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1482         (F_REG_READ, F_REG_WRITE): New.
1483         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1484         AARCH64_OPND_SYSREG.
1485         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1486         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1487         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1488         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1489         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1490         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1491         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1492         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1493         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1494         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1495         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1496         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1497         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1498         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1499         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1500         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1501         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1502
1503 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1504
1505         PR binutils/21446
1506         * aarch64-dis.c (no_notes: New.
1507         (parse_aarch64_dis_option): Support notes.
1508         (aarch64_decode_insn, print_operands): Likewise.
1509         (print_aarch64_disassembler_options): Document notes.
1510         * aarch64-opc.c (aarch64_print_operand): Support notes.
1511
1512 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1513
1514         PR binutils/21446
1515         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1516         and take error struct.
1517         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1518         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1519         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1520         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1521         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1522         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1523         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1524         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1525         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1526         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1527         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1528         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1529         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1530         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1531         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1532         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1533         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1534         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1535         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1536         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1537         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1538         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1539         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1540         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1541         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1542         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1543         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1544         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1545         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1546         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1547         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1548         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1549         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1550         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1551         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1552         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1553         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1554         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1555         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1556         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1557         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1558         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1559         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1560         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1561         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1562         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1563         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1564         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1565         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1566         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1567         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1568         (determine_disassembling_preference, aarch64_decode_insn,
1569         print_insn_aarch64_word, print_insn_data): Take errors struct.
1570         (print_insn_aarch64): Use errors.
1571         * aarch64-asm-2.c: Regenerate.
1572         * aarch64-dis-2.c: Regenerate.
1573         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1574         boolean in aarch64_insert_operan.
1575         (print_operand_extractor): Likewise.
1576         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1577
1578 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1579
1580         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1581
1582 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1583
1584         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1585
1586 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1587
1588         * cr16-opc.c (cr16_instruction): Comment typo fix.
1589         * hppa-dis.c (print_insn_hppa): Likewise.
1590
1591 2018-05-08  Jim Wilson  <jimw@sifive.com>
1592
1593         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1594         (match_c_slli64, match_srxi_as_c_srxi): New.
1595         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1596         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1597         <c.slli, c.srli, c.srai>: Use match_s_slli.
1598         <c.slli64, c.srli64, c.srai64>: New.
1599
1600 2018-05-08  Alan Modra  <amodra@gmail.com>
1601
1602         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1603         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1604         partition opcode space for index lookup.
1605
1606 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1607
1608         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1609         <insn_length>: ...with this.  Update usage.
1610         Remove duplicate call to *info->memory_error_func.
1611
1612 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1613             H.J. Lu  <hongjiu.lu@intel.com>
1614
1615         * i386-dis.c (Gva): New.
1616         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1617         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1618         (prefix_table): New instructions (see prefix above).
1619         (mod_table): New instructions (see prefix above).
1620         (OP_G): Handle va_mode.
1621         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1622         CPU_MOVDIR64B_FLAGS.
1623         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1624         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1625         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1626         * i386-opc.tbl: Add movidir{i,64b}.
1627         * i386-init.h: Regenerated.
1628         * i386-tbl.h: Likewise.
1629
1630 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1631
1632         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1633         AddrPrefixOpReg.
1634         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1635         (AddrPrefixOpReg): This.
1636         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1637         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1638
1639 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1640
1641         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1642         (vle_num_opcodes): Likewise.
1643         (spe2_num_opcodes): Likewise.
1644         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1645         initialization loop.
1646         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1647         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1648         only once.
1649
1650 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1651
1652         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1653
1654 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1655
1656         Makefile.am: Added nfp-dis.c.
1657         configure.ac: Added bfd_nfp_arch.
1658         disassemble.h: Added print_insn_nfp prototype.
1659         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1660         nfp-dis.c: New, for NFP support.
1661         po/POTFILES.in: Added nfp-dis.c to the list.
1662         Makefile.in: Regenerate.
1663         configure: Regenerate.
1664
1665 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1666
1667         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1668         templates into their base ones.
1669         * i386-tlb.h: Re-generate.
1670
1671 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1672
1673         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1674         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1675         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1676         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1677         * i386-init.h: Re-generate.
1678
1679 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1680
1681         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1682         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1683         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1684         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1685         comment.
1686         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1687         and CpuRegMask.
1688         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1689         CpuRegMask: Delete.
1690         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1691         cpuregzmm, and cpuregmask.
1692         * i386-init.h: Re-generate.
1693         * i386-tbl.h: Re-generate.
1694
1695 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1696
1697         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1698         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1699         * i386-init.h: Re-generate.
1700
1701 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1702
1703         * i386-gen.c (VexImmExt): Delete.
1704         * i386-opc.h (VexImmExt, veximmext): Delete.
1705         * i386-opc.tbl: Drop all VexImmExt uses.
1706         * i386-tlb.h: Re-generate.
1707
1708 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1709
1710         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1711         register-only forms.
1712         * i386-tlb.h: Re-generate.
1713
1714 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1715
1716         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1717
1718 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1719
1720         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1721         PREFIX_0F1C.
1722         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1723         (cpu_flags): Add CpuCLDEMOTE.
1724         * i386-init.h: Regenerate.
1725         * i386-opc.h (enum): Add CpuCLDEMOTE,
1726         (i386_cpu_flags): Add cpucldemote.
1727         * i386-opc.tbl: Add cldemote.
1728         * i386-tbl.h: Regenerate.
1729
1730 2018-04-16  Alan Modra  <amodra@gmail.com>
1731
1732         * Makefile.am: Remove sh5 and sh64 support.
1733         * configure.ac: Likewise.
1734         * disassemble.c: Likewise.
1735         * disassemble.h: Likewise.
1736         * sh-dis.c: Likewise.
1737         * sh64-dis.c: Delete.
1738         * sh64-opc.c: Delete.
1739         * sh64-opc.h: Delete.
1740         * Makefile.in: Regenerate.
1741         * configure: Regenerate.
1742         * po/POTFILES.in: Regenerate.
1743
1744 2018-04-16  Alan Modra  <amodra@gmail.com>
1745
1746         * Makefile.am: Remove w65 support.
1747         * configure.ac: Likewise.
1748         * disassemble.c: Likewise.
1749         * disassemble.h: Likewise.
1750         * w65-dis.c: Delete.
1751         * w65-opc.h: Delete.
1752         * Makefile.in: Regenerate.
1753         * configure: Regenerate.
1754         * po/POTFILES.in: Regenerate.
1755
1756 2018-04-16  Alan Modra  <amodra@gmail.com>
1757
1758         * configure.ac: Remove we32k support.
1759         * configure: Regenerate.
1760
1761 2018-04-16  Alan Modra  <amodra@gmail.com>
1762
1763         * Makefile.am: Remove m88k support.
1764         * configure.ac: Likewise.
1765         * disassemble.c: Likewise.
1766         * disassemble.h: Likewise.
1767         * m88k-dis.c: Delete.
1768         * Makefile.in: Regenerate.
1769         * configure: Regenerate.
1770         * po/POTFILES.in: Regenerate.
1771
1772 2018-04-16  Alan Modra  <amodra@gmail.com>
1773
1774         * Makefile.am: Remove i370 support.
1775         * configure.ac: Likewise.
1776         * disassemble.c: Likewise.
1777         * disassemble.h: Likewise.
1778         * i370-dis.c: Delete.
1779         * i370-opc.c: Delete.
1780         * Makefile.in: Regenerate.
1781         * configure: Regenerate.
1782         * po/POTFILES.in: Regenerate.
1783
1784 2018-04-16  Alan Modra  <amodra@gmail.com>
1785
1786         * Makefile.am: Remove h8500 support.
1787         * configure.ac: Likewise.
1788         * disassemble.c: Likewise.
1789         * disassemble.h: Likewise.
1790         * h8500-dis.c: Delete.
1791         * h8500-opc.h: Delete.
1792         * Makefile.in: Regenerate.
1793         * configure: Regenerate.
1794         * po/POTFILES.in: Regenerate.
1795
1796 2018-04-16  Alan Modra  <amodra@gmail.com>
1797
1798         * configure.ac: Remove tahoe support.
1799         * configure: Regenerate.
1800
1801 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1802
1803         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1804         umwait.
1805         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1806         64-bit mode.
1807         * i386-tbl.h: Regenerated.
1808
1809 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1810
1811         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1812         PREFIX_MOD_1_0FAE_REG_6.
1813         (va_mode): New.
1814         (OP_E_register): Use va_mode.
1815         * i386-dis-evex.h (prefix_table):
1816         New instructions (see prefixes above).
1817         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1818         (cpu_flags): Likewise.
1819         * i386-opc.h (enum): Likewise.
1820         (i386_cpu_flags): Likewise.
1821         * i386-opc.tbl: Add umonitor, umwait, tpause.
1822         * i386-init.h: Regenerate.
1823         * i386-tbl.h: Likewise.
1824
1825 2018-04-11  Alan Modra  <amodra@gmail.com>
1826
1827         * opcodes/i860-dis.c: Delete.
1828         * opcodes/i960-dis.c: Delete.
1829         * Makefile.am: Remove i860 and i960 support.
1830         * configure.ac: Likewise.
1831         * disassemble.c: Likewise.
1832         * disassemble.h: Likewise.
1833         * Makefile.in: Regenerate.
1834         * configure: Regenerate.
1835         * po/POTFILES.in: Regenerate.
1836
1837 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1838
1839         PR binutils/23025
1840         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1841         to 0.
1842         (print_insn): Clear vex instead of vex.evex.
1843
1844 2018-04-04  Nick Clifton  <nickc@redhat.com>
1845
1846         * po/es.po: Updated Spanish translation.
1847
1848 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1849
1850         * i386-gen.c (opcode_modifiers): Delete VecESize.
1851         * i386-opc.h (VecESize): Delete.
1852         (struct i386_opcode_modifier): Delete vecesize.
1853         * i386-opc.tbl: Drop VecESize.
1854         * i386-tlb.h: Re-generate.
1855
1856 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1857
1858         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1859         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1860         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1861         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1862         * i386-tlb.h: Re-generate.
1863
1864 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1865
1866         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1867         Fold AVX512 forms
1868         * i386-tlb.h: Re-generate.
1869
1870 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1871
1872         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1873         (vex_len_table): Drop Y for vcvt*2si.
1874         (putop): Replace plain 'Y' handling by abort().
1875
1876 2018-03-28  Nick Clifton  <nickc@redhat.com>
1877
1878         PR 22988
1879         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1880         instructions with only a base address register.
1881         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1882         handle AARHC64_OPND_SVE_ADDR_R.
1883         (aarch64_print_operand): Likewise.
1884         * aarch64-asm-2.c: Regenerate.
1885         * aarch64_dis-2.c: Regenerate.
1886         * aarch64-opc-2.c: Regenerate.
1887
1888 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1889
1890         * i386-opc.tbl: Drop VecESize from register only insn forms and
1891         memory forms not allowing broadcast.
1892         * i386-tlb.h: Re-generate.
1893
1894 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1895
1896         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1897         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1898         sha256*): Drop Disp<N>.
1899
1900 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1901
1902         * i386-dis.c (EbndS, bnd_swap_mode): New.
1903         (prefix_table): Use EbndS.
1904         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1905         * i386-opc.tbl (bndmov): Move misplaced Load.
1906         * i386-tlb.h: Re-generate.
1907
1908 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1909
1910         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1911         templates allowing memory operands and folded ones for register
1912         only flavors.
1913         * i386-tlb.h: Re-generate.
1914
1915 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1916
1917         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1918         256-bit templates. Drop redundant leftover Disp<N>.
1919         * i386-tlb.h: Re-generate.
1920
1921 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1922
1923         * riscv-opc.c (riscv_insn_types): New.
1924
1925 2018-03-13  Nick Clifton  <nickc@redhat.com>
1926
1927         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1928
1929 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1930
1931         * i386-opc.tbl: Add Optimize to clr.
1932         * i386-tbl.h: Regenerated.
1933
1934 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1935
1936         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1937         * i386-opc.h (OldGcc): Removed.
1938         (i386_opcode_modifier): Remove oldgcc.
1939         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1940         instructions for old (<= 2.8.1) versions of gcc.
1941         * i386-tbl.h: Regenerated.
1942
1943 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1944
1945         * i386-opc.h (EVEXDYN): New.
1946         * i386-opc.tbl: Fold various AVX512VL templates.
1947         * i386-tlb.h: Re-generate.
1948
1949 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1950
1951         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1952         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1953         vpexpandd, vpexpandq): Fold AFX512VF templates.
1954         * i386-tlb.h: Re-generate.
1955
1956 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1957
1958         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1959         Fold 128- and 256-bit VEX-encoded templates.
1960         * i386-tlb.h: Re-generate.
1961
1962 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1963
1964         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1965         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1966         vpexpandd, vpexpandq): Fold AVX512F templates.
1967         * i386-tlb.h: Re-generate.
1968
1969 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1970
1971         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1972         64-bit templates. Drop Disp<N>.
1973         * i386-tlb.h: Re-generate.
1974
1975 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1976
1977         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1978         and 256-bit templates.
1979         * i386-tlb.h: Re-generate.
1980
1981 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1982
1983         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1984         * i386-tlb.h: Re-generate.
1985
1986 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1987
1988         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1989         Drop NoAVX.
1990         * i386-tlb.h: Re-generate.
1991
1992 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1993
1994         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1995         * i386-tlb.h: Re-generate.
1996
1997 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1998
1999         * i386-gen.c (opcode_modifiers): Delete FloatD.
2000         * i386-opc.h (FloatD): Delete.
2001         (struct i386_opcode_modifier): Delete floatd.
2002         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2003         FloatD by D.
2004         * i386-tlb.h: Re-generate.
2005
2006 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2007
2008         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2009
2010 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2011
2012         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2013         * i386-tlb.h: Re-generate.
2014
2015 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2016
2017         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2018         forms.
2019         * i386-tlb.h: Re-generate.
2020
2021 2018-03-07  Alan Modra  <amodra@gmail.com>
2022
2023         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2024         bfd_arch_rs6000.
2025         * disassemble.h (print_insn_rs6000): Delete.
2026         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2027         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2028         (print_insn_rs6000): Delete.
2029
2030 2018-03-03  Alan Modra  <amodra@gmail.com>
2031
2032         * sysdep.h (opcodes_error_handler): Define.
2033         (_bfd_error_handler): Declare.
2034         * Makefile.am: Remove stray #.
2035         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2036         EDIT" comment.
2037         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2038         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2039         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2040         opcodes_error_handler to print errors.  Standardize error messages.
2041         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2042         and include opintl.h.
2043         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2044         * i386-gen.c: Standardize error messages.
2045         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2046         * Makefile.in: Regenerate.
2047         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2048         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2049         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2050         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2051         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2052         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2053         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2054         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2055         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2056         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2057         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2058         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2059         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2060
2061 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2062
2063         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2064         vpsub[bwdq] instructions.
2065         * i386-tbl.h: Regenerated.
2066
2067 2018-03-01  Alan Modra  <amodra@gmail.com>
2068
2069         * configure.ac (ALL_LINGUAS): Sort.
2070         * configure: Regenerate.
2071
2072 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2073
2074         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2075         macro by assignements.
2076
2077 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2078
2079         PR gas/22871
2080         * i386-gen.c (opcode_modifiers): Add Optimize.
2081         * i386-opc.h (Optimize): New enum.
2082         (i386_opcode_modifier): Add optimize.
2083         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2084         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2085         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2086         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2087         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2088         vpxord and vpxorq.
2089         * i386-tbl.h: Regenerated.
2090
2091 2018-02-26  Alan Modra  <amodra@gmail.com>
2092
2093         * crx-dis.c (getregliststring): Allocate a large enough buffer
2094         to silence false positive gcc8 warning.
2095
2096 2018-02-22  Shea Levy <shea@shealevy.com>
2097
2098         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2099
2100 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2101
2102         * i386-opc.tbl: Add {rex},
2103         * i386-tbl.h: Regenerated.
2104
2105 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2106
2107         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2108         (mips16_opcodes): Replace `M' with `m' for "restore".
2109
2110 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2111
2112         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2113
2114 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2115
2116         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2117         variable to `function_index'.
2118
2119 2018-02-13  Nick Clifton  <nickc@redhat.com>
2120
2121         PR 22823
2122         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2123         about truncation of printing.
2124
2125 2018-02-12  Henry Wong <henry@stuffedcow.net>
2126
2127         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2128
2129 2018-02-05  Nick Clifton  <nickc@redhat.com>
2130
2131         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2132
2133 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2134
2135         * i386-dis.c (enum): Add pconfig.
2136         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2137         (cpu_flags): Add CpuPCONFIG.
2138         * i386-opc.h (enum): Add CpuPCONFIG.
2139         (i386_cpu_flags): Add cpupconfig.
2140         * i386-opc.tbl: Add PCONFIG instruction.
2141         * i386-init.h: Regenerate.
2142         * i386-tbl.h: Likewise.
2143
2144 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2145
2146         * i386-dis.c (enum): Add PREFIX_0F09.
2147         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2148         (cpu_flags): Add CpuWBNOINVD.
2149         * i386-opc.h (enum): Add CpuWBNOINVD.
2150         (i386_cpu_flags): Add cpuwbnoinvd.
2151         * i386-opc.tbl: Add WBNOINVD instruction.
2152         * i386-init.h: Regenerate.
2153         * i386-tbl.h: Likewise.
2154
2155 2018-01-17  Jim Wilson  <jimw@sifive.com>
2156
2157         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2158
2159 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2160
2161         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2162         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2163         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2164         (cpu_flags): Add CpuIBT, CpuSHSTK.
2165         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2166         (i386_cpu_flags): Add cpuibt, cpushstk.
2167         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2168         * i386-init.h: Regenerate.
2169         * i386-tbl.h: Likewise.
2170
2171 2018-01-16  Nick Clifton  <nickc@redhat.com>
2172
2173         * po/pt_BR.po: Updated Brazilian Portugese translation.
2174         * po/de.po: Updated German translation.
2175
2176 2018-01-15  Jim Wilson  <jimw@sifive.com>
2177
2178         * riscv-opc.c (match_c_nop): New.
2179         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2180
2181 2018-01-15  Nick Clifton  <nickc@redhat.com>
2182
2183         * po/uk.po: Updated Ukranian translation.
2184
2185 2018-01-13  Nick Clifton  <nickc@redhat.com>
2186
2187         * po/opcodes.pot: Regenerated.
2188
2189 2018-01-13  Nick Clifton  <nickc@redhat.com>
2190
2191         * configure: Regenerate.
2192
2193 2018-01-13  Nick Clifton  <nickc@redhat.com>
2194
2195         2.30 branch created.
2196
2197 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2198
2199         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2200         * i386-tbl.h: Regenerate.
2201
2202 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2203
2204         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2205         * i386-tbl.h: Re-generate.
2206
2207 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2208
2209         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2210         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2211         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2212         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2213         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2214         Disp8MemShift of AVX512VL forms.
2215         * i386-tbl.h: Re-generate.
2216
2217 2018-01-09  Jim Wilson  <jimw@sifive.com>
2218
2219         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2220         then the hi_addr value is zero.
2221
2222 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2223
2224         * arm-dis.c (arm_opcodes): Add csdb.
2225         (thumb32_opcodes): Add csdb.
2226
2227 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2228
2229         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2230         * aarch64-asm-2.c: Regenerate.
2231         * aarch64-dis-2.c: Regenerate.
2232         * aarch64-opc-2.c: Regenerate.
2233
2234 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2235
2236         PR gas/22681
2237         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2238         Remove AVX512 vmovd with 64-bit operands.
2239         * i386-tbl.h: Regenerated.
2240
2241 2018-01-05  Jim Wilson  <jimw@sifive.com>
2242
2243         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2244         jalr.
2245
2246 2018-01-03  Alan Modra  <amodra@gmail.com>
2247
2248         Update year range in copyright notice of all files.
2249
2250 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2251
2252         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2253         and OPERAND_TYPE_REGZMM entries.
2254
2255 For older changes see ChangeLog-2017
2256 \f
2257 Copyright (C) 2018 Free Software Foundation, Inc.
2258
2259 Copying and distribution of this file, with or without modification,
2260 are permitted in any medium without royalty provided the copyright
2261 notice and this notice are preserved.
2262
2263 Local Variables:
2264 mode: change-log
2265 left-margin: 8
2266 fill-column: 74
2267 version-control: never
2268 End: