1 /* aarch64-dis.c -- AArch64 disassembler.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
22 #include "bfd_stdint.h"
24 #include "libiberty.h"
26 #include "aarch64-dis.h"
36 /* Cached mapping symbol state. */
43 static enum map_type last_type
;
44 static int last_mapping_sym
= -1;
45 static bfd_vma last_mapping_addr
= 0;
48 static int no_aliases
= 0; /* If set disassemble as most general inst. */
52 set_default_aarch64_dis_options (struct disassemble_info
*info ATTRIBUTE_UNUSED
)
57 parse_aarch64_dis_option (const char *option
, unsigned int len ATTRIBUTE_UNUSED
)
59 /* Try to match options that are simple flags */
60 if (CONST_STRNEQ (option
, "no-aliases"))
66 if (CONST_STRNEQ (option
, "aliases"))
73 if (CONST_STRNEQ (option
, "debug_dump"))
78 #endif /* DEBUG_AARCH64 */
81 fprintf (stderr
, _("Unrecognised disassembler option: %s\n"), option
);
85 parse_aarch64_dis_options (const char *options
)
87 const char *option_end
;
92 while (*options
!= '\0')
94 /* Skip empty options. */
101 /* We know that *options is neither NUL or a comma. */
102 option_end
= options
+ 1;
103 while (*option_end
!= ',' && *option_end
!= '\0')
106 parse_aarch64_dis_option (options
, option_end
- options
);
108 /* Go on to the next one. If option_end points to a comma, it
109 will be skipped above. */
110 options
= option_end
;
114 /* Functions doing the instruction disassembling. */
116 /* The unnamed arguments consist of the number of fields and information about
117 these fields where the VALUE will be extracted from CODE and returned.
118 MASK can be zero or the base mask of the opcode.
120 N.B. the fields are required to be in such an order than the most signficant
121 field for VALUE comes the first, e.g. the <index> in
122 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
123 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
124 the order of H, L, M. */
127 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...)
130 const aarch64_field
*field
;
131 enum aarch64_field_kind kind
;
135 num
= va_arg (va
, uint32_t);
137 aarch64_insn value
= 0x0;
140 kind
= va_arg (va
, enum aarch64_field_kind
);
141 field
= &fields
[kind
];
142 value
<<= field
->width
;
143 value
|= extract_field (kind
, code
, mask
);
148 /* Extract the value of all fields in SELF->fields from instruction CODE.
149 The least significant bit comes from the final field. */
152 extract_all_fields (const aarch64_operand
*self
, aarch64_insn code
)
156 enum aarch64_field_kind kind
;
159 for (i
= 0; i
< ARRAY_SIZE (self
->fields
) && self
->fields
[i
] != FLD_NIL
; ++i
)
161 kind
= self
->fields
[i
];
162 value
<<= fields
[kind
].width
;
163 value
|= extract_field (kind
, code
, 0);
168 /* Sign-extend bit I of VALUE. */
169 static inline int32_t
170 sign_extend (aarch64_insn value
, unsigned i
)
172 uint32_t ret
= value
;
175 if ((value
>> i
) & 0x1)
177 uint32_t val
= (uint32_t)(-1) << i
;
180 return (int32_t) ret
;
183 /* N.B. the following inline helpfer functions create a dependency on the
184 order of operand qualifier enumerators. */
186 /* Given VALUE, return qualifier for a general purpose register. */
187 static inline enum aarch64_opnd_qualifier
188 get_greg_qualifier_from_value (aarch64_insn value
)
190 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_W
+ value
;
192 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
196 /* Given VALUE, return qualifier for a vector register. This does not support
197 decoding instructions that accept the 2H vector type. */
199 static inline enum aarch64_opnd_qualifier
200 get_vreg_qualifier_from_value (aarch64_insn value
)
202 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_V_8B
+ value
;
204 /* Instructions using vector type 2H should not call this function. Skip over
206 if (qualifier
>= AARCH64_OPND_QLF_V_2H
)
210 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
214 /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
215 static inline enum aarch64_opnd_qualifier
216 get_sreg_qualifier_from_value (aarch64_insn value
)
218 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_S_B
+ value
;
221 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
225 /* Given the instruction in *INST which is probably half way through the
226 decoding and our caller wants to know the expected qualifier for operand
227 I. Return such a qualifier if we can establish it; otherwise return
228 AARCH64_OPND_QLF_NIL. */
230 static aarch64_opnd_qualifier_t
231 get_expected_qualifier (const aarch64_inst
*inst
, int i
)
233 aarch64_opnd_qualifier_seq_t qualifiers
;
234 /* Should not be called if the qualifier is known. */
235 assert (inst
->operands
[i
].qualifier
== AARCH64_OPND_QLF_NIL
);
236 if (aarch64_find_best_match (inst
, inst
->opcode
->qualifiers_list
,
238 return qualifiers
[i
];
240 return AARCH64_OPND_QLF_NIL
;
243 /* Operand extractors. */
246 aarch64_ext_regno (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
247 const aarch64_insn code
,
248 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
250 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
255 aarch64_ext_regno_pair (const aarch64_operand
*self ATTRIBUTE_UNUSED
, aarch64_opnd_info
*info
,
256 const aarch64_insn code ATTRIBUTE_UNUSED
,
257 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
259 assert (info
->idx
== 1
261 info
->reg
.regno
= inst
->operands
[info
->idx
- 1].reg
.regno
+ 1;
265 /* e.g. IC <ic_op>{, <Xt>}. */
267 aarch64_ext_regrt_sysins (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
268 const aarch64_insn code
,
269 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
271 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
272 assert (info
->idx
== 1
273 && (aarch64_get_operand_class (inst
->operands
[0].type
)
274 == AARCH64_OPND_CLASS_SYSTEM
));
275 /* This will make the constraint checking happy and more importantly will
276 help the disassembler determine whether this operand is optional or
278 info
->present
= aarch64_sys_ins_reg_has_xt (inst
->operands
[0].sysins_op
);
283 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
285 aarch64_ext_reglane (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
286 const aarch64_insn code
,
287 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
290 info
->reglane
.regno
= extract_field (self
->fields
[0], code
,
293 /* Index and/or type. */
294 if (inst
->opcode
->iclass
== asisdone
295 || inst
->opcode
->iclass
== asimdins
)
297 if (info
->type
== AARCH64_OPND_En
298 && inst
->opcode
->operands
[0] == AARCH64_OPND_Ed
)
301 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
302 assert (info
->idx
== 1); /* Vn */
303 aarch64_insn value
= extract_field (FLD_imm4
, code
, 0);
304 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
305 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
306 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
307 info
->reglane
.index
= value
>> shift
;
311 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
319 aarch64_insn value
= extract_field (FLD_imm5
, code
, 0);
320 while (++pos
<= 3 && (value
& 0x1) == 0)
324 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
325 info
->reglane
.index
= (unsigned) (value
>> 1);
330 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
331 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
333 /* Need information in other operand(s) to help decoding. */
334 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
335 switch (info
->qualifier
)
337 case AARCH64_OPND_QLF_S_H
:
339 info
->reglane
.index
= extract_fields (code
, 0, 3, FLD_H
, FLD_L
,
341 info
->reglane
.regno
&= 0xf;
343 case AARCH64_OPND_QLF_S_S
:
345 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
347 case AARCH64_OPND_QLF_S_D
:
349 info
->reglane
.index
= extract_field (FLD_H
, code
, 0);
360 aarch64_ext_reglist (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
361 const aarch64_insn code
,
362 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
365 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
367 info
->reglist
.num_regs
= extract_field (FLD_len
, code
, 0) + 1;
371 /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
373 aarch64_ext_ldst_reglist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
374 aarch64_opnd_info
*info
, const aarch64_insn code
,
375 const aarch64_inst
*inst
)
378 /* Number of elements in each structure to be loaded/stored. */
379 unsigned expected_num
= get_opcode_dependent_value (inst
->opcode
);
383 unsigned is_reserved
;
385 unsigned num_elements
;
401 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
403 value
= extract_field (FLD_opcode
, code
, 0);
404 if (expected_num
!= data
[value
].num_elements
|| data
[value
].is_reserved
)
406 info
->reglist
.num_regs
= data
[value
].num_regs
;
411 /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
412 lanes instructions. */
414 aarch64_ext_ldst_reglist_r (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
415 aarch64_opnd_info
*info
, const aarch64_insn code
,
416 const aarch64_inst
*inst
)
421 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
423 value
= extract_field (FLD_S
, code
, 0);
425 /* Number of registers is equal to the number of elements in
426 each structure to be loaded/stored. */
427 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
428 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
430 /* Except when it is LD1R. */
431 if (info
->reglist
.num_regs
== 1 && value
== (aarch64_insn
) 1)
432 info
->reglist
.num_regs
= 2;
437 /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
438 load/store single element instructions. */
440 aarch64_ext_ldst_elemlist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
441 aarch64_opnd_info
*info
, const aarch64_insn code
,
442 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
444 aarch64_field field
= {0, 0};
445 aarch64_insn QSsize
; /* fields Q:S:size. */
446 aarch64_insn opcodeh2
; /* opcode<2:1> */
449 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
451 /* Decode the index, opcode<2:1> and size. */
452 gen_sub_field (FLD_asisdlso_opcode
, 1, 2, &field
);
453 opcodeh2
= extract_field_2 (&field
, code
, 0);
454 QSsize
= extract_fields (code
, 0, 3, FLD_Q
, FLD_S
, FLD_vldst_size
);
458 info
->qualifier
= AARCH64_OPND_QLF_S_B
;
459 /* Index encoded in "Q:S:size". */
460 info
->reglist
.index
= QSsize
;
466 info
->qualifier
= AARCH64_OPND_QLF_S_H
;
467 /* Index encoded in "Q:S:size<1>". */
468 info
->reglist
.index
= QSsize
>> 1;
471 if ((QSsize
>> 1) & 0x1)
474 if ((QSsize
& 0x1) == 0)
476 info
->qualifier
= AARCH64_OPND_QLF_S_S
;
477 /* Index encoded in "Q:S". */
478 info
->reglist
.index
= QSsize
>> 2;
482 if (extract_field (FLD_S
, code
, 0))
485 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
486 /* Index encoded in "Q". */
487 info
->reglist
.index
= QSsize
>> 3;
494 info
->reglist
.has_index
= 1;
495 info
->reglist
.num_regs
= 0;
496 /* Number of registers is equal to the number of elements in
497 each structure to be loaded/stored. */
498 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
499 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
504 /* Decode fields immh:immb and/or Q for e.g.
505 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
506 or SSHR <V><d>, <V><n>, #<shift>. */
509 aarch64_ext_advsimd_imm_shift (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
510 aarch64_opnd_info
*info
, const aarch64_insn code
,
511 const aarch64_inst
*inst
)
514 aarch64_insn Q
, imm
, immh
;
515 enum aarch64_insn_class iclass
= inst
->opcode
->iclass
;
517 immh
= extract_field (FLD_immh
, code
, 0);
520 imm
= extract_fields (code
, 0, 2, FLD_immh
, FLD_immb
);
522 /* Get highest set bit in immh. */
523 while (--pos
>= 0 && (immh
& 0x8) == 0)
526 assert ((iclass
== asimdshf
|| iclass
== asisdshf
)
527 && (info
->type
== AARCH64_OPND_IMM_VLSR
528 || info
->type
== AARCH64_OPND_IMM_VLSL
));
530 if (iclass
== asimdshf
)
532 Q
= extract_field (FLD_Q
, code
, 0);
534 0000 x SEE AdvSIMD modified immediate
544 get_vreg_qualifier_from_value ((pos
<< 1) | (int) Q
);
547 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
549 if (info
->type
== AARCH64_OPND_IMM_VLSR
)
551 0000 SEE AdvSIMD modified immediate
552 0001 (16-UInt(immh:immb))
553 001x (32-UInt(immh:immb))
554 01xx (64-UInt(immh:immb))
555 1xxx (128-UInt(immh:immb)) */
556 info
->imm
.value
= (16 << pos
) - imm
;
560 0000 SEE AdvSIMD modified immediate
561 0001 (UInt(immh:immb)-8)
562 001x (UInt(immh:immb)-16)
563 01xx (UInt(immh:immb)-32)
564 1xxx (UInt(immh:immb)-64) */
565 info
->imm
.value
= imm
- (8 << pos
);
570 /* Decode shift immediate for e.g. sshr (imm). */
572 aarch64_ext_shll_imm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
573 aarch64_opnd_info
*info
, const aarch64_insn code
,
574 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
578 val
= extract_field (FLD_size
, code
, 0);
581 case 0: imm
= 8; break;
582 case 1: imm
= 16; break;
583 case 2: imm
= 32; break;
586 info
->imm
.value
= imm
;
590 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
591 value in the field(s) will be extracted as unsigned immediate value. */
593 aarch64_ext_imm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
594 const aarch64_insn code
,
595 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
599 imm
= extract_all_fields (self
, code
);
601 if (operand_need_sign_extension (self
))
602 imm
= sign_extend (imm
, get_operand_fields_width (self
) - 1);
604 if (operand_need_shift_by_two (self
))
607 if (info
->type
== AARCH64_OPND_ADDR_ADRP
)
610 info
->imm
.value
= imm
;
614 /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
616 aarch64_ext_imm_half (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
617 const aarch64_insn code
,
618 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
620 aarch64_ext_imm (self
, info
, code
, inst
);
621 info
->shifter
.kind
= AARCH64_MOD_LSL
;
622 info
->shifter
.amount
= extract_field (FLD_hw
, code
, 0) << 4;
626 /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
627 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
629 aarch64_ext_advsimd_imm_modified (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
630 aarch64_opnd_info
*info
,
631 const aarch64_insn code
,
632 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
635 enum aarch64_opnd_qualifier opnd0_qualifier
= inst
->operands
[0].qualifier
;
636 aarch64_field field
= {0, 0};
638 assert (info
->idx
== 1);
640 if (info
->type
== AARCH64_OPND_SIMD_FPIMM
)
643 /* a:b:c:d:e:f:g:h */
644 imm
= extract_fields (code
, 0, 2, FLD_abc
, FLD_defgh
);
645 if (!info
->imm
.is_fp
&& aarch64_get_qualifier_esize (opnd0_qualifier
) == 8)
647 /* Either MOVI <Dd>, #<imm>
648 or MOVI <Vd>.2D, #<imm>.
649 <imm> is a 64-bit immediate
650 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
651 encoded in "a:b:c:d:e:f:g:h". */
653 unsigned abcdefgh
= imm
;
654 for (imm
= 0ull, i
= 0; i
< 8; i
++)
655 if (((abcdefgh
>> i
) & 0x1) != 0)
656 imm
|= 0xffull
<< (8 * i
);
658 info
->imm
.value
= imm
;
661 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
662 switch (info
->qualifier
)
664 case AARCH64_OPND_QLF_NIL
:
666 info
->shifter
.kind
= AARCH64_MOD_NONE
;
668 case AARCH64_OPND_QLF_LSL
:
670 info
->shifter
.kind
= AARCH64_MOD_LSL
;
671 switch (aarch64_get_qualifier_esize (opnd0_qualifier
))
673 case 4: gen_sub_field (FLD_cmode
, 1, 2, &field
); break; /* per word */
674 case 2: gen_sub_field (FLD_cmode
, 1, 1, &field
); break; /* per half */
675 case 1: gen_sub_field (FLD_cmode
, 1, 0, &field
); break; /* per byte */
676 default: assert (0); return 0;
678 /* 00: 0; 01: 8; 10:16; 11:24. */
679 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) << 3;
681 case AARCH64_OPND_QLF_MSL
:
683 info
->shifter
.kind
= AARCH64_MOD_MSL
;
684 gen_sub_field (FLD_cmode
, 0, 1, &field
); /* per word */
685 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) ? 16 : 8;
695 /* Decode an 8-bit floating-point immediate. */
697 aarch64_ext_fpimm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
698 const aarch64_insn code
,
699 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
701 info
->imm
.value
= extract_all_fields (self
, code
);
706 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
708 aarch64_ext_fbits (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
709 aarch64_opnd_info
*info
, const aarch64_insn code
,
710 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
712 info
->imm
.value
= 64- extract_field (FLD_scale
, code
, 0);
716 /* Decode arithmetic immediate for e.g.
717 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
719 aarch64_ext_aimm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
720 aarch64_opnd_info
*info
, const aarch64_insn code
,
721 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
725 info
->shifter
.kind
= AARCH64_MOD_LSL
;
727 value
= extract_field (FLD_shift
, code
, 0);
730 info
->shifter
.amount
= value
? 12 : 0;
731 /* imm12 (unsigned) */
732 info
->imm
.value
= extract_field (FLD_imm12
, code
, 0);
737 /* Return true if VALUE is a valid logical immediate encoding, storing the
738 decoded value in *RESULT if so. ESIZE is the number of bytes in the
739 decoded immediate. */
741 decode_limm (uint32_t esize
, aarch64_insn value
, int64_t *result
)
747 /* value is N:immr:imms. */
749 R
= (value
>> 6) & 0x3f;
750 N
= (value
>> 12) & 0x1;
752 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
753 (in other words, right rotated by R), then replicated. */
757 mask
= 0xffffffffffffffffull
;
763 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size
= 32; break;
764 case 0x20 ... 0x2f: /* 10xxxx */ simd_size
= 16; S
&= 0xf; break;
765 case 0x30 ... 0x37: /* 110xxx */ simd_size
= 8; S
&= 0x7; break;
766 case 0x38 ... 0x3b: /* 1110xx */ simd_size
= 4; S
&= 0x3; break;
767 case 0x3c ... 0x3d: /* 11110x */ simd_size
= 2; S
&= 0x1; break;
770 mask
= (1ull << simd_size
) - 1;
771 /* Top bits are IGNORED. */
775 if (simd_size
> esize
* 8)
778 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
779 if (S
== simd_size
- 1)
781 /* S+1 consecutive bits to 1. */
782 /* NOTE: S can't be 63 due to detection above. */
783 imm
= (1ull << (S
+ 1)) - 1;
784 /* Rotate to the left by simd_size - R. */
786 imm
= ((imm
<< (simd_size
- R
)) & mask
) | (imm
>> R
);
787 /* Replicate the value according to SIMD size. */
790 case 2: imm
= (imm
<< 2) | imm
;
792 case 4: imm
= (imm
<< 4) | imm
;
794 case 8: imm
= (imm
<< 8) | imm
;
796 case 16: imm
= (imm
<< 16) | imm
;
798 case 32: imm
= (imm
<< 32) | imm
;
801 default: assert (0); return 0;
804 *result
= imm
& ~((uint64_t) -1 << (esize
* 4) << (esize
* 4));
809 /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
811 aarch64_ext_limm (const aarch64_operand
*self
,
812 aarch64_opnd_info
*info
, const aarch64_insn code
,
813 const aarch64_inst
*inst
)
818 value
= extract_fields (code
, 0, 3, self
->fields
[0], self
->fields
[1],
820 esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
821 return decode_limm (esize
, value
, &info
->imm
.value
);
824 /* Decode a logical immediate for the BIC alias of AND (etc.). */
826 aarch64_ext_inv_limm (const aarch64_operand
*self
,
827 aarch64_opnd_info
*info
, const aarch64_insn code
,
828 const aarch64_inst
*inst
)
830 if (!aarch64_ext_limm (self
, info
, code
, inst
))
832 info
->imm
.value
= ~info
->imm
.value
;
836 /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
837 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
839 aarch64_ext_ft (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
840 aarch64_opnd_info
*info
,
841 const aarch64_insn code
, const aarch64_inst
*inst
)
846 info
->reg
.regno
= extract_field (FLD_Rt
, code
, 0);
849 value
= extract_field (FLD_ldst_size
, code
, 0);
850 if (inst
->opcode
->iclass
== ldstpair_indexed
851 || inst
->opcode
->iclass
== ldstnapair_offs
852 || inst
->opcode
->iclass
== ldstpair_off
853 || inst
->opcode
->iclass
== loadlit
)
855 enum aarch64_opnd_qualifier qualifier
;
858 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
859 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
860 case 2: qualifier
= AARCH64_OPND_QLF_S_Q
; break;
863 info
->qualifier
= qualifier
;
868 value
= extract_fields (code
, 0, 2, FLD_opc1
, FLD_ldst_size
);
871 info
->qualifier
= get_sreg_qualifier_from_value (value
);
877 /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
879 aarch64_ext_addr_simple (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
880 aarch64_opnd_info
*info
,
882 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
885 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
889 /* Decode the address operand for e.g.
890 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
892 aarch64_ext_addr_regoff (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
893 aarch64_opnd_info
*info
,
894 aarch64_insn code
, const aarch64_inst
*inst
)
896 aarch64_insn S
, value
;
899 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
901 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
903 value
= extract_field (FLD_option
, code
, 0);
905 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
906 /* Fix-up the shifter kind; although the table-driven approach is
907 efficient, it is slightly inflexible, thus needing this fix-up. */
908 if (info
->shifter
.kind
== AARCH64_MOD_UXTX
)
909 info
->shifter
.kind
= AARCH64_MOD_LSL
;
911 S
= extract_field (FLD_S
, code
, 0);
914 info
->shifter
.amount
= 0;
915 info
->shifter
.amount_present
= 0;
920 /* Need information in other operand(s) to help achieve the decoding
922 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
923 /* Get the size of the data element that is accessed, which may be
924 different from that of the source register size, e.g. in strb/ldrb. */
925 size
= aarch64_get_qualifier_esize (info
->qualifier
);
926 info
->shifter
.amount
= get_logsz (size
);
927 info
->shifter
.amount_present
= 1;
933 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
935 aarch64_ext_addr_simm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
936 aarch64_insn code
, const aarch64_inst
*inst
)
939 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
942 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
943 /* simm (imm9 or imm7) */
944 imm
= extract_field (self
->fields
[0], code
, 0);
945 info
->addr
.offset
.imm
= sign_extend (imm
, fields
[self
->fields
[0]].width
- 1);
946 if (self
->fields
[0] == FLD_imm7
)
947 /* scaled immediate in ld/st pair instructions. */
948 info
->addr
.offset
.imm
*= aarch64_get_qualifier_esize (info
->qualifier
);
950 if (inst
->opcode
->iclass
== ldst_unscaled
951 || inst
->opcode
->iclass
== ldstnapair_offs
952 || inst
->opcode
->iclass
== ldstpair_off
953 || inst
->opcode
->iclass
== ldst_unpriv
)
954 info
->addr
.writeback
= 0;
957 /* pre/post- index */
958 info
->addr
.writeback
= 1;
959 if (extract_field (self
->fields
[1], code
, 0) == 1)
960 info
->addr
.preind
= 1;
962 info
->addr
.postind
= 1;
968 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
970 aarch64_ext_addr_uimm12 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
972 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
975 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
976 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
978 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
980 info
->addr
.offset
.imm
= extract_field (self
->fields
[1], code
, 0) << shift
;
984 /* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
986 aarch64_ext_addr_simm10 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
988 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
992 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
994 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
996 imm
= extract_fields (code
, 0, 2, self
->fields
[1], self
->fields
[2]);
997 info
->addr
.offset
.imm
= sign_extend (imm
, 9) << 3;
998 if (extract_field (self
->fields
[3], code
, 0) == 1) {
999 info
->addr
.writeback
= 1;
1000 info
->addr
.preind
= 1;
1005 /* Decode the address operand for e.g.
1006 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
1008 aarch64_ext_simd_addr_post (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1009 aarch64_opnd_info
*info
,
1010 aarch64_insn code
, const aarch64_inst
*inst
)
1012 /* The opcode dependent area stores the number of elements in
1013 each structure to be loaded/stored. */
1014 int is_ld1r
= get_opcode_dependent_value (inst
->opcode
) == 1;
1017 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
1018 /* Rm | #<amount> */
1019 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
1020 if (info
->addr
.offset
.regno
== 31)
1022 if (inst
->opcode
->operands
[0] == AARCH64_OPND_LVt_AL
)
1023 /* Special handling of loading single structure to all lane. */
1024 info
->addr
.offset
.imm
= (is_ld1r
? 1
1025 : inst
->operands
[0].reglist
.num_regs
)
1026 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1028 info
->addr
.offset
.imm
= inst
->operands
[0].reglist
.num_regs
1029 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
)
1030 * aarch64_get_qualifier_nelem (inst
->operands
[0].qualifier
);
1033 info
->addr
.offset
.is_reg
= 1;
1034 info
->addr
.writeback
= 1;
1039 /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
1041 aarch64_ext_cond (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1042 aarch64_opnd_info
*info
,
1043 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1047 value
= extract_field (FLD_cond
, code
, 0);
1048 info
->cond
= get_cond_from_value (value
);
1052 /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
1054 aarch64_ext_sysreg (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1055 aarch64_opnd_info
*info
,
1057 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1059 /* op0:op1:CRn:CRm:op2 */
1060 info
->sysreg
= extract_fields (code
, 0, 5, FLD_op0
, FLD_op1
, FLD_CRn
,
1065 /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
1067 aarch64_ext_pstatefield (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1068 aarch64_opnd_info
*info
, aarch64_insn code
,
1069 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1073 info
->pstatefield
= extract_fields (code
, 0, 2, FLD_op1
, FLD_op2
);
1074 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
1075 if (aarch64_pstatefields
[i
].value
== (aarch64_insn
)info
->pstatefield
)
1077 /* Reserved value in <pstatefield>. */
1081 /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
1083 aarch64_ext_sysins_op (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1084 aarch64_opnd_info
*info
,
1086 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1090 const aarch64_sys_ins_reg
*sysins_ops
;
1091 /* op0:op1:CRn:CRm:op2 */
1092 value
= extract_fields (code
, 0, 5,
1093 FLD_op0
, FLD_op1
, FLD_CRn
,
1098 case AARCH64_OPND_SYSREG_AT
: sysins_ops
= aarch64_sys_regs_at
; break;
1099 case AARCH64_OPND_SYSREG_DC
: sysins_ops
= aarch64_sys_regs_dc
; break;
1100 case AARCH64_OPND_SYSREG_IC
: sysins_ops
= aarch64_sys_regs_ic
; break;
1101 case AARCH64_OPND_SYSREG_TLBI
: sysins_ops
= aarch64_sys_regs_tlbi
; break;
1102 default: assert (0); return 0;
1105 for (i
= 0; sysins_ops
[i
].name
!= NULL
; ++i
)
1106 if (sysins_ops
[i
].value
== value
)
1108 info
->sysins_op
= sysins_ops
+ i
;
1109 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1110 info
->sysins_op
->name
,
1111 (unsigned)info
->sysins_op
->value
,
1112 aarch64_sys_ins_reg_has_xt (info
->sysins_op
), i
);
1119 /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
1122 aarch64_ext_barrier (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1123 aarch64_opnd_info
*info
,
1125 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1128 info
->barrier
= aarch64_barrier_options
+ extract_field (FLD_CRm
, code
, 0);
1132 /* Decode the prefetch operation option operand for e.g.
1133 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
1136 aarch64_ext_prfop (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1137 aarch64_opnd_info
*info
,
1138 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1141 info
->prfop
= aarch64_prfops
+ extract_field (FLD_Rt
, code
, 0);
1145 /* Decode the hint number for an alias taking an operand. Set info->hint_option
1146 to the matching name/value pair in aarch64_hint_options. */
1149 aarch64_ext_hint (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1150 aarch64_opnd_info
*info
,
1152 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1155 unsigned hint_number
;
1158 hint_number
= extract_fields (code
, 0, 2, FLD_CRm
, FLD_op2
);
1160 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
1162 if (hint_number
== aarch64_hint_options
[i
].value
)
1164 info
->hint_option
= &(aarch64_hint_options
[i
]);
1172 /* Decode the extended register operand for e.g.
1173 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1175 aarch64_ext_reg_extended (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1176 aarch64_opnd_info
*info
,
1178 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1183 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1185 value
= extract_field (FLD_option
, code
, 0);
1186 info
->shifter
.kind
=
1187 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
1189 info
->shifter
.amount
= extract_field (FLD_imm3
, code
, 0);
1191 /* This makes the constraint checking happy. */
1192 info
->shifter
.operator_present
= 1;
1194 /* Assume inst->operands[0].qualifier has been resolved. */
1195 assert (inst
->operands
[0].qualifier
!= AARCH64_OPND_QLF_NIL
);
1196 info
->qualifier
= AARCH64_OPND_QLF_W
;
1197 if (inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_X
1198 && (info
->shifter
.kind
== AARCH64_MOD_UXTX
1199 || info
->shifter
.kind
== AARCH64_MOD_SXTX
))
1200 info
->qualifier
= AARCH64_OPND_QLF_X
;
1205 /* Decode the shifted register operand for e.g.
1206 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
1208 aarch64_ext_reg_shifted (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1209 aarch64_opnd_info
*info
,
1211 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1216 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1218 value
= extract_field (FLD_shift
, code
, 0);
1219 info
->shifter
.kind
=
1220 aarch64_get_operand_modifier_from_value (value
, FALSE
/* extend_p */);
1221 if (info
->shifter
.kind
== AARCH64_MOD_ROR
1222 && inst
->opcode
->iclass
!= log_shift
)
1223 /* ROR is not available for the shifted register operand in arithmetic
1227 info
->shifter
.amount
= extract_field (FLD_imm6
, code
, 0);
1229 /* This makes the constraint checking happy. */
1230 info
->shifter
.operator_present
= 1;
1235 /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
1236 where <offset> is given by the OFFSET parameter and where <factor> is
1237 1 plus SELF's operand-dependent value. fields[0] specifies the field
1238 that holds <base>. */
1240 aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand
*self
,
1241 aarch64_opnd_info
*info
, aarch64_insn code
,
1244 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1245 info
->addr
.offset
.imm
= offset
* (1 + get_operand_specific_data (self
));
1246 info
->addr
.offset
.is_reg
= FALSE
;
1247 info
->addr
.writeback
= FALSE
;
1248 info
->addr
.preind
= TRUE
;
1250 info
->shifter
.kind
= AARCH64_MOD_MUL_VL
;
1251 info
->shifter
.amount
= 1;
1252 info
->shifter
.operator_present
= (info
->addr
.offset
.imm
!= 0);
1253 info
->shifter
.amount_present
= FALSE
;
1257 /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
1258 where <simm4> is a 4-bit signed value and where <factor> is 1 plus
1259 SELF's operand-dependent value. fields[0] specifies the field that
1260 holds <base>. <simm4> is encoded in the SVE_imm4 field. */
1262 aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand
*self
,
1263 aarch64_opnd_info
*info
, aarch64_insn code
,
1264 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1268 offset
= extract_field (FLD_SVE_imm4
, code
, 0);
1269 offset
= ((offset
+ 8) & 15) - 8;
1270 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1273 /* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
1274 where <simm6> is a 6-bit signed value and where <factor> is 1 plus
1275 SELF's operand-dependent value. fields[0] specifies the field that
1276 holds <base>. <simm6> is encoded in the SVE_imm6 field. */
1278 aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand
*self
,
1279 aarch64_opnd_info
*info
, aarch64_insn code
,
1280 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1284 offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1285 offset
= (((offset
+ 32) & 63) - 32);
1286 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1289 /* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
1290 where <simm9> is a 9-bit signed value and where <factor> is 1 plus
1291 SELF's operand-dependent value. fields[0] specifies the field that
1292 holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
1293 and imm3 fields, with imm3 being the less-significant part. */
1295 aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand
*self
,
1296 aarch64_opnd_info
*info
,
1298 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1302 offset
= extract_fields (code
, 0, 2, FLD_SVE_imm6
, FLD_imm3
);
1303 offset
= (((offset
+ 256) & 511) - 256);
1304 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1307 /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
1308 is given by the OFFSET parameter and where <shift> is SELF's operand-
1309 dependent value. fields[0] specifies the base register field <base>. */
1311 aarch64_ext_sve_addr_reg_imm (const aarch64_operand
*self
,
1312 aarch64_opnd_info
*info
, aarch64_insn code
,
1315 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1316 info
->addr
.offset
.imm
= offset
* (1 << get_operand_specific_data (self
));
1317 info
->addr
.offset
.is_reg
= FALSE
;
1318 info
->addr
.writeback
= FALSE
;
1319 info
->addr
.preind
= TRUE
;
1320 info
->shifter
.operator_present
= FALSE
;
1321 info
->shifter
.amount_present
= FALSE
;
1325 /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1326 is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1327 value. fields[0] specifies the base register field. */
1329 aarch64_ext_sve_addr_ri_u6 (const aarch64_operand
*self
,
1330 aarch64_opnd_info
*info
, aarch64_insn code
,
1331 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1333 int offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1334 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1337 /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1338 is SELF's operand-dependent value. fields[0] specifies the base
1339 register field and fields[1] specifies the offset register field. */
1341 aarch64_ext_sve_addr_rr_lsl (const aarch64_operand
*self
,
1342 aarch64_opnd_info
*info
, aarch64_insn code
,
1343 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1347 index_regno
= extract_field (self
->fields
[1], code
, 0);
1348 if (index_regno
== 31 && (self
->flags
& OPD_F_NO_ZR
) != 0)
1351 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1352 info
->addr
.offset
.regno
= index_regno
;
1353 info
->addr
.offset
.is_reg
= TRUE
;
1354 info
->addr
.writeback
= FALSE
;
1355 info
->addr
.preind
= TRUE
;
1356 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1357 info
->shifter
.amount
= get_operand_specific_data (self
);
1358 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1359 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1363 /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1364 <shift> is SELF's operand-dependent value. fields[0] specifies the
1365 base register field, fields[1] specifies the offset register field and
1366 fields[2] is a single-bit field that selects SXTW over UXTW. */
1368 aarch64_ext_sve_addr_rz_xtw (const aarch64_operand
*self
,
1369 aarch64_opnd_info
*info
, aarch64_insn code
,
1370 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1372 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1373 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1374 info
->addr
.offset
.is_reg
= TRUE
;
1375 info
->addr
.writeback
= FALSE
;
1376 info
->addr
.preind
= TRUE
;
1377 if (extract_field (self
->fields
[2], code
, 0))
1378 info
->shifter
.kind
= AARCH64_MOD_SXTW
;
1380 info
->shifter
.kind
= AARCH64_MOD_UXTW
;
1381 info
->shifter
.amount
= get_operand_specific_data (self
);
1382 info
->shifter
.operator_present
= TRUE
;
1383 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1387 /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1388 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1389 fields[0] specifies the base register field. */
1391 aarch64_ext_sve_addr_zi_u5 (const aarch64_operand
*self
,
1392 aarch64_opnd_info
*info
, aarch64_insn code
,
1393 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1395 int offset
= extract_field (FLD_imm5
, code
, 0);
1396 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1399 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1400 where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
1401 number. fields[0] specifies the base register field and fields[1]
1402 specifies the offset register field. */
1404 aarch64_ext_sve_addr_zz (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1405 aarch64_insn code
, enum aarch64_modifier_kind kind
)
1407 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1408 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1409 info
->addr
.offset
.is_reg
= TRUE
;
1410 info
->addr
.writeback
= FALSE
;
1411 info
->addr
.preind
= TRUE
;
1412 info
->shifter
.kind
= kind
;
1413 info
->shifter
.amount
= extract_field (FLD_SVE_msz
, code
, 0);
1414 info
->shifter
.operator_present
= (kind
!= AARCH64_MOD_LSL
1415 || info
->shifter
.amount
!= 0);
1416 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1420 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1421 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1422 field and fields[1] specifies the offset register field. */
1424 aarch64_ext_sve_addr_zz_lsl (const aarch64_operand
*self
,
1425 aarch64_opnd_info
*info
, aarch64_insn code
,
1426 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1428 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_LSL
);
1431 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1432 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1433 field and fields[1] specifies the offset register field. */
1435 aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand
*self
,
1436 aarch64_opnd_info
*info
, aarch64_insn code
,
1437 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1439 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_SXTW
);
1442 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1443 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1444 field and fields[1] specifies the offset register field. */
1446 aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand
*self
,
1447 aarch64_opnd_info
*info
, aarch64_insn code
,
1448 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1450 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_UXTW
);
1453 /* Finish decoding an SVE arithmetic immediate, given that INFO already
1454 has the raw field value and that the low 8 bits decode to VALUE. */
1456 decode_sve_aimm (aarch64_opnd_info
*info
, int64_t value
)
1458 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1459 info
->shifter
.amount
= 0;
1460 if (info
->imm
.value
& 0x100)
1463 /* Decode 0x100 as #0, LSL #8. */
1464 info
->shifter
.amount
= 8;
1468 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1469 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1470 info
->imm
.value
= value
;
1474 /* Decode an SVE ADD/SUB immediate. */
1476 aarch64_ext_sve_aimm (const aarch64_operand
*self
,
1477 aarch64_opnd_info
*info
, const aarch64_insn code
,
1478 const aarch64_inst
*inst
)
1480 return (aarch64_ext_imm (self
, info
, code
, inst
)
1481 && decode_sve_aimm (info
, (uint8_t) info
->imm
.value
));
1484 /* Decode an SVE CPY/DUP immediate. */
1486 aarch64_ext_sve_asimm (const aarch64_operand
*self
,
1487 aarch64_opnd_info
*info
, const aarch64_insn code
,
1488 const aarch64_inst
*inst
)
1490 return (aarch64_ext_imm (self
, info
, code
, inst
)
1491 && decode_sve_aimm (info
, (int8_t) info
->imm
.value
));
1494 /* Decode a single-bit immediate that selects between #0.5 and #1.0.
1495 The fields array specifies which field to use. */
1497 aarch64_ext_sve_float_half_one (const aarch64_operand
*self
,
1498 aarch64_opnd_info
*info
, aarch64_insn code
,
1499 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1501 if (extract_field (self
->fields
[0], code
, 0))
1502 info
->imm
.value
= 0x3f800000;
1504 info
->imm
.value
= 0x3f000000;
1505 info
->imm
.is_fp
= TRUE
;
1509 /* Decode a single-bit immediate that selects between #0.5 and #2.0.
1510 The fields array specifies which field to use. */
1512 aarch64_ext_sve_float_half_two (const aarch64_operand
*self
,
1513 aarch64_opnd_info
*info
, aarch64_insn code
,
1514 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1516 if (extract_field (self
->fields
[0], code
, 0))
1517 info
->imm
.value
= 0x40000000;
1519 info
->imm
.value
= 0x3f000000;
1520 info
->imm
.is_fp
= TRUE
;
1524 /* Decode a single-bit immediate that selects between #0.0 and #1.0.
1525 The fields array specifies which field to use. */
1527 aarch64_ext_sve_float_zero_one (const aarch64_operand
*self
,
1528 aarch64_opnd_info
*info
, aarch64_insn code
,
1529 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1531 if (extract_field (self
->fields
[0], code
, 0))
1532 info
->imm
.value
= 0x3f800000;
1534 info
->imm
.value
= 0x0;
1535 info
->imm
.is_fp
= TRUE
;
1539 /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
1540 array specifies which field to use for Zn. MM is encoded in the
1541 concatenation of imm5 and SVE_tszh, with imm5 being the less
1542 significant part. */
1544 aarch64_ext_sve_index (const aarch64_operand
*self
,
1545 aarch64_opnd_info
*info
, aarch64_insn code
,
1546 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1550 info
->reglane
.regno
= extract_field (self
->fields
[0], code
, 0);
1551 val
= extract_fields (code
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1552 if ((val
& 15) == 0)
1554 while ((val
& 1) == 0)
1556 info
->reglane
.index
= val
/ 2;
1560 /* Decode a logical immediate for the MOV alias of SVE DUPM. */
1562 aarch64_ext_sve_limm_mov (const aarch64_operand
*self
,
1563 aarch64_opnd_info
*info
, const aarch64_insn code
,
1564 const aarch64_inst
*inst
)
1566 int esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1567 return (aarch64_ext_limm (self
, info
, code
, inst
)
1568 && aarch64_sve_dupm_mov_immediate_p (info
->imm
.value
, esize
));
1571 /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
1572 to use for Zn. The opcode-dependent value specifies the number
1573 of registers in the list. */
1575 aarch64_ext_sve_reglist (const aarch64_operand
*self
,
1576 aarch64_opnd_info
*info
, aarch64_insn code
,
1577 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1579 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
1580 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
1584 /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
1585 fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
1588 aarch64_ext_sve_scale (const aarch64_operand
*self
,
1589 aarch64_opnd_info
*info
, aarch64_insn code
,
1590 const aarch64_inst
*inst
)
1594 if (!aarch64_ext_imm (self
, info
, code
, inst
))
1596 val
= extract_field (FLD_SVE_imm4
, code
, 0);
1597 info
->shifter
.kind
= AARCH64_MOD_MUL
;
1598 info
->shifter
.amount
= val
+ 1;
1599 info
->shifter
.operator_present
= (val
!= 0);
1600 info
->shifter
.amount_present
= (val
!= 0);
1604 /* Return the top set bit in VALUE, which is expected to be relatively
1607 get_top_bit (uint64_t value
)
1609 while ((value
& -value
) != value
)
1610 value
-= value
& -value
;
1614 /* Decode an SVE shift-left immediate. */
1616 aarch64_ext_sve_shlimm (const aarch64_operand
*self
,
1617 aarch64_opnd_info
*info
, const aarch64_insn code
,
1618 const aarch64_inst
*inst
)
1620 if (!aarch64_ext_imm (self
, info
, code
, inst
)
1621 || info
->imm
.value
== 0)
1624 info
->imm
.value
-= get_top_bit (info
->imm
.value
);
1628 /* Decode an SVE shift-right immediate. */
1630 aarch64_ext_sve_shrimm (const aarch64_operand
*self
,
1631 aarch64_opnd_info
*info
, const aarch64_insn code
,
1632 const aarch64_inst
*inst
)
1634 if (!aarch64_ext_imm (self
, info
, code
, inst
)
1635 || info
->imm
.value
== 0)
1638 info
->imm
.value
= get_top_bit (info
->imm
.value
) * 2 - info
->imm
.value
;
1642 /* Bitfields that are commonly used to encode certain operands' information
1643 may be partially used as part of the base opcode in some instructions.
1644 For example, the bit 1 of the field 'size' in
1645 FCVTXN <Vb><d>, <Va><n>
1646 is actually part of the base opcode, while only size<0> is available
1647 for encoding the register type. Another example is the AdvSIMD
1648 instruction ORR (register), in which the field 'size' is also used for
1649 the base opcode, leaving only the field 'Q' available to encode the
1650 vector register arrangement specifier '8B' or '16B'.
1652 This function tries to deduce the qualifier from the value of partially
1653 constrained field(s). Given the VALUE of such a field or fields, the
1654 qualifiers CANDIDATES and the MASK (indicating which bits are valid for
1655 operand encoding), the function returns the matching qualifier or
1656 AARCH64_OPND_QLF_NIL if nothing matches.
1658 N.B. CANDIDATES is a group of possible qualifiers that are valid for
1659 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
1660 may end with AARCH64_OPND_QLF_NIL. */
1662 static enum aarch64_opnd_qualifier
1663 get_qualifier_from_partial_encoding (aarch64_insn value
,
1664 const enum aarch64_opnd_qualifier
* \
1669 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value
, (int)mask
);
1670 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1672 aarch64_insn standard_value
;
1673 if (candidates
[i
] == AARCH64_OPND_QLF_NIL
)
1675 standard_value
= aarch64_get_qualifier_standard_value (candidates
[i
]);
1676 if ((standard_value
& mask
) == (value
& mask
))
1677 return candidates
[i
];
1679 return AARCH64_OPND_QLF_NIL
;
1682 /* Given a list of qualifier sequences, return all possible valid qualifiers
1683 for operand IDX in QUALIFIERS.
1684 Assume QUALIFIERS is an array whose length is large enough. */
1687 get_operand_possible_qualifiers (int idx
,
1688 const aarch64_opnd_qualifier_seq_t
*list
,
1689 enum aarch64_opnd_qualifier
*qualifiers
)
1692 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1693 if ((qualifiers
[i
] = list
[i
][idx
]) == AARCH64_OPND_QLF_NIL
)
1697 /* Decode the size Q field for e.g. SHADD.
1698 We tag one operand with the qualifer according to the code;
1699 whether the qualifier is valid for this opcode or not, it is the
1700 duty of the semantic checking. */
1703 decode_sizeq (aarch64_inst
*inst
)
1706 enum aarch64_opnd_qualifier qualifier
;
1708 aarch64_insn value
, mask
;
1709 enum aarch64_field_kind fld_sz
;
1710 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1712 if (inst
->opcode
->iclass
== asisdlse
1713 || inst
->opcode
->iclass
== asisdlsep
1714 || inst
->opcode
->iclass
== asisdlso
1715 || inst
->opcode
->iclass
== asisdlsop
)
1716 fld_sz
= FLD_vldst_size
;
1721 value
= extract_fields (code
, inst
->opcode
->mask
, 2, fld_sz
, FLD_Q
);
1722 /* Obtain the info that which bits of fields Q and size are actually
1723 available for operand encoding. Opcodes like FMAXNM and FMLA have
1724 size[1] unavailable. */
1725 mask
= extract_fields (~inst
->opcode
->mask
, 0, 2, fld_sz
, FLD_Q
);
1727 /* The index of the operand we are going to tag a qualifier and the qualifer
1728 itself are reasoned from the value of the size and Q fields and the
1729 possible valid qualifier lists. */
1730 idx
= aarch64_select_operand_for_sizeq_field_coding (inst
->opcode
);
1731 DEBUG_TRACE ("key idx: %d", idx
);
1733 /* For most related instruciton, size:Q are fully available for operand
1737 inst
->operands
[idx
].qualifier
= get_vreg_qualifier_from_value (value
);
1741 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1743 #ifdef DEBUG_AARCH64
1747 for (i
= 0; candidates
[i
] != AARCH64_OPND_QLF_NIL
1748 && i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1749 DEBUG_TRACE ("qualifier %d: %s", i
,
1750 aarch64_get_qualifier_name(candidates
[i
]));
1751 DEBUG_TRACE ("%d, %d", (int)value
, (int)mask
);
1753 #endif /* DEBUG_AARCH64 */
1755 qualifier
= get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1757 if (qualifier
== AARCH64_OPND_QLF_NIL
)
1760 inst
->operands
[idx
].qualifier
= qualifier
;
1764 /* Decode size[0]:Q, i.e. bit 22 and bit 30, for
1765 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1768 decode_asimd_fcvt (aarch64_inst
*inst
)
1770 aarch64_field field
= {0, 0};
1772 enum aarch64_opnd_qualifier qualifier
;
1774 gen_sub_field (FLD_size
, 0, 1, &field
);
1775 value
= extract_field_2 (&field
, inst
->value
, 0);
1776 qualifier
= value
== 0 ? AARCH64_OPND_QLF_V_4S
1777 : AARCH64_OPND_QLF_V_2D
;
1778 switch (inst
->opcode
->op
)
1782 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1783 inst
->operands
[1].qualifier
= qualifier
;
1787 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
1788 inst
->operands
[0].qualifier
= qualifier
;
1798 /* Decode size[0], i.e. bit 22, for
1799 e.g. FCVTXN <Vb><d>, <Va><n>. */
1802 decode_asisd_fcvtxn (aarch64_inst
*inst
)
1804 aarch64_field field
= {0, 0};
1805 gen_sub_field (FLD_size
, 0, 1, &field
);
1806 if (!extract_field_2 (&field
, inst
->value
, 0))
1808 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_S_S
;
1812 /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
1814 decode_fcvt (aarch64_inst
*inst
)
1816 enum aarch64_opnd_qualifier qualifier
;
1818 const aarch64_field field
= {15, 2};
1821 value
= extract_field_2 (&field
, inst
->value
, 0);
1824 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
1825 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
1826 case 3: qualifier
= AARCH64_OPND_QLF_S_H
; break;
1829 inst
->operands
[0].qualifier
= qualifier
;
1834 /* Do miscellaneous decodings that are not common enough to be driven by
1838 do_misc_decoding (aarch64_inst
*inst
)
1841 switch (inst
->opcode
->op
)
1844 return decode_fcvt (inst
);
1850 return decode_asimd_fcvt (inst
);
1853 return decode_asisd_fcvtxn (inst
);
1857 value
= extract_field (FLD_SVE_Pn
, inst
->value
, 0);
1858 return (value
== extract_field (FLD_SVE_Pm
, inst
->value
, 0)
1859 && value
== extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
1862 return (extract_field (FLD_SVE_Zd
, inst
->value
, 0)
1863 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
1866 /* Index must be zero. */
1867 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1868 return value
== 1 || value
== 2 || value
== 4 || value
== 8;
1871 return (extract_field (FLD_SVE_Zn
, inst
->value
, 0)
1872 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
1875 /* Index must be nonzero. */
1876 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1877 return value
!= 1 && value
!= 2 && value
!= 4 && value
!= 8;
1880 return (extract_field (FLD_SVE_Pd
, inst
->value
, 0)
1881 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
1883 case OP_MOVZS_P_P_P
:
1885 return (extract_field (FLD_SVE_Pn
, inst
->value
, 0)
1886 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
1888 case OP_NOTS_P_P_P_Z
:
1889 case OP_NOT_P_P_P_Z
:
1890 return (extract_field (FLD_SVE_Pm
, inst
->value
, 0)
1891 == extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
1898 /* Opcodes that have fields shared by multiple operands are usually flagged
1899 with flags. In this function, we detect such flags, decode the related
1900 field(s) and store the information in one of the related operands. The
1901 'one' operand is not any operand but one of the operands that can
1902 accommadate all the information that has been decoded. */
1905 do_special_decoding (aarch64_inst
*inst
)
1909 /* Condition for truly conditional executed instructions, e.g. b.cond. */
1910 if (inst
->opcode
->flags
& F_COND
)
1912 value
= extract_field (FLD_cond2
, inst
->value
, 0);
1913 inst
->cond
= get_cond_from_value (value
);
1916 if (inst
->opcode
->flags
& F_SF
)
1918 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
1919 value
= extract_field (FLD_sf
, inst
->value
, 0);
1920 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1921 if ((inst
->opcode
->flags
& F_N
)
1922 && extract_field (FLD_N
, inst
->value
, 0) != value
)
1926 if (inst
->opcode
->flags
& F_LSE_SZ
)
1928 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
1929 value
= extract_field (FLD_lse_sz
, inst
->value
, 0);
1930 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1932 /* size:Q fields. */
1933 if (inst
->opcode
->flags
& F_SIZEQ
)
1934 return decode_sizeq (inst
);
1936 if (inst
->opcode
->flags
& F_FPTYPE
)
1938 idx
= select_operand_for_fptype_field_coding (inst
->opcode
);
1939 value
= extract_field (FLD_type
, inst
->value
, 0);
1942 case 0: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_S
; break;
1943 case 1: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_D
; break;
1944 case 3: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_H
; break;
1949 if (inst
->opcode
->flags
& F_SSIZE
)
1951 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
1952 of the base opcode. */
1954 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1955 idx
= select_operand_for_scalar_size_field_coding (inst
->opcode
);
1956 value
= extract_field (FLD_size
, inst
->value
, inst
->opcode
->mask
);
1957 mask
= extract_field (FLD_size
, ~inst
->opcode
->mask
, 0);
1958 /* For most related instruciton, the 'size' field is fully available for
1959 operand encoding. */
1961 inst
->operands
[idx
].qualifier
= get_sreg_qualifier_from_value (value
);
1964 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1966 inst
->operands
[idx
].qualifier
1967 = get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1971 if (inst
->opcode
->flags
& F_T
)
1973 /* Num of consecutive '0's on the right side of imm5<3:0>. */
1976 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1977 == AARCH64_OPND_CLASS_SIMD_REG
);
1988 val
= extract_field (FLD_imm5
, inst
->value
, 0);
1989 while ((val
& 0x1) == 0 && ++num
<= 3)
1993 Q
= (unsigned) extract_field (FLD_Q
, inst
->value
, inst
->opcode
->mask
);
1994 inst
->operands
[0].qualifier
=
1995 get_vreg_qualifier_from_value ((num
<< 1) | Q
);
1998 if (inst
->opcode
->flags
& F_GPRSIZE_IN_Q
)
2000 /* Use Rt to encode in the case of e.g.
2001 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
2002 idx
= aarch64_operand_index (inst
->opcode
->operands
, AARCH64_OPND_Rt
);
2005 /* Otherwise use the result operand, which has to be a integer
2007 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2008 == AARCH64_OPND_CLASS_INT_REG
);
2011 assert (idx
== 0 || idx
== 1);
2012 value
= extract_field (FLD_Q
, inst
->value
, 0);
2013 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
2016 if (inst
->opcode
->flags
& F_LDS_SIZE
)
2018 aarch64_field field
= {0, 0};
2019 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2020 == AARCH64_OPND_CLASS_INT_REG
);
2021 gen_sub_field (FLD_opc
, 0, 1, &field
);
2022 value
= extract_field_2 (&field
, inst
->value
, 0);
2023 inst
->operands
[0].qualifier
2024 = value
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2027 /* Miscellaneous decoding; done as the last step. */
2028 if (inst
->opcode
->flags
& F_MISC
)
2029 return do_misc_decoding (inst
);
2034 /* Converters converting a real opcode instruction to its alias form. */
2036 /* ROR <Wd>, <Ws>, #<shift>
2038 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
2040 convert_extr_to_ror (aarch64_inst
*inst
)
2042 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2044 copy_operand_info (inst
, 2, 3);
2045 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2051 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
2053 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
2055 convert_shll_to_xtl (aarch64_inst
*inst
)
2057 if (inst
->operands
[2].imm
.value
== 0)
2059 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2066 UBFM <Xd>, <Xn>, #<shift>, #63.
2068 LSR <Xd>, <Xn>, #<shift>. */
2070 convert_bfm_to_sr (aarch64_inst
*inst
)
2074 imms
= inst
->operands
[3].imm
.value
;
2075 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2078 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2085 /* Convert MOV to ORR. */
2087 convert_orr_to_mov (aarch64_inst
*inst
)
2089 /* MOV <Vd>.<T>, <Vn>.<T>
2091 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
2092 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2094 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2100 /* When <imms> >= <immr>, the instruction written:
2101 SBFX <Xd>, <Xn>, #<lsb>, #<width>
2103 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
2106 convert_bfm_to_bfx (aarch64_inst
*inst
)
2110 immr
= inst
->operands
[2].imm
.value
;
2111 imms
= inst
->operands
[3].imm
.value
;
2115 inst
->operands
[2].imm
.value
= lsb
;
2116 inst
->operands
[3].imm
.value
= imms
+ 1 - lsb
;
2117 /* The two opcodes have different qualifiers for
2118 the immediate operands; reset to help the checking. */
2119 reset_operand_qualifier (inst
, 2);
2120 reset_operand_qualifier (inst
, 3);
2127 /* When <imms> < <immr>, the instruction written:
2128 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
2130 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
2133 convert_bfm_to_bfi (aarch64_inst
*inst
)
2135 int64_t immr
, imms
, val
;
2137 immr
= inst
->operands
[2].imm
.value
;
2138 imms
= inst
->operands
[3].imm
.value
;
2139 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2142 inst
->operands
[2].imm
.value
= (val
- immr
) & (val
- 1);
2143 inst
->operands
[3].imm
.value
= imms
+ 1;
2144 /* The two opcodes have different qualifiers for
2145 the immediate operands; reset to help the checking. */
2146 reset_operand_qualifier (inst
, 2);
2147 reset_operand_qualifier (inst
, 3);
2154 /* The instruction written:
2155 BFC <Xd>, #<lsb>, #<width>
2157 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
2160 convert_bfm_to_bfc (aarch64_inst
*inst
)
2162 int64_t immr
, imms
, val
;
2164 /* Should have been assured by the base opcode value. */
2165 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2167 immr
= inst
->operands
[2].imm
.value
;
2168 imms
= inst
->operands
[3].imm
.value
;
2169 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2172 /* Drop XZR from the second operand. */
2173 copy_operand_info (inst
, 1, 2);
2174 copy_operand_info (inst
, 2, 3);
2175 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2177 /* Recalculate the immediates. */
2178 inst
->operands
[1].imm
.value
= (val
- immr
) & (val
- 1);
2179 inst
->operands
[2].imm
.value
= imms
+ 1;
2181 /* The two opcodes have different qualifiers for the operands; reset to
2182 help the checking. */
2183 reset_operand_qualifier (inst
, 1);
2184 reset_operand_qualifier (inst
, 2);
2185 reset_operand_qualifier (inst
, 3);
2193 /* The instruction written:
2194 LSL <Xd>, <Xn>, #<shift>
2196 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
2199 convert_ubfm_to_lsl (aarch64_inst
*inst
)
2201 int64_t immr
= inst
->operands
[2].imm
.value
;
2202 int64_t imms
= inst
->operands
[3].imm
.value
;
2204 = inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2206 if ((immr
== 0 && imms
== val
) || immr
== imms
+ 1)
2208 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2209 inst
->operands
[2].imm
.value
= val
- imms
;
2216 /* CINC <Wd>, <Wn>, <cond>
2218 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
2219 where <cond> is not AL or NV. */
2222 convert_from_csel (aarch64_inst
*inst
)
2224 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
2225 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2227 copy_operand_info (inst
, 2, 3);
2228 inst
->operands
[2].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2229 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2235 /* CSET <Wd>, <cond>
2237 CSINC <Wd>, WZR, WZR, invert(<cond>)
2238 where <cond> is not AL or NV. */
2241 convert_csinc_to_cset (aarch64_inst
*inst
)
2243 if (inst
->operands
[1].reg
.regno
== 0x1f
2244 && inst
->operands
[2].reg
.regno
== 0x1f
2245 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2247 copy_operand_info (inst
, 1, 3);
2248 inst
->operands
[1].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2249 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2250 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2258 MOVZ <Wd>, #<imm16>, LSL #<shift>.
2260 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2261 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2262 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2263 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2264 machine-instruction mnemonic must be used. */
2267 convert_movewide_to_mov (aarch64_inst
*inst
)
2269 uint64_t value
= inst
->operands
[1].imm
.value
;
2270 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
2271 if (value
== 0 && inst
->operands
[1].shifter
.amount
!= 0)
2273 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2274 inst
->operands
[1].shifter
.kind
= AARCH64_MOD_NONE
;
2275 value
<<= inst
->operands
[1].shifter
.amount
;
2276 /* As an alias convertor, it has to be clear that the INST->OPCODE
2277 is the opcode of the real instruction. */
2278 if (inst
->opcode
->op
== OP_MOVN
)
2280 int is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2282 /* A MOVN has an immediate that could be encoded by MOVZ. */
2283 if (aarch64_wide_constant_p (value
, is32
, NULL
) == TRUE
)
2286 inst
->operands
[1].imm
.value
= value
;
2287 inst
->operands
[1].shifter
.amount
= 0;
2293 ORR <Wd>, WZR, #<imm>.
2295 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2296 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2297 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2298 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2299 machine-instruction mnemonic must be used. */
2302 convert_movebitmask_to_mov (aarch64_inst
*inst
)
2307 /* Should have been assured by the base opcode value. */
2308 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2309 copy_operand_info (inst
, 1, 2);
2310 is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2311 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2312 value
= inst
->operands
[1].imm
.value
;
2313 /* ORR has an immediate that could be generated by a MOVZ or MOVN
2315 if (inst
->operands
[0].reg
.regno
!= 0x1f
2316 && (aarch64_wide_constant_p (value
, is32
, NULL
) == TRUE
2317 || aarch64_wide_constant_p (~value
, is32
, NULL
) == TRUE
))
2320 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2324 /* Some alias opcodes are disassembled by being converted from their real-form.
2325 N.B. INST->OPCODE is the real opcode rather than the alias. */
2328 convert_to_alias (aarch64_inst
*inst
, const aarch64_opcode
*alias
)
2334 return convert_bfm_to_sr (inst
);
2336 return convert_ubfm_to_lsl (inst
);
2340 return convert_from_csel (inst
);
2343 return convert_csinc_to_cset (inst
);
2347 return convert_bfm_to_bfx (inst
);
2351 return convert_bfm_to_bfi (inst
);
2353 return convert_bfm_to_bfc (inst
);
2355 return convert_orr_to_mov (inst
);
2356 case OP_MOV_IMM_WIDE
:
2357 case OP_MOV_IMM_WIDEN
:
2358 return convert_movewide_to_mov (inst
);
2359 case OP_MOV_IMM_LOG
:
2360 return convert_movebitmask_to_mov (inst
);
2362 return convert_extr_to_ror (inst
);
2367 return convert_shll_to_xtl (inst
);
2373 static int aarch64_opcode_decode (const aarch64_opcode
*, const aarch64_insn
,
2374 aarch64_inst
*, int);
2376 /* Given the instruction information in *INST, check if the instruction has
2377 any alias form that can be used to represent *INST. If the answer is yes,
2378 update *INST to be in the form of the determined alias. */
2380 /* In the opcode description table, the following flags are used in opcode
2381 entries to help establish the relations between the real and alias opcodes:
2383 F_ALIAS: opcode is an alias
2384 F_HAS_ALIAS: opcode has alias(es)
2387 F_P3: Disassembly preference priority 1-3 (the larger the
2388 higher). If nothing is specified, it is the priority
2389 0 by default, i.e. the lowest priority.
2391 Although the relation between the machine and the alias instructions are not
2392 explicitly described, it can be easily determined from the base opcode
2393 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
2394 description entries:
2396 The mask of an alias opcode must be equal to or a super-set (i.e. more
2397 constrained) of that of the aliased opcode; so is the base opcode value.
2399 if (opcode_has_alias (real) && alias_opcode_p (opcode)
2400 && (opcode->mask & real->mask) == real->mask
2401 && (real->mask & opcode->opcode) == (real->mask & real->opcode))
2402 then OPCODE is an alias of, and only of, the REAL instruction
2404 The alias relationship is forced flat-structured to keep related algorithm
2405 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
2407 During the disassembling, the decoding decision tree (in
2408 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
2409 if the decoding of such a machine instruction succeeds (and -Mno-aliases is
2410 not specified), the disassembler will check whether there is any alias
2411 instruction exists for this real instruction. If there is, the disassembler
2412 will try to disassemble the 32-bit binary again using the alias's rule, or
2413 try to convert the IR to the form of the alias. In the case of the multiple
2414 aliases, the aliases are tried one by one from the highest priority
2415 (currently the flag F_P3) to the lowest priority (no priority flag), and the
2416 first succeeds first adopted.
2418 You may ask why there is a need for the conversion of IR from one form to
2419 another in handling certain aliases. This is because on one hand it avoids
2420 adding more operand code to handle unusual encoding/decoding; on other
2421 hand, during the disassembling, the conversion is an effective approach to
2422 check the condition of an alias (as an alias may be adopted only if certain
2423 conditions are met).
2425 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
2426 aarch64_opcode_table and generated aarch64_find_alias_opcode and
2427 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
2430 determine_disassembling_preference (struct aarch64_inst
*inst
)
2432 const aarch64_opcode
*opcode
;
2433 const aarch64_opcode
*alias
;
2435 opcode
= inst
->opcode
;
2437 /* This opcode does not have an alias, so use itself. */
2438 if (opcode_has_alias (opcode
) == FALSE
)
2441 alias
= aarch64_find_alias_opcode (opcode
);
2444 #ifdef DEBUG_AARCH64
2447 const aarch64_opcode
*tmp
= alias
;
2448 printf ("#### LIST orderd: ");
2451 printf ("%s, ", tmp
->name
);
2452 tmp
= aarch64_find_next_alias_opcode (tmp
);
2456 #endif /* DEBUG_AARCH64 */
2458 for (; alias
; alias
= aarch64_find_next_alias_opcode (alias
))
2460 DEBUG_TRACE ("try %s", alias
->name
);
2461 assert (alias_opcode_p (alias
) || opcode_has_alias (opcode
));
2463 /* An alias can be a pseudo opcode which will never be used in the
2464 disassembly, e.g. BIC logical immediate is such a pseudo opcode
2466 if (pseudo_opcode_p (alias
))
2468 DEBUG_TRACE ("skip pseudo %s", alias
->name
);
2472 if ((inst
->value
& alias
->mask
) != alias
->opcode
)
2474 DEBUG_TRACE ("skip %s as base opcode not match", alias
->name
);
2477 /* No need to do any complicated transformation on operands, if the alias
2478 opcode does not have any operand. */
2479 if (aarch64_num_of_operands (alias
) == 0 && alias
->opcode
== inst
->value
)
2481 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias
->name
);
2482 aarch64_replace_opcode (inst
, alias
);
2485 if (alias
->flags
& F_CONV
)
2488 memcpy (©
, inst
, sizeof (aarch64_inst
));
2489 /* ALIAS is the preference as long as the instruction can be
2490 successfully converted to the form of ALIAS. */
2491 if (convert_to_alias (©
, alias
) == 1)
2493 aarch64_replace_opcode (©
, alias
);
2494 assert (aarch64_match_operands_constraint (©
, NULL
));
2495 DEBUG_TRACE ("succeed with %s via conversion", alias
->name
);
2496 memcpy (inst
, ©
, sizeof (aarch64_inst
));
2502 /* Directly decode the alias opcode. */
2504 memset (&temp
, '\0', sizeof (aarch64_inst
));
2505 if (aarch64_opcode_decode (alias
, inst
->value
, &temp
, 1) == 1)
2507 DEBUG_TRACE ("succeed with %s via direct decoding", alias
->name
);
2508 memcpy (inst
, &temp
, sizeof (aarch64_inst
));
2515 /* Some instructions (including all SVE ones) use the instruction class
2516 to describe how a qualifiers_list index is represented in the instruction
2517 encoding. If INST is such an instruction, decode the appropriate fields
2518 and fill in the operand qualifiers accordingly. Return true if no
2519 problems are found. */
2522 aarch64_decode_variant_using_iclass (aarch64_inst
*inst
)
2527 switch (inst
->opcode
->iclass
)
2530 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_14
);
2534 i
= extract_field (FLD_SVE_tsz
, inst
->value
, 0);
2537 while ((i
& 1) == 0)
2545 /* Pick the smallest applicable element size. */
2546 if ((inst
->value
& 0x20600) == 0x600)
2548 else if ((inst
->value
& 0x20400) == 0x400)
2550 else if ((inst
->value
& 0x20000) == 0)
2557 /* sve_misc instructions have only a single variant. */
2561 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_16
);
2565 variant
= extract_field (FLD_SVE_M_4
, inst
->value
, 0);
2568 case sve_shift_pred
:
2569 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_8
);
2580 case sve_shift_unpred
:
2581 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_19
);
2585 variant
= extract_field (FLD_size
, inst
->value
, 0);
2591 variant
= extract_field (FLD_size
, inst
->value
, 0);
2595 i
= extract_field (FLD_size
, inst
->value
, 0);
2602 variant
= extract_field (FLD_SVE_sz
, inst
->value
, 0);
2606 /* No mapping between instruction class and qualifiers. */
2610 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2611 inst
->operands
[i
].qualifier
= inst
->opcode
->qualifiers_list
[variant
][i
];
2614 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
2615 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
2618 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
2619 determined and used to disassemble CODE; this is done just before the
2623 aarch64_opcode_decode (const aarch64_opcode
*opcode
, const aarch64_insn code
,
2624 aarch64_inst
*inst
, int noaliases_p
)
2628 DEBUG_TRACE ("enter with %s", opcode
->name
);
2630 assert (opcode
&& inst
);
2632 /* Check the base opcode. */
2633 if ((code
& opcode
->mask
) != (opcode
->opcode
& opcode
->mask
))
2635 DEBUG_TRACE ("base opcode match FAIL");
2640 memset (inst
, '\0', sizeof (aarch64_inst
));
2642 inst
->opcode
= opcode
;
2645 /* Assign operand codes and indexes. */
2646 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2648 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
)
2650 inst
->operands
[i
].type
= opcode
->operands
[i
];
2651 inst
->operands
[i
].idx
= i
;
2654 /* Call the opcode decoder indicated by flags. */
2655 if (opcode_has_special_coder (opcode
) && do_special_decoding (inst
) == 0)
2657 DEBUG_TRACE ("opcode flag-based decoder FAIL");
2661 /* Possibly use the instruction class to determine the correct
2663 if (!aarch64_decode_variant_using_iclass (inst
))
2665 DEBUG_TRACE ("iclass-based decoder FAIL");
2669 /* Call operand decoders. */
2670 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2672 const aarch64_operand
*opnd
;
2673 enum aarch64_opnd type
;
2675 type
= opcode
->operands
[i
];
2676 if (type
== AARCH64_OPND_NIL
)
2678 opnd
= &aarch64_operands
[type
];
2679 if (operand_has_extractor (opnd
)
2680 && (! aarch64_extract_operand (opnd
, &inst
->operands
[i
], code
, inst
)))
2682 DEBUG_TRACE ("operand decoder FAIL at operand %d", i
);
2687 /* If the opcode has a verifier, then check it now. */
2688 if (opcode
->verifier
&& ! opcode
->verifier (opcode
, code
))
2690 DEBUG_TRACE ("operand verifier FAIL");
2694 /* Match the qualifiers. */
2695 if (aarch64_match_operands_constraint (inst
, NULL
) == 1)
2697 /* Arriving here, the CODE has been determined as a valid instruction
2698 of OPCODE and *INST has been filled with information of this OPCODE
2699 instruction. Before the return, check if the instruction has any
2700 alias and should be disassembled in the form of its alias instead.
2701 If the answer is yes, *INST will be updated. */
2703 determine_disassembling_preference (inst
);
2704 DEBUG_TRACE ("SUCCESS");
2709 DEBUG_TRACE ("constraint matching FAIL");
2716 /* This does some user-friendly fix-up to *INST. It is currently focus on
2717 the adjustment of qualifiers to help the printed instruction
2718 recognized/understood more easily. */
2721 user_friendly_fixup (aarch64_inst
*inst
)
2723 switch (inst
->opcode
->iclass
)
2726 /* TBNZ Xn|Wn, #uimm6, label
2727 Test and Branch Not Zero: conditionally jumps to label if bit number
2728 uimm6 in register Xn is not zero. The bit number implies the width of
2729 the register, which may be written and should be disassembled as Wn if
2730 uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
2732 if (inst
->operands
[1].imm
.value
< 32)
2733 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
2739 /* Decode INSN and fill in *INST the instruction information. An alias
2740 opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
2744 aarch64_decode_insn (aarch64_insn insn
, aarch64_inst
*inst
,
2745 bfd_boolean noaliases_p
)
2747 const aarch64_opcode
*opcode
= aarch64_opcode_lookup (insn
);
2749 #ifdef DEBUG_AARCH64
2752 const aarch64_opcode
*tmp
= opcode
;
2754 DEBUG_TRACE ("opcode lookup:");
2757 aarch64_verbose (" %s", tmp
->name
);
2758 tmp
= aarch64_find_next_opcode (tmp
);
2761 #endif /* DEBUG_AARCH64 */
2763 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
2764 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
2765 opcode field and value, apart from the difference that one of them has an
2766 extra field as part of the opcode, but such a field is used for operand
2767 encoding in other opcode(s) ('immh' in the case of the example). */
2768 while (opcode
!= NULL
)
2770 /* But only one opcode can be decoded successfully for, as the
2771 decoding routine will check the constraint carefully. */
2772 if (aarch64_opcode_decode (opcode
, insn
, inst
, noaliases_p
) == 1)
2774 opcode
= aarch64_find_next_opcode (opcode
);
2780 /* Print operands. */
2783 print_operands (bfd_vma pc
, const aarch64_opcode
*opcode
,
2784 const aarch64_opnd_info
*opnds
, struct disassemble_info
*info
)
2786 int i
, pcrel_p
, num_printed
;
2787 for (i
= 0, num_printed
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2790 /* We regard the opcode operand info more, however we also look into
2791 the inst->operands to support the disassembling of the optional
2793 The two operand code should be the same in all cases, apart from
2794 when the operand can be optional. */
2795 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
2796 || opnds
[i
].type
== AARCH64_OPND_NIL
)
2799 /* Generate the operand string in STR. */
2800 aarch64_print_operand (str
, sizeof (str
), pc
, opcode
, opnds
, i
, &pcrel_p
,
2803 /* Print the delimiter (taking account of omitted operand(s)). */
2805 (*info
->fprintf_func
) (info
->stream
, "%s",
2806 num_printed
++ == 0 ? "\t" : ", ");
2808 /* Print the operand. */
2810 (*info
->print_address_func
) (info
->target
, info
);
2812 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
2816 /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */
2819 remove_dot_suffix (char *name
, const aarch64_inst
*inst
)
2824 ptr
= strchr (inst
->opcode
->name
, '.');
2825 assert (ptr
&& inst
->cond
);
2826 len
= ptr
- inst
->opcode
->name
;
2828 strncpy (name
, inst
->opcode
->name
, len
);
2832 /* Print the instruction mnemonic name. */
2835 print_mnemonic_name (const aarch64_inst
*inst
, struct disassemble_info
*info
)
2837 if (inst
->opcode
->flags
& F_COND
)
2839 /* For instructions that are truly conditionally executed, e.g. b.cond,
2840 prepare the full mnemonic name with the corresponding condition
2844 remove_dot_suffix (name
, inst
);
2845 (*info
->fprintf_func
) (info
->stream
, "%s.%s", name
, inst
->cond
->names
[0]);
2848 (*info
->fprintf_func
) (info
->stream
, "%s", inst
->opcode
->name
);
2851 /* Decide whether we need to print a comment after the operands of
2852 instruction INST. */
2855 print_comment (const aarch64_inst
*inst
, struct disassemble_info
*info
)
2857 if (inst
->opcode
->flags
& F_COND
)
2860 unsigned int i
, num_conds
;
2862 remove_dot_suffix (name
, inst
);
2863 num_conds
= ARRAY_SIZE (inst
->cond
->names
);
2864 for (i
= 1; i
< num_conds
&& inst
->cond
->names
[i
]; ++i
)
2865 (*info
->fprintf_func
) (info
->stream
, "%s %s.%s",
2866 i
== 1 ? " //" : ",",
2867 name
, inst
->cond
->names
[i
]);
2871 /* Print the instruction according to *INST. */
2874 print_aarch64_insn (bfd_vma pc
, const aarch64_inst
*inst
,
2875 struct disassemble_info
*info
)
2877 print_mnemonic_name (inst
, info
);
2878 print_operands (pc
, inst
->opcode
, inst
->operands
, info
);
2879 print_comment (inst
, info
);
2882 /* Entry-point of the instruction disassembler and printer. */
2885 print_insn_aarch64_word (bfd_vma pc
,
2887 struct disassemble_info
*info
)
2889 static const char *err_msg
[6] =
2892 [-ERR_UND
] = "undefined",
2893 [-ERR_UNP
] = "unpredictable",
2900 info
->insn_info_valid
= 1;
2901 info
->branch_delay_insns
= 0;
2902 info
->data_size
= 0;
2906 if (info
->flags
& INSN_HAS_RELOC
)
2907 /* If the instruction has a reloc associated with it, then
2908 the offset field in the instruction will actually be the
2909 addend for the reloc. (If we are using REL type relocs).
2910 In such cases, we can ignore the pc when computing
2911 addresses, since the addend is not currently pc-relative. */
2914 ret
= aarch64_decode_insn (word
, &inst
, no_aliases
);
2916 if (((word
>> 21) & 0x3ff) == 1)
2918 /* RESERVED for ALES. */
2919 assert (ret
!= ERR_OK
);
2928 /* Handle undefined instructions. */
2929 info
->insn_type
= dis_noninsn
;
2930 (*info
->fprintf_func
) (info
->stream
,".inst\t0x%08x ; %s",
2931 word
, err_msg
[-ret
]);
2934 user_friendly_fixup (&inst
);
2935 print_aarch64_insn (pc
, &inst
, info
);
2942 /* Disallow mapping symbols ($x, $d etc) from
2943 being displayed in symbol relative addresses. */
2946 aarch64_symbol_is_valid (asymbol
* sym
,
2947 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
2954 name
= bfd_asymbol_name (sym
);
2958 || (name
[1] != 'x' && name
[1] != 'd')
2959 || (name
[2] != '\0' && name
[2] != '.'));
2962 /* Print data bytes on INFO->STREAM. */
2965 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
2967 struct disassemble_info
*info
)
2969 switch (info
->bytes_per_chunk
)
2972 info
->fprintf_func (info
->stream
, ".byte\t0x%02x", word
);
2975 info
->fprintf_func (info
->stream
, ".short\t0x%04x", word
);
2978 info
->fprintf_func (info
->stream
, ".word\t0x%08x", word
);
2985 /* Try to infer the code or data type from a symbol.
2986 Returns nonzero if *MAP_TYPE was set. */
2989 get_sym_code_type (struct disassemble_info
*info
, int n
,
2990 enum map_type
*map_type
)
2992 elf_symbol_type
*es
;
2996 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
2997 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
2999 /* If the symbol has function type then use that. */
3000 if (type
== STT_FUNC
)
3002 *map_type
= MAP_INSN
;
3006 /* Check for mapping symbols. */
3007 name
= bfd_asymbol_name(info
->symtab
[n
]);
3009 && (name
[1] == 'x' || name
[1] == 'd')
3010 && (name
[2] == '\0' || name
[2] == '.'))
3012 *map_type
= (name
[1] == 'x' ? MAP_INSN
: MAP_DATA
);
3019 /* Entry-point of the AArch64 disassembler. */
3022 print_insn_aarch64 (bfd_vma pc
,
3023 struct disassemble_info
*info
)
3025 bfd_byte buffer
[INSNLEN
];
3027 void (*printer
) (bfd_vma
, uint32_t, struct disassemble_info
*);
3028 bfd_boolean found
= FALSE
;
3029 unsigned int size
= 4;
3032 if (info
->disassembler_options
)
3034 set_default_aarch64_dis_options (info
);
3036 parse_aarch64_dis_options (info
->disassembler_options
);
3038 /* To avoid repeated parsing of these options, we remove them here. */
3039 info
->disassembler_options
= NULL
;
3042 /* Aarch64 instructions are always little-endian */
3043 info
->endian_code
= BFD_ENDIAN_LITTLE
;
3045 /* First check the full symtab for a mapping symbol, even if there
3046 are no usable non-mapping symbols for this address. */
3047 if (info
->symtab_size
!= 0
3048 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
3050 enum map_type type
= MAP_INSN
;
3055 if (pc
<= last_mapping_addr
)
3056 last_mapping_sym
= -1;
3058 /* Start scanning at the start of the function, or wherever
3059 we finished last time. */
3060 n
= info
->symtab_pos
+ 1;
3061 if (n
< last_mapping_sym
)
3062 n
= last_mapping_sym
;
3064 /* Scan up to the location being disassembled. */
3065 for (; n
< info
->symtab_size
; n
++)
3067 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3070 if ((info
->section
== NULL
3071 || info
->section
== info
->symtab
[n
]->section
)
3072 && get_sym_code_type (info
, n
, &type
))
3081 n
= info
->symtab_pos
;
3082 if (n
< last_mapping_sym
)
3083 n
= last_mapping_sym
;
3085 /* No mapping symbol found at this address. Look backwards
3086 for a preceeding one. */
3089 if (get_sym_code_type (info
, n
, &type
))
3098 last_mapping_sym
= last_sym
;
3101 /* Look a little bit ahead to see if we should print out
3102 less than four bytes of data. If there's a symbol,
3103 mapping or otherwise, after two bytes then don't
3105 if (last_type
== MAP_DATA
)
3107 size
= 4 - (pc
& 3);
3108 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
3110 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3113 if (addr
- pc
< size
)
3118 /* If the next symbol is after three bytes, we need to
3119 print only part of the data, so that we can use either
3122 size
= (pc
& 1) ? 1 : 2;
3126 if (last_type
== MAP_DATA
)
3128 /* size was set above. */
3129 info
->bytes_per_chunk
= size
;
3130 info
->display_endian
= info
->endian
;
3131 printer
= print_insn_data
;
3135 info
->bytes_per_chunk
= size
= INSNLEN
;
3136 info
->display_endian
= info
->endian_code
;
3137 printer
= print_insn_aarch64_word
;
3140 status
= (*info
->read_memory_func
) (pc
, buffer
, size
, info
);
3143 (*info
->memory_error_func
) (status
, pc
, info
);
3147 data
= bfd_get_bits (buffer
, size
* 8,
3148 info
->display_endian
== BFD_ENDIAN_BIG
);
3150 (*printer
) (pc
, data
, info
);
3156 print_aarch64_disassembler_options (FILE *stream
)
3158 fprintf (stream
, _("\n\
3159 The following AARCH64 specific disassembler options are supported for use\n\
3160 with the -M switch (multiple options should be separated by commas):\n"));
3162 fprintf (stream
, _("\n\
3163 no-aliases Don't print instruction aliases.\n"));
3165 fprintf (stream
, _("\n\
3166 aliases Do print instruction aliases.\n"));
3168 #ifdef DEBUG_AARCH64
3169 fprintf (stream
, _("\n\
3170 debug_dump Temp switch for debug trace.\n"));
3171 #endif /* DEBUG_AARCH64 */
3173 fprintf (stream
, _("\n"));