1 /* aarch64-dis.c -- AArch64 disassembler.
2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
22 #include "bfd_stdint.h"
23 #include "disassemble.h"
24 #include "libiberty.h"
26 #include "aarch64-dis.h"
36 /* Cached mapping symbol state. */
43 static enum map_type last_type
;
44 static int last_mapping_sym
= -1;
45 static bfd_vma last_mapping_addr
= 0;
48 static int no_aliases
= 0; /* If set disassemble as most general inst. */
49 \fstatic int no_notes
= 1; /* If set do not print disassemble notes in the
50 output as comments. */
53 set_default_aarch64_dis_options (struct disassemble_info
*info ATTRIBUTE_UNUSED
)
58 parse_aarch64_dis_option (const char *option
, unsigned int len ATTRIBUTE_UNUSED
)
60 /* Try to match options that are simple flags */
61 if (CONST_STRNEQ (option
, "no-aliases"))
67 if (CONST_STRNEQ (option
, "aliases"))
73 if (CONST_STRNEQ (option
, "no-notes"))
79 if (CONST_STRNEQ (option
, "notes"))
86 if (CONST_STRNEQ (option
, "debug_dump"))
91 #endif /* DEBUG_AARCH64 */
94 opcodes_error_handler (_("unrecognised disassembler option: %s"), option
);
98 parse_aarch64_dis_options (const char *options
)
100 const char *option_end
;
105 while (*options
!= '\0')
107 /* Skip empty options. */
114 /* We know that *options is neither NUL or a comma. */
115 option_end
= options
+ 1;
116 while (*option_end
!= ',' && *option_end
!= '\0')
119 parse_aarch64_dis_option (options
, option_end
- options
);
121 /* Go on to the next one. If option_end points to a comma, it
122 will be skipped above. */
123 options
= option_end
;
127 /* Functions doing the instruction disassembling. */
129 /* The unnamed arguments consist of the number of fields and information about
130 these fields where the VALUE will be extracted from CODE and returned.
131 MASK can be zero or the base mask of the opcode.
133 N.B. the fields are required to be in such an order than the most signficant
134 field for VALUE comes the first, e.g. the <index> in
135 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
136 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
137 the order of H, L, M. */
140 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...)
143 const aarch64_field
*field
;
144 enum aarch64_field_kind kind
;
148 num
= va_arg (va
, uint32_t);
150 aarch64_insn value
= 0x0;
153 kind
= va_arg (va
, enum aarch64_field_kind
);
154 field
= &fields
[kind
];
155 value
<<= field
->width
;
156 value
|= extract_field (kind
, code
, mask
);
161 /* Extract the value of all fields in SELF->fields from instruction CODE.
162 The least significant bit comes from the final field. */
165 extract_all_fields (const aarch64_operand
*self
, aarch64_insn code
)
169 enum aarch64_field_kind kind
;
172 for (i
= 0; i
< ARRAY_SIZE (self
->fields
) && self
->fields
[i
] != FLD_NIL
; ++i
)
174 kind
= self
->fields
[i
];
175 value
<<= fields
[kind
].width
;
176 value
|= extract_field (kind
, code
, 0);
181 /* Sign-extend bit I of VALUE. */
182 static inline int32_t
183 sign_extend (aarch64_insn value
, unsigned i
)
185 uint32_t ret
= value
;
188 if ((value
>> i
) & 0x1)
190 uint32_t val
= (uint32_t)(-1) << i
;
193 return (int32_t) ret
;
196 /* N.B. the following inline helpfer functions create a dependency on the
197 order of operand qualifier enumerators. */
199 /* Given VALUE, return qualifier for a general purpose register. */
200 static inline enum aarch64_opnd_qualifier
201 get_greg_qualifier_from_value (aarch64_insn value
)
203 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_W
+ value
;
205 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
209 /* Given VALUE, return qualifier for a vector register. This does not support
210 decoding instructions that accept the 2H vector type. */
212 static inline enum aarch64_opnd_qualifier
213 get_vreg_qualifier_from_value (aarch64_insn value
)
215 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_V_8B
+ value
;
217 /* Instructions using vector type 2H should not call this function. Skip over
219 if (qualifier
>= AARCH64_OPND_QLF_V_2H
)
223 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
227 /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
228 static inline enum aarch64_opnd_qualifier
229 get_sreg_qualifier_from_value (aarch64_insn value
)
231 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_S_B
+ value
;
234 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
238 /* Given the instruction in *INST which is probably half way through the
239 decoding and our caller wants to know the expected qualifier for operand
240 I. Return such a qualifier if we can establish it; otherwise return
241 AARCH64_OPND_QLF_NIL. */
243 static aarch64_opnd_qualifier_t
244 get_expected_qualifier (const aarch64_inst
*inst
, int i
)
246 aarch64_opnd_qualifier_seq_t qualifiers
;
247 /* Should not be called if the qualifier is known. */
248 assert (inst
->operands
[i
].qualifier
== AARCH64_OPND_QLF_NIL
);
249 if (aarch64_find_best_match (inst
, inst
->opcode
->qualifiers_list
,
251 return qualifiers
[i
];
253 return AARCH64_OPND_QLF_NIL
;
256 /* Operand extractors. */
259 aarch64_ext_regno (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
260 const aarch64_insn code
,
261 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
262 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
264 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
269 aarch64_ext_regno_pair (const aarch64_operand
*self ATTRIBUTE_UNUSED
, aarch64_opnd_info
*info
,
270 const aarch64_insn code ATTRIBUTE_UNUSED
,
271 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
272 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
274 assert (info
->idx
== 1
276 info
->reg
.regno
= inst
->operands
[info
->idx
- 1].reg
.regno
+ 1;
280 /* e.g. IC <ic_op>{, <Xt>}. */
282 aarch64_ext_regrt_sysins (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
283 const aarch64_insn code
,
284 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
285 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
287 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
288 assert (info
->idx
== 1
289 && (aarch64_get_operand_class (inst
->operands
[0].type
)
290 == AARCH64_OPND_CLASS_SYSTEM
));
291 /* This will make the constraint checking happy and more importantly will
292 help the disassembler determine whether this operand is optional or
294 info
->present
= aarch64_sys_ins_reg_has_xt (inst
->operands
[0].sysins_op
);
299 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
301 aarch64_ext_reglane (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
302 const aarch64_insn code
,
303 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
304 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
307 info
->reglane
.regno
= extract_field (self
->fields
[0], code
,
310 /* Index and/or type. */
311 if (inst
->opcode
->iclass
== asisdone
312 || inst
->opcode
->iclass
== asimdins
)
314 if (info
->type
== AARCH64_OPND_En
315 && inst
->opcode
->operands
[0] == AARCH64_OPND_Ed
)
318 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
319 assert (info
->idx
== 1); /* Vn */
320 aarch64_insn value
= extract_field (FLD_imm4
, code
, 0);
321 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
322 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
323 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
324 info
->reglane
.index
= value
>> shift
;
328 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
336 aarch64_insn value
= extract_field (FLD_imm5
, code
, 0);
337 while (++pos
<= 3 && (value
& 0x1) == 0)
341 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
342 info
->reglane
.index
= (unsigned) (value
>> 1);
345 else if (inst
->opcode
->iclass
== dotproduct
)
347 /* Need information in other operand(s) to help decoding. */
348 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
349 switch (info
->qualifier
)
351 case AARCH64_OPND_QLF_S_4B
:
353 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
354 info
->reglane
.regno
&= 0x1f;
360 else if (inst
->opcode
->iclass
== cryptosm3
)
362 /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */
363 info
->reglane
.index
= extract_field (FLD_SM3_imm2
, code
, 0);
367 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
368 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
370 /* Need information in other operand(s) to help decoding. */
371 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
372 switch (info
->qualifier
)
374 case AARCH64_OPND_QLF_S_H
:
376 info
->reglane
.index
= extract_fields (code
, 0, 3, FLD_H
, FLD_L
,
378 info
->reglane
.regno
&= 0xf;
380 case AARCH64_OPND_QLF_S_S
:
382 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
384 case AARCH64_OPND_QLF_S_D
:
386 info
->reglane
.index
= extract_field (FLD_H
, code
, 0);
392 if (inst
->opcode
->op
== OP_FCMLA_ELEM
)
394 /* Complex operand takes two elements. */
395 if (info
->reglane
.index
& 1)
397 info
->reglane
.index
/= 2;
405 aarch64_ext_reglist (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
406 const aarch64_insn code
,
407 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
408 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
411 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
413 info
->reglist
.num_regs
= extract_field (FLD_len
, code
, 0) + 1;
417 /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
419 aarch64_ext_ldst_reglist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
420 aarch64_opnd_info
*info
, const aarch64_insn code
,
421 const aarch64_inst
*inst
,
422 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
425 /* Number of elements in each structure to be loaded/stored. */
426 unsigned expected_num
= get_opcode_dependent_value (inst
->opcode
);
430 unsigned is_reserved
;
432 unsigned num_elements
;
448 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
450 value
= extract_field (FLD_opcode
, code
, 0);
451 /* PR 21595: Check for a bogus value. */
452 if (value
>= ARRAY_SIZE (data
))
454 if (expected_num
!= data
[value
].num_elements
|| data
[value
].is_reserved
)
456 info
->reglist
.num_regs
= data
[value
].num_regs
;
461 /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
462 lanes instructions. */
464 aarch64_ext_ldst_reglist_r (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
465 aarch64_opnd_info
*info
, const aarch64_insn code
,
466 const aarch64_inst
*inst
,
467 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
472 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
474 value
= extract_field (FLD_S
, code
, 0);
476 /* Number of registers is equal to the number of elements in
477 each structure to be loaded/stored. */
478 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
479 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
481 /* Except when it is LD1R. */
482 if (info
->reglist
.num_regs
== 1 && value
== (aarch64_insn
) 1)
483 info
->reglist
.num_regs
= 2;
488 /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
489 load/store single element instructions. */
491 aarch64_ext_ldst_elemlist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
492 aarch64_opnd_info
*info
, const aarch64_insn code
,
493 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
494 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
496 aarch64_field field
= {0, 0};
497 aarch64_insn QSsize
; /* fields Q:S:size. */
498 aarch64_insn opcodeh2
; /* opcode<2:1> */
501 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
503 /* Decode the index, opcode<2:1> and size. */
504 gen_sub_field (FLD_asisdlso_opcode
, 1, 2, &field
);
505 opcodeh2
= extract_field_2 (&field
, code
, 0);
506 QSsize
= extract_fields (code
, 0, 3, FLD_Q
, FLD_S
, FLD_vldst_size
);
510 info
->qualifier
= AARCH64_OPND_QLF_S_B
;
511 /* Index encoded in "Q:S:size". */
512 info
->reglist
.index
= QSsize
;
518 info
->qualifier
= AARCH64_OPND_QLF_S_H
;
519 /* Index encoded in "Q:S:size<1>". */
520 info
->reglist
.index
= QSsize
>> 1;
523 if ((QSsize
>> 1) & 0x1)
526 if ((QSsize
& 0x1) == 0)
528 info
->qualifier
= AARCH64_OPND_QLF_S_S
;
529 /* Index encoded in "Q:S". */
530 info
->reglist
.index
= QSsize
>> 2;
534 if (extract_field (FLD_S
, code
, 0))
537 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
538 /* Index encoded in "Q". */
539 info
->reglist
.index
= QSsize
>> 3;
546 info
->reglist
.has_index
= 1;
547 info
->reglist
.num_regs
= 0;
548 /* Number of registers is equal to the number of elements in
549 each structure to be loaded/stored. */
550 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
551 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
556 /* Decode fields immh:immb and/or Q for e.g.
557 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
558 or SSHR <V><d>, <V><n>, #<shift>. */
561 aarch64_ext_advsimd_imm_shift (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
562 aarch64_opnd_info
*info
, const aarch64_insn code
,
563 const aarch64_inst
*inst
,
564 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
567 aarch64_insn Q
, imm
, immh
;
568 enum aarch64_insn_class iclass
= inst
->opcode
->iclass
;
570 immh
= extract_field (FLD_immh
, code
, 0);
573 imm
= extract_fields (code
, 0, 2, FLD_immh
, FLD_immb
);
575 /* Get highest set bit in immh. */
576 while (--pos
>= 0 && (immh
& 0x8) == 0)
579 assert ((iclass
== asimdshf
|| iclass
== asisdshf
)
580 && (info
->type
== AARCH64_OPND_IMM_VLSR
581 || info
->type
== AARCH64_OPND_IMM_VLSL
));
583 if (iclass
== asimdshf
)
585 Q
= extract_field (FLD_Q
, code
, 0);
587 0000 x SEE AdvSIMD modified immediate
597 get_vreg_qualifier_from_value ((pos
<< 1) | (int) Q
);
600 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
602 if (info
->type
== AARCH64_OPND_IMM_VLSR
)
604 0000 SEE AdvSIMD modified immediate
605 0001 (16-UInt(immh:immb))
606 001x (32-UInt(immh:immb))
607 01xx (64-UInt(immh:immb))
608 1xxx (128-UInt(immh:immb)) */
609 info
->imm
.value
= (16 << pos
) - imm
;
613 0000 SEE AdvSIMD modified immediate
614 0001 (UInt(immh:immb)-8)
615 001x (UInt(immh:immb)-16)
616 01xx (UInt(immh:immb)-32)
617 1xxx (UInt(immh:immb)-64) */
618 info
->imm
.value
= imm
- (8 << pos
);
623 /* Decode shift immediate for e.g. sshr (imm). */
625 aarch64_ext_shll_imm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
626 aarch64_opnd_info
*info
, const aarch64_insn code
,
627 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
628 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
632 val
= extract_field (FLD_size
, code
, 0);
635 case 0: imm
= 8; break;
636 case 1: imm
= 16; break;
637 case 2: imm
= 32; break;
638 default: return FALSE
;
640 info
->imm
.value
= imm
;
644 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
645 value in the field(s) will be extracted as unsigned immediate value. */
647 aarch64_ext_imm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
648 const aarch64_insn code
,
649 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
650 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
654 imm
= extract_all_fields (self
, code
);
656 if (operand_need_sign_extension (self
))
657 imm
= sign_extend (imm
, get_operand_fields_width (self
) - 1);
659 if (operand_need_shift_by_two (self
))
662 if (info
->type
== AARCH64_OPND_ADDR_ADRP
)
665 info
->imm
.value
= imm
;
669 /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
671 aarch64_ext_imm_half (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
672 const aarch64_insn code
,
673 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
674 aarch64_operand_error
*errors
)
676 aarch64_ext_imm (self
, info
, code
, inst
, errors
);
677 info
->shifter
.kind
= AARCH64_MOD_LSL
;
678 info
->shifter
.amount
= extract_field (FLD_hw
, code
, 0) << 4;
682 /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
683 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
685 aarch64_ext_advsimd_imm_modified (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
686 aarch64_opnd_info
*info
,
687 const aarch64_insn code
,
688 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
689 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
692 enum aarch64_opnd_qualifier opnd0_qualifier
= inst
->operands
[0].qualifier
;
693 aarch64_field field
= {0, 0};
695 assert (info
->idx
== 1);
697 if (info
->type
== AARCH64_OPND_SIMD_FPIMM
)
700 /* a:b:c:d:e:f:g:h */
701 imm
= extract_fields (code
, 0, 2, FLD_abc
, FLD_defgh
);
702 if (!info
->imm
.is_fp
&& aarch64_get_qualifier_esize (opnd0_qualifier
) == 8)
704 /* Either MOVI <Dd>, #<imm>
705 or MOVI <Vd>.2D, #<imm>.
706 <imm> is a 64-bit immediate
707 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
708 encoded in "a:b:c:d:e:f:g:h". */
710 unsigned abcdefgh
= imm
;
711 for (imm
= 0ull, i
= 0; i
< 8; i
++)
712 if (((abcdefgh
>> i
) & 0x1) != 0)
713 imm
|= 0xffull
<< (8 * i
);
715 info
->imm
.value
= imm
;
718 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
719 switch (info
->qualifier
)
721 case AARCH64_OPND_QLF_NIL
:
723 info
->shifter
.kind
= AARCH64_MOD_NONE
;
725 case AARCH64_OPND_QLF_LSL
:
727 info
->shifter
.kind
= AARCH64_MOD_LSL
;
728 switch (aarch64_get_qualifier_esize (opnd0_qualifier
))
730 case 4: gen_sub_field (FLD_cmode
, 1, 2, &field
); break; /* per word */
731 case 2: gen_sub_field (FLD_cmode
, 1, 1, &field
); break; /* per half */
732 case 1: gen_sub_field (FLD_cmode
, 1, 0, &field
); break; /* per byte */
733 default: assert (0); return FALSE
;
735 /* 00: 0; 01: 8; 10:16; 11:24. */
736 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) << 3;
738 case AARCH64_OPND_QLF_MSL
:
740 info
->shifter
.kind
= AARCH64_MOD_MSL
;
741 gen_sub_field (FLD_cmode
, 0, 1, &field
); /* per word */
742 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) ? 16 : 8;
752 /* Decode an 8-bit floating-point immediate. */
754 aarch64_ext_fpimm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
755 const aarch64_insn code
,
756 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
757 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
759 info
->imm
.value
= extract_all_fields (self
, code
);
764 /* Decode a 1-bit rotate immediate (#90 or #270). */
766 aarch64_ext_imm_rotate1 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
767 const aarch64_insn code
,
768 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
769 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
771 uint64_t rot
= extract_field (self
->fields
[0], code
, 0);
773 info
->imm
.value
= rot
* 180 + 90;
777 /* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */
779 aarch64_ext_imm_rotate2 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
780 const aarch64_insn code
,
781 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
782 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
784 uint64_t rot
= extract_field (self
->fields
[0], code
, 0);
786 info
->imm
.value
= rot
* 90;
790 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
792 aarch64_ext_fbits (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
793 aarch64_opnd_info
*info
, const aarch64_insn code
,
794 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
795 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
797 info
->imm
.value
= 64- extract_field (FLD_scale
, code
, 0);
801 /* Decode arithmetic immediate for e.g.
802 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
804 aarch64_ext_aimm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
805 aarch64_opnd_info
*info
, const aarch64_insn code
,
806 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
807 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
811 info
->shifter
.kind
= AARCH64_MOD_LSL
;
813 value
= extract_field (FLD_shift
, code
, 0);
816 info
->shifter
.amount
= value
? 12 : 0;
817 /* imm12 (unsigned) */
818 info
->imm
.value
= extract_field (FLD_imm12
, code
, 0);
823 /* Return true if VALUE is a valid logical immediate encoding, storing the
824 decoded value in *RESULT if so. ESIZE is the number of bytes in the
825 decoded immediate. */
827 decode_limm (uint32_t esize
, aarch64_insn value
, int64_t *result
)
833 /* value is N:immr:imms. */
835 R
= (value
>> 6) & 0x3f;
836 N
= (value
>> 12) & 0x1;
838 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
839 (in other words, right rotated by R), then replicated. */
843 mask
= 0xffffffffffffffffull
;
849 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size
= 32; break;
850 case 0x20 ... 0x2f: /* 10xxxx */ simd_size
= 16; S
&= 0xf; break;
851 case 0x30 ... 0x37: /* 110xxx */ simd_size
= 8; S
&= 0x7; break;
852 case 0x38 ... 0x3b: /* 1110xx */ simd_size
= 4; S
&= 0x3; break;
853 case 0x3c ... 0x3d: /* 11110x */ simd_size
= 2; S
&= 0x1; break;
854 default: return FALSE
;
856 mask
= (1ull << simd_size
) - 1;
857 /* Top bits are IGNORED. */
861 if (simd_size
> esize
* 8)
864 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
865 if (S
== simd_size
- 1)
867 /* S+1 consecutive bits to 1. */
868 /* NOTE: S can't be 63 due to detection above. */
869 imm
= (1ull << (S
+ 1)) - 1;
870 /* Rotate to the left by simd_size - R. */
872 imm
= ((imm
<< (simd_size
- R
)) & mask
) | (imm
>> R
);
873 /* Replicate the value according to SIMD size. */
876 case 2: imm
= (imm
<< 2) | imm
;
878 case 4: imm
= (imm
<< 4) | imm
;
880 case 8: imm
= (imm
<< 8) | imm
;
882 case 16: imm
= (imm
<< 16) | imm
;
884 case 32: imm
= (imm
<< 32) | imm
;
887 default: assert (0); return 0;
890 *result
= imm
& ~((uint64_t) -1 << (esize
* 4) << (esize
* 4));
895 /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
897 aarch64_ext_limm (const aarch64_operand
*self
,
898 aarch64_opnd_info
*info
, const aarch64_insn code
,
899 const aarch64_inst
*inst
,
900 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
905 value
= extract_fields (code
, 0, 3, self
->fields
[0], self
->fields
[1],
907 esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
908 return decode_limm (esize
, value
, &info
->imm
.value
);
911 /* Decode a logical immediate for the BIC alias of AND (etc.). */
913 aarch64_ext_inv_limm (const aarch64_operand
*self
,
914 aarch64_opnd_info
*info
, const aarch64_insn code
,
915 const aarch64_inst
*inst
,
916 aarch64_operand_error
*errors
)
918 if (!aarch64_ext_limm (self
, info
, code
, inst
, errors
))
920 info
->imm
.value
= ~info
->imm
.value
;
924 /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
925 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
927 aarch64_ext_ft (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
928 aarch64_opnd_info
*info
,
929 const aarch64_insn code
, const aarch64_inst
*inst
,
930 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
935 info
->reg
.regno
= extract_field (FLD_Rt
, code
, 0);
938 value
= extract_field (FLD_ldst_size
, code
, 0);
939 if (inst
->opcode
->iclass
== ldstpair_indexed
940 || inst
->opcode
->iclass
== ldstnapair_offs
941 || inst
->opcode
->iclass
== ldstpair_off
942 || inst
->opcode
->iclass
== loadlit
)
944 enum aarch64_opnd_qualifier qualifier
;
947 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
948 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
949 case 2: qualifier
= AARCH64_OPND_QLF_S_Q
; break;
950 default: return FALSE
;
952 info
->qualifier
= qualifier
;
957 value
= extract_fields (code
, 0, 2, FLD_opc1
, FLD_ldst_size
);
960 info
->qualifier
= get_sreg_qualifier_from_value (value
);
966 /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
968 aarch64_ext_addr_simple (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
969 aarch64_opnd_info
*info
,
971 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
972 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
975 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
979 /* Decode the address operand for e.g.
980 stlur <Xt>, [<Xn|SP>{, <amount>}]. */
982 aarch64_ext_addr_offset (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
983 aarch64_opnd_info
*info
,
984 aarch64_insn code
, const aarch64_inst
*inst
,
985 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
987 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
990 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
993 aarch64_insn imm
= extract_fields (code
, 0, 1, self
->fields
[1]);
994 info
->addr
.offset
.imm
= sign_extend (imm
, 8);
995 if (extract_field (self
->fields
[2], code
, 0) == 1) {
996 info
->addr
.writeback
= 1;
997 info
->addr
.preind
= 1;
1002 /* Decode the address operand for e.g.
1003 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1005 aarch64_ext_addr_regoff (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1006 aarch64_opnd_info
*info
,
1007 aarch64_insn code
, const aarch64_inst
*inst
,
1008 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1010 aarch64_insn S
, value
;
1013 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
1015 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
1017 value
= extract_field (FLD_option
, code
, 0);
1018 info
->shifter
.kind
=
1019 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
1020 /* Fix-up the shifter kind; although the table-driven approach is
1021 efficient, it is slightly inflexible, thus needing this fix-up. */
1022 if (info
->shifter
.kind
== AARCH64_MOD_UXTX
)
1023 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1025 S
= extract_field (FLD_S
, code
, 0);
1028 info
->shifter
.amount
= 0;
1029 info
->shifter
.amount_present
= 0;
1034 /* Need information in other operand(s) to help achieve the decoding
1036 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1037 /* Get the size of the data element that is accessed, which may be
1038 different from that of the source register size, e.g. in strb/ldrb. */
1039 size
= aarch64_get_qualifier_esize (info
->qualifier
);
1040 info
->shifter
.amount
= get_logsz (size
);
1041 info
->shifter
.amount_present
= 1;
1047 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
1049 aarch64_ext_addr_simm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1050 aarch64_insn code
, const aarch64_inst
*inst
,
1051 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1054 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1057 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
1058 /* simm (imm9 or imm7) */
1059 imm
= extract_field (self
->fields
[0], code
, 0);
1060 info
->addr
.offset
.imm
= sign_extend (imm
, fields
[self
->fields
[0]].width
- 1);
1061 if (self
->fields
[0] == FLD_imm7
)
1062 /* scaled immediate in ld/st pair instructions. */
1063 info
->addr
.offset
.imm
*= aarch64_get_qualifier_esize (info
->qualifier
);
1065 if (inst
->opcode
->iclass
== ldst_unscaled
1066 || inst
->opcode
->iclass
== ldstnapair_offs
1067 || inst
->opcode
->iclass
== ldstpair_off
1068 || inst
->opcode
->iclass
== ldst_unpriv
)
1069 info
->addr
.writeback
= 0;
1072 /* pre/post- index */
1073 info
->addr
.writeback
= 1;
1074 if (extract_field (self
->fields
[1], code
, 0) == 1)
1075 info
->addr
.preind
= 1;
1077 info
->addr
.postind
= 1;
1083 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
1085 aarch64_ext_addr_uimm12 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1087 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1088 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1091 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1092 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
1094 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1096 info
->addr
.offset
.imm
= extract_field (self
->fields
[1], code
, 0) << shift
;
1100 /* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
1102 aarch64_ext_addr_simm10 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1104 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1105 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1109 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1111 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1113 imm
= extract_fields (code
, 0, 2, self
->fields
[1], self
->fields
[2]);
1114 info
->addr
.offset
.imm
= sign_extend (imm
, 9) << 3;
1115 if (extract_field (self
->fields
[3], code
, 0) == 1) {
1116 info
->addr
.writeback
= 1;
1117 info
->addr
.preind
= 1;
1122 /* Decode the address operand for e.g.
1123 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
1125 aarch64_ext_simd_addr_post (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1126 aarch64_opnd_info
*info
,
1127 aarch64_insn code
, const aarch64_inst
*inst
,
1128 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1130 /* The opcode dependent area stores the number of elements in
1131 each structure to be loaded/stored. */
1132 int is_ld1r
= get_opcode_dependent_value (inst
->opcode
) == 1;
1135 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
1136 /* Rm | #<amount> */
1137 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
1138 if (info
->addr
.offset
.regno
== 31)
1140 if (inst
->opcode
->operands
[0] == AARCH64_OPND_LVt_AL
)
1141 /* Special handling of loading single structure to all lane. */
1142 info
->addr
.offset
.imm
= (is_ld1r
? 1
1143 : inst
->operands
[0].reglist
.num_regs
)
1144 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1146 info
->addr
.offset
.imm
= inst
->operands
[0].reglist
.num_regs
1147 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
)
1148 * aarch64_get_qualifier_nelem (inst
->operands
[0].qualifier
);
1151 info
->addr
.offset
.is_reg
= 1;
1152 info
->addr
.writeback
= 1;
1157 /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
1159 aarch64_ext_cond (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1160 aarch64_opnd_info
*info
,
1161 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1162 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1166 value
= extract_field (FLD_cond
, code
, 0);
1167 info
->cond
= get_cond_from_value (value
);
1171 /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
1173 aarch64_ext_sysreg (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1174 aarch64_opnd_info
*info
,
1176 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1177 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1179 /* op0:op1:CRn:CRm:op2 */
1180 info
->sysreg
.value
= extract_fields (code
, 0, 5, FLD_op0
, FLD_op1
, FLD_CRn
,
1185 /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
1187 aarch64_ext_pstatefield (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1188 aarch64_opnd_info
*info
, aarch64_insn code
,
1189 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1190 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1194 info
->pstatefield
= extract_fields (code
, 0, 2, FLD_op1
, FLD_op2
);
1195 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
1196 if (aarch64_pstatefields
[i
].value
== (aarch64_insn
)info
->pstatefield
)
1198 /* Reserved value in <pstatefield>. */
1202 /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
1204 aarch64_ext_sysins_op (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1205 aarch64_opnd_info
*info
,
1207 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1208 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1212 const aarch64_sys_ins_reg
*sysins_ops
;
1213 /* op0:op1:CRn:CRm:op2 */
1214 value
= extract_fields (code
, 0, 5,
1215 FLD_op0
, FLD_op1
, FLD_CRn
,
1220 case AARCH64_OPND_SYSREG_AT
: sysins_ops
= aarch64_sys_regs_at
; break;
1221 case AARCH64_OPND_SYSREG_DC
: sysins_ops
= aarch64_sys_regs_dc
; break;
1222 case AARCH64_OPND_SYSREG_IC
: sysins_ops
= aarch64_sys_regs_ic
; break;
1223 case AARCH64_OPND_SYSREG_TLBI
: sysins_ops
= aarch64_sys_regs_tlbi
; break;
1224 default: assert (0); return FALSE
;
1227 for (i
= 0; sysins_ops
[i
].name
!= NULL
; ++i
)
1228 if (sysins_ops
[i
].value
== value
)
1230 info
->sysins_op
= sysins_ops
+ i
;
1231 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1232 info
->sysins_op
->name
,
1233 (unsigned)info
->sysins_op
->value
,
1234 aarch64_sys_ins_reg_has_xt (info
->sysins_op
), i
);
1241 /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
1244 aarch64_ext_barrier (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1245 aarch64_opnd_info
*info
,
1247 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1248 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1251 info
->barrier
= aarch64_barrier_options
+ extract_field (FLD_CRm
, code
, 0);
1255 /* Decode the prefetch operation option operand for e.g.
1256 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
1259 aarch64_ext_prfop (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1260 aarch64_opnd_info
*info
,
1261 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1262 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1265 info
->prfop
= aarch64_prfops
+ extract_field (FLD_Rt
, code
, 0);
1269 /* Decode the hint number for an alias taking an operand. Set info->hint_option
1270 to the matching name/value pair in aarch64_hint_options. */
1273 aarch64_ext_hint (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1274 aarch64_opnd_info
*info
,
1276 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1277 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1280 unsigned hint_number
;
1283 hint_number
= extract_fields (code
, 0, 2, FLD_CRm
, FLD_op2
);
1285 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
1287 if (hint_number
== aarch64_hint_options
[i
].value
)
1289 info
->hint_option
= &(aarch64_hint_options
[i
]);
1297 /* Decode the extended register operand for e.g.
1298 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1300 aarch64_ext_reg_extended (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1301 aarch64_opnd_info
*info
,
1303 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1304 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1309 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1311 value
= extract_field (FLD_option
, code
, 0);
1312 info
->shifter
.kind
=
1313 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
1315 info
->shifter
.amount
= extract_field (FLD_imm3
, code
, 0);
1317 /* This makes the constraint checking happy. */
1318 info
->shifter
.operator_present
= 1;
1320 /* Assume inst->operands[0].qualifier has been resolved. */
1321 assert (inst
->operands
[0].qualifier
!= AARCH64_OPND_QLF_NIL
);
1322 info
->qualifier
= AARCH64_OPND_QLF_W
;
1323 if (inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_X
1324 && (info
->shifter
.kind
== AARCH64_MOD_UXTX
1325 || info
->shifter
.kind
== AARCH64_MOD_SXTX
))
1326 info
->qualifier
= AARCH64_OPND_QLF_X
;
1331 /* Decode the shifted register operand for e.g.
1332 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
1334 aarch64_ext_reg_shifted (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1335 aarch64_opnd_info
*info
,
1337 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1338 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1343 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1345 value
= extract_field (FLD_shift
, code
, 0);
1346 info
->shifter
.kind
=
1347 aarch64_get_operand_modifier_from_value (value
, FALSE
/* extend_p */);
1348 if (info
->shifter
.kind
== AARCH64_MOD_ROR
1349 && inst
->opcode
->iclass
!= log_shift
)
1350 /* ROR is not available for the shifted register operand in arithmetic
1354 info
->shifter
.amount
= extract_field (FLD_imm6
, code
, 0);
1356 /* This makes the constraint checking happy. */
1357 info
->shifter
.operator_present
= 1;
1362 /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
1363 where <offset> is given by the OFFSET parameter and where <factor> is
1364 1 plus SELF's operand-dependent value. fields[0] specifies the field
1365 that holds <base>. */
1367 aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand
*self
,
1368 aarch64_opnd_info
*info
, aarch64_insn code
,
1371 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1372 info
->addr
.offset
.imm
= offset
* (1 + get_operand_specific_data (self
));
1373 info
->addr
.offset
.is_reg
= FALSE
;
1374 info
->addr
.writeback
= FALSE
;
1375 info
->addr
.preind
= TRUE
;
1377 info
->shifter
.kind
= AARCH64_MOD_MUL_VL
;
1378 info
->shifter
.amount
= 1;
1379 info
->shifter
.operator_present
= (info
->addr
.offset
.imm
!= 0);
1380 info
->shifter
.amount_present
= FALSE
;
1384 /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
1385 where <simm4> is a 4-bit signed value and where <factor> is 1 plus
1386 SELF's operand-dependent value. fields[0] specifies the field that
1387 holds <base>. <simm4> is encoded in the SVE_imm4 field. */
1389 aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand
*self
,
1390 aarch64_opnd_info
*info
, aarch64_insn code
,
1391 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1392 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1396 offset
= extract_field (FLD_SVE_imm4
, code
, 0);
1397 offset
= ((offset
+ 8) & 15) - 8;
1398 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1401 /* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
1402 where <simm6> is a 6-bit signed value and where <factor> is 1 plus
1403 SELF's operand-dependent value. fields[0] specifies the field that
1404 holds <base>. <simm6> is encoded in the SVE_imm6 field. */
1406 aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand
*self
,
1407 aarch64_opnd_info
*info
, aarch64_insn code
,
1408 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1409 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1413 offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1414 offset
= (((offset
+ 32) & 63) - 32);
1415 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1418 /* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
1419 where <simm9> is a 9-bit signed value and where <factor> is 1 plus
1420 SELF's operand-dependent value. fields[0] specifies the field that
1421 holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
1422 and imm3 fields, with imm3 being the less-significant part. */
1424 aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand
*self
,
1425 aarch64_opnd_info
*info
,
1427 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1428 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1432 offset
= extract_fields (code
, 0, 2, FLD_SVE_imm6
, FLD_imm3
);
1433 offset
= (((offset
+ 256) & 511) - 256);
1434 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1437 /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
1438 is given by the OFFSET parameter and where <shift> is SELF's operand-
1439 dependent value. fields[0] specifies the base register field <base>. */
1441 aarch64_ext_sve_addr_reg_imm (const aarch64_operand
*self
,
1442 aarch64_opnd_info
*info
, aarch64_insn code
,
1445 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1446 info
->addr
.offset
.imm
= offset
* (1 << get_operand_specific_data (self
));
1447 info
->addr
.offset
.is_reg
= FALSE
;
1448 info
->addr
.writeback
= FALSE
;
1449 info
->addr
.preind
= TRUE
;
1450 info
->shifter
.operator_present
= FALSE
;
1451 info
->shifter
.amount_present
= FALSE
;
1455 /* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
1456 is a 4-bit signed number and where <shift> is SELF's operand-dependent
1457 value. fields[0] specifies the base register field. */
1459 aarch64_ext_sve_addr_ri_s4 (const aarch64_operand
*self
,
1460 aarch64_opnd_info
*info
, aarch64_insn code
,
1461 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1462 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1464 int offset
= sign_extend (extract_field (FLD_SVE_imm4
, code
, 0), 3);
1465 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1468 /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1469 is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1470 value. fields[0] specifies the base register field. */
1472 aarch64_ext_sve_addr_ri_u6 (const aarch64_operand
*self
,
1473 aarch64_opnd_info
*info
, aarch64_insn code
,
1474 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1475 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1477 int offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1478 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1481 /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1482 is SELF's operand-dependent value. fields[0] specifies the base
1483 register field and fields[1] specifies the offset register field. */
1485 aarch64_ext_sve_addr_rr_lsl (const aarch64_operand
*self
,
1486 aarch64_opnd_info
*info
, aarch64_insn code
,
1487 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1488 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1492 index_regno
= extract_field (self
->fields
[1], code
, 0);
1493 if (index_regno
== 31 && (self
->flags
& OPD_F_NO_ZR
) != 0)
1496 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1497 info
->addr
.offset
.regno
= index_regno
;
1498 info
->addr
.offset
.is_reg
= TRUE
;
1499 info
->addr
.writeback
= FALSE
;
1500 info
->addr
.preind
= TRUE
;
1501 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1502 info
->shifter
.amount
= get_operand_specific_data (self
);
1503 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1504 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1508 /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1509 <shift> is SELF's operand-dependent value. fields[0] specifies the
1510 base register field, fields[1] specifies the offset register field and
1511 fields[2] is a single-bit field that selects SXTW over UXTW. */
1513 aarch64_ext_sve_addr_rz_xtw (const aarch64_operand
*self
,
1514 aarch64_opnd_info
*info
, aarch64_insn code
,
1515 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1516 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1518 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1519 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1520 info
->addr
.offset
.is_reg
= TRUE
;
1521 info
->addr
.writeback
= FALSE
;
1522 info
->addr
.preind
= TRUE
;
1523 if (extract_field (self
->fields
[2], code
, 0))
1524 info
->shifter
.kind
= AARCH64_MOD_SXTW
;
1526 info
->shifter
.kind
= AARCH64_MOD_UXTW
;
1527 info
->shifter
.amount
= get_operand_specific_data (self
);
1528 info
->shifter
.operator_present
= TRUE
;
1529 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1533 /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1534 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1535 fields[0] specifies the base register field. */
1537 aarch64_ext_sve_addr_zi_u5 (const aarch64_operand
*self
,
1538 aarch64_opnd_info
*info
, aarch64_insn code
,
1539 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1540 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1542 int offset
= extract_field (FLD_imm5
, code
, 0);
1543 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1546 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1547 where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
1548 number. fields[0] specifies the base register field and fields[1]
1549 specifies the offset register field. */
1551 aarch64_ext_sve_addr_zz (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1552 aarch64_insn code
, enum aarch64_modifier_kind kind
)
1554 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1555 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1556 info
->addr
.offset
.is_reg
= TRUE
;
1557 info
->addr
.writeback
= FALSE
;
1558 info
->addr
.preind
= TRUE
;
1559 info
->shifter
.kind
= kind
;
1560 info
->shifter
.amount
= extract_field (FLD_SVE_msz
, code
, 0);
1561 info
->shifter
.operator_present
= (kind
!= AARCH64_MOD_LSL
1562 || info
->shifter
.amount
!= 0);
1563 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1567 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1568 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1569 field and fields[1] specifies the offset register field. */
1571 aarch64_ext_sve_addr_zz_lsl (const aarch64_operand
*self
,
1572 aarch64_opnd_info
*info
, aarch64_insn code
,
1573 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1574 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1576 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_LSL
);
1579 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1580 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1581 field and fields[1] specifies the offset register field. */
1583 aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand
*self
,
1584 aarch64_opnd_info
*info
, aarch64_insn code
,
1585 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1586 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1588 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_SXTW
);
1591 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1592 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1593 field and fields[1] specifies the offset register field. */
1595 aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand
*self
,
1596 aarch64_opnd_info
*info
, aarch64_insn code
,
1597 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1598 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1600 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_UXTW
);
1603 /* Finish decoding an SVE arithmetic immediate, given that INFO already
1604 has the raw field value and that the low 8 bits decode to VALUE. */
1606 decode_sve_aimm (aarch64_opnd_info
*info
, int64_t value
)
1608 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1609 info
->shifter
.amount
= 0;
1610 if (info
->imm
.value
& 0x100)
1613 /* Decode 0x100 as #0, LSL #8. */
1614 info
->shifter
.amount
= 8;
1618 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1619 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1620 info
->imm
.value
= value
;
1624 /* Decode an SVE ADD/SUB immediate. */
1626 aarch64_ext_sve_aimm (const aarch64_operand
*self
,
1627 aarch64_opnd_info
*info
, const aarch64_insn code
,
1628 const aarch64_inst
*inst
,
1629 aarch64_operand_error
*errors
)
1631 return (aarch64_ext_imm (self
, info
, code
, inst
, errors
)
1632 && decode_sve_aimm (info
, (uint8_t) info
->imm
.value
));
1635 /* Decode an SVE CPY/DUP immediate. */
1637 aarch64_ext_sve_asimm (const aarch64_operand
*self
,
1638 aarch64_opnd_info
*info
, const aarch64_insn code
,
1639 const aarch64_inst
*inst
,
1640 aarch64_operand_error
*errors
)
1642 return (aarch64_ext_imm (self
, info
, code
, inst
, errors
)
1643 && decode_sve_aimm (info
, (int8_t) info
->imm
.value
));
1646 /* Decode a single-bit immediate that selects between #0.5 and #1.0.
1647 The fields array specifies which field to use. */
1649 aarch64_ext_sve_float_half_one (const aarch64_operand
*self
,
1650 aarch64_opnd_info
*info
, aarch64_insn code
,
1651 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1652 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1654 if (extract_field (self
->fields
[0], code
, 0))
1655 info
->imm
.value
= 0x3f800000;
1657 info
->imm
.value
= 0x3f000000;
1658 info
->imm
.is_fp
= TRUE
;
1662 /* Decode a single-bit immediate that selects between #0.5 and #2.0.
1663 The fields array specifies which field to use. */
1665 aarch64_ext_sve_float_half_two (const aarch64_operand
*self
,
1666 aarch64_opnd_info
*info
, aarch64_insn code
,
1667 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1668 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1670 if (extract_field (self
->fields
[0], code
, 0))
1671 info
->imm
.value
= 0x40000000;
1673 info
->imm
.value
= 0x3f000000;
1674 info
->imm
.is_fp
= TRUE
;
1678 /* Decode a single-bit immediate that selects between #0.0 and #1.0.
1679 The fields array specifies which field to use. */
1681 aarch64_ext_sve_float_zero_one (const aarch64_operand
*self
,
1682 aarch64_opnd_info
*info
, aarch64_insn code
,
1683 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1684 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1686 if (extract_field (self
->fields
[0], code
, 0))
1687 info
->imm
.value
= 0x3f800000;
1689 info
->imm
.value
= 0x0;
1690 info
->imm
.is_fp
= TRUE
;
1694 /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
1695 array specifies which field to use for Zn. MM is encoded in the
1696 concatenation of imm5 and SVE_tszh, with imm5 being the less
1697 significant part. */
1699 aarch64_ext_sve_index (const aarch64_operand
*self
,
1700 aarch64_opnd_info
*info
, aarch64_insn code
,
1701 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1702 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1706 info
->reglane
.regno
= extract_field (self
->fields
[0], code
, 0);
1707 val
= extract_fields (code
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1708 if ((val
& 31) == 0)
1710 while ((val
& 1) == 0)
1712 info
->reglane
.index
= val
/ 2;
1716 /* Decode a logical immediate for the MOV alias of SVE DUPM. */
1718 aarch64_ext_sve_limm_mov (const aarch64_operand
*self
,
1719 aarch64_opnd_info
*info
, const aarch64_insn code
,
1720 const aarch64_inst
*inst
,
1721 aarch64_operand_error
*errors
)
1723 int esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1724 return (aarch64_ext_limm (self
, info
, code
, inst
, errors
)
1725 && aarch64_sve_dupm_mov_immediate_p (info
->imm
.value
, esize
));
1728 /* Decode Zn[MM], where Zn occupies the least-significant part of the field
1729 and where MM occupies the most-significant part. The operand-dependent
1730 value specifies the number of bits in Zn. */
1732 aarch64_ext_sve_quad_index (const aarch64_operand
*self
,
1733 aarch64_opnd_info
*info
, aarch64_insn code
,
1734 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1735 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1737 unsigned int reg_bits
= get_operand_specific_data (self
);
1738 unsigned int val
= extract_all_fields (self
, code
);
1739 info
->reglane
.regno
= val
& ((1 << reg_bits
) - 1);
1740 info
->reglane
.index
= val
>> reg_bits
;
1744 /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
1745 to use for Zn. The opcode-dependent value specifies the number
1746 of registers in the list. */
1748 aarch64_ext_sve_reglist (const aarch64_operand
*self
,
1749 aarch64_opnd_info
*info
, aarch64_insn code
,
1750 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1751 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1753 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
1754 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
1758 /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
1759 fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
1762 aarch64_ext_sve_scale (const aarch64_operand
*self
,
1763 aarch64_opnd_info
*info
, aarch64_insn code
,
1764 const aarch64_inst
*inst
, aarch64_operand_error
*errors
)
1768 if (!aarch64_ext_imm (self
, info
, code
, inst
, errors
))
1770 val
= extract_field (FLD_SVE_imm4
, code
, 0);
1771 info
->shifter
.kind
= AARCH64_MOD_MUL
;
1772 info
->shifter
.amount
= val
+ 1;
1773 info
->shifter
.operator_present
= (val
!= 0);
1774 info
->shifter
.amount_present
= (val
!= 0);
1778 /* Return the top set bit in VALUE, which is expected to be relatively
1781 get_top_bit (uint64_t value
)
1783 while ((value
& -value
) != value
)
1784 value
-= value
& -value
;
1788 /* Decode an SVE shift-left immediate. */
1790 aarch64_ext_sve_shlimm (const aarch64_operand
*self
,
1791 aarch64_opnd_info
*info
, const aarch64_insn code
,
1792 const aarch64_inst
*inst
, aarch64_operand_error
*errors
)
1794 if (!aarch64_ext_imm (self
, info
, code
, inst
, errors
)
1795 || info
->imm
.value
== 0)
1798 info
->imm
.value
-= get_top_bit (info
->imm
.value
);
1802 /* Decode an SVE shift-right immediate. */
1804 aarch64_ext_sve_shrimm (const aarch64_operand
*self
,
1805 aarch64_opnd_info
*info
, const aarch64_insn code
,
1806 const aarch64_inst
*inst
, aarch64_operand_error
*errors
)
1808 if (!aarch64_ext_imm (self
, info
, code
, inst
, errors
)
1809 || info
->imm
.value
== 0)
1812 info
->imm
.value
= get_top_bit (info
->imm
.value
) * 2 - info
->imm
.value
;
1816 /* Bitfields that are commonly used to encode certain operands' information
1817 may be partially used as part of the base opcode in some instructions.
1818 For example, the bit 1 of the field 'size' in
1819 FCVTXN <Vb><d>, <Va><n>
1820 is actually part of the base opcode, while only size<0> is available
1821 for encoding the register type. Another example is the AdvSIMD
1822 instruction ORR (register), in which the field 'size' is also used for
1823 the base opcode, leaving only the field 'Q' available to encode the
1824 vector register arrangement specifier '8B' or '16B'.
1826 This function tries to deduce the qualifier from the value of partially
1827 constrained field(s). Given the VALUE of such a field or fields, the
1828 qualifiers CANDIDATES and the MASK (indicating which bits are valid for
1829 operand encoding), the function returns the matching qualifier or
1830 AARCH64_OPND_QLF_NIL if nothing matches.
1832 N.B. CANDIDATES is a group of possible qualifiers that are valid for
1833 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
1834 may end with AARCH64_OPND_QLF_NIL. */
1836 static enum aarch64_opnd_qualifier
1837 get_qualifier_from_partial_encoding (aarch64_insn value
,
1838 const enum aarch64_opnd_qualifier
* \
1843 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value
, (int)mask
);
1844 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1846 aarch64_insn standard_value
;
1847 if (candidates
[i
] == AARCH64_OPND_QLF_NIL
)
1849 standard_value
= aarch64_get_qualifier_standard_value (candidates
[i
]);
1850 if ((standard_value
& mask
) == (value
& mask
))
1851 return candidates
[i
];
1853 return AARCH64_OPND_QLF_NIL
;
1856 /* Given a list of qualifier sequences, return all possible valid qualifiers
1857 for operand IDX in QUALIFIERS.
1858 Assume QUALIFIERS is an array whose length is large enough. */
1861 get_operand_possible_qualifiers (int idx
,
1862 const aarch64_opnd_qualifier_seq_t
*list
,
1863 enum aarch64_opnd_qualifier
*qualifiers
)
1866 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1867 if ((qualifiers
[i
] = list
[i
][idx
]) == AARCH64_OPND_QLF_NIL
)
1871 /* Decode the size Q field for e.g. SHADD.
1872 We tag one operand with the qualifer according to the code;
1873 whether the qualifier is valid for this opcode or not, it is the
1874 duty of the semantic checking. */
1877 decode_sizeq (aarch64_inst
*inst
)
1880 enum aarch64_opnd_qualifier qualifier
;
1882 aarch64_insn value
, mask
;
1883 enum aarch64_field_kind fld_sz
;
1884 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1886 if (inst
->opcode
->iclass
== asisdlse
1887 || inst
->opcode
->iclass
== asisdlsep
1888 || inst
->opcode
->iclass
== asisdlso
1889 || inst
->opcode
->iclass
== asisdlsop
)
1890 fld_sz
= FLD_vldst_size
;
1895 value
= extract_fields (code
, inst
->opcode
->mask
, 2, fld_sz
, FLD_Q
);
1896 /* Obtain the info that which bits of fields Q and size are actually
1897 available for operand encoding. Opcodes like FMAXNM and FMLA have
1898 size[1] unavailable. */
1899 mask
= extract_fields (~inst
->opcode
->mask
, 0, 2, fld_sz
, FLD_Q
);
1901 /* The index of the operand we are going to tag a qualifier and the qualifer
1902 itself are reasoned from the value of the size and Q fields and the
1903 possible valid qualifier lists. */
1904 idx
= aarch64_select_operand_for_sizeq_field_coding (inst
->opcode
);
1905 DEBUG_TRACE ("key idx: %d", idx
);
1907 /* For most related instruciton, size:Q are fully available for operand
1911 inst
->operands
[idx
].qualifier
= get_vreg_qualifier_from_value (value
);
1915 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1917 #ifdef DEBUG_AARCH64
1921 for (i
= 0; candidates
[i
] != AARCH64_OPND_QLF_NIL
1922 && i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1923 DEBUG_TRACE ("qualifier %d: %s", i
,
1924 aarch64_get_qualifier_name(candidates
[i
]));
1925 DEBUG_TRACE ("%d, %d", (int)value
, (int)mask
);
1927 #endif /* DEBUG_AARCH64 */
1929 qualifier
= get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1931 if (qualifier
== AARCH64_OPND_QLF_NIL
)
1934 inst
->operands
[idx
].qualifier
= qualifier
;
1938 /* Decode size[0]:Q, i.e. bit 22 and bit 30, for
1939 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1942 decode_asimd_fcvt (aarch64_inst
*inst
)
1944 aarch64_field field
= {0, 0};
1946 enum aarch64_opnd_qualifier qualifier
;
1948 gen_sub_field (FLD_size
, 0, 1, &field
);
1949 value
= extract_field_2 (&field
, inst
->value
, 0);
1950 qualifier
= value
== 0 ? AARCH64_OPND_QLF_V_4S
1951 : AARCH64_OPND_QLF_V_2D
;
1952 switch (inst
->opcode
->op
)
1956 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1957 inst
->operands
[1].qualifier
= qualifier
;
1961 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
1962 inst
->operands
[0].qualifier
= qualifier
;
1972 /* Decode size[0], i.e. bit 22, for
1973 e.g. FCVTXN <Vb><d>, <Va><n>. */
1976 decode_asisd_fcvtxn (aarch64_inst
*inst
)
1978 aarch64_field field
= {0, 0};
1979 gen_sub_field (FLD_size
, 0, 1, &field
);
1980 if (!extract_field_2 (&field
, inst
->value
, 0))
1982 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_S_S
;
1986 /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
1988 decode_fcvt (aarch64_inst
*inst
)
1990 enum aarch64_opnd_qualifier qualifier
;
1992 const aarch64_field field
= {15, 2};
1995 value
= extract_field_2 (&field
, inst
->value
, 0);
1998 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
1999 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
2000 case 3: qualifier
= AARCH64_OPND_QLF_S_H
; break;
2003 inst
->operands
[0].qualifier
= qualifier
;
2008 /* Do miscellaneous decodings that are not common enough to be driven by
2012 do_misc_decoding (aarch64_inst
*inst
)
2015 switch (inst
->opcode
->op
)
2018 return decode_fcvt (inst
);
2024 return decode_asimd_fcvt (inst
);
2027 return decode_asisd_fcvtxn (inst
);
2031 value
= extract_field (FLD_SVE_Pn
, inst
->value
, 0);
2032 return (value
== extract_field (FLD_SVE_Pm
, inst
->value
, 0)
2033 && value
== extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
2036 return (extract_field (FLD_SVE_Zd
, inst
->value
, 0)
2037 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
2040 /* Index must be zero. */
2041 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
2042 return value
> 0 && value
<= 16 && value
== (value
& -value
);
2045 return (extract_field (FLD_SVE_Zn
, inst
->value
, 0)
2046 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
2049 /* Index must be nonzero. */
2050 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
2051 return value
> 0 && value
!= (value
& -value
);
2054 return (extract_field (FLD_SVE_Pd
, inst
->value
, 0)
2055 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
2057 case OP_MOVZS_P_P_P
:
2059 return (extract_field (FLD_SVE_Pn
, inst
->value
, 0)
2060 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
2062 case OP_NOTS_P_P_P_Z
:
2063 case OP_NOT_P_P_P_Z
:
2064 return (extract_field (FLD_SVE_Pm
, inst
->value
, 0)
2065 == extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
2072 /* Opcodes that have fields shared by multiple operands are usually flagged
2073 with flags. In this function, we detect such flags, decode the related
2074 field(s) and store the information in one of the related operands. The
2075 'one' operand is not any operand but one of the operands that can
2076 accommadate all the information that has been decoded. */
2079 do_special_decoding (aarch64_inst
*inst
)
2083 /* Condition for truly conditional executed instructions, e.g. b.cond. */
2084 if (inst
->opcode
->flags
& F_COND
)
2086 value
= extract_field (FLD_cond2
, inst
->value
, 0);
2087 inst
->cond
= get_cond_from_value (value
);
2090 if (inst
->opcode
->flags
& F_SF
)
2092 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
2093 value
= extract_field (FLD_sf
, inst
->value
, 0);
2094 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
2095 if ((inst
->opcode
->flags
& F_N
)
2096 && extract_field (FLD_N
, inst
->value
, 0) != value
)
2100 if (inst
->opcode
->flags
& F_LSE_SZ
)
2102 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
2103 value
= extract_field (FLD_lse_sz
, inst
->value
, 0);
2104 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
2106 /* size:Q fields. */
2107 if (inst
->opcode
->flags
& F_SIZEQ
)
2108 return decode_sizeq (inst
);
2110 if (inst
->opcode
->flags
& F_FPTYPE
)
2112 idx
= select_operand_for_fptype_field_coding (inst
->opcode
);
2113 value
= extract_field (FLD_type
, inst
->value
, 0);
2116 case 0: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_S
; break;
2117 case 1: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_D
; break;
2118 case 3: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_H
; break;
2123 if (inst
->opcode
->flags
& F_SSIZE
)
2125 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
2126 of the base opcode. */
2128 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
2129 idx
= select_operand_for_scalar_size_field_coding (inst
->opcode
);
2130 value
= extract_field (FLD_size
, inst
->value
, inst
->opcode
->mask
);
2131 mask
= extract_field (FLD_size
, ~inst
->opcode
->mask
, 0);
2132 /* For most related instruciton, the 'size' field is fully available for
2133 operand encoding. */
2135 inst
->operands
[idx
].qualifier
= get_sreg_qualifier_from_value (value
);
2138 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
2140 inst
->operands
[idx
].qualifier
2141 = get_qualifier_from_partial_encoding (value
, candidates
, mask
);
2145 if (inst
->opcode
->flags
& F_T
)
2147 /* Num of consecutive '0's on the right side of imm5<3:0>. */
2150 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2151 == AARCH64_OPND_CLASS_SIMD_REG
);
2162 val
= extract_field (FLD_imm5
, inst
->value
, 0);
2163 while ((val
& 0x1) == 0 && ++num
<= 3)
2167 Q
= (unsigned) extract_field (FLD_Q
, inst
->value
, inst
->opcode
->mask
);
2168 inst
->operands
[0].qualifier
=
2169 get_vreg_qualifier_from_value ((num
<< 1) | Q
);
2172 if (inst
->opcode
->flags
& F_GPRSIZE_IN_Q
)
2174 /* Use Rt to encode in the case of e.g.
2175 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
2176 idx
= aarch64_operand_index (inst
->opcode
->operands
, AARCH64_OPND_Rt
);
2179 /* Otherwise use the result operand, which has to be a integer
2181 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2182 == AARCH64_OPND_CLASS_INT_REG
);
2185 assert (idx
== 0 || idx
== 1);
2186 value
= extract_field (FLD_Q
, inst
->value
, 0);
2187 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
2190 if (inst
->opcode
->flags
& F_LDS_SIZE
)
2192 aarch64_field field
= {0, 0};
2193 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2194 == AARCH64_OPND_CLASS_INT_REG
);
2195 gen_sub_field (FLD_opc
, 0, 1, &field
);
2196 value
= extract_field_2 (&field
, inst
->value
, 0);
2197 inst
->operands
[0].qualifier
2198 = value
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2201 /* Miscellaneous decoding; done as the last step. */
2202 if (inst
->opcode
->flags
& F_MISC
)
2203 return do_misc_decoding (inst
);
2208 /* Converters converting a real opcode instruction to its alias form. */
2210 /* ROR <Wd>, <Ws>, #<shift>
2212 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
2214 convert_extr_to_ror (aarch64_inst
*inst
)
2216 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2218 copy_operand_info (inst
, 2, 3);
2219 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2225 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
2227 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
2229 convert_shll_to_xtl (aarch64_inst
*inst
)
2231 if (inst
->operands
[2].imm
.value
== 0)
2233 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2240 UBFM <Xd>, <Xn>, #<shift>, #63.
2242 LSR <Xd>, <Xn>, #<shift>. */
2244 convert_bfm_to_sr (aarch64_inst
*inst
)
2248 imms
= inst
->operands
[3].imm
.value
;
2249 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2252 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2259 /* Convert MOV to ORR. */
2261 convert_orr_to_mov (aarch64_inst
*inst
)
2263 /* MOV <Vd>.<T>, <Vn>.<T>
2265 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
2266 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2268 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2274 /* When <imms> >= <immr>, the instruction written:
2275 SBFX <Xd>, <Xn>, #<lsb>, #<width>
2277 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
2280 convert_bfm_to_bfx (aarch64_inst
*inst
)
2284 immr
= inst
->operands
[2].imm
.value
;
2285 imms
= inst
->operands
[3].imm
.value
;
2289 inst
->operands
[2].imm
.value
= lsb
;
2290 inst
->operands
[3].imm
.value
= imms
+ 1 - lsb
;
2291 /* The two opcodes have different qualifiers for
2292 the immediate operands; reset to help the checking. */
2293 reset_operand_qualifier (inst
, 2);
2294 reset_operand_qualifier (inst
, 3);
2301 /* When <imms> < <immr>, the instruction written:
2302 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
2304 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
2307 convert_bfm_to_bfi (aarch64_inst
*inst
)
2309 int64_t immr
, imms
, val
;
2311 immr
= inst
->operands
[2].imm
.value
;
2312 imms
= inst
->operands
[3].imm
.value
;
2313 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2316 inst
->operands
[2].imm
.value
= (val
- immr
) & (val
- 1);
2317 inst
->operands
[3].imm
.value
= imms
+ 1;
2318 /* The two opcodes have different qualifiers for
2319 the immediate operands; reset to help the checking. */
2320 reset_operand_qualifier (inst
, 2);
2321 reset_operand_qualifier (inst
, 3);
2328 /* The instruction written:
2329 BFC <Xd>, #<lsb>, #<width>
2331 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
2334 convert_bfm_to_bfc (aarch64_inst
*inst
)
2336 int64_t immr
, imms
, val
;
2338 /* Should have been assured by the base opcode value. */
2339 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2341 immr
= inst
->operands
[2].imm
.value
;
2342 imms
= inst
->operands
[3].imm
.value
;
2343 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2346 /* Drop XZR from the second operand. */
2347 copy_operand_info (inst
, 1, 2);
2348 copy_operand_info (inst
, 2, 3);
2349 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2351 /* Recalculate the immediates. */
2352 inst
->operands
[1].imm
.value
= (val
- immr
) & (val
- 1);
2353 inst
->operands
[2].imm
.value
= imms
+ 1;
2355 /* The two opcodes have different qualifiers for the operands; reset to
2356 help the checking. */
2357 reset_operand_qualifier (inst
, 1);
2358 reset_operand_qualifier (inst
, 2);
2359 reset_operand_qualifier (inst
, 3);
2367 /* The instruction written:
2368 LSL <Xd>, <Xn>, #<shift>
2370 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
2373 convert_ubfm_to_lsl (aarch64_inst
*inst
)
2375 int64_t immr
= inst
->operands
[2].imm
.value
;
2376 int64_t imms
= inst
->operands
[3].imm
.value
;
2378 = inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2380 if ((immr
== 0 && imms
== val
) || immr
== imms
+ 1)
2382 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2383 inst
->operands
[2].imm
.value
= val
- imms
;
2390 /* CINC <Wd>, <Wn>, <cond>
2392 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
2393 where <cond> is not AL or NV. */
2396 convert_from_csel (aarch64_inst
*inst
)
2398 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
2399 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2401 copy_operand_info (inst
, 2, 3);
2402 inst
->operands
[2].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2403 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2409 /* CSET <Wd>, <cond>
2411 CSINC <Wd>, WZR, WZR, invert(<cond>)
2412 where <cond> is not AL or NV. */
2415 convert_csinc_to_cset (aarch64_inst
*inst
)
2417 if (inst
->operands
[1].reg
.regno
== 0x1f
2418 && inst
->operands
[2].reg
.regno
== 0x1f
2419 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2421 copy_operand_info (inst
, 1, 3);
2422 inst
->operands
[1].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2423 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2424 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2432 MOVZ <Wd>, #<imm16>, LSL #<shift>.
2434 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2435 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2436 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2437 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2438 machine-instruction mnemonic must be used. */
2441 convert_movewide_to_mov (aarch64_inst
*inst
)
2443 uint64_t value
= inst
->operands
[1].imm
.value
;
2444 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
2445 if (value
== 0 && inst
->operands
[1].shifter
.amount
!= 0)
2447 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2448 inst
->operands
[1].shifter
.kind
= AARCH64_MOD_NONE
;
2449 value
<<= inst
->operands
[1].shifter
.amount
;
2450 /* As an alias convertor, it has to be clear that the INST->OPCODE
2451 is the opcode of the real instruction. */
2452 if (inst
->opcode
->op
== OP_MOVN
)
2454 int is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2456 /* A MOVN has an immediate that could be encoded by MOVZ. */
2457 if (aarch64_wide_constant_p (value
, is32
, NULL
))
2460 inst
->operands
[1].imm
.value
= value
;
2461 inst
->operands
[1].shifter
.amount
= 0;
2467 ORR <Wd>, WZR, #<imm>.
2469 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2470 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2471 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2472 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2473 machine-instruction mnemonic must be used. */
2476 convert_movebitmask_to_mov (aarch64_inst
*inst
)
2481 /* Should have been assured by the base opcode value. */
2482 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2483 copy_operand_info (inst
, 1, 2);
2484 is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2485 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2486 value
= inst
->operands
[1].imm
.value
;
2487 /* ORR has an immediate that could be generated by a MOVZ or MOVN
2489 if (inst
->operands
[0].reg
.regno
!= 0x1f
2490 && (aarch64_wide_constant_p (value
, is32
, NULL
)
2491 || aarch64_wide_constant_p (~value
, is32
, NULL
)))
2494 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2498 /* Some alias opcodes are disassembled by being converted from their real-form.
2499 N.B. INST->OPCODE is the real opcode rather than the alias. */
2502 convert_to_alias (aarch64_inst
*inst
, const aarch64_opcode
*alias
)
2508 return convert_bfm_to_sr (inst
);
2510 return convert_ubfm_to_lsl (inst
);
2514 return convert_from_csel (inst
);
2517 return convert_csinc_to_cset (inst
);
2521 return convert_bfm_to_bfx (inst
);
2525 return convert_bfm_to_bfi (inst
);
2527 return convert_bfm_to_bfc (inst
);
2529 return convert_orr_to_mov (inst
);
2530 case OP_MOV_IMM_WIDE
:
2531 case OP_MOV_IMM_WIDEN
:
2532 return convert_movewide_to_mov (inst
);
2533 case OP_MOV_IMM_LOG
:
2534 return convert_movebitmask_to_mov (inst
);
2536 return convert_extr_to_ror (inst
);
2541 return convert_shll_to_xtl (inst
);
2548 aarch64_opcode_decode (const aarch64_opcode
*, const aarch64_insn
,
2549 aarch64_inst
*, int, aarch64_operand_error
*errors
);
2551 /* Given the instruction information in *INST, check if the instruction has
2552 any alias form that can be used to represent *INST. If the answer is yes,
2553 update *INST to be in the form of the determined alias. */
2555 /* In the opcode description table, the following flags are used in opcode
2556 entries to help establish the relations between the real and alias opcodes:
2558 F_ALIAS: opcode is an alias
2559 F_HAS_ALIAS: opcode has alias(es)
2562 F_P3: Disassembly preference priority 1-3 (the larger the
2563 higher). If nothing is specified, it is the priority
2564 0 by default, i.e. the lowest priority.
2566 Although the relation between the machine and the alias instructions are not
2567 explicitly described, it can be easily determined from the base opcode
2568 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
2569 description entries:
2571 The mask of an alias opcode must be equal to or a super-set (i.e. more
2572 constrained) of that of the aliased opcode; so is the base opcode value.
2574 if (opcode_has_alias (real) && alias_opcode_p (opcode)
2575 && (opcode->mask & real->mask) == real->mask
2576 && (real->mask & opcode->opcode) == (real->mask & real->opcode))
2577 then OPCODE is an alias of, and only of, the REAL instruction
2579 The alias relationship is forced flat-structured to keep related algorithm
2580 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
2582 During the disassembling, the decoding decision tree (in
2583 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
2584 if the decoding of such a machine instruction succeeds (and -Mno-aliases is
2585 not specified), the disassembler will check whether there is any alias
2586 instruction exists for this real instruction. If there is, the disassembler
2587 will try to disassemble the 32-bit binary again using the alias's rule, or
2588 try to convert the IR to the form of the alias. In the case of the multiple
2589 aliases, the aliases are tried one by one from the highest priority
2590 (currently the flag F_P3) to the lowest priority (no priority flag), and the
2591 first succeeds first adopted.
2593 You may ask why there is a need for the conversion of IR from one form to
2594 another in handling certain aliases. This is because on one hand it avoids
2595 adding more operand code to handle unusual encoding/decoding; on other
2596 hand, during the disassembling, the conversion is an effective approach to
2597 check the condition of an alias (as an alias may be adopted only if certain
2598 conditions are met).
2600 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
2601 aarch64_opcode_table and generated aarch64_find_alias_opcode and
2602 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
2605 determine_disassembling_preference (struct aarch64_inst
*inst
,
2606 aarch64_operand_error
*errors
)
2608 const aarch64_opcode
*opcode
;
2609 const aarch64_opcode
*alias
;
2611 opcode
= inst
->opcode
;
2613 /* This opcode does not have an alias, so use itself. */
2614 if (!opcode_has_alias (opcode
))
2617 alias
= aarch64_find_alias_opcode (opcode
);
2620 #ifdef DEBUG_AARCH64
2623 const aarch64_opcode
*tmp
= alias
;
2624 printf ("#### LIST orderd: ");
2627 printf ("%s, ", tmp
->name
);
2628 tmp
= aarch64_find_next_alias_opcode (tmp
);
2632 #endif /* DEBUG_AARCH64 */
2634 for (; alias
; alias
= aarch64_find_next_alias_opcode (alias
))
2636 DEBUG_TRACE ("try %s", alias
->name
);
2637 assert (alias_opcode_p (alias
) || opcode_has_alias (opcode
));
2639 /* An alias can be a pseudo opcode which will never be used in the
2640 disassembly, e.g. BIC logical immediate is such a pseudo opcode
2642 if (pseudo_opcode_p (alias
))
2644 DEBUG_TRACE ("skip pseudo %s", alias
->name
);
2648 if ((inst
->value
& alias
->mask
) != alias
->opcode
)
2650 DEBUG_TRACE ("skip %s as base opcode not match", alias
->name
);
2653 /* No need to do any complicated transformation on operands, if the alias
2654 opcode does not have any operand. */
2655 if (aarch64_num_of_operands (alias
) == 0 && alias
->opcode
== inst
->value
)
2657 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias
->name
);
2658 aarch64_replace_opcode (inst
, alias
);
2661 if (alias
->flags
& F_CONV
)
2664 memcpy (©
, inst
, sizeof (aarch64_inst
));
2665 /* ALIAS is the preference as long as the instruction can be
2666 successfully converted to the form of ALIAS. */
2667 if (convert_to_alias (©
, alias
) == 1)
2669 aarch64_replace_opcode (©
, alias
);
2670 assert (aarch64_match_operands_constraint (©
, NULL
));
2671 DEBUG_TRACE ("succeed with %s via conversion", alias
->name
);
2672 memcpy (inst
, ©
, sizeof (aarch64_inst
));
2678 /* Directly decode the alias opcode. */
2680 memset (&temp
, '\0', sizeof (aarch64_inst
));
2681 if (aarch64_opcode_decode (alias
, inst
->value
, &temp
, 1, errors
) == 1)
2683 DEBUG_TRACE ("succeed with %s via direct decoding", alias
->name
);
2684 memcpy (inst
, &temp
, sizeof (aarch64_inst
));
2691 /* Some instructions (including all SVE ones) use the instruction class
2692 to describe how a qualifiers_list index is represented in the instruction
2693 encoding. If INST is such an instruction, decode the appropriate fields
2694 and fill in the operand qualifiers accordingly. Return true if no
2695 problems are found. */
2698 aarch64_decode_variant_using_iclass (aarch64_inst
*inst
)
2703 switch (inst
->opcode
->iclass
)
2706 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_14
);
2710 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
2713 while ((i
& 1) == 0)
2721 /* Pick the smallest applicable element size. */
2722 if ((inst
->value
& 0x20600) == 0x600)
2724 else if ((inst
->value
& 0x20400) == 0x400)
2726 else if ((inst
->value
& 0x20000) == 0)
2733 /* sve_misc instructions have only a single variant. */
2737 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_16
);
2741 variant
= extract_field (FLD_SVE_M_4
, inst
->value
, 0);
2744 case sve_shift_pred
:
2745 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_8
);
2756 case sve_shift_unpred
:
2757 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_19
);
2761 variant
= extract_field (FLD_size
, inst
->value
, 0);
2767 variant
= extract_field (FLD_size
, inst
->value
, 0);
2771 i
= extract_field (FLD_size
, inst
->value
, 0);
2778 variant
= extract_field (FLD_SVE_sz
, inst
->value
, 0);
2782 /* No mapping between instruction class and qualifiers. */
2786 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2787 inst
->operands
[i
].qualifier
= inst
->opcode
->qualifiers_list
[variant
][i
];
2790 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
2791 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
2794 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
2795 determined and used to disassemble CODE; this is done just before the
2799 aarch64_opcode_decode (const aarch64_opcode
*opcode
, const aarch64_insn code
,
2800 aarch64_inst
*inst
, int noaliases_p
,
2801 aarch64_operand_error
*errors
)
2805 DEBUG_TRACE ("enter with %s", opcode
->name
);
2807 assert (opcode
&& inst
);
2810 memset (inst
, '\0', sizeof (aarch64_inst
));
2812 /* Check the base opcode. */
2813 if ((code
& opcode
->mask
) != (opcode
->opcode
& opcode
->mask
))
2815 DEBUG_TRACE ("base opcode match FAIL");
2819 inst
->opcode
= opcode
;
2822 /* Assign operand codes and indexes. */
2823 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2825 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
)
2827 inst
->operands
[i
].type
= opcode
->operands
[i
];
2828 inst
->operands
[i
].idx
= i
;
2831 /* Call the opcode decoder indicated by flags. */
2832 if (opcode_has_special_coder (opcode
) && do_special_decoding (inst
) == 0)
2834 DEBUG_TRACE ("opcode flag-based decoder FAIL");
2838 /* Possibly use the instruction class to determine the correct
2840 if (!aarch64_decode_variant_using_iclass (inst
))
2842 DEBUG_TRACE ("iclass-based decoder FAIL");
2846 /* Call operand decoders. */
2847 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2849 const aarch64_operand
*opnd
;
2850 enum aarch64_opnd type
;
2852 type
= opcode
->operands
[i
];
2853 if (type
== AARCH64_OPND_NIL
)
2855 opnd
= &aarch64_operands
[type
];
2856 if (operand_has_extractor (opnd
)
2857 && (! aarch64_extract_operand (opnd
, &inst
->operands
[i
], code
, inst
,
2860 DEBUG_TRACE ("operand decoder FAIL at operand %d", i
);
2865 /* If the opcode has a verifier, then check it now. */
2866 if (opcode
->verifier
&& ! opcode
->verifier (opcode
, code
))
2868 DEBUG_TRACE ("operand verifier FAIL");
2872 /* Match the qualifiers. */
2873 if (aarch64_match_operands_constraint (inst
, NULL
) == 1)
2875 /* Arriving here, the CODE has been determined as a valid instruction
2876 of OPCODE and *INST has been filled with information of this OPCODE
2877 instruction. Before the return, check if the instruction has any
2878 alias and should be disassembled in the form of its alias instead.
2879 If the answer is yes, *INST will be updated. */
2881 determine_disassembling_preference (inst
, errors
);
2882 DEBUG_TRACE ("SUCCESS");
2887 DEBUG_TRACE ("constraint matching FAIL");
2894 /* This does some user-friendly fix-up to *INST. It is currently focus on
2895 the adjustment of qualifiers to help the printed instruction
2896 recognized/understood more easily. */
2899 user_friendly_fixup (aarch64_inst
*inst
)
2901 switch (inst
->opcode
->iclass
)
2904 /* TBNZ Xn|Wn, #uimm6, label
2905 Test and Branch Not Zero: conditionally jumps to label if bit number
2906 uimm6 in register Xn is not zero. The bit number implies the width of
2907 the register, which may be written and should be disassembled as Wn if
2908 uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
2910 if (inst
->operands
[1].imm
.value
< 32)
2911 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
2917 /* Decode INSN and fill in *INST the instruction information. An alias
2918 opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
2922 aarch64_decode_insn (aarch64_insn insn
, aarch64_inst
*inst
,
2923 bfd_boolean noaliases_p
,
2924 aarch64_operand_error
*errors
)
2926 const aarch64_opcode
*opcode
= aarch64_opcode_lookup (insn
);
2928 #ifdef DEBUG_AARCH64
2931 const aarch64_opcode
*tmp
= opcode
;
2933 DEBUG_TRACE ("opcode lookup:");
2936 aarch64_verbose (" %s", tmp
->name
);
2937 tmp
= aarch64_find_next_opcode (tmp
);
2940 #endif /* DEBUG_AARCH64 */
2942 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
2943 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
2944 opcode field and value, apart from the difference that one of them has an
2945 extra field as part of the opcode, but such a field is used for operand
2946 encoding in other opcode(s) ('immh' in the case of the example). */
2947 while (opcode
!= NULL
)
2949 /* But only one opcode can be decoded successfully for, as the
2950 decoding routine will check the constraint carefully. */
2951 if (aarch64_opcode_decode (opcode
, insn
, inst
, noaliases_p
, errors
) == 1)
2953 opcode
= aarch64_find_next_opcode (opcode
);
2959 /* Print operands. */
2962 print_operands (bfd_vma pc
, const aarch64_opcode
*opcode
,
2963 const aarch64_opnd_info
*opnds
, struct disassemble_info
*info
)
2965 int i
, pcrel_p
, num_printed
;
2967 for (i
= 0, num_printed
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2970 /* We regard the opcode operand info more, however we also look into
2971 the inst->operands to support the disassembling of the optional
2973 The two operand code should be the same in all cases, apart from
2974 when the operand can be optional. */
2975 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
2976 || opnds
[i
].type
== AARCH64_OPND_NIL
)
2979 /* Generate the operand string in STR. */
2980 aarch64_print_operand (str
, sizeof (str
), pc
, opcode
, opnds
, i
, &pcrel_p
,
2981 &info
->target
, ¬es
);
2983 /* Print the delimiter (taking account of omitted operand(s)). */
2985 (*info
->fprintf_func
) (info
->stream
, "%s",
2986 num_printed
++ == 0 ? "\t" : ", ");
2988 /* Print the operand. */
2990 (*info
->print_address_func
) (info
->target
, info
);
2992 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
2995 if (notes
&& !no_notes
)
2996 (*info
->fprintf_func
) (info
->stream
, "\t; note: %s", notes
);
2999 /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */
3002 remove_dot_suffix (char *name
, const aarch64_inst
*inst
)
3007 ptr
= strchr (inst
->opcode
->name
, '.');
3008 assert (ptr
&& inst
->cond
);
3009 len
= ptr
- inst
->opcode
->name
;
3011 strncpy (name
, inst
->opcode
->name
, len
);
3015 /* Print the instruction mnemonic name. */
3018 print_mnemonic_name (const aarch64_inst
*inst
, struct disassemble_info
*info
)
3020 if (inst
->opcode
->flags
& F_COND
)
3022 /* For instructions that are truly conditionally executed, e.g. b.cond,
3023 prepare the full mnemonic name with the corresponding condition
3027 remove_dot_suffix (name
, inst
);
3028 (*info
->fprintf_func
) (info
->stream
, "%s.%s", name
, inst
->cond
->names
[0]);
3031 (*info
->fprintf_func
) (info
->stream
, "%s", inst
->opcode
->name
);
3034 /* Decide whether we need to print a comment after the operands of
3035 instruction INST. */
3038 print_comment (const aarch64_inst
*inst
, struct disassemble_info
*info
)
3040 if (inst
->opcode
->flags
& F_COND
)
3043 unsigned int i
, num_conds
;
3045 remove_dot_suffix (name
, inst
);
3046 num_conds
= ARRAY_SIZE (inst
->cond
->names
);
3047 for (i
= 1; i
< num_conds
&& inst
->cond
->names
[i
]; ++i
)
3048 (*info
->fprintf_func
) (info
->stream
, "%s %s.%s",
3049 i
== 1 ? " //" : ",",
3050 name
, inst
->cond
->names
[i
]);
3054 /* Print the instruction according to *INST. */
3057 print_aarch64_insn (bfd_vma pc
, const aarch64_inst
*inst
,
3058 struct disassemble_info
*info
)
3060 print_mnemonic_name (inst
, info
);
3061 print_operands (pc
, inst
->opcode
, inst
->operands
, info
);
3062 print_comment (inst
, info
);
3065 /* Entry-point of the instruction disassembler and printer. */
3068 print_insn_aarch64_word (bfd_vma pc
,
3070 struct disassemble_info
*info
,
3071 aarch64_operand_error
*errors
)
3073 static const char *err_msg
[6] =
3076 [-ERR_UND
] = "undefined",
3077 [-ERR_UNP
] = "unpredictable",
3084 info
->insn_info_valid
= 1;
3085 info
->branch_delay_insns
= 0;
3086 info
->data_size
= 0;
3090 if (info
->flags
& INSN_HAS_RELOC
)
3091 /* If the instruction has a reloc associated with it, then
3092 the offset field in the instruction will actually be the
3093 addend for the reloc. (If we are using REL type relocs).
3094 In such cases, we can ignore the pc when computing
3095 addresses, since the addend is not currently pc-relative. */
3098 ret
= aarch64_decode_insn (word
, &inst
, no_aliases
, errors
);
3100 if (((word
>> 21) & 0x3ff) == 1)
3102 /* RESERVED for ALES. */
3103 assert (ret
!= ERR_OK
);
3112 /* Handle undefined instructions. */
3113 info
->insn_type
= dis_noninsn
;
3114 (*info
->fprintf_func
) (info
->stream
,".inst\t0x%08x ; %s",
3115 word
, err_msg
[-ret
]);
3118 user_friendly_fixup (&inst
);
3119 print_aarch64_insn (pc
, &inst
, info
);
3126 /* Disallow mapping symbols ($x, $d etc) from
3127 being displayed in symbol relative addresses. */
3130 aarch64_symbol_is_valid (asymbol
* sym
,
3131 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
3138 name
= bfd_asymbol_name (sym
);
3142 || (name
[1] != 'x' && name
[1] != 'd')
3143 || (name
[2] != '\0' && name
[2] != '.'));
3146 /* Print data bytes on INFO->STREAM. */
3149 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
3151 struct disassemble_info
*info
,
3152 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
3154 switch (info
->bytes_per_chunk
)
3157 info
->fprintf_func (info
->stream
, ".byte\t0x%02x", word
);
3160 info
->fprintf_func (info
->stream
, ".short\t0x%04x", word
);
3163 info
->fprintf_func (info
->stream
, ".word\t0x%08x", word
);
3170 /* Try to infer the code or data type from a symbol.
3171 Returns nonzero if *MAP_TYPE was set. */
3174 get_sym_code_type (struct disassemble_info
*info
, int n
,
3175 enum map_type
*map_type
)
3177 elf_symbol_type
*es
;
3181 /* If the symbol is in a different section, ignore it. */
3182 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
3185 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
3186 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
3188 /* If the symbol has function type then use that. */
3189 if (type
== STT_FUNC
)
3191 *map_type
= MAP_INSN
;
3195 /* Check for mapping symbols. */
3196 name
= bfd_asymbol_name(info
->symtab
[n
]);
3198 && (name
[1] == 'x' || name
[1] == 'd')
3199 && (name
[2] == '\0' || name
[2] == '.'))
3201 *map_type
= (name
[1] == 'x' ? MAP_INSN
: MAP_DATA
);
3208 /* Entry-point of the AArch64 disassembler. */
3211 print_insn_aarch64 (bfd_vma pc
,
3212 struct disassemble_info
*info
)
3214 bfd_byte buffer
[INSNLEN
];
3216 void (*printer
) (bfd_vma
, uint32_t, struct disassemble_info
*,
3217 aarch64_operand_error
*);
3218 bfd_boolean found
= FALSE
;
3219 unsigned int size
= 4;
3221 aarch64_operand_error errors
;
3223 if (info
->disassembler_options
)
3225 set_default_aarch64_dis_options (info
);
3227 parse_aarch64_dis_options (info
->disassembler_options
);
3229 /* To avoid repeated parsing of these options, we remove them here. */
3230 info
->disassembler_options
= NULL
;
3233 /* Aarch64 instructions are always little-endian */
3234 info
->endian_code
= BFD_ENDIAN_LITTLE
;
3236 /* First check the full symtab for a mapping symbol, even if there
3237 are no usable non-mapping symbols for this address. */
3238 if (info
->symtab_size
!= 0
3239 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
3241 enum map_type type
= MAP_INSN
;
3246 if (pc
<= last_mapping_addr
)
3247 last_mapping_sym
= -1;
3249 /* Start scanning at the start of the function, or wherever
3250 we finished last time. */
3251 n
= info
->symtab_pos
+ 1;
3252 if (n
< last_mapping_sym
)
3253 n
= last_mapping_sym
;
3255 /* Scan up to the location being disassembled. */
3256 for (; n
< info
->symtab_size
; n
++)
3258 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3261 if (get_sym_code_type (info
, n
, &type
))
3270 n
= info
->symtab_pos
;
3271 if (n
< last_mapping_sym
)
3272 n
= last_mapping_sym
;
3274 /* No mapping symbol found at this address. Look backwards
3275 for a preceeding one. */
3278 if (get_sym_code_type (info
, n
, &type
))
3287 last_mapping_sym
= last_sym
;
3290 /* Look a little bit ahead to see if we should print out
3291 less than four bytes of data. If there's a symbol,
3292 mapping or otherwise, after two bytes then don't
3294 if (last_type
== MAP_DATA
)
3296 size
= 4 - (pc
& 3);
3297 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
3299 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3302 if (addr
- pc
< size
)
3307 /* If the next symbol is after three bytes, we need to
3308 print only part of the data, so that we can use either
3311 size
= (pc
& 1) ? 1 : 2;
3315 if (last_type
== MAP_DATA
)
3317 /* size was set above. */
3318 info
->bytes_per_chunk
= size
;
3319 info
->display_endian
= info
->endian
;
3320 printer
= print_insn_data
;
3324 info
->bytes_per_chunk
= size
= INSNLEN
;
3325 info
->display_endian
= info
->endian_code
;
3326 printer
= print_insn_aarch64_word
;
3329 status
= (*info
->read_memory_func
) (pc
, buffer
, size
, info
);
3332 (*info
->memory_error_func
) (status
, pc
, info
);
3336 data
= bfd_get_bits (buffer
, size
* 8,
3337 info
->display_endian
== BFD_ENDIAN_BIG
);
3339 (*printer
) (pc
, data
, info
, &errors
);
3345 print_aarch64_disassembler_options (FILE *stream
)
3347 fprintf (stream
, _("\n\
3348 The following AARCH64 specific disassembler options are supported for use\n\
3349 with the -M switch (multiple options should be separated by commas):\n"));
3351 fprintf (stream
, _("\n\
3352 no-aliases Don't print instruction aliases.\n"));
3354 fprintf (stream
, _("\n\
3355 aliases Do print instruction aliases.\n"));
3357 fprintf (stream
, _("\n\
3358 no-notes Don't print instruction notes.\n"));
3360 fprintf (stream
, _("\n\
3361 notes Do print instruction notes.\n"));
3363 #ifdef DEBUG_AARCH64
3364 fprintf (stream
, _("\n\
3365 debug_dump Temp switch for debug trace.\n"));
3366 #endif /* DEBUG_AARCH64 */
3368 fprintf (stream
, _("\n"));