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[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers
[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c
1 /* aarch64-opc.c -- AArch64 opcode support.
2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21 #include "sysdep.h"
22 #include <assert.h>
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include <stdint.h>
26 #include <stdarg.h>
27 #include <inttypes.h>
28
29 #include "opintl.h"
30 #include "libiberty.h"
31
32 #include "aarch64-opc.h"
33
34 #ifdef DEBUG_AARCH64
35 int debug_dump = FALSE;
36 #endif /* DEBUG_AARCH64 */
37
38 /* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40 const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77 };
78
79 /* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81 const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100 };
101
102 /* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105 static inline bfd_boolean
106 vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107 {
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111 }
112
113 static inline bfd_boolean
114 fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115 {
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119 }
120
121 enum data_pattern
122 {
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128 };
129
130 static const char significant_operand_index [] =
131 {
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137 };
138
139 /* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144 static enum data_pattern
145 get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146 {
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185 }
186
187 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189 /* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195 int
196 aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197 {
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200 }
201 \f
202 const aarch64_field fields[] =
203 {
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
243 { 15, 6 }, /* imm6_2: in rmif instructions. */
244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
245 { 0, 4 }, /* imm4_2: in rmif instructions. */
246 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
247 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
248 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
249 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
250 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
251 { 5, 14 }, /* imm14: in test bit and branch instructions. */
252 { 5, 16 }, /* imm16: in exception instructions. */
253 { 0, 26 }, /* imm26: in unconditional branch instructions. */
254 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
255 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
256 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
257 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
258 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
259 { 22, 1 }, /* N: in logical (immediate) instructions. */
260 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
261 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
262 { 31, 1 }, /* sf: in integer data processing instructions. */
263 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
264 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
265 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
266 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
267 { 31, 1 }, /* b5: in the test bit and branch instructions. */
268 { 19, 5 }, /* b40: in the test bit and branch instructions. */
269 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
270 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
271 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
272 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
273 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
274 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
275 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
276 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
277 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
278 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
279 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
280 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
281 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
282 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
283 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
284 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
285 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
286 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
288 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
289 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
290 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
291 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
292 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
293 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
294 { 5, 1 }, /* SVE_i1: single-bit immediate. */
295 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
296 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
297 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
298 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
299 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
300 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
301 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
302 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
303 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
304 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
305 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
306 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
307 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
308 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
309 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
310 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
311 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
312 { 16, 4 }, /* SVE_tsz: triangular size select. */
313 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
314 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
315 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
316 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
317 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
318 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
319 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
320 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
321 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
322 };
323
324 enum aarch64_operand_class
325 aarch64_get_operand_class (enum aarch64_opnd type)
326 {
327 return aarch64_operands[type].op_class;
328 }
329
330 const char *
331 aarch64_get_operand_name (enum aarch64_opnd type)
332 {
333 return aarch64_operands[type].name;
334 }
335
336 /* Get operand description string.
337 This is usually for the diagnosis purpose. */
338 const char *
339 aarch64_get_operand_desc (enum aarch64_opnd type)
340 {
341 return aarch64_operands[type].desc;
342 }
343
344 /* Table of all conditional affixes. */
345 const aarch64_cond aarch64_conds[16] =
346 {
347 {{"eq", "none"}, 0x0},
348 {{"ne", "any"}, 0x1},
349 {{"cs", "hs", "nlast"}, 0x2},
350 {{"cc", "lo", "ul", "last"}, 0x3},
351 {{"mi", "first"}, 0x4},
352 {{"pl", "nfrst"}, 0x5},
353 {{"vs"}, 0x6},
354 {{"vc"}, 0x7},
355 {{"hi", "pmore"}, 0x8},
356 {{"ls", "plast"}, 0x9},
357 {{"ge", "tcont"}, 0xa},
358 {{"lt", "tstop"}, 0xb},
359 {{"gt"}, 0xc},
360 {{"le"}, 0xd},
361 {{"al"}, 0xe},
362 {{"nv"}, 0xf},
363 };
364
365 const aarch64_cond *
366 get_cond_from_value (aarch64_insn value)
367 {
368 assert (value < 16);
369 return &aarch64_conds[(unsigned int) value];
370 }
371
372 const aarch64_cond *
373 get_inverted_cond (const aarch64_cond *cond)
374 {
375 return &aarch64_conds[cond->value ^ 0x1];
376 }
377
378 /* Table describing the operand extension/shifting operators; indexed by
379 enum aarch64_modifier_kind.
380
381 The value column provides the most common values for encoding modifiers,
382 which enables table-driven encoding/decoding for the modifiers. */
383 const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
384 {
385 {"none", 0x0},
386 {"msl", 0x0},
387 {"ror", 0x3},
388 {"asr", 0x2},
389 {"lsr", 0x1},
390 {"lsl", 0x0},
391 {"uxtb", 0x0},
392 {"uxth", 0x1},
393 {"uxtw", 0x2},
394 {"uxtx", 0x3},
395 {"sxtb", 0x4},
396 {"sxth", 0x5},
397 {"sxtw", 0x6},
398 {"sxtx", 0x7},
399 {"mul", 0x0},
400 {"mul vl", 0x0},
401 {NULL, 0},
402 };
403
404 enum aarch64_modifier_kind
405 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
406 {
407 return desc - aarch64_operand_modifiers;
408 }
409
410 aarch64_insn
411 aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
412 {
413 return aarch64_operand_modifiers[kind].value;
414 }
415
416 enum aarch64_modifier_kind
417 aarch64_get_operand_modifier_from_value (aarch64_insn value,
418 bfd_boolean extend_p)
419 {
420 if (extend_p == TRUE)
421 return AARCH64_MOD_UXTB + value;
422 else
423 return AARCH64_MOD_LSL - value;
424 }
425
426 bfd_boolean
427 aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
428 {
429 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
430 ? TRUE : FALSE;
431 }
432
433 static inline bfd_boolean
434 aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
435 {
436 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
437 ? TRUE : FALSE;
438 }
439
440 const struct aarch64_name_value_pair aarch64_barrier_options[16] =
441 {
442 { "#0x00", 0x0 },
443 { "oshld", 0x1 },
444 { "oshst", 0x2 },
445 { "osh", 0x3 },
446 { "#0x04", 0x4 },
447 { "nshld", 0x5 },
448 { "nshst", 0x6 },
449 { "nsh", 0x7 },
450 { "#0x08", 0x8 },
451 { "ishld", 0x9 },
452 { "ishst", 0xa },
453 { "ish", 0xb },
454 { "#0x0c", 0xc },
455 { "ld", 0xd },
456 { "st", 0xe },
457 { "sy", 0xf },
458 };
459
460 /* Table describing the operands supported by the aliases of the HINT
461 instruction.
462
463 The name column is the operand that is accepted for the alias. The value
464 column is the hint number of the alias. The list of operands is terminated
465 by NULL in the name column. */
466
467 const struct aarch64_name_value_pair aarch64_hint_options[] =
468 {
469 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
470 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
471 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
472 { "c", HINT_OPD_C }, /* BTI C. */
473 { "j", HINT_OPD_J }, /* BTI J. */
474 { "jc", HINT_OPD_JC }, /* BTI JC. */
475 { NULL, HINT_OPD_NULL },
476 };
477
478 /* op -> op: load = 0 instruction = 1 store = 2
479 l -> level: 1-3
480 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
481 #define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
482 const struct aarch64_name_value_pair aarch64_prfops[32] =
483 {
484 { "pldl1keep", B(0, 1, 0) },
485 { "pldl1strm", B(0, 1, 1) },
486 { "pldl2keep", B(0, 2, 0) },
487 { "pldl2strm", B(0, 2, 1) },
488 { "pldl3keep", B(0, 3, 0) },
489 { "pldl3strm", B(0, 3, 1) },
490 { NULL, 0x06 },
491 { NULL, 0x07 },
492 { "plil1keep", B(1, 1, 0) },
493 { "plil1strm", B(1, 1, 1) },
494 { "plil2keep", B(1, 2, 0) },
495 { "plil2strm", B(1, 2, 1) },
496 { "plil3keep", B(1, 3, 0) },
497 { "plil3strm", B(1, 3, 1) },
498 { NULL, 0x0e },
499 { NULL, 0x0f },
500 { "pstl1keep", B(2, 1, 0) },
501 { "pstl1strm", B(2, 1, 1) },
502 { "pstl2keep", B(2, 2, 0) },
503 { "pstl2strm", B(2, 2, 1) },
504 { "pstl3keep", B(2, 3, 0) },
505 { "pstl3strm", B(2, 3, 1) },
506 { NULL, 0x16 },
507 { NULL, 0x17 },
508 { NULL, 0x18 },
509 { NULL, 0x19 },
510 { NULL, 0x1a },
511 { NULL, 0x1b },
512 { NULL, 0x1c },
513 { NULL, 0x1d },
514 { NULL, 0x1e },
515 { NULL, 0x1f },
516 };
517 #undef B
518 \f
519 /* Utilities on value constraint. */
520
521 static inline int
522 value_in_range_p (int64_t value, int low, int high)
523 {
524 return (value >= low && value <= high) ? 1 : 0;
525 }
526
527 /* Return true if VALUE is a multiple of ALIGN. */
528 static inline int
529 value_aligned_p (int64_t value, int align)
530 {
531 return (value % align) == 0;
532 }
533
534 /* A signed value fits in a field. */
535 static inline int
536 value_fit_signed_field_p (int64_t value, unsigned width)
537 {
538 assert (width < 32);
539 if (width < sizeof (value) * 8)
540 {
541 int64_t lim = (int64_t)1 << (width - 1);
542 if (value >= -lim && value < lim)
543 return 1;
544 }
545 return 0;
546 }
547
548 /* An unsigned value fits in a field. */
549 static inline int
550 value_fit_unsigned_field_p (int64_t value, unsigned width)
551 {
552 assert (width < 32);
553 if (width < sizeof (value) * 8)
554 {
555 int64_t lim = (int64_t)1 << width;
556 if (value >= 0 && value < lim)
557 return 1;
558 }
559 return 0;
560 }
561
562 /* Return 1 if OPERAND is SP or WSP. */
563 int
564 aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
565 {
566 return ((aarch64_get_operand_class (operand->type)
567 == AARCH64_OPND_CLASS_INT_REG)
568 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
569 && operand->reg.regno == 31);
570 }
571
572 /* Return 1 if OPERAND is XZR or WZP. */
573 int
574 aarch64_zero_register_p (const aarch64_opnd_info *operand)
575 {
576 return ((aarch64_get_operand_class (operand->type)
577 == AARCH64_OPND_CLASS_INT_REG)
578 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
579 && operand->reg.regno == 31);
580 }
581
582 /* Return true if the operand *OPERAND that has the operand code
583 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
584 qualified by the qualifier TARGET. */
585
586 static inline int
587 operand_also_qualified_p (const struct aarch64_opnd_info *operand,
588 aarch64_opnd_qualifier_t target)
589 {
590 switch (operand->qualifier)
591 {
592 case AARCH64_OPND_QLF_W:
593 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
594 return 1;
595 break;
596 case AARCH64_OPND_QLF_X:
597 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
598 return 1;
599 break;
600 case AARCH64_OPND_QLF_WSP:
601 if (target == AARCH64_OPND_QLF_W
602 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
603 return 1;
604 break;
605 case AARCH64_OPND_QLF_SP:
606 if (target == AARCH64_OPND_QLF_X
607 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
608 return 1;
609 break;
610 default:
611 break;
612 }
613
614 return 0;
615 }
616
617 /* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
618 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
619
620 Return NIL if more than one expected qualifiers are found. */
621
622 aarch64_opnd_qualifier_t
623 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
624 int idx,
625 const aarch64_opnd_qualifier_t known_qlf,
626 int known_idx)
627 {
628 int i, saved_i;
629
630 /* Special case.
631
632 When the known qualifier is NIL, we have to assume that there is only
633 one qualifier sequence in the *QSEQ_LIST and return the corresponding
634 qualifier directly. One scenario is that for instruction
635 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
636 which has only one possible valid qualifier sequence
637 NIL, S_D
638 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
639 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
640
641 Because the qualifier NIL has dual roles in the qualifier sequence:
642 it can mean no qualifier for the operand, or the qualifer sequence is
643 not in use (when all qualifiers in the sequence are NILs), we have to
644 handle this special case here. */
645 if (known_qlf == AARCH64_OPND_NIL)
646 {
647 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
648 return qseq_list[0][idx];
649 }
650
651 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
652 {
653 if (qseq_list[i][known_idx] == known_qlf)
654 {
655 if (saved_i != -1)
656 /* More than one sequences are found to have KNOWN_QLF at
657 KNOWN_IDX. */
658 return AARCH64_OPND_NIL;
659 saved_i = i;
660 }
661 }
662
663 return qseq_list[saved_i][idx];
664 }
665
666 enum operand_qualifier_kind
667 {
668 OQK_NIL,
669 OQK_OPD_VARIANT,
670 OQK_VALUE_IN_RANGE,
671 OQK_MISC,
672 };
673
674 /* Operand qualifier description. */
675 struct operand_qualifier_data
676 {
677 /* The usage of the three data fields depends on the qualifier kind. */
678 int data0;
679 int data1;
680 int data2;
681 /* Description. */
682 const char *desc;
683 /* Kind. */
684 enum operand_qualifier_kind kind;
685 };
686
687 /* Indexed by the operand qualifier enumerators. */
688 struct operand_qualifier_data aarch64_opnd_qualifiers[] =
689 {
690 {0, 0, 0, "NIL", OQK_NIL},
691
692 /* Operand variant qualifiers.
693 First 3 fields:
694 element size, number of elements and common value for encoding. */
695
696 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
697 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
698 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
699 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
700
701 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
702 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
703 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
704 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
705 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
706 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
707
708 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
709 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
710 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
711 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
712 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
713 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
714 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
715 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
716 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
717 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
718 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
719
720 {0, 0, 0, "z", OQK_OPD_VARIANT},
721 {0, 0, 0, "m", OQK_OPD_VARIANT},
722
723 /* Qualifiers constraining the value range.
724 First 3 fields:
725 Lower bound, higher bound, unused. */
726
727 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
728 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
729 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
730 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
731 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
732 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
733 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
734
735 /* Qualifiers for miscellaneous purpose.
736 First 3 fields:
737 unused, unused and unused. */
738
739 {0, 0, 0, "lsl", 0},
740 {0, 0, 0, "msl", 0},
741
742 {0, 0, 0, "retrieving", 0},
743 };
744
745 static inline bfd_boolean
746 operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
747 {
748 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
749 ? TRUE : FALSE;
750 }
751
752 static inline bfd_boolean
753 qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
754 {
755 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
756 ? TRUE : FALSE;
757 }
758
759 const char*
760 aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
761 {
762 return aarch64_opnd_qualifiers[qualifier].desc;
763 }
764
765 /* Given an operand qualifier, return the expected data element size
766 of a qualified operand. */
767 unsigned char
768 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
769 {
770 assert (operand_variant_qualifier_p (qualifier) == TRUE);
771 return aarch64_opnd_qualifiers[qualifier].data0;
772 }
773
774 unsigned char
775 aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
776 {
777 assert (operand_variant_qualifier_p (qualifier) == TRUE);
778 return aarch64_opnd_qualifiers[qualifier].data1;
779 }
780
781 aarch64_insn
782 aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
783 {
784 assert (operand_variant_qualifier_p (qualifier) == TRUE);
785 return aarch64_opnd_qualifiers[qualifier].data2;
786 }
787
788 static int
789 get_lower_bound (aarch64_opnd_qualifier_t qualifier)
790 {
791 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
792 return aarch64_opnd_qualifiers[qualifier].data0;
793 }
794
795 static int
796 get_upper_bound (aarch64_opnd_qualifier_t qualifier)
797 {
798 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
799 return aarch64_opnd_qualifiers[qualifier].data1;
800 }
801
802 #ifdef DEBUG_AARCH64
803 void
804 aarch64_verbose (const char *str, ...)
805 {
806 va_list ap;
807 va_start (ap, str);
808 printf ("#### ");
809 vprintf (str, ap);
810 printf ("\n");
811 va_end (ap);
812 }
813
814 static inline void
815 dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
816 {
817 int i;
818 printf ("#### \t");
819 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
820 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
821 printf ("\n");
822 }
823
824 static void
825 dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
826 const aarch64_opnd_qualifier_t *qualifier)
827 {
828 int i;
829 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
830
831 aarch64_verbose ("dump_match_qualifiers:");
832 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
833 curr[i] = opnd[i].qualifier;
834 dump_qualifier_sequence (curr);
835 aarch64_verbose ("against");
836 dump_qualifier_sequence (qualifier);
837 }
838 #endif /* DEBUG_AARCH64 */
839
840 /* This function checks if the given instruction INSN is a destructive
841 instruction based on the usage of the registers. It does not recognize
842 unary destructive instructions. */
843 bfd_boolean
844 aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
845 {
846 int i = 0;
847 const enum aarch64_opnd *opnds = opcode->operands;
848
849 if (opnds[0] == AARCH64_OPND_NIL)
850 return FALSE;
851
852 while (opnds[++i] != AARCH64_OPND_NIL)
853 if (opnds[i] == opnds[0])
854 return TRUE;
855
856 return FALSE;
857 }
858
859 /* TODO improve this, we can have an extra field at the runtime to
860 store the number of operands rather than calculating it every time. */
861
862 int
863 aarch64_num_of_operands (const aarch64_opcode *opcode)
864 {
865 int i = 0;
866 const enum aarch64_opnd *opnds = opcode->operands;
867 while (opnds[i++] != AARCH64_OPND_NIL)
868 ;
869 --i;
870 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
871 return i;
872 }
873
874 /* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
875 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
876
877 N.B. on the entry, it is very likely that only some operands in *INST
878 have had their qualifiers been established.
879
880 If STOP_AT is not -1, the function will only try to match
881 the qualifier sequence for operands before and including the operand
882 of index STOP_AT; and on success *RET will only be filled with the first
883 (STOP_AT+1) qualifiers.
884
885 A couple examples of the matching algorithm:
886
887 X,W,NIL should match
888 X,W,NIL
889
890 NIL,NIL should match
891 X ,NIL
892
893 Apart from serving the main encoding routine, this can also be called
894 during or after the operand decoding. */
895
896 int
897 aarch64_find_best_match (const aarch64_inst *inst,
898 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
899 int stop_at, aarch64_opnd_qualifier_t *ret)
900 {
901 int found = 0;
902 int i, num_opnds;
903 const aarch64_opnd_qualifier_t *qualifiers;
904
905 num_opnds = aarch64_num_of_operands (inst->opcode);
906 if (num_opnds == 0)
907 {
908 DEBUG_TRACE ("SUCCEED: no operand");
909 return 1;
910 }
911
912 if (stop_at < 0 || stop_at >= num_opnds)
913 stop_at = num_opnds - 1;
914
915 /* For each pattern. */
916 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
917 {
918 int j;
919 qualifiers = *qualifiers_list;
920
921 /* Start as positive. */
922 found = 1;
923
924 DEBUG_TRACE ("%d", i);
925 #ifdef DEBUG_AARCH64
926 if (debug_dump)
927 dump_match_qualifiers (inst->operands, qualifiers);
928 #endif
929
930 /* Most opcodes has much fewer patterns in the list.
931 First NIL qualifier indicates the end in the list. */
932 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
933 {
934 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
935 if (i)
936 found = 0;
937 break;
938 }
939
940 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
941 {
942 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
943 {
944 /* Either the operand does not have qualifier, or the qualifier
945 for the operand needs to be deduced from the qualifier
946 sequence.
947 In the latter case, any constraint checking related with
948 the obtained qualifier should be done later in
949 operand_general_constraint_met_p. */
950 continue;
951 }
952 else if (*qualifiers != inst->operands[j].qualifier)
953 {
954 /* Unless the target qualifier can also qualify the operand
955 (which has already had a non-nil qualifier), non-equal
956 qualifiers are generally un-matched. */
957 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
958 continue;
959 else
960 {
961 found = 0;
962 break;
963 }
964 }
965 else
966 continue; /* Equal qualifiers are certainly matched. */
967 }
968
969 /* Qualifiers established. */
970 if (found == 1)
971 break;
972 }
973
974 if (found == 1)
975 {
976 /* Fill the result in *RET. */
977 int j;
978 qualifiers = *qualifiers_list;
979
980 DEBUG_TRACE ("complete qualifiers using list %d", i);
981 #ifdef DEBUG_AARCH64
982 if (debug_dump)
983 dump_qualifier_sequence (qualifiers);
984 #endif
985
986 for (j = 0; j <= stop_at; ++j, ++qualifiers)
987 ret[j] = *qualifiers;
988 for (; j < AARCH64_MAX_OPND_NUM; ++j)
989 ret[j] = AARCH64_OPND_QLF_NIL;
990
991 DEBUG_TRACE ("SUCCESS");
992 return 1;
993 }
994
995 DEBUG_TRACE ("FAIL");
996 return 0;
997 }
998
999 /* Operand qualifier matching and resolving.
1000
1001 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1002 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1003
1004 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1005 succeeds. */
1006
1007 static int
1008 match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1009 {
1010 int i, nops;
1011 aarch64_opnd_qualifier_seq_t qualifiers;
1012
1013 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1014 qualifiers))
1015 {
1016 DEBUG_TRACE ("matching FAIL");
1017 return 0;
1018 }
1019
1020 if (inst->opcode->flags & F_STRICT)
1021 {
1022 /* Require an exact qualifier match, even for NIL qualifiers. */
1023 nops = aarch64_num_of_operands (inst->opcode);
1024 for (i = 0; i < nops; ++i)
1025 if (inst->operands[i].qualifier != qualifiers[i])
1026 return FALSE;
1027 }
1028
1029 /* Update the qualifiers. */
1030 if (update_p == TRUE)
1031 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1032 {
1033 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1034 break;
1035 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1036 "update %s with %s for operand %d",
1037 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1038 aarch64_get_qualifier_name (qualifiers[i]), i);
1039 inst->operands[i].qualifier = qualifiers[i];
1040 }
1041
1042 DEBUG_TRACE ("matching SUCCESS");
1043 return 1;
1044 }
1045
1046 /* Return TRUE if VALUE is a wide constant that can be moved into a general
1047 register by MOVZ.
1048
1049 IS32 indicates whether value is a 32-bit immediate or not.
1050 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1051 amount will be returned in *SHIFT_AMOUNT. */
1052
1053 bfd_boolean
1054 aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1055 {
1056 int amount;
1057
1058 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1059
1060 if (is32)
1061 {
1062 /* Allow all zeros or all ones in top 32-bits, so that
1063 32-bit constant expressions like ~0x80000000 are
1064 permitted. */
1065 uint64_t ext = value;
1066 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1067 /* Immediate out of range. */
1068 return FALSE;
1069 value &= (int64_t) 0xffffffff;
1070 }
1071
1072 /* first, try movz then movn */
1073 amount = -1;
1074 if ((value & ((int64_t) 0xffff << 0)) == value)
1075 amount = 0;
1076 else if ((value & ((int64_t) 0xffff << 16)) == value)
1077 amount = 16;
1078 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1079 amount = 32;
1080 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1081 amount = 48;
1082
1083 if (amount == -1)
1084 {
1085 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1086 return FALSE;
1087 }
1088
1089 if (shift_amount != NULL)
1090 *shift_amount = amount;
1091
1092 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1093
1094 return TRUE;
1095 }
1096
1097 /* Build the accepted values for immediate logical SIMD instructions.
1098
1099 The standard encodings of the immediate value are:
1100 N imms immr SIMD size R S
1101 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1102 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1103 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1104 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1105 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1106 0 11110s 00000r 2 UInt(r) UInt(s)
1107 where all-ones value of S is reserved.
1108
1109 Let's call E the SIMD size.
1110
1111 The immediate value is: S+1 bits '1' rotated to the right by R.
1112
1113 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1114 (remember S != E - 1). */
1115
1116 #define TOTAL_IMM_NB 5334
1117
1118 typedef struct
1119 {
1120 uint64_t imm;
1121 aarch64_insn encoding;
1122 } simd_imm_encoding;
1123
1124 static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1125
1126 static int
1127 simd_imm_encoding_cmp(const void *i1, const void *i2)
1128 {
1129 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1130 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1131
1132 if (imm1->imm < imm2->imm)
1133 return -1;
1134 if (imm1->imm > imm2->imm)
1135 return +1;
1136 return 0;
1137 }
1138
1139 /* immediate bitfield standard encoding
1140 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1141 1 ssssss rrrrrr 64 rrrrrr ssssss
1142 0 0sssss 0rrrrr 32 rrrrr sssss
1143 0 10ssss 00rrrr 16 rrrr ssss
1144 0 110sss 000rrr 8 rrr sss
1145 0 1110ss 0000rr 4 rr ss
1146 0 11110s 00000r 2 r s */
1147 static inline int
1148 encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1149 {
1150 return (is64 << 12) | (r << 6) | s;
1151 }
1152
1153 static void
1154 build_immediate_table (void)
1155 {
1156 uint32_t log_e, e, s, r, s_mask;
1157 uint64_t mask, imm;
1158 int nb_imms;
1159 int is64;
1160
1161 nb_imms = 0;
1162 for (log_e = 1; log_e <= 6; log_e++)
1163 {
1164 /* Get element size. */
1165 e = 1u << log_e;
1166 if (log_e == 6)
1167 {
1168 is64 = 1;
1169 mask = 0xffffffffffffffffull;
1170 s_mask = 0;
1171 }
1172 else
1173 {
1174 is64 = 0;
1175 mask = (1ull << e) - 1;
1176 /* log_e s_mask
1177 1 ((1 << 4) - 1) << 2 = 111100
1178 2 ((1 << 3) - 1) << 3 = 111000
1179 3 ((1 << 2) - 1) << 4 = 110000
1180 4 ((1 << 1) - 1) << 5 = 100000
1181 5 ((1 << 0) - 1) << 6 = 000000 */
1182 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1183 }
1184 for (s = 0; s < e - 1; s++)
1185 for (r = 0; r < e; r++)
1186 {
1187 /* s+1 consecutive bits to 1 (s < 63) */
1188 imm = (1ull << (s + 1)) - 1;
1189 /* rotate right by r */
1190 if (r != 0)
1191 imm = (imm >> r) | ((imm << (e - r)) & mask);
1192 /* replicate the constant depending on SIMD size */
1193 switch (log_e)
1194 {
1195 case 1: imm = (imm << 2) | imm;
1196 /* Fall through. */
1197 case 2: imm = (imm << 4) | imm;
1198 /* Fall through. */
1199 case 3: imm = (imm << 8) | imm;
1200 /* Fall through. */
1201 case 4: imm = (imm << 16) | imm;
1202 /* Fall through. */
1203 case 5: imm = (imm << 32) | imm;
1204 /* Fall through. */
1205 case 6: break;
1206 default: abort ();
1207 }
1208 simd_immediates[nb_imms].imm = imm;
1209 simd_immediates[nb_imms].encoding =
1210 encode_immediate_bitfield(is64, s | s_mask, r);
1211 nb_imms++;
1212 }
1213 }
1214 assert (nb_imms == TOTAL_IMM_NB);
1215 qsort(simd_immediates, nb_imms,
1216 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1217 }
1218
1219 /* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1220 be accepted by logical (immediate) instructions
1221 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1222
1223 ESIZE is the number of bytes in the decoded immediate value.
1224 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1225 VALUE will be returned in *ENCODING. */
1226
1227 bfd_boolean
1228 aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
1229 {
1230 simd_imm_encoding imm_enc;
1231 const simd_imm_encoding *imm_encoding;
1232 static bfd_boolean initialized = FALSE;
1233 uint64_t upper;
1234 int i;
1235
1236 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1237 value, esize);
1238
1239 if (!initialized)
1240 {
1241 build_immediate_table ();
1242 initialized = TRUE;
1243 }
1244
1245 /* Allow all zeros or all ones in top bits, so that
1246 constant expressions like ~1 are permitted. */
1247 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1248 if ((value & ~upper) != value && (value | upper) != value)
1249 return FALSE;
1250
1251 /* Replicate to a full 64-bit value. */
1252 value &= ~upper;
1253 for (i = esize * 8; i < 64; i *= 2)
1254 value |= (value << i);
1255
1256 imm_enc.imm = value;
1257 imm_encoding = (const simd_imm_encoding *)
1258 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1259 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1260 if (imm_encoding == NULL)
1261 {
1262 DEBUG_TRACE ("exit with FALSE");
1263 return FALSE;
1264 }
1265 if (encoding != NULL)
1266 *encoding = imm_encoding->encoding;
1267 DEBUG_TRACE ("exit with TRUE");
1268 return TRUE;
1269 }
1270
1271 /* If 64-bit immediate IMM is in the format of
1272 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1273 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1274 of value "abcdefgh". Otherwise return -1. */
1275 int
1276 aarch64_shrink_expanded_imm8 (uint64_t imm)
1277 {
1278 int i, ret;
1279 uint32_t byte;
1280
1281 ret = 0;
1282 for (i = 0; i < 8; i++)
1283 {
1284 byte = (imm >> (8 * i)) & 0xff;
1285 if (byte == 0xff)
1286 ret |= 1 << i;
1287 else if (byte != 0x00)
1288 return -1;
1289 }
1290 return ret;
1291 }
1292
1293 /* Utility inline functions for operand_general_constraint_met_p. */
1294
1295 static inline void
1296 set_error (aarch64_operand_error *mismatch_detail,
1297 enum aarch64_operand_error_kind kind, int idx,
1298 const char* error)
1299 {
1300 if (mismatch_detail == NULL)
1301 return;
1302 mismatch_detail->kind = kind;
1303 mismatch_detail->index = idx;
1304 mismatch_detail->error = error;
1305 }
1306
1307 static inline void
1308 set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1309 const char* error)
1310 {
1311 if (mismatch_detail == NULL)
1312 return;
1313 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1314 }
1315
1316 static inline void
1317 set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1318 int idx, int lower_bound, int upper_bound,
1319 const char* error)
1320 {
1321 if (mismatch_detail == NULL)
1322 return;
1323 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1324 mismatch_detail->data[0] = lower_bound;
1325 mismatch_detail->data[1] = upper_bound;
1326 }
1327
1328 static inline void
1329 set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1330 int idx, int lower_bound, int upper_bound)
1331 {
1332 if (mismatch_detail == NULL)
1333 return;
1334 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1335 _("immediate value"));
1336 }
1337
1338 static inline void
1339 set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1340 int idx, int lower_bound, int upper_bound)
1341 {
1342 if (mismatch_detail == NULL)
1343 return;
1344 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1345 _("immediate offset"));
1346 }
1347
1348 static inline void
1349 set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1350 int idx, int lower_bound, int upper_bound)
1351 {
1352 if (mismatch_detail == NULL)
1353 return;
1354 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1355 _("register number"));
1356 }
1357
1358 static inline void
1359 set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1360 int idx, int lower_bound, int upper_bound)
1361 {
1362 if (mismatch_detail == NULL)
1363 return;
1364 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1365 _("register element index"));
1366 }
1367
1368 static inline void
1369 set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1370 int idx, int lower_bound, int upper_bound)
1371 {
1372 if (mismatch_detail == NULL)
1373 return;
1374 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1375 _("shift amount"));
1376 }
1377
1378 /* Report that the MUL modifier in operand IDX should be in the range
1379 [LOWER_BOUND, UPPER_BOUND]. */
1380 static inline void
1381 set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1382 int idx, int lower_bound, int upper_bound)
1383 {
1384 if (mismatch_detail == NULL)
1385 return;
1386 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1387 _("multiplier"));
1388 }
1389
1390 static inline void
1391 set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1392 int alignment)
1393 {
1394 if (mismatch_detail == NULL)
1395 return;
1396 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1397 mismatch_detail->data[0] = alignment;
1398 }
1399
1400 static inline void
1401 set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1402 int expected_num)
1403 {
1404 if (mismatch_detail == NULL)
1405 return;
1406 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1407 mismatch_detail->data[0] = expected_num;
1408 }
1409
1410 static inline void
1411 set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1412 const char* error)
1413 {
1414 if (mismatch_detail == NULL)
1415 return;
1416 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1417 }
1418
1419 /* General constraint checking based on operand code.
1420
1421 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1422 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1423
1424 This function has to be called after the qualifiers for all operands
1425 have been resolved.
1426
1427 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1428 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1429 of error message during the disassembling where error message is not
1430 wanted. We avoid the dynamic construction of strings of error messages
1431 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1432 use a combination of error code, static string and some integer data to
1433 represent an error. */
1434
1435 static int
1436 operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1437 enum aarch64_opnd type,
1438 const aarch64_opcode *opcode,
1439 aarch64_operand_error *mismatch_detail)
1440 {
1441 unsigned num, modifiers, shift;
1442 unsigned char size;
1443 int64_t imm, min_value, max_value;
1444 uint64_t uvalue, mask;
1445 const aarch64_opnd_info *opnd = opnds + idx;
1446 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1447
1448 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1449
1450 switch (aarch64_operands[type].op_class)
1451 {
1452 case AARCH64_OPND_CLASS_INT_REG:
1453 /* Check pair reg constraints for cas* instructions. */
1454 if (type == AARCH64_OPND_PAIRREG)
1455 {
1456 assert (idx == 1 || idx == 3);
1457 if (opnds[idx - 1].reg.regno % 2 != 0)
1458 {
1459 set_syntax_error (mismatch_detail, idx - 1,
1460 _("reg pair must start from even reg"));
1461 return 0;
1462 }
1463 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1464 {
1465 set_syntax_error (mismatch_detail, idx,
1466 _("reg pair must be contiguous"));
1467 return 0;
1468 }
1469 break;
1470 }
1471
1472 /* <Xt> may be optional in some IC and TLBI instructions. */
1473 if (type == AARCH64_OPND_Rt_SYS)
1474 {
1475 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1476 == AARCH64_OPND_CLASS_SYSTEM));
1477 if (opnds[1].present
1478 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1479 {
1480 set_other_error (mismatch_detail, idx, _("extraneous register"));
1481 return 0;
1482 }
1483 if (!opnds[1].present
1484 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1485 {
1486 set_other_error (mismatch_detail, idx, _("missing register"));
1487 return 0;
1488 }
1489 }
1490 switch (qualifier)
1491 {
1492 case AARCH64_OPND_QLF_WSP:
1493 case AARCH64_OPND_QLF_SP:
1494 if (!aarch64_stack_pointer_p (opnd))
1495 {
1496 set_other_error (mismatch_detail, idx,
1497 _("stack pointer register expected"));
1498 return 0;
1499 }
1500 break;
1501 default:
1502 break;
1503 }
1504 break;
1505
1506 case AARCH64_OPND_CLASS_SVE_REG:
1507 switch (type)
1508 {
1509 case AARCH64_OPND_SVE_Zm3_INDEX:
1510 case AARCH64_OPND_SVE_Zm3_22_INDEX:
1511 case AARCH64_OPND_SVE_Zm4_INDEX:
1512 size = get_operand_fields_width (get_operand_from_code (type));
1513 shift = get_operand_specific_data (&aarch64_operands[type]);
1514 mask = (1 << shift) - 1;
1515 if (opnd->reg.regno > mask)
1516 {
1517 assert (mask == 7 || mask == 15);
1518 set_other_error (mismatch_detail, idx,
1519 mask == 15
1520 ? _("z0-z15 expected")
1521 : _("z0-z7 expected"));
1522 return 0;
1523 }
1524 mask = (1 << (size - shift)) - 1;
1525 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1526 {
1527 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1528 return 0;
1529 }
1530 break;
1531
1532 case AARCH64_OPND_SVE_Zn_INDEX:
1533 size = aarch64_get_qualifier_esize (opnd->qualifier);
1534 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1535 {
1536 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1537 0, 64 / size - 1);
1538 return 0;
1539 }
1540 break;
1541
1542 case AARCH64_OPND_SVE_ZnxN:
1543 case AARCH64_OPND_SVE_ZtxN:
1544 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1545 {
1546 set_other_error (mismatch_detail, idx,
1547 _("invalid register list"));
1548 return 0;
1549 }
1550 break;
1551
1552 default:
1553 break;
1554 }
1555 break;
1556
1557 case AARCH64_OPND_CLASS_PRED_REG:
1558 if (opnd->reg.regno >= 8
1559 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1560 {
1561 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1562 return 0;
1563 }
1564 break;
1565
1566 case AARCH64_OPND_CLASS_COND:
1567 if (type == AARCH64_OPND_COND1
1568 && (opnds[idx].cond->value & 0xe) == 0xe)
1569 {
1570 /* Not allow AL or NV. */
1571 set_syntax_error (mismatch_detail, idx, NULL);
1572 }
1573 break;
1574
1575 case AARCH64_OPND_CLASS_ADDRESS:
1576 /* Check writeback. */
1577 switch (opcode->iclass)
1578 {
1579 case ldst_pos:
1580 case ldst_unscaled:
1581 case ldstnapair_offs:
1582 case ldstpair_off:
1583 case ldst_unpriv:
1584 if (opnd->addr.writeback == 1)
1585 {
1586 set_syntax_error (mismatch_detail, idx,
1587 _("unexpected address writeback"));
1588 return 0;
1589 }
1590 break;
1591 case ldst_imm10:
1592 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1593 {
1594 set_syntax_error (mismatch_detail, idx,
1595 _("unexpected address writeback"));
1596 return 0;
1597 }
1598 break;
1599 case ldst_imm9:
1600 case ldstpair_indexed:
1601 case asisdlsep:
1602 case asisdlsop:
1603 if (opnd->addr.writeback == 0)
1604 {
1605 set_syntax_error (mismatch_detail, idx,
1606 _("address writeback expected"));
1607 return 0;
1608 }
1609 break;
1610 default:
1611 assert (opnd->addr.writeback == 0);
1612 break;
1613 }
1614 switch (type)
1615 {
1616 case AARCH64_OPND_ADDR_SIMM7:
1617 /* Scaled signed 7 bits immediate offset. */
1618 /* Get the size of the data element that is accessed, which may be
1619 different from that of the source register size,
1620 e.g. in strb/ldrb. */
1621 size = aarch64_get_qualifier_esize (opnd->qualifier);
1622 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1623 {
1624 set_offset_out_of_range_error (mismatch_detail, idx,
1625 -64 * size, 63 * size);
1626 return 0;
1627 }
1628 if (!value_aligned_p (opnd->addr.offset.imm, size))
1629 {
1630 set_unaligned_error (mismatch_detail, idx, size);
1631 return 0;
1632 }
1633 break;
1634 case AARCH64_OPND_ADDR_OFFSET:
1635 case AARCH64_OPND_ADDR_SIMM9:
1636 /* Unscaled signed 9 bits immediate offset. */
1637 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1638 {
1639 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1640 return 0;
1641 }
1642 break;
1643
1644 case AARCH64_OPND_ADDR_SIMM9_2:
1645 /* Unscaled signed 9 bits immediate offset, which has to be negative
1646 or unaligned. */
1647 size = aarch64_get_qualifier_esize (qualifier);
1648 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1649 && !value_aligned_p (opnd->addr.offset.imm, size))
1650 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1651 return 1;
1652 set_other_error (mismatch_detail, idx,
1653 _("negative or unaligned offset expected"));
1654 return 0;
1655
1656 case AARCH64_OPND_ADDR_SIMM10:
1657 /* Scaled signed 10 bits immediate offset. */
1658 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1659 {
1660 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1661 return 0;
1662 }
1663 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1664 {
1665 set_unaligned_error (mismatch_detail, idx, 8);
1666 return 0;
1667 }
1668 break;
1669
1670 case AARCH64_OPND_SIMD_ADDR_POST:
1671 /* AdvSIMD load/store multiple structures, post-index. */
1672 assert (idx == 1);
1673 if (opnd->addr.offset.is_reg)
1674 {
1675 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1676 return 1;
1677 else
1678 {
1679 set_other_error (mismatch_detail, idx,
1680 _("invalid register offset"));
1681 return 0;
1682 }
1683 }
1684 else
1685 {
1686 const aarch64_opnd_info *prev = &opnds[idx-1];
1687 unsigned num_bytes; /* total number of bytes transferred. */
1688 /* The opcode dependent area stores the number of elements in
1689 each structure to be loaded/stored. */
1690 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1691 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1692 /* Special handling of loading single structure to all lane. */
1693 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1694 * aarch64_get_qualifier_esize (prev->qualifier);
1695 else
1696 num_bytes = prev->reglist.num_regs
1697 * aarch64_get_qualifier_esize (prev->qualifier)
1698 * aarch64_get_qualifier_nelem (prev->qualifier);
1699 if ((int) num_bytes != opnd->addr.offset.imm)
1700 {
1701 set_other_error (mismatch_detail, idx,
1702 _("invalid post-increment amount"));
1703 return 0;
1704 }
1705 }
1706 break;
1707
1708 case AARCH64_OPND_ADDR_REGOFF:
1709 /* Get the size of the data element that is accessed, which may be
1710 different from that of the source register size,
1711 e.g. in strb/ldrb. */
1712 size = aarch64_get_qualifier_esize (opnd->qualifier);
1713 /* It is either no shift or shift by the binary logarithm of SIZE. */
1714 if (opnd->shifter.amount != 0
1715 && opnd->shifter.amount != (int)get_logsz (size))
1716 {
1717 set_other_error (mismatch_detail, idx,
1718 _("invalid shift amount"));
1719 return 0;
1720 }
1721 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1722 operators. */
1723 switch (opnd->shifter.kind)
1724 {
1725 case AARCH64_MOD_UXTW:
1726 case AARCH64_MOD_LSL:
1727 case AARCH64_MOD_SXTW:
1728 case AARCH64_MOD_SXTX: break;
1729 default:
1730 set_other_error (mismatch_detail, idx,
1731 _("invalid extend/shift operator"));
1732 return 0;
1733 }
1734 break;
1735
1736 case AARCH64_OPND_ADDR_UIMM12:
1737 imm = opnd->addr.offset.imm;
1738 /* Get the size of the data element that is accessed, which may be
1739 different from that of the source register size,
1740 e.g. in strb/ldrb. */
1741 size = aarch64_get_qualifier_esize (qualifier);
1742 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1743 {
1744 set_offset_out_of_range_error (mismatch_detail, idx,
1745 0, 4095 * size);
1746 return 0;
1747 }
1748 if (!value_aligned_p (opnd->addr.offset.imm, size))
1749 {
1750 set_unaligned_error (mismatch_detail, idx, size);
1751 return 0;
1752 }
1753 break;
1754
1755 case AARCH64_OPND_ADDR_PCREL14:
1756 case AARCH64_OPND_ADDR_PCREL19:
1757 case AARCH64_OPND_ADDR_PCREL21:
1758 case AARCH64_OPND_ADDR_PCREL26:
1759 imm = opnd->imm.value;
1760 if (operand_need_shift_by_two (get_operand_from_code (type)))
1761 {
1762 /* The offset value in a PC-relative branch instruction is alway
1763 4-byte aligned and is encoded without the lowest 2 bits. */
1764 if (!value_aligned_p (imm, 4))
1765 {
1766 set_unaligned_error (mismatch_detail, idx, 4);
1767 return 0;
1768 }
1769 /* Right shift by 2 so that we can carry out the following check
1770 canonically. */
1771 imm >>= 2;
1772 }
1773 size = get_operand_fields_width (get_operand_from_code (type));
1774 if (!value_fit_signed_field_p (imm, size))
1775 {
1776 set_other_error (mismatch_detail, idx,
1777 _("immediate out of range"));
1778 return 0;
1779 }
1780 break;
1781
1782 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1783 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1784 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1785 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1786 min_value = -8;
1787 max_value = 7;
1788 sve_imm_offset_vl:
1789 assert (!opnd->addr.offset.is_reg);
1790 assert (opnd->addr.preind);
1791 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1792 min_value *= num;
1793 max_value *= num;
1794 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1795 || (opnd->shifter.operator_present
1796 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1797 {
1798 set_other_error (mismatch_detail, idx,
1799 _("invalid addressing mode"));
1800 return 0;
1801 }
1802 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1803 {
1804 set_offset_out_of_range_error (mismatch_detail, idx,
1805 min_value, max_value);
1806 return 0;
1807 }
1808 if (!value_aligned_p (opnd->addr.offset.imm, num))
1809 {
1810 set_unaligned_error (mismatch_detail, idx, num);
1811 return 0;
1812 }
1813 break;
1814
1815 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1816 min_value = -32;
1817 max_value = 31;
1818 goto sve_imm_offset_vl;
1819
1820 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1821 min_value = -256;
1822 max_value = 255;
1823 goto sve_imm_offset_vl;
1824
1825 case AARCH64_OPND_SVE_ADDR_RI_U6:
1826 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1827 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1828 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1829 min_value = 0;
1830 max_value = 63;
1831 sve_imm_offset:
1832 assert (!opnd->addr.offset.is_reg);
1833 assert (opnd->addr.preind);
1834 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1835 min_value *= num;
1836 max_value *= num;
1837 if (opnd->shifter.operator_present
1838 || opnd->shifter.amount_present)
1839 {
1840 set_other_error (mismatch_detail, idx,
1841 _("invalid addressing mode"));
1842 return 0;
1843 }
1844 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1845 {
1846 set_offset_out_of_range_error (mismatch_detail, idx,
1847 min_value, max_value);
1848 return 0;
1849 }
1850 if (!value_aligned_p (opnd->addr.offset.imm, num))
1851 {
1852 set_unaligned_error (mismatch_detail, idx, num);
1853 return 0;
1854 }
1855 break;
1856
1857 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
1858 min_value = -8;
1859 max_value = 7;
1860 goto sve_imm_offset;
1861
1862 case AARCH64_OPND_SVE_ADDR_R:
1863 case AARCH64_OPND_SVE_ADDR_RR:
1864 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1865 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1866 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1867 case AARCH64_OPND_SVE_ADDR_RX:
1868 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1869 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1870 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1871 case AARCH64_OPND_SVE_ADDR_RZ:
1872 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1873 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1874 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1875 modifiers = 1 << AARCH64_MOD_LSL;
1876 sve_rr_operand:
1877 assert (opnd->addr.offset.is_reg);
1878 assert (opnd->addr.preind);
1879 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1880 && opnd->addr.offset.regno == 31)
1881 {
1882 set_other_error (mismatch_detail, idx,
1883 _("index register xzr is not allowed"));
1884 return 0;
1885 }
1886 if (((1 << opnd->shifter.kind) & modifiers) == 0
1887 || (opnd->shifter.amount
1888 != get_operand_specific_data (&aarch64_operands[type])))
1889 {
1890 set_other_error (mismatch_detail, idx,
1891 _("invalid addressing mode"));
1892 return 0;
1893 }
1894 break;
1895
1896 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1897 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1898 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1899 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1900 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1901 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1902 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1903 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1904 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1905 goto sve_rr_operand;
1906
1907 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1908 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1909 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1910 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1911 min_value = 0;
1912 max_value = 31;
1913 goto sve_imm_offset;
1914
1915 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1916 modifiers = 1 << AARCH64_MOD_LSL;
1917 sve_zz_operand:
1918 assert (opnd->addr.offset.is_reg);
1919 assert (opnd->addr.preind);
1920 if (((1 << opnd->shifter.kind) & modifiers) == 0
1921 || opnd->shifter.amount < 0
1922 || opnd->shifter.amount > 3)
1923 {
1924 set_other_error (mismatch_detail, idx,
1925 _("invalid addressing mode"));
1926 return 0;
1927 }
1928 break;
1929
1930 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1931 modifiers = (1 << AARCH64_MOD_SXTW);
1932 goto sve_zz_operand;
1933
1934 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1935 modifiers = 1 << AARCH64_MOD_UXTW;
1936 goto sve_zz_operand;
1937
1938 default:
1939 break;
1940 }
1941 break;
1942
1943 case AARCH64_OPND_CLASS_SIMD_REGLIST:
1944 if (type == AARCH64_OPND_LEt)
1945 {
1946 /* Get the upper bound for the element index. */
1947 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
1948 if (!value_in_range_p (opnd->reglist.index, 0, num))
1949 {
1950 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
1951 return 0;
1952 }
1953 }
1954 /* The opcode dependent area stores the number of elements in
1955 each structure to be loaded/stored. */
1956 num = get_opcode_dependent_value (opcode);
1957 switch (type)
1958 {
1959 case AARCH64_OPND_LVt:
1960 assert (num >= 1 && num <= 4);
1961 /* Unless LD1/ST1, the number of registers should be equal to that
1962 of the structure elements. */
1963 if (num != 1 && opnd->reglist.num_regs != num)
1964 {
1965 set_reg_list_error (mismatch_detail, idx, num);
1966 return 0;
1967 }
1968 break;
1969 case AARCH64_OPND_LVt_AL:
1970 case AARCH64_OPND_LEt:
1971 assert (num >= 1 && num <= 4);
1972 /* The number of registers should be equal to that of the structure
1973 elements. */
1974 if (opnd->reglist.num_regs != num)
1975 {
1976 set_reg_list_error (mismatch_detail, idx, num);
1977 return 0;
1978 }
1979 break;
1980 default:
1981 break;
1982 }
1983 break;
1984
1985 case AARCH64_OPND_CLASS_IMMEDIATE:
1986 /* Constraint check on immediate operand. */
1987 imm = opnd->imm.value;
1988 /* E.g. imm_0_31 constrains value to be 0..31. */
1989 if (qualifier_value_in_range_constraint_p (qualifier)
1990 && !value_in_range_p (imm, get_lower_bound (qualifier),
1991 get_upper_bound (qualifier)))
1992 {
1993 set_imm_out_of_range_error (mismatch_detail, idx,
1994 get_lower_bound (qualifier),
1995 get_upper_bound (qualifier));
1996 return 0;
1997 }
1998
1999 switch (type)
2000 {
2001 case AARCH64_OPND_AIMM:
2002 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2003 {
2004 set_other_error (mismatch_detail, idx,
2005 _("invalid shift operator"));
2006 return 0;
2007 }
2008 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2009 {
2010 set_other_error (mismatch_detail, idx,
2011 _("shift amount must be 0 or 12"));
2012 return 0;
2013 }
2014 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2015 {
2016 set_other_error (mismatch_detail, idx,
2017 _("immediate out of range"));
2018 return 0;
2019 }
2020 break;
2021
2022 case AARCH64_OPND_HALF:
2023 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2024 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2025 {
2026 set_other_error (mismatch_detail, idx,
2027 _("invalid shift operator"));
2028 return 0;
2029 }
2030 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2031 if (!value_aligned_p (opnd->shifter.amount, 16))
2032 {
2033 set_other_error (mismatch_detail, idx,
2034 _("shift amount must be a multiple of 16"));
2035 return 0;
2036 }
2037 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2038 {
2039 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2040 0, size * 8 - 16);
2041 return 0;
2042 }
2043 if (opnd->imm.value < 0)
2044 {
2045 set_other_error (mismatch_detail, idx,
2046 _("negative immediate value not allowed"));
2047 return 0;
2048 }
2049 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2050 {
2051 set_other_error (mismatch_detail, idx,
2052 _("immediate out of range"));
2053 return 0;
2054 }
2055 break;
2056
2057 case AARCH64_OPND_IMM_MOV:
2058 {
2059 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2060 imm = opnd->imm.value;
2061 assert (idx == 1);
2062 switch (opcode->op)
2063 {
2064 case OP_MOV_IMM_WIDEN:
2065 imm = ~imm;
2066 /* Fall through. */
2067 case OP_MOV_IMM_WIDE:
2068 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
2069 {
2070 set_other_error (mismatch_detail, idx,
2071 _("immediate out of range"));
2072 return 0;
2073 }
2074 break;
2075 case OP_MOV_IMM_LOG:
2076 if (!aarch64_logical_immediate_p (imm, esize, NULL))
2077 {
2078 set_other_error (mismatch_detail, idx,
2079 _("immediate out of range"));
2080 return 0;
2081 }
2082 break;
2083 default:
2084 assert (0);
2085 return 0;
2086 }
2087 }
2088 break;
2089
2090 case AARCH64_OPND_NZCV:
2091 case AARCH64_OPND_CCMP_IMM:
2092 case AARCH64_OPND_EXCEPTION:
2093 case AARCH64_OPND_UIMM4:
2094 case AARCH64_OPND_UIMM7:
2095 case AARCH64_OPND_UIMM3_OP1:
2096 case AARCH64_OPND_UIMM3_OP2:
2097 case AARCH64_OPND_SVE_UIMM3:
2098 case AARCH64_OPND_SVE_UIMM7:
2099 case AARCH64_OPND_SVE_UIMM8:
2100 case AARCH64_OPND_SVE_UIMM8_53:
2101 size = get_operand_fields_width (get_operand_from_code (type));
2102 assert (size < 32);
2103 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2104 {
2105 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2106 (1 << size) - 1);
2107 return 0;
2108 }
2109 break;
2110
2111 case AARCH64_OPND_SIMM5:
2112 case AARCH64_OPND_SVE_SIMM5:
2113 case AARCH64_OPND_SVE_SIMM5B:
2114 case AARCH64_OPND_SVE_SIMM6:
2115 case AARCH64_OPND_SVE_SIMM8:
2116 size = get_operand_fields_width (get_operand_from_code (type));
2117 assert (size < 32);
2118 if (!value_fit_signed_field_p (opnd->imm.value, size))
2119 {
2120 set_imm_out_of_range_error (mismatch_detail, idx,
2121 -(1 << (size - 1)),
2122 (1 << (size - 1)) - 1);
2123 return 0;
2124 }
2125 break;
2126
2127 case AARCH64_OPND_WIDTH:
2128 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
2129 && opnds[0].type == AARCH64_OPND_Rd);
2130 size = get_upper_bound (qualifier);
2131 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2132 /* lsb+width <= reg.size */
2133 {
2134 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2135 size - opnds[idx-1].imm.value);
2136 return 0;
2137 }
2138 break;
2139
2140 case AARCH64_OPND_LIMM:
2141 case AARCH64_OPND_SVE_LIMM:
2142 {
2143 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2144 uint64_t uimm = opnd->imm.value;
2145 if (opcode->op == OP_BIC)
2146 uimm = ~uimm;
2147 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2148 {
2149 set_other_error (mismatch_detail, idx,
2150 _("immediate out of range"));
2151 return 0;
2152 }
2153 }
2154 break;
2155
2156 case AARCH64_OPND_IMM0:
2157 case AARCH64_OPND_FPIMM0:
2158 if (opnd->imm.value != 0)
2159 {
2160 set_other_error (mismatch_detail, idx,
2161 _("immediate zero expected"));
2162 return 0;
2163 }
2164 break;
2165
2166 case AARCH64_OPND_IMM_ROT1:
2167 case AARCH64_OPND_IMM_ROT2:
2168 case AARCH64_OPND_SVE_IMM_ROT2:
2169 if (opnd->imm.value != 0
2170 && opnd->imm.value != 90
2171 && opnd->imm.value != 180
2172 && opnd->imm.value != 270)
2173 {
2174 set_other_error (mismatch_detail, idx,
2175 _("rotate expected to be 0, 90, 180 or 270"));
2176 return 0;
2177 }
2178 break;
2179
2180 case AARCH64_OPND_IMM_ROT3:
2181 case AARCH64_OPND_SVE_IMM_ROT1:
2182 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2183 {
2184 set_other_error (mismatch_detail, idx,
2185 _("rotate expected to be 90 or 270"));
2186 return 0;
2187 }
2188 break;
2189
2190 case AARCH64_OPND_SHLL_IMM:
2191 assert (idx == 2);
2192 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2193 if (opnd->imm.value != size)
2194 {
2195 set_other_error (mismatch_detail, idx,
2196 _("invalid shift amount"));
2197 return 0;
2198 }
2199 break;
2200
2201 case AARCH64_OPND_IMM_VLSL:
2202 size = aarch64_get_qualifier_esize (qualifier);
2203 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2204 {
2205 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2206 size * 8 - 1);
2207 return 0;
2208 }
2209 break;
2210
2211 case AARCH64_OPND_IMM_VLSR:
2212 size = aarch64_get_qualifier_esize (qualifier);
2213 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2214 {
2215 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2216 return 0;
2217 }
2218 break;
2219
2220 case AARCH64_OPND_SIMD_IMM:
2221 case AARCH64_OPND_SIMD_IMM_SFT:
2222 /* Qualifier check. */
2223 switch (qualifier)
2224 {
2225 case AARCH64_OPND_QLF_LSL:
2226 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2227 {
2228 set_other_error (mismatch_detail, idx,
2229 _("invalid shift operator"));
2230 return 0;
2231 }
2232 break;
2233 case AARCH64_OPND_QLF_MSL:
2234 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2235 {
2236 set_other_error (mismatch_detail, idx,
2237 _("invalid shift operator"));
2238 return 0;
2239 }
2240 break;
2241 case AARCH64_OPND_QLF_NIL:
2242 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2243 {
2244 set_other_error (mismatch_detail, idx,
2245 _("shift is not permitted"));
2246 return 0;
2247 }
2248 break;
2249 default:
2250 assert (0);
2251 return 0;
2252 }
2253 /* Is the immediate valid? */
2254 assert (idx == 1);
2255 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2256 {
2257 /* uimm8 or simm8 */
2258 if (!value_in_range_p (opnd->imm.value, -128, 255))
2259 {
2260 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
2261 return 0;
2262 }
2263 }
2264 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2265 {
2266 /* uimm64 is not
2267 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2268 ffffffffgggggggghhhhhhhh'. */
2269 set_other_error (mismatch_detail, idx,
2270 _("invalid value for immediate"));
2271 return 0;
2272 }
2273 /* Is the shift amount valid? */
2274 switch (opnd->shifter.kind)
2275 {
2276 case AARCH64_MOD_LSL:
2277 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2278 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
2279 {
2280 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2281 (size - 1) * 8);
2282 return 0;
2283 }
2284 if (!value_aligned_p (opnd->shifter.amount, 8))
2285 {
2286 set_unaligned_error (mismatch_detail, idx, 8);
2287 return 0;
2288 }
2289 break;
2290 case AARCH64_MOD_MSL:
2291 /* Only 8 and 16 are valid shift amount. */
2292 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2293 {
2294 set_other_error (mismatch_detail, idx,
2295 _("shift amount must be 0 or 16"));
2296 return 0;
2297 }
2298 break;
2299 default:
2300 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2301 {
2302 set_other_error (mismatch_detail, idx,
2303 _("invalid shift operator"));
2304 return 0;
2305 }
2306 break;
2307 }
2308 break;
2309
2310 case AARCH64_OPND_FPIMM:
2311 case AARCH64_OPND_SIMD_FPIMM:
2312 case AARCH64_OPND_SVE_FPIMM8:
2313 if (opnd->imm.is_fp == 0)
2314 {
2315 set_other_error (mismatch_detail, idx,
2316 _("floating-point immediate expected"));
2317 return 0;
2318 }
2319 /* The value is expected to be an 8-bit floating-point constant with
2320 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2321 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2322 instruction). */
2323 if (!value_in_range_p (opnd->imm.value, 0, 255))
2324 {
2325 set_other_error (mismatch_detail, idx,
2326 _("immediate out of range"));
2327 return 0;
2328 }
2329 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2330 {
2331 set_other_error (mismatch_detail, idx,
2332 _("invalid shift operator"));
2333 return 0;
2334 }
2335 break;
2336
2337 case AARCH64_OPND_SVE_AIMM:
2338 min_value = 0;
2339 sve_aimm:
2340 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2341 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2342 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2343 uvalue = opnd->imm.value;
2344 shift = opnd->shifter.amount;
2345 if (size == 1)
2346 {
2347 if (shift != 0)
2348 {
2349 set_other_error (mismatch_detail, idx,
2350 _("no shift amount allowed for"
2351 " 8-bit constants"));
2352 return 0;
2353 }
2354 }
2355 else
2356 {
2357 if (shift != 0 && shift != 8)
2358 {
2359 set_other_error (mismatch_detail, idx,
2360 _("shift amount must be 0 or 8"));
2361 return 0;
2362 }
2363 if (shift == 0 && (uvalue & 0xff) == 0)
2364 {
2365 shift = 8;
2366 uvalue = (int64_t) uvalue / 256;
2367 }
2368 }
2369 mask >>= shift;
2370 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2371 {
2372 set_other_error (mismatch_detail, idx,
2373 _("immediate too big for element size"));
2374 return 0;
2375 }
2376 uvalue = (uvalue - min_value) & mask;
2377 if (uvalue > 0xff)
2378 {
2379 set_other_error (mismatch_detail, idx,
2380 _("invalid arithmetic immediate"));
2381 return 0;
2382 }
2383 break;
2384
2385 case AARCH64_OPND_SVE_ASIMM:
2386 min_value = -128;
2387 goto sve_aimm;
2388
2389 case AARCH64_OPND_SVE_I1_HALF_ONE:
2390 assert (opnd->imm.is_fp);
2391 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2392 {
2393 set_other_error (mismatch_detail, idx,
2394 _("floating-point value must be 0.5 or 1.0"));
2395 return 0;
2396 }
2397 break;
2398
2399 case AARCH64_OPND_SVE_I1_HALF_TWO:
2400 assert (opnd->imm.is_fp);
2401 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2402 {
2403 set_other_error (mismatch_detail, idx,
2404 _("floating-point value must be 0.5 or 2.0"));
2405 return 0;
2406 }
2407 break;
2408
2409 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2410 assert (opnd->imm.is_fp);
2411 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2412 {
2413 set_other_error (mismatch_detail, idx,
2414 _("floating-point value must be 0.0 or 1.0"));
2415 return 0;
2416 }
2417 break;
2418
2419 case AARCH64_OPND_SVE_INV_LIMM:
2420 {
2421 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2422 uint64_t uimm = ~opnd->imm.value;
2423 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2424 {
2425 set_other_error (mismatch_detail, idx,
2426 _("immediate out of range"));
2427 return 0;
2428 }
2429 }
2430 break;
2431
2432 case AARCH64_OPND_SVE_LIMM_MOV:
2433 {
2434 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2435 uint64_t uimm = opnd->imm.value;
2436 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2437 {
2438 set_other_error (mismatch_detail, idx,
2439 _("immediate out of range"));
2440 return 0;
2441 }
2442 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2443 {
2444 set_other_error (mismatch_detail, idx,
2445 _("invalid replicated MOV immediate"));
2446 return 0;
2447 }
2448 }
2449 break;
2450
2451 case AARCH64_OPND_SVE_PATTERN_SCALED:
2452 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2453 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2454 {
2455 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2456 return 0;
2457 }
2458 break;
2459
2460 case AARCH64_OPND_SVE_SHLIMM_PRED:
2461 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
2462 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2463 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2464 {
2465 set_imm_out_of_range_error (mismatch_detail, idx,
2466 0, 8 * size - 1);
2467 return 0;
2468 }
2469 break;
2470
2471 case AARCH64_OPND_SVE_SHRIMM_PRED:
2472 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
2473 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2474 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2475 {
2476 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
2477 return 0;
2478 }
2479 break;
2480
2481 default:
2482 break;
2483 }
2484 break;
2485
2486 case AARCH64_OPND_CLASS_SYSTEM:
2487 switch (type)
2488 {
2489 case AARCH64_OPND_PSTATEFIELD:
2490 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
2491 /* MSR UAO, #uimm4
2492 MSR PAN, #uimm4
2493 The immediate must be #0 or #1. */
2494 if ((opnd->pstatefield == 0x03 /* UAO. */
2495 || opnd->pstatefield == 0x04 /* PAN. */
2496 || opnd->pstatefield == 0x1a) /* DIT. */
2497 && opnds[1].imm.value > 1)
2498 {
2499 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2500 return 0;
2501 }
2502 /* MSR SPSel, #uimm4
2503 Uses uimm4 as a control value to select the stack pointer: if
2504 bit 0 is set it selects the current exception level's stack
2505 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2506 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2507 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2508 {
2509 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2510 return 0;
2511 }
2512 break;
2513 default:
2514 break;
2515 }
2516 break;
2517
2518 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2519 /* Get the upper bound for the element index. */
2520 if (opcode->op == OP_FCMLA_ELEM)
2521 /* FCMLA index range depends on the vector size of other operands
2522 and is halfed because complex numbers take two elements. */
2523 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2524 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2525 else
2526 num = 16;
2527 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
2528
2529 /* Index out-of-range. */
2530 if (!value_in_range_p (opnd->reglane.index, 0, num))
2531 {
2532 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2533 return 0;
2534 }
2535 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2536 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2537 number is encoded in "size:M:Rm":
2538 size <Vm>
2539 00 RESERVED
2540 01 0:Rm
2541 10 M:Rm
2542 11 RESERVED */
2543 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
2544 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2545 {
2546 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2547 return 0;
2548 }
2549 break;
2550
2551 case AARCH64_OPND_CLASS_MODIFIED_REG:
2552 assert (idx == 1 || idx == 2);
2553 switch (type)
2554 {
2555 case AARCH64_OPND_Rm_EXT:
2556 if (!aarch64_extend_operator_p (opnd->shifter.kind)
2557 && opnd->shifter.kind != AARCH64_MOD_LSL)
2558 {
2559 set_other_error (mismatch_detail, idx,
2560 _("extend operator expected"));
2561 return 0;
2562 }
2563 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2564 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2565 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2566 case. */
2567 if (!aarch64_stack_pointer_p (opnds + 0)
2568 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2569 {
2570 if (!opnd->shifter.operator_present)
2571 {
2572 set_other_error (mismatch_detail, idx,
2573 _("missing extend operator"));
2574 return 0;
2575 }
2576 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2577 {
2578 set_other_error (mismatch_detail, idx,
2579 _("'LSL' operator not allowed"));
2580 return 0;
2581 }
2582 }
2583 assert (opnd->shifter.operator_present /* Default to LSL. */
2584 || opnd->shifter.kind == AARCH64_MOD_LSL);
2585 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2586 {
2587 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2588 return 0;
2589 }
2590 /* In the 64-bit form, the final register operand is written as Wm
2591 for all but the (possibly omitted) UXTX/LSL and SXTX
2592 operators.
2593 N.B. GAS allows X register to be used with any operator as a
2594 programming convenience. */
2595 if (qualifier == AARCH64_OPND_QLF_X
2596 && opnd->shifter.kind != AARCH64_MOD_LSL
2597 && opnd->shifter.kind != AARCH64_MOD_UXTX
2598 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2599 {
2600 set_other_error (mismatch_detail, idx, _("W register expected"));
2601 return 0;
2602 }
2603 break;
2604
2605 case AARCH64_OPND_Rm_SFT:
2606 /* ROR is not available to the shifted register operand in
2607 arithmetic instructions. */
2608 if (!aarch64_shift_operator_p (opnd->shifter.kind))
2609 {
2610 set_other_error (mismatch_detail, idx,
2611 _("shift operator expected"));
2612 return 0;
2613 }
2614 if (opnd->shifter.kind == AARCH64_MOD_ROR
2615 && opcode->iclass != log_shift)
2616 {
2617 set_other_error (mismatch_detail, idx,
2618 _("'ROR' operator not allowed"));
2619 return 0;
2620 }
2621 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2622 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2623 {
2624 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2625 return 0;
2626 }
2627 break;
2628
2629 default:
2630 break;
2631 }
2632 break;
2633
2634 default:
2635 break;
2636 }
2637
2638 return 1;
2639 }
2640
2641 /* Main entrypoint for the operand constraint checking.
2642
2643 Return 1 if operands of *INST meet the constraint applied by the operand
2644 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2645 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2646 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2647 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2648 error kind when it is notified that an instruction does not pass the check).
2649
2650 Un-determined operand qualifiers may get established during the process. */
2651
2652 int
2653 aarch64_match_operands_constraint (aarch64_inst *inst,
2654 aarch64_operand_error *mismatch_detail)
2655 {
2656 int i;
2657
2658 DEBUG_TRACE ("enter");
2659
2660 /* Check for cases where a source register needs to be the same as the
2661 destination register. Do this before matching qualifiers since if
2662 an instruction has both invalid tying and invalid qualifiers,
2663 the error about qualifiers would suggest several alternative
2664 instructions that also have invalid tying. */
2665 i = inst->opcode->tied_operand;
2666 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2667 {
2668 if (mismatch_detail)
2669 {
2670 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2671 mismatch_detail->index = i;
2672 mismatch_detail->error = NULL;
2673 }
2674 return 0;
2675 }
2676
2677 /* Match operands' qualifier.
2678 *INST has already had qualifier establish for some, if not all, of
2679 its operands; we need to find out whether these established
2680 qualifiers match one of the qualifier sequence in
2681 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2682 with the corresponding qualifier in such a sequence.
2683 Only basic operand constraint checking is done here; the more thorough
2684 constraint checking will carried out by operand_general_constraint_met_p,
2685 which has be to called after this in order to get all of the operands'
2686 qualifiers established. */
2687 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2688 {
2689 DEBUG_TRACE ("FAIL on operand qualifier matching");
2690 if (mismatch_detail)
2691 {
2692 /* Return an error type to indicate that it is the qualifier
2693 matching failure; we don't care about which operand as there
2694 are enough information in the opcode table to reproduce it. */
2695 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2696 mismatch_detail->index = -1;
2697 mismatch_detail->error = NULL;
2698 }
2699 return 0;
2700 }
2701
2702 /* Match operands' constraint. */
2703 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2704 {
2705 enum aarch64_opnd type = inst->opcode->operands[i];
2706 if (type == AARCH64_OPND_NIL)
2707 break;
2708 if (inst->operands[i].skip)
2709 {
2710 DEBUG_TRACE ("skip the incomplete operand %d", i);
2711 continue;
2712 }
2713 if (operand_general_constraint_met_p (inst->operands, i, type,
2714 inst->opcode, mismatch_detail) == 0)
2715 {
2716 DEBUG_TRACE ("FAIL on operand %d", i);
2717 return 0;
2718 }
2719 }
2720
2721 DEBUG_TRACE ("PASS");
2722
2723 return 1;
2724 }
2725
2726 /* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2727 Also updates the TYPE of each INST->OPERANDS with the corresponding
2728 value of OPCODE->OPERANDS.
2729
2730 Note that some operand qualifiers may need to be manually cleared by
2731 the caller before it further calls the aarch64_opcode_encode; by
2732 doing this, it helps the qualifier matching facilities work
2733 properly. */
2734
2735 const aarch64_opcode*
2736 aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2737 {
2738 int i;
2739 const aarch64_opcode *old = inst->opcode;
2740
2741 inst->opcode = opcode;
2742
2743 /* Update the operand types. */
2744 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2745 {
2746 inst->operands[i].type = opcode->operands[i];
2747 if (opcode->operands[i] == AARCH64_OPND_NIL)
2748 break;
2749 }
2750
2751 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2752
2753 return old;
2754 }
2755
2756 int
2757 aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2758 {
2759 int i;
2760 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2761 if (operands[i] == operand)
2762 return i;
2763 else if (operands[i] == AARCH64_OPND_NIL)
2764 break;
2765 return -1;
2766 }
2767 \f
2768 /* R0...R30, followed by FOR31. */
2769 #define BANK(R, FOR31) \
2770 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2771 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2772 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2773 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
2774 /* [0][0] 32-bit integer regs with sp Wn
2775 [0][1] 64-bit integer regs with sp Xn sf=1
2776 [1][0] 32-bit integer regs with #0 Wn
2777 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2778 static const char *int_reg[2][2][32] = {
2779 #define R32(X) "w" #X
2780 #define R64(X) "x" #X
2781 { BANK (R32, "wsp"), BANK (R64, "sp") },
2782 { BANK (R32, "wzr"), BANK (R64, "xzr") }
2783 #undef R64
2784 #undef R32
2785 };
2786
2787 /* Names of the SVE vector registers, first with .S suffixes,
2788 then with .D suffixes. */
2789
2790 static const char *sve_reg[2][32] = {
2791 #define ZS(X) "z" #X ".s"
2792 #define ZD(X) "z" #X ".d"
2793 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2794 #undef ZD
2795 #undef ZS
2796 };
2797 #undef BANK
2798
2799 /* Return the integer register name.
2800 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2801
2802 static inline const char *
2803 get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2804 {
2805 const int has_zr = sp_reg_p ? 0 : 1;
2806 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2807 return int_reg[has_zr][is_64][regno];
2808 }
2809
2810 /* Like get_int_reg_name, but IS_64 is always 1. */
2811
2812 static inline const char *
2813 get_64bit_int_reg_name (int regno, int sp_reg_p)
2814 {
2815 const int has_zr = sp_reg_p ? 0 : 1;
2816 return int_reg[has_zr][1][regno];
2817 }
2818
2819 /* Get the name of the integer offset register in OPND, using the shift type
2820 to decide whether it's a word or doubleword. */
2821
2822 static inline const char *
2823 get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2824 {
2825 switch (opnd->shifter.kind)
2826 {
2827 case AARCH64_MOD_UXTW:
2828 case AARCH64_MOD_SXTW:
2829 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2830
2831 case AARCH64_MOD_LSL:
2832 case AARCH64_MOD_SXTX:
2833 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2834
2835 default:
2836 abort ();
2837 }
2838 }
2839
2840 /* Get the name of the SVE vector offset register in OPND, using the operand
2841 qualifier to decide whether the suffix should be .S or .D. */
2842
2843 static inline const char *
2844 get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2845 {
2846 assert (qualifier == AARCH64_OPND_QLF_S_S
2847 || qualifier == AARCH64_OPND_QLF_S_D);
2848 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2849 }
2850
2851 /* Types for expanding an encoded 8-bit value to a floating-point value. */
2852
2853 typedef union
2854 {
2855 uint64_t i;
2856 double d;
2857 } double_conv_t;
2858
2859 typedef union
2860 {
2861 uint32_t i;
2862 float f;
2863 } single_conv_t;
2864
2865 typedef union
2866 {
2867 uint32_t i;
2868 float f;
2869 } half_conv_t;
2870
2871 /* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2872 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2873 (depending on the type of the instruction). IMM8 will be expanded to a
2874 single-precision floating-point value (SIZE == 4) or a double-precision
2875 floating-point value (SIZE == 8). A half-precision floating-point value
2876 (SIZE == 2) is expanded to a single-precision floating-point value. The
2877 expanded value is returned. */
2878
2879 static uint64_t
2880 expand_fp_imm (int size, uint32_t imm8)
2881 {
2882 uint64_t imm = 0;
2883 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2884
2885 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2886 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2887 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2888 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2889 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
2890 if (size == 8)
2891 {
2892 imm = (imm8_7 << (63-32)) /* imm8<7> */
2893 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2894 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2895 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2896 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2897 imm <<= 32;
2898 }
2899 else if (size == 4 || size == 2)
2900 {
2901 imm = (imm8_7 << 31) /* imm8<7> */
2902 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2903 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2904 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2905 }
2906 else
2907 {
2908 /* An unsupported size. */
2909 assert (0);
2910 }
2911
2912 return imm;
2913 }
2914
2915 /* Produce the string representation of the register list operand *OPND
2916 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2917 the register name that comes before the register number, such as "v". */
2918 static void
2919 print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
2920 const char *prefix)
2921 {
2922 const int num_regs = opnd->reglist.num_regs;
2923 const int first_reg = opnd->reglist.first_regno;
2924 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
2925 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
2926 char tb[8]; /* Temporary buffer. */
2927
2928 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
2929 assert (num_regs >= 1 && num_regs <= 4);
2930
2931 /* Prepare the index if any. */
2932 if (opnd->reglist.has_index)
2933 /* PR 21096: The %100 is to silence a warning about possible truncation. */
2934 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
2935 else
2936 tb[0] = '\0';
2937
2938 /* The hyphenated form is preferred for disassembly if there are
2939 more than two registers in the list, and the register numbers
2940 are monotonically increasing in increments of one. */
2941 if (num_regs > 2 && last_reg > first_reg)
2942 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
2943 prefix, last_reg, qlf_name, tb);
2944 else
2945 {
2946 const int reg0 = first_reg;
2947 const int reg1 = (first_reg + 1) & 0x1f;
2948 const int reg2 = (first_reg + 2) & 0x1f;
2949 const int reg3 = (first_reg + 3) & 0x1f;
2950
2951 switch (num_regs)
2952 {
2953 case 1:
2954 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
2955 break;
2956 case 2:
2957 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
2958 prefix, reg1, qlf_name, tb);
2959 break;
2960 case 3:
2961 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
2962 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
2963 prefix, reg2, qlf_name, tb);
2964 break;
2965 case 4:
2966 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
2967 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
2968 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
2969 break;
2970 }
2971 }
2972 }
2973
2974 /* Print the register+immediate address in OPND to BUF, which has SIZE
2975 characters. BASE is the name of the base register. */
2976
2977 static void
2978 print_immediate_offset_address (char *buf, size_t size,
2979 const aarch64_opnd_info *opnd,
2980 const char *base)
2981 {
2982 if (opnd->addr.writeback)
2983 {
2984 if (opnd->addr.preind)
2985 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
2986 else
2987 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
2988 }
2989 else
2990 {
2991 if (opnd->shifter.operator_present)
2992 {
2993 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
2994 snprintf (buf, size, "[%s, #%d, mul vl]",
2995 base, opnd->addr.offset.imm);
2996 }
2997 else if (opnd->addr.offset.imm)
2998 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
2999 else
3000 snprintf (buf, size, "[%s]", base);
3001 }
3002 }
3003
3004 /* Produce the string representation of the register offset address operand
3005 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3006 the names of the base and offset registers. */
3007 static void
3008 print_register_offset_address (char *buf, size_t size,
3009 const aarch64_opnd_info *opnd,
3010 const char *base, const char *offset)
3011 {
3012 char tb[16]; /* Temporary buffer. */
3013 bfd_boolean print_extend_p = TRUE;
3014 bfd_boolean print_amount_p = TRUE;
3015 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3016
3017 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3018 || !opnd->shifter.amount_present))
3019 {
3020 /* Not print the shift/extend amount when the amount is zero and
3021 when it is not the special case of 8-bit load/store instruction. */
3022 print_amount_p = FALSE;
3023 /* Likewise, no need to print the shift operator LSL in such a
3024 situation. */
3025 if (opnd->shifter.kind == AARCH64_MOD_LSL)
3026 print_extend_p = FALSE;
3027 }
3028
3029 /* Prepare for the extend/shift. */
3030 if (print_extend_p)
3031 {
3032 if (print_amount_p)
3033 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
3034 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3035 (opnd->shifter.amount % 100));
3036 else
3037 snprintf (tb, sizeof (tb), ", %s", shift_name);
3038 }
3039 else
3040 tb[0] = '\0';
3041
3042 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
3043 }
3044
3045 /* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3046 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3047 PC, PCREL_P and ADDRESS are used to pass in and return information about
3048 the PC-relative address calculation, where the PC value is passed in
3049 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3050 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3051 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3052
3053 The function serves both the disassembler and the assembler diagnostics
3054 issuer, which is the reason why it lives in this file. */
3055
3056 void
3057 aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3058 const aarch64_opcode *opcode,
3059 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
3060 bfd_vma *address, char** notes)
3061 {
3062 unsigned int i, num_conds;
3063 const char *name = NULL;
3064 const aarch64_opnd_info *opnd = opnds + idx;
3065 enum aarch64_modifier_kind kind;
3066 uint64_t addr, enum_value;
3067
3068 buf[0] = '\0';
3069 if (pcrel_p)
3070 *pcrel_p = 0;
3071
3072 switch (opnd->type)
3073 {
3074 case AARCH64_OPND_Rd:
3075 case AARCH64_OPND_Rn:
3076 case AARCH64_OPND_Rm:
3077 case AARCH64_OPND_Rt:
3078 case AARCH64_OPND_Rt2:
3079 case AARCH64_OPND_Rs:
3080 case AARCH64_OPND_Ra:
3081 case AARCH64_OPND_Rt_SYS:
3082 case AARCH64_OPND_PAIRREG:
3083 case AARCH64_OPND_SVE_Rm:
3084 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
3085 the <ic_op>, therefore we use opnd->present to override the
3086 generic optional-ness information. */
3087 if (opnd->type == AARCH64_OPND_Rt_SYS)
3088 {
3089 if (!opnd->present)
3090 break;
3091 }
3092 /* Omit the operand, e.g. RET. */
3093 else if (optional_operand_p (opcode, idx)
3094 && (opnd->reg.regno
3095 == get_optional_operand_default_value (opcode)))
3096 break;
3097 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3098 || opnd->qualifier == AARCH64_OPND_QLF_X);
3099 snprintf (buf, size, "%s",
3100 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3101 break;
3102
3103 case AARCH64_OPND_Rd_SP:
3104 case AARCH64_OPND_Rn_SP:
3105 case AARCH64_OPND_SVE_Rn_SP:
3106 case AARCH64_OPND_Rm_SP:
3107 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3108 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3109 || opnd->qualifier == AARCH64_OPND_QLF_X
3110 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3111 snprintf (buf, size, "%s",
3112 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3113 break;
3114
3115 case AARCH64_OPND_Rm_EXT:
3116 kind = opnd->shifter.kind;
3117 assert (idx == 1 || idx == 2);
3118 if ((aarch64_stack_pointer_p (opnds)
3119 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3120 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3121 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3122 && kind == AARCH64_MOD_UXTW)
3123 || (opnd->qualifier == AARCH64_OPND_QLF_X
3124 && kind == AARCH64_MOD_UXTX)))
3125 {
3126 /* 'LSL' is the preferred form in this case. */
3127 kind = AARCH64_MOD_LSL;
3128 if (opnd->shifter.amount == 0)
3129 {
3130 /* Shifter omitted. */
3131 snprintf (buf, size, "%s",
3132 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3133 break;
3134 }
3135 }
3136 if (opnd->shifter.amount)
3137 snprintf (buf, size, "%s, %s #%" PRIi64,
3138 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3139 aarch64_operand_modifiers[kind].name,
3140 opnd->shifter.amount);
3141 else
3142 snprintf (buf, size, "%s, %s",
3143 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3144 aarch64_operand_modifiers[kind].name);
3145 break;
3146
3147 case AARCH64_OPND_Rm_SFT:
3148 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3149 || opnd->qualifier == AARCH64_OPND_QLF_X);
3150 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3151 snprintf (buf, size, "%s",
3152 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3153 else
3154 snprintf (buf, size, "%s, %s #%" PRIi64,
3155 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3156 aarch64_operand_modifiers[opnd->shifter.kind].name,
3157 opnd->shifter.amount);
3158 break;
3159
3160 case AARCH64_OPND_Fd:
3161 case AARCH64_OPND_Fn:
3162 case AARCH64_OPND_Fm:
3163 case AARCH64_OPND_Fa:
3164 case AARCH64_OPND_Ft:
3165 case AARCH64_OPND_Ft2:
3166 case AARCH64_OPND_Sd:
3167 case AARCH64_OPND_Sn:
3168 case AARCH64_OPND_Sm:
3169 case AARCH64_OPND_SVE_VZn:
3170 case AARCH64_OPND_SVE_Vd:
3171 case AARCH64_OPND_SVE_Vm:
3172 case AARCH64_OPND_SVE_Vn:
3173 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3174 opnd->reg.regno);
3175 break;
3176
3177 case AARCH64_OPND_Va:
3178 case AARCH64_OPND_Vd:
3179 case AARCH64_OPND_Vn:
3180 case AARCH64_OPND_Vm:
3181 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3182 aarch64_get_qualifier_name (opnd->qualifier));
3183 break;
3184
3185 case AARCH64_OPND_Ed:
3186 case AARCH64_OPND_En:
3187 case AARCH64_OPND_Em:
3188 case AARCH64_OPND_Em16:
3189 case AARCH64_OPND_SM3_IMM2:
3190 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3191 aarch64_get_qualifier_name (opnd->qualifier),
3192 opnd->reglane.index);
3193 break;
3194
3195 case AARCH64_OPND_VdD1:
3196 case AARCH64_OPND_VnD1:
3197 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3198 break;
3199
3200 case AARCH64_OPND_LVn:
3201 case AARCH64_OPND_LVt:
3202 case AARCH64_OPND_LVt_AL:
3203 case AARCH64_OPND_LEt:
3204 print_register_list (buf, size, opnd, "v");
3205 break;
3206
3207 case AARCH64_OPND_SVE_Pd:
3208 case AARCH64_OPND_SVE_Pg3:
3209 case AARCH64_OPND_SVE_Pg4_5:
3210 case AARCH64_OPND_SVE_Pg4_10:
3211 case AARCH64_OPND_SVE_Pg4_16:
3212 case AARCH64_OPND_SVE_Pm:
3213 case AARCH64_OPND_SVE_Pn:
3214 case AARCH64_OPND_SVE_Pt:
3215 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3216 snprintf (buf, size, "p%d", opnd->reg.regno);
3217 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3218 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3219 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3220 aarch64_get_qualifier_name (opnd->qualifier));
3221 else
3222 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3223 aarch64_get_qualifier_name (opnd->qualifier));
3224 break;
3225
3226 case AARCH64_OPND_SVE_Za_5:
3227 case AARCH64_OPND_SVE_Za_16:
3228 case AARCH64_OPND_SVE_Zd:
3229 case AARCH64_OPND_SVE_Zm_5:
3230 case AARCH64_OPND_SVE_Zm_16:
3231 case AARCH64_OPND_SVE_Zn:
3232 case AARCH64_OPND_SVE_Zt:
3233 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3234 snprintf (buf, size, "z%d", opnd->reg.regno);
3235 else
3236 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3237 aarch64_get_qualifier_name (opnd->qualifier));
3238 break;
3239
3240 case AARCH64_OPND_SVE_ZnxN:
3241 case AARCH64_OPND_SVE_ZtxN:
3242 print_register_list (buf, size, opnd, "z");
3243 break;
3244
3245 case AARCH64_OPND_SVE_Zm3_INDEX:
3246 case AARCH64_OPND_SVE_Zm3_22_INDEX:
3247 case AARCH64_OPND_SVE_Zm4_INDEX:
3248 case AARCH64_OPND_SVE_Zn_INDEX:
3249 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3250 aarch64_get_qualifier_name (opnd->qualifier),
3251 opnd->reglane.index);
3252 break;
3253
3254 case AARCH64_OPND_CRn:
3255 case AARCH64_OPND_CRm:
3256 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
3257 break;
3258
3259 case AARCH64_OPND_IDX:
3260 case AARCH64_OPND_MASK:
3261 case AARCH64_OPND_IMM:
3262 case AARCH64_OPND_IMM_2:
3263 case AARCH64_OPND_WIDTH:
3264 case AARCH64_OPND_UIMM3_OP1:
3265 case AARCH64_OPND_UIMM3_OP2:
3266 case AARCH64_OPND_BIT_NUM:
3267 case AARCH64_OPND_IMM_VLSL:
3268 case AARCH64_OPND_IMM_VLSR:
3269 case AARCH64_OPND_SHLL_IMM:
3270 case AARCH64_OPND_IMM0:
3271 case AARCH64_OPND_IMMR:
3272 case AARCH64_OPND_IMMS:
3273 case AARCH64_OPND_FBITS:
3274 case AARCH64_OPND_SIMM5:
3275 case AARCH64_OPND_SVE_SHLIMM_PRED:
3276 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
3277 case AARCH64_OPND_SVE_SHRIMM_PRED:
3278 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3279 case AARCH64_OPND_SVE_SIMM5:
3280 case AARCH64_OPND_SVE_SIMM5B:
3281 case AARCH64_OPND_SVE_SIMM6:
3282 case AARCH64_OPND_SVE_SIMM8:
3283 case AARCH64_OPND_SVE_UIMM3:
3284 case AARCH64_OPND_SVE_UIMM7:
3285 case AARCH64_OPND_SVE_UIMM8:
3286 case AARCH64_OPND_SVE_UIMM8_53:
3287 case AARCH64_OPND_IMM_ROT1:
3288 case AARCH64_OPND_IMM_ROT2:
3289 case AARCH64_OPND_IMM_ROT3:
3290 case AARCH64_OPND_SVE_IMM_ROT1:
3291 case AARCH64_OPND_SVE_IMM_ROT2:
3292 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3293 break;
3294
3295 case AARCH64_OPND_SVE_I1_HALF_ONE:
3296 case AARCH64_OPND_SVE_I1_HALF_TWO:
3297 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3298 {
3299 single_conv_t c;
3300 c.i = opnd->imm.value;
3301 snprintf (buf, size, "#%.1f", c.f);
3302 break;
3303 }
3304
3305 case AARCH64_OPND_SVE_PATTERN:
3306 if (optional_operand_p (opcode, idx)
3307 && opnd->imm.value == get_optional_operand_default_value (opcode))
3308 break;
3309 enum_value = opnd->imm.value;
3310 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3311 if (aarch64_sve_pattern_array[enum_value])
3312 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3313 else
3314 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3315 break;
3316
3317 case AARCH64_OPND_SVE_PATTERN_SCALED:
3318 if (optional_operand_p (opcode, idx)
3319 && !opnd->shifter.operator_present
3320 && opnd->imm.value == get_optional_operand_default_value (opcode))
3321 break;
3322 enum_value = opnd->imm.value;
3323 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3324 if (aarch64_sve_pattern_array[opnd->imm.value])
3325 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3326 else
3327 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3328 if (opnd->shifter.operator_present)
3329 {
3330 size_t len = strlen (buf);
3331 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3332 aarch64_operand_modifiers[opnd->shifter.kind].name,
3333 opnd->shifter.amount);
3334 }
3335 break;
3336
3337 case AARCH64_OPND_SVE_PRFOP:
3338 enum_value = opnd->imm.value;
3339 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3340 if (aarch64_sve_prfop_array[enum_value])
3341 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3342 else
3343 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3344 break;
3345
3346 case AARCH64_OPND_IMM_MOV:
3347 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3348 {
3349 case 4: /* e.g. MOV Wd, #<imm32>. */
3350 {
3351 int imm32 = opnd->imm.value;
3352 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3353 }
3354 break;
3355 case 8: /* e.g. MOV Xd, #<imm64>. */
3356 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3357 opnd->imm.value, opnd->imm.value);
3358 break;
3359 default: assert (0);
3360 }
3361 break;
3362
3363 case AARCH64_OPND_FPIMM0:
3364 snprintf (buf, size, "#0.0");
3365 break;
3366
3367 case AARCH64_OPND_LIMM:
3368 case AARCH64_OPND_AIMM:
3369 case AARCH64_OPND_HALF:
3370 case AARCH64_OPND_SVE_INV_LIMM:
3371 case AARCH64_OPND_SVE_LIMM:
3372 case AARCH64_OPND_SVE_LIMM_MOV:
3373 if (opnd->shifter.amount)
3374 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
3375 opnd->shifter.amount);
3376 else
3377 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3378 break;
3379
3380 case AARCH64_OPND_SIMD_IMM:
3381 case AARCH64_OPND_SIMD_IMM_SFT:
3382 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3383 || opnd->shifter.kind == AARCH64_MOD_NONE)
3384 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3385 else
3386 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
3387 aarch64_operand_modifiers[opnd->shifter.kind].name,
3388 opnd->shifter.amount);
3389 break;
3390
3391 case AARCH64_OPND_SVE_AIMM:
3392 case AARCH64_OPND_SVE_ASIMM:
3393 if (opnd->shifter.amount)
3394 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3395 opnd->shifter.amount);
3396 else
3397 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3398 break;
3399
3400 case AARCH64_OPND_FPIMM:
3401 case AARCH64_OPND_SIMD_FPIMM:
3402 case AARCH64_OPND_SVE_FPIMM8:
3403 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3404 {
3405 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3406 {
3407 half_conv_t c;
3408 c.i = expand_fp_imm (2, opnd->imm.value);
3409 snprintf (buf, size, "#%.18e", c.f);
3410 }
3411 break;
3412 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3413 {
3414 single_conv_t c;
3415 c.i = expand_fp_imm (4, opnd->imm.value);
3416 snprintf (buf, size, "#%.18e", c.f);
3417 }
3418 break;
3419 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3420 {
3421 double_conv_t c;
3422 c.i = expand_fp_imm (8, opnd->imm.value);
3423 snprintf (buf, size, "#%.18e", c.d);
3424 }
3425 break;
3426 default: assert (0);
3427 }
3428 break;
3429
3430 case AARCH64_OPND_CCMP_IMM:
3431 case AARCH64_OPND_NZCV:
3432 case AARCH64_OPND_EXCEPTION:
3433 case AARCH64_OPND_UIMM4:
3434 case AARCH64_OPND_UIMM7:
3435 if (optional_operand_p (opcode, idx) == TRUE
3436 && (opnd->imm.value ==
3437 (int64_t) get_optional_operand_default_value (opcode)))
3438 /* Omit the operand, e.g. DCPS1. */
3439 break;
3440 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3441 break;
3442
3443 case AARCH64_OPND_COND:
3444 case AARCH64_OPND_COND1:
3445 snprintf (buf, size, "%s", opnd->cond->names[0]);
3446 num_conds = ARRAY_SIZE (opnd->cond->names);
3447 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3448 {
3449 size_t len = strlen (buf);
3450 if (i == 1)
3451 snprintf (buf + len, size - len, " // %s = %s",
3452 opnd->cond->names[0], opnd->cond->names[i]);
3453 else
3454 snprintf (buf + len, size - len, ", %s",
3455 opnd->cond->names[i]);
3456 }
3457 break;
3458
3459 case AARCH64_OPND_ADDR_ADRP:
3460 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3461 + opnd->imm.value;
3462 if (pcrel_p)
3463 *pcrel_p = 1;
3464 if (address)
3465 *address = addr;
3466 /* This is not necessary during the disassembling, as print_address_func
3467 in the disassemble_info will take care of the printing. But some
3468 other callers may be still interested in getting the string in *STR,
3469 so here we do snprintf regardless. */
3470 snprintf (buf, size, "#0x%" PRIx64, addr);
3471 break;
3472
3473 case AARCH64_OPND_ADDR_PCREL14:
3474 case AARCH64_OPND_ADDR_PCREL19:
3475 case AARCH64_OPND_ADDR_PCREL21:
3476 case AARCH64_OPND_ADDR_PCREL26:
3477 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3478 if (pcrel_p)
3479 *pcrel_p = 1;
3480 if (address)
3481 *address = addr;
3482 /* This is not necessary during the disassembling, as print_address_func
3483 in the disassemble_info will take care of the printing. But some
3484 other callers may be still interested in getting the string in *STR,
3485 so here we do snprintf regardless. */
3486 snprintf (buf, size, "#0x%" PRIx64, addr);
3487 break;
3488
3489 case AARCH64_OPND_ADDR_SIMPLE:
3490 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3491 case AARCH64_OPND_SIMD_ADDR_POST:
3492 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3493 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3494 {
3495 if (opnd->addr.offset.is_reg)
3496 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3497 else
3498 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3499 }
3500 else
3501 snprintf (buf, size, "[%s]", name);
3502 break;
3503
3504 case AARCH64_OPND_ADDR_REGOFF:
3505 case AARCH64_OPND_SVE_ADDR_R:
3506 case AARCH64_OPND_SVE_ADDR_RR:
3507 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3508 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3509 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3510 case AARCH64_OPND_SVE_ADDR_RX:
3511 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3512 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3513 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
3514 print_register_offset_address
3515 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3516 get_offset_int_reg_name (opnd));
3517 break;
3518
3519 case AARCH64_OPND_SVE_ADDR_RZ:
3520 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3521 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3522 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3523 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3524 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3525 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3526 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3527 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3528 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3529 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3530 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3531 print_register_offset_address
3532 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3533 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3534 break;
3535
3536 case AARCH64_OPND_ADDR_SIMM7:
3537 case AARCH64_OPND_ADDR_SIMM9:
3538 case AARCH64_OPND_ADDR_SIMM9_2:
3539 case AARCH64_OPND_ADDR_SIMM10:
3540 case AARCH64_OPND_ADDR_OFFSET:
3541 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
3542 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3543 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3544 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3545 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3546 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3547 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
3548 case AARCH64_OPND_SVE_ADDR_RI_U6:
3549 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3550 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3551 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
3552 print_immediate_offset_address
3553 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
3554 break;
3555
3556 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3557 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3558 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3559 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3560 print_immediate_offset_address
3561 (buf, size, opnd,
3562 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3563 break;
3564
3565 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3566 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3567 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3568 print_register_offset_address
3569 (buf, size, opnd,
3570 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3571 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3572 break;
3573
3574 case AARCH64_OPND_ADDR_UIMM12:
3575 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3576 if (opnd->addr.offset.imm)
3577 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
3578 else
3579 snprintf (buf, size, "[%s]", name);
3580 break;
3581
3582 case AARCH64_OPND_SYSREG:
3583 for (i = 0; aarch64_sys_regs[i].name; ++i)
3584 {
3585 bfd_boolean exact_match
3586 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3587 == opnd->sysreg.flags;
3588
3589 /* Try and find an exact match, But if that fails, return the first
3590 partial match that was found. */
3591 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3592 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3593 && (name == NULL || exact_match))
3594 {
3595 name = aarch64_sys_regs[i].name;
3596 if (exact_match)
3597 {
3598 if (notes)
3599 *notes = NULL;
3600 break;
3601 }
3602
3603 /* If we didn't match exactly, that means the presense of a flag
3604 indicates what we didn't want for this instruction. e.g. If
3605 F_REG_READ is there, that means we were looking for a write
3606 register. See aarch64_ext_sysreg. */
3607 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
3608 *notes = _("reading from a write-only register");
3609 else if (aarch64_sys_regs[i].flags & F_REG_READ)
3610 *notes = _("writing to a read-only register");
3611 }
3612 }
3613
3614 if (name)
3615 snprintf (buf, size, "%s", name);
3616 else
3617 {
3618 /* Implementation defined system register. */
3619 unsigned int value = opnd->sysreg.value;
3620 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3621 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3622 value & 0x7);
3623 }
3624 break;
3625
3626 case AARCH64_OPND_PSTATEFIELD:
3627 for (i = 0; aarch64_pstatefields[i].name; ++i)
3628 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3629 break;
3630 assert (aarch64_pstatefields[i].name);
3631 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3632 break;
3633
3634 case AARCH64_OPND_SYSREG_AT:
3635 case AARCH64_OPND_SYSREG_DC:
3636 case AARCH64_OPND_SYSREG_IC:
3637 case AARCH64_OPND_SYSREG_TLBI:
3638 case AARCH64_OPND_SYSREG_SR:
3639 snprintf (buf, size, "%s", opnd->sysins_op->name);
3640 break;
3641
3642 case AARCH64_OPND_BARRIER:
3643 snprintf (buf, size, "%s", opnd->barrier->name);
3644 break;
3645
3646 case AARCH64_OPND_BARRIER_ISB:
3647 /* Operand can be omitted, e.g. in DCPS1. */
3648 if (! optional_operand_p (opcode, idx)
3649 || (opnd->barrier->value
3650 != get_optional_operand_default_value (opcode)))
3651 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3652 break;
3653
3654 case AARCH64_OPND_PRFOP:
3655 if (opnd->prfop->name != NULL)
3656 snprintf (buf, size, "%s", opnd->prfop->name);
3657 else
3658 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
3659 break;
3660
3661 case AARCH64_OPND_BARRIER_PSB:
3662 case AARCH64_OPND_BTI_TARGET:
3663 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3664 snprintf (buf, size, "%s", opnd->hint_option->name);
3665 break;
3666
3667 default:
3668 assert (0);
3669 }
3670 }
3671 \f
3672 #define CPENC(op0,op1,crn,crm,op2) \
3673 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3674 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3675 #define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3676 /* for 3.9.10 System Instructions */
3677 #define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3678
3679 #define C0 0
3680 #define C1 1
3681 #define C2 2
3682 #define C3 3
3683 #define C4 4
3684 #define C5 5
3685 #define C6 6
3686 #define C7 7
3687 #define C8 8
3688 #define C9 9
3689 #define C10 10
3690 #define C11 11
3691 #define C12 12
3692 #define C13 13
3693 #define C14 14
3694 #define C15 15
3695
3696 /* TODO there is one more issues need to be resolved
3697 1. handle cpu-implementation-defined system registers. */
3698 const aarch64_sys_reg aarch64_sys_regs [] =
3699 {
3700 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
3701 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
3702 { "elr_el1", CPEN_(0,C0,1), 0 },
3703 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
3704 { "sp_el0", CPEN_(0,C1,0), 0 },
3705 { "spsel", CPEN_(0,C2,0), 0 },
3706 { "daif", CPEN_(3,C2,1), 0 },
3707 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
3708 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
3709 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
3710 { "nzcv", CPEN_(3,C2,0), 0 },
3711 { "fpcr", CPEN_(3,C4,0), 0 },
3712 { "fpsr", CPEN_(3,C4,1), 0 },
3713 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3714 { "dlr_el0", CPEN_(3,C5,1), 0 },
3715 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3716 { "elr_el2", CPEN_(4,C0,1), 0 },
3717 { "sp_el1", CPEN_(4,C1,0), 0 },
3718 { "spsr_irq", CPEN_(4,C3,0), 0 },
3719 { "spsr_abt", CPEN_(4,C3,1), 0 },
3720 { "spsr_und", CPEN_(4,C3,2), 0 },
3721 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3722 { "spsr_el3", CPEN_(6,C0,0), 0 },
3723 { "elr_el3", CPEN_(6,C0,1), 0 },
3724 { "sp_el2", CPEN_(6,C1,0), 0 },
3725 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3726 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
3727 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3728 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3729 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3730 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3731 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3732 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3733 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3734 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3735 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
3736 { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
3737 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3738 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3739 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3740 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3741 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3742 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3743 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3744 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3745 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3746 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3747 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3748 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3749 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3750 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3751 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3752 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3753 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3754 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3755 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3756 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3757 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3758 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3759 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3760 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3761 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3762 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3763 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3764 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3765 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
3766 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
3767 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3768 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3769 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3770 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3771 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
3772 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
3773 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3774 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3775 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3776 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
3777 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
3778 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3779 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3780 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3781 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3782 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3783 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3784 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3785 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
3786 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3787 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3788 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3789 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3790 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
3791 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3792 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3793 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
3794 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
3795 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
3796 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3797 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
3798 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3799 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3800 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3801 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
3802 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
3803 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
3804 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3805 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3806 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3807 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3808 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3809 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3810 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3811 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3812 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3813 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
3814 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3815 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3816 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3817 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3818 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
3819 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
3820 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
3821 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
3822 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3823 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3824 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
3825 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
3826 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
3827 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
3828 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
3829 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
3830 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
3831 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3832 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3833 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3834 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3835 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
3836 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3837 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3838 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
3839 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
3840 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3841 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3842 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3843 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3844 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
3845 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
3846 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3847 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3848 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
3849 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
3850 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3851 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3852 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
3853 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
3854 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3855 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3856 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
3857 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3858 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3859 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
3860 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
3861 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3862 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
3863 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
3864 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3865 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
3866 { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
3867 { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
3868 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
3869 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
3870 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3871 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3872 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
3873 { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
3874 { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
3875 { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
3876 { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
3877 { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
3878 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
3879 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3880 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3881 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
3882 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3883 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
3884 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
3885 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
3886 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
3887 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
3888 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
3889 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
3890 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
3891 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
3892 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
3893 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
3894 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
3895 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
3896 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
3897 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
3898 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
3899 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
3900 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
3901 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
3902 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
3903 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
3904 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
3905 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
3906 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
3907 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
3908 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
3909 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
3910 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
3911 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
3912 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
3913 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
3914 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
3915 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
3916 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
3917 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
3918 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
3919 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
3920 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
3921 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
3922 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
3923 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
3924 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
3925 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
3926 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
3927 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
3928 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
3929 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
3930 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
3931 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
3932 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
3933 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
3934 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
3935 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
3936 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
3937 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
3938 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
3939 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
3940 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
3941 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
3942 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
3943 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
3944 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
3945 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
3946 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
3947 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
3948 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
3949 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
3950 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
3951 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
3952 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
3953 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
3954 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
3955 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
3956 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
3957 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
3958 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
3959 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
3960 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
3961 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
3962 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
3963 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
3964 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
3965 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
3966 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
3967 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
3968 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
3969 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
3970 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
3971 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
3972 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
3973 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
3974 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
3975 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
3976 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
3977 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
3978 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
3979 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
3980 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
3981 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
3982 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
3983 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
3984 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
3985 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
3986 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
3987 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
3988 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
3989 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
3990 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
3991 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
3992 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
3993 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
3994 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
3995 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
3996 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
3997 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
3998 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
3999 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
4000 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
4001 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
4002 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
4003 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
4004 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
4005 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
4006 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
4007 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
4008 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
4009 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
4010 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
4011 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
4012 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
4013 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
4014 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
4015 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4016 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4017 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4018 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4019 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4020 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4021 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4022 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4023 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4024 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4025 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4026 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4027 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4028 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4029 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4030 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4031 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4032 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4033 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4034 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4035 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4036 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4037 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4038 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4039 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4040 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4041 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4042 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4043 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4044 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4045 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4046 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4047 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4048 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4049 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4050 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4051 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4052 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4053 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4054 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4055 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4056 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4057 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4058 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4059 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4060 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4061 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4062 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4063 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4064 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4065 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4066 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4067 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4068 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4069 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4070 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4071 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4072 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4073 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4074 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4075 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4076 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4077 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4078 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4079 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4080 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4081 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4082 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4083 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
4084
4085 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4086 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4087 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4088 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4089 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4090 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4091 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4092 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4093 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4094 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4095 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
4096 { 0, CPENC(0,0,0,0,0), 0 },
4097 };
4098
4099 bfd_boolean
4100 aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4101 {
4102 return (reg->flags & F_DEPRECATED) != 0;
4103 }
4104
4105 bfd_boolean
4106 aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4107 const aarch64_sys_reg *reg)
4108 {
4109 if (!(reg->flags & F_ARCHEXT))
4110 return TRUE;
4111
4112 /* PAN. Values are from aarch64_sys_regs. */
4113 if (reg->value == CPEN_(0,C2,3)
4114 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4115 return FALSE;
4116
4117 /* SCXTNUM_ELx registers. */
4118 if ((reg->value == CPENC (3, 3, C13, C0, 7)
4119 || reg->value == CPENC (3, 0, C13, C0, 7)
4120 || reg->value == CPENC (3, 4, C13, C0, 7)
4121 || reg->value == CPENC (3, 6, C13, C0, 7)
4122 || reg->value == CPENC (3, 5, C13, C0, 7))
4123 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
4124 return FALSE;
4125
4126 /* ID_PFR2_EL1 register. */
4127 if (reg->value == CPENC(3, 0, C0, C3, 4)
4128 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
4129 return FALSE;
4130
4131 /* Virtualization host extensions: system registers. */
4132 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4133 || reg->value == CPENC (3, 4, C13, C0, 1)
4134 || reg->value == CPENC (3, 4, C14, C3, 0)
4135 || reg->value == CPENC (3, 4, C14, C3, 1)
4136 || reg->value == CPENC (3, 4, C14, C3, 2))
4137 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4138 return FALSE;
4139
4140 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4141 if ((reg->value == CPEN_ (5, C0, 0)
4142 || reg->value == CPEN_ (5, C0, 1)
4143 || reg->value == CPENC (3, 5, C1, C0, 0)
4144 || reg->value == CPENC (3, 5, C1, C0, 2)
4145 || reg->value == CPENC (3, 5, C2, C0, 0)
4146 || reg->value == CPENC (3, 5, C2, C0, 1)
4147 || reg->value == CPENC (3, 5, C2, C0, 2)
4148 || reg->value == CPENC (3, 5, C5, C1, 0)
4149 || reg->value == CPENC (3, 5, C5, C1, 1)
4150 || reg->value == CPENC (3, 5, C5, C2, 0)
4151 || reg->value == CPENC (3, 5, C6, C0, 0)
4152 || reg->value == CPENC (3, 5, C10, C2, 0)
4153 || reg->value == CPENC (3, 5, C10, C3, 0)
4154 || reg->value == CPENC (3, 5, C12, C0, 0)
4155 || reg->value == CPENC (3, 5, C13, C0, 1)
4156 || reg->value == CPENC (3, 5, C14, C1, 0))
4157 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4158 return FALSE;
4159
4160 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4161 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4162 || reg->value == CPENC (3, 5, C14, C2, 1)
4163 || reg->value == CPENC (3, 5, C14, C2, 2)
4164 || reg->value == CPENC (3, 5, C14, C3, 0)
4165 || reg->value == CPENC (3, 5, C14, C3, 1)
4166 || reg->value == CPENC (3, 5, C14, C3, 2))
4167 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4168 return FALSE;
4169
4170 /* ARMv8.2 features. */
4171
4172 /* ID_AA64MMFR2_EL1. */
4173 if (reg->value == CPENC (3, 0, C0, C7, 2)
4174 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4175 return FALSE;
4176
4177 /* PSTATE.UAO. */
4178 if (reg->value == CPEN_ (0, C2, 4)
4179 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4180 return FALSE;
4181
4182 /* RAS extension. */
4183
4184 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4185 ERXMISC0_EL1 AND ERXMISC1_EL1. */
4186 if ((reg->value == CPENC (3, 0, C5, C3, 0)
4187 || reg->value == CPENC (3, 0, C5, C3, 1)
4188 || reg->value == CPENC (3, 0, C5, C3, 2)
4189 || reg->value == CPENC (3, 0, C5, C3, 3)
4190 || reg->value == CPENC (3, 0, C5, C4, 0)
4191 || reg->value == CPENC (3, 0, C5, C4, 1)
4192 || reg->value == CPENC (3, 0, C5, C4, 2)
4193 || reg->value == CPENC (3, 0, C5, C4, 3)
4194 || reg->value == CPENC (3, 0, C5, C5, 0)
4195 || reg->value == CPENC (3, 0, C5, C5, 1))
4196 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4197 return FALSE;
4198
4199 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4200 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4201 || reg->value == CPENC (3, 0, C12, C1, 1)
4202 || reg->value == CPENC (3, 4, C12, C1, 1))
4203 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4204 return FALSE;
4205
4206 /* Statistical Profiling extension. */
4207 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4208 || reg->value == CPENC (3, 0, C9, C10, 1)
4209 || reg->value == CPENC (3, 0, C9, C10, 3)
4210 || reg->value == CPENC (3, 0, C9, C10, 7)
4211 || reg->value == CPENC (3, 0, C9, C9, 0)
4212 || reg->value == CPENC (3, 0, C9, C9, 2)
4213 || reg->value == CPENC (3, 0, C9, C9, 3)
4214 || reg->value == CPENC (3, 0, C9, C9, 4)
4215 || reg->value == CPENC (3, 0, C9, C9, 5)
4216 || reg->value == CPENC (3, 0, C9, C9, 6)
4217 || reg->value == CPENC (3, 0, C9, C9, 7)
4218 || reg->value == CPENC (3, 4, C9, C9, 0)
4219 || reg->value == CPENC (3, 5, C9, C9, 0))
4220 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4221 return FALSE;
4222
4223 /* ARMv8.3 Pointer authentication keys. */
4224 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4225 || reg->value == CPENC (3, 0, C2, C1, 1)
4226 || reg->value == CPENC (3, 0, C2, C1, 2)
4227 || reg->value == CPENC (3, 0, C2, C1, 3)
4228 || reg->value == CPENC (3, 0, C2, C2, 0)
4229 || reg->value == CPENC (3, 0, C2, C2, 1)
4230 || reg->value == CPENC (3, 0, C2, C2, 2)
4231 || reg->value == CPENC (3, 0, C2, C2, 3)
4232 || reg->value == CPENC (3, 0, C2, C3, 0)
4233 || reg->value == CPENC (3, 0, C2, C3, 1))
4234 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4235 return FALSE;
4236
4237 /* SVE. */
4238 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4239 || reg->value == CPENC (3, 0, C1, C2, 0)
4240 || reg->value == CPENC (3, 4, C1, C2, 0)
4241 || reg->value == CPENC (3, 6, C1, C2, 0)
4242 || reg->value == CPENC (3, 5, C1, C2, 0)
4243 || reg->value == CPENC (3, 0, C0, C0, 7))
4244 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4245 return FALSE;
4246
4247 /* ARMv8.4 features. */
4248
4249 /* PSTATE.DIT. */
4250 if (reg->value == CPEN_ (3, C2, 5)
4251 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4252 return FALSE;
4253
4254 /* Virtualization extensions. */
4255 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4256 || reg->value == CPENC(3, 4, C2, C6, 0)
4257 || reg->value == CPENC(3, 4, C14, C4, 0)
4258 || reg->value == CPENC(3, 4, C14, C4, 2)
4259 || reg->value == CPENC(3, 4, C14, C4, 1)
4260 || reg->value == CPENC(3, 4, C14, C5, 0)
4261 || reg->value == CPENC(3, 4, C14, C5, 2)
4262 || reg->value == CPENC(3, 4, C14, C5, 1)
4263 || reg->value == CPENC(3, 4, C1, C3, 1)
4264 || reg->value == CPENC(3, 4, C2, C2, 0))
4265 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4266 return FALSE;
4267
4268 /* ARMv8.4 TLB instructions. */
4269 if ((reg->value == CPENS (0, C8, C1, 0)
4270 || reg->value == CPENS (0, C8, C1, 1)
4271 || reg->value == CPENS (0, C8, C1, 2)
4272 || reg->value == CPENS (0, C8, C1, 3)
4273 || reg->value == CPENS (0, C8, C1, 5)
4274 || reg->value == CPENS (0, C8, C1, 7)
4275 || reg->value == CPENS (4, C8, C4, 0)
4276 || reg->value == CPENS (4, C8, C4, 4)
4277 || reg->value == CPENS (4, C8, C1, 1)
4278 || reg->value == CPENS (4, C8, C1, 5)
4279 || reg->value == CPENS (4, C8, C1, 6)
4280 || reg->value == CPENS (6, C8, C1, 1)
4281 || reg->value == CPENS (6, C8, C1, 5)
4282 || reg->value == CPENS (4, C8, C1, 0)
4283 || reg->value == CPENS (4, C8, C1, 4)
4284 || reg->value == CPENS (6, C8, C1, 0)
4285 || reg->value == CPENS (0, C8, C6, 1)
4286 || reg->value == CPENS (0, C8, C6, 3)
4287 || reg->value == CPENS (0, C8, C6, 5)
4288 || reg->value == CPENS (0, C8, C6, 7)
4289 || reg->value == CPENS (0, C8, C2, 1)
4290 || reg->value == CPENS (0, C8, C2, 3)
4291 || reg->value == CPENS (0, C8, C2, 5)
4292 || reg->value == CPENS (0, C8, C2, 7)
4293 || reg->value == CPENS (0, C8, C5, 1)
4294 || reg->value == CPENS (0, C8, C5, 3)
4295 || reg->value == CPENS (0, C8, C5, 5)
4296 || reg->value == CPENS (0, C8, C5, 7)
4297 || reg->value == CPENS (4, C8, C0, 2)
4298 || reg->value == CPENS (4, C8, C0, 6)
4299 || reg->value == CPENS (4, C8, C4, 2)
4300 || reg->value == CPENS (4, C8, C4, 6)
4301 || reg->value == CPENS (4, C8, C4, 3)
4302 || reg->value == CPENS (4, C8, C4, 7)
4303 || reg->value == CPENS (4, C8, C6, 1)
4304 || reg->value == CPENS (4, C8, C6, 5)
4305 || reg->value == CPENS (4, C8, C2, 1)
4306 || reg->value == CPENS (4, C8, C2, 5)
4307 || reg->value == CPENS (4, C8, C5, 1)
4308 || reg->value == CPENS (4, C8, C5, 5)
4309 || reg->value == CPENS (6, C8, C6, 1)
4310 || reg->value == CPENS (6, C8, C6, 5)
4311 || reg->value == CPENS (6, C8, C2, 1)
4312 || reg->value == CPENS (6, C8, C2, 5)
4313 || reg->value == CPENS (6, C8, C5, 1)
4314 || reg->value == CPENS (6, C8, C5, 5))
4315 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4316 return FALSE;
4317
4318 /* Random Number Instructions. For now they are available
4319 (and optional) only with ARMv8.5-A. */
4320 if ((reg->value == CPENC (3, 3, C2, C4, 0)
4321 || reg->value == CPENC (3, 3, C2, C4, 1))
4322 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
4323 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
4324 return FALSE;
4325
4326 return TRUE;
4327 }
4328
4329 /* The CPENC below is fairly misleading, the fields
4330 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4331 by ins_pstatefield, which just shifts the value by the width of the fields
4332 in a loop. So if you CPENC them only the first value will be set, the rest
4333 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4334 value of 0b110000000001000000 (0x30040) while what you want is
4335 0b011010 (0x1a). */
4336 const aarch64_sys_reg aarch64_pstatefields [] =
4337 {
4338 { "spsel", 0x05, 0 },
4339 { "daifset", 0x1e, 0 },
4340 { "daifclr", 0x1f, 0 },
4341 { "pan", 0x04, F_ARCHEXT },
4342 { "uao", 0x03, F_ARCHEXT },
4343 { "dit", 0x1a, F_ARCHEXT },
4344 { 0, CPENC(0,0,0,0,0), 0 },
4345 };
4346
4347 bfd_boolean
4348 aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4349 const aarch64_sys_reg *reg)
4350 {
4351 if (!(reg->flags & F_ARCHEXT))
4352 return TRUE;
4353
4354 /* PAN. Values are from aarch64_pstatefields. */
4355 if (reg->value == 0x04
4356 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4357 return FALSE;
4358
4359 /* UAO. Values are from aarch64_pstatefields. */
4360 if (reg->value == 0x03
4361 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4362 return FALSE;
4363
4364 /* DIT. Values are from aarch64_pstatefields. */
4365 if (reg->value == 0x1a
4366 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4367 return FALSE;
4368
4369 return TRUE;
4370 }
4371
4372 const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4373 {
4374 { "ialluis", CPENS(0,C7,C1,0), 0 },
4375 { "iallu", CPENS(0,C7,C5,0), 0 },
4376 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
4377 { 0, CPENS(0,0,0,0), 0 }
4378 };
4379
4380 const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4381 {
4382 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
4383 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
4384 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
4385 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
4386 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
4387 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
4388 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
4389 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
4390 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
4391 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
4392 { 0, CPENS(0,0,0,0), 0 }
4393 };
4394
4395 const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4396 {
4397 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4398 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4399 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4400 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4401 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4402 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4403 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4404 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4405 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4406 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4407 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4408 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
4409 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4410 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
4411 { 0, CPENS(0,0,0,0), 0 }
4412 };
4413
4414 const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4415 {
4416 { "vmalle1", CPENS(0,C8,C7,0), 0 },
4417 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4418 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4419 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
4420 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
4421 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4422 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4423 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4424 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4425 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4426 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4427 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4428 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4429 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
4430 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4431 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
4432 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4433 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
4434 { "alle2", CPENS(4,C8,C7,0), 0 },
4435 { "alle2is", CPENS(4,C8,C3,0), 0 },
4436 { "alle1", CPENS(4,C8,C7,4), 0 },
4437 { "alle1is", CPENS(4,C8,C3,4), 0 },
4438 { "alle3", CPENS(6,C8,C7,0), 0 },
4439 { "alle3is", CPENS(6,C8,C3,0), 0 },
4440 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4441 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4442 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4443 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4444 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4445 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4446 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4447 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
4448
4449 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4450 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4451 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4452 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4453 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4454 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4455 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4456 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4457 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4458 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4459 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4460 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4461 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4462 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4463 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4464 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4465
4466 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4467 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4468 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4469 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4470 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4471 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4472 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4473 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4474 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4475 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4476 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4477 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4478 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4479 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4480 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4481 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4482 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4483 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4484 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4485 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4486 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4487 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4488 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4489 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4490 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4491 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4492 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4493 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4494 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4495 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4496
4497 { 0, CPENS(0,0,0,0), 0 }
4498 };
4499
4500 const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4501 {
4502 /* RCTX is somewhat unique in a way that it has different values
4503 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4504 Thus op2 is masked out and instead encoded directly in the
4505 aarch64_opcode_table entries for the respective instructions. */
4506 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4507
4508 { 0, CPENS(0,0,0,0), 0 }
4509 };
4510
4511 bfd_boolean
4512 aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4513 {
4514 return (sys_ins_reg->flags & F_HASXT) != 0;
4515 }
4516
4517 extern bfd_boolean
4518 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4519 const aarch64_sys_ins_reg *reg)
4520 {
4521 if (!(reg->flags & F_ARCHEXT))
4522 return TRUE;
4523
4524 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4525 if (reg->value == CPENS (3, C7, C12, 1)
4526 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4527 return FALSE;
4528
4529 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4530 if (reg->value == CPENS (3, C7, C13, 1)
4531 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4532 return FALSE;
4533
4534 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4535 if ((reg->value == CPENS (0, C7, C9, 0)
4536 || reg->value == CPENS (0, C7, C9, 1))
4537 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4538 return FALSE;
4539
4540 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4541 if (reg->value == CPENS (3, C7, C3, 0)
4542 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4543 return FALSE;
4544
4545 return TRUE;
4546 }
4547
4548 #undef C0
4549 #undef C1
4550 #undef C2
4551 #undef C3
4552 #undef C4
4553 #undef C5
4554 #undef C6
4555 #undef C7
4556 #undef C8
4557 #undef C9
4558 #undef C10
4559 #undef C11
4560 #undef C12
4561 #undef C13
4562 #undef C14
4563 #undef C15
4564
4565 #define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4566 #define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4567
4568 static enum err_type
4569 verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4570 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4571 bfd_boolean encoding ATTRIBUTE_UNUSED,
4572 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4573 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4574 {
4575 int t = BITS (insn, 4, 0);
4576 int n = BITS (insn, 9, 5);
4577 int t2 = BITS (insn, 14, 10);
4578
4579 if (BIT (insn, 23))
4580 {
4581 /* Write back enabled. */
4582 if ((t == n || t2 == n) && n != 31)
4583 return ERR_UND;
4584 }
4585
4586 if (BIT (insn, 22))
4587 {
4588 /* Load */
4589 if (t == t2)
4590 return ERR_UND;
4591 }
4592
4593 return ERR_OK;
4594 }
4595
4596 /* Initialize an instruction sequence insn_sequence with the instruction INST.
4597 If INST is NULL the given insn_sequence is cleared and the sequence is left
4598 uninitialized. */
4599
4600 void
4601 init_insn_sequence (const struct aarch64_inst *inst,
4602 aarch64_instr_sequence *insn_sequence)
4603 {
4604 int num_req_entries = 0;
4605 insn_sequence->next_insn = 0;
4606 insn_sequence->num_insns = num_req_entries;
4607 if (insn_sequence->instr)
4608 XDELETE (insn_sequence->instr);
4609 insn_sequence->instr = NULL;
4610
4611 if (inst)
4612 {
4613 insn_sequence->instr = XNEW (aarch64_inst);
4614 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4615 }
4616
4617 /* Handle all the cases here. May need to think of something smarter than
4618 a giant if/else chain if this grows. At that time, a lookup table may be
4619 best. */
4620 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4621 num_req_entries = 1;
4622
4623 if (insn_sequence->current_insns)
4624 XDELETEVEC (insn_sequence->current_insns);
4625 insn_sequence->current_insns = NULL;
4626
4627 if (num_req_entries != 0)
4628 {
4629 size_t size = num_req_entries * sizeof (aarch64_inst);
4630 insn_sequence->current_insns
4631 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4632 memset (insn_sequence->current_insns, 0, size);
4633 }
4634 }
4635
4636
4637 /* This function verifies that the instruction INST adheres to its specified
4638 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4639 returned and MISMATCH_DETAIL contains the reason why verification failed.
4640
4641 The function is called both during assembly and disassembly. If assembling
4642 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4643 and will contain the PC of the current instruction w.r.t to the section.
4644
4645 If ENCODING and PC=0 then you are at a start of a section. The constraints
4646 are verified against the given state insn_sequence which is updated as it
4647 transitions through the verification. */
4648
4649 enum err_type
4650 verify_constraints (const struct aarch64_inst *inst,
4651 const aarch64_insn insn ATTRIBUTE_UNUSED,
4652 bfd_vma pc,
4653 bfd_boolean encoding,
4654 aarch64_operand_error *mismatch_detail,
4655 aarch64_instr_sequence *insn_sequence)
4656 {
4657 assert (inst);
4658 assert (inst->opcode);
4659
4660 const struct aarch64_opcode *opcode = inst->opcode;
4661 if (!opcode->constraints && !insn_sequence->instr)
4662 return ERR_OK;
4663
4664 assert (insn_sequence);
4665
4666 enum err_type res = ERR_OK;
4667
4668 /* This instruction puts a constraint on the insn_sequence. */
4669 if (opcode->flags & F_SCAN)
4670 {
4671 if (insn_sequence->instr)
4672 {
4673 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4674 mismatch_detail->error = _("instruction opens new dependency "
4675 "sequence without ending previous one");
4676 mismatch_detail->index = -1;
4677 mismatch_detail->non_fatal = TRUE;
4678 res = ERR_VFI;
4679 }
4680
4681 init_insn_sequence (inst, insn_sequence);
4682 return res;
4683 }
4684
4685 /* Verify constraints on an existing sequence. */
4686 if (insn_sequence->instr)
4687 {
4688 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4689 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4690 closed a previous one that we should have. */
4691 if (!encoding && pc == 0)
4692 {
4693 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4694 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4695 mismatch_detail->index = -1;
4696 mismatch_detail->non_fatal = TRUE;
4697 res = ERR_VFI;
4698 /* Reset the sequence. */
4699 init_insn_sequence (NULL, insn_sequence);
4700 return res;
4701 }
4702
4703 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4704 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4705 {
4706 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4707 instruction for better error messages. */
4708 if (!opcode->avariant || !(*opcode->avariant & AARCH64_FEATURE_SVE))
4709 {
4710 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4711 mismatch_detail->error = _("SVE instruction expected after "
4712 "`movprfx'");
4713 mismatch_detail->index = -1;
4714 mismatch_detail->non_fatal = TRUE;
4715 res = ERR_VFI;
4716 goto done;
4717 }
4718
4719 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4720 instruction that is allowed to be used with a MOVPRFX. */
4721 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4722 {
4723 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4724 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4725 "expected");
4726 mismatch_detail->index = -1;
4727 mismatch_detail->non_fatal = TRUE;
4728 res = ERR_VFI;
4729 goto done;
4730 }
4731
4732 /* Next check for usage of the predicate register. */
4733 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
4734 aarch64_opnd_info blk_pred, inst_pred;
4735 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4736 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
4737 bfd_boolean predicated = FALSE;
4738 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4739
4740 /* Determine if the movprfx instruction used is predicated or not. */
4741 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4742 {
4743 predicated = TRUE;
4744 blk_pred = insn_sequence->instr->operands[1];
4745 }
4746
4747 unsigned char max_elem_size = 0;
4748 unsigned char current_elem_size;
4749 int num_op_used = 0, last_op_usage = 0;
4750 int i, inst_pred_idx = -1;
4751 int num_ops = aarch64_num_of_operands (opcode);
4752 for (i = 0; i < num_ops; i++)
4753 {
4754 aarch64_opnd_info inst_op = inst->operands[i];
4755 switch (inst_op.type)
4756 {
4757 case AARCH64_OPND_SVE_Zd:
4758 case AARCH64_OPND_SVE_Zm_5:
4759 case AARCH64_OPND_SVE_Zm_16:
4760 case AARCH64_OPND_SVE_Zn:
4761 case AARCH64_OPND_SVE_Zt:
4762 case AARCH64_OPND_SVE_Vm:
4763 case AARCH64_OPND_SVE_Vn:
4764 case AARCH64_OPND_Va:
4765 case AARCH64_OPND_Vn:
4766 case AARCH64_OPND_Vm:
4767 case AARCH64_OPND_Sn:
4768 case AARCH64_OPND_Sm:
4769 case AARCH64_OPND_Rn:
4770 case AARCH64_OPND_Rm:
4771 case AARCH64_OPND_Rn_SP:
4772 case AARCH64_OPND_Rm_SP:
4773 if (inst_op.reg.regno == blk_dest.reg.regno)
4774 {
4775 num_op_used++;
4776 last_op_usage = i;
4777 }
4778 current_elem_size
4779 = aarch64_get_qualifier_esize (inst_op.qualifier);
4780 if (current_elem_size > max_elem_size)
4781 max_elem_size = current_elem_size;
4782 break;
4783 case AARCH64_OPND_SVE_Pd:
4784 case AARCH64_OPND_SVE_Pg3:
4785 case AARCH64_OPND_SVE_Pg4_5:
4786 case AARCH64_OPND_SVE_Pg4_10:
4787 case AARCH64_OPND_SVE_Pg4_16:
4788 case AARCH64_OPND_SVE_Pm:
4789 case AARCH64_OPND_SVE_Pn:
4790 case AARCH64_OPND_SVE_Pt:
4791 inst_pred = inst_op;
4792 inst_pred_idx = i;
4793 break;
4794 default:
4795 break;
4796 }
4797 }
4798
4799 assert (max_elem_size != 0);
4800 aarch64_opnd_info inst_dest = inst->operands[0];
4801 /* Determine the size that should be used to compare against the
4802 movprfx size. */
4803 current_elem_size
4804 = opcode->constraints & C_MAX_ELEM
4805 ? max_elem_size
4806 : aarch64_get_qualifier_esize (inst_dest.qualifier);
4807
4808 /* If movprfx is predicated do some extra checks. */
4809 if (predicated)
4810 {
4811 /* The instruction must be predicated. */
4812 if (inst_pred_idx < 0)
4813 {
4814 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4815 mismatch_detail->error = _("predicated instruction expected "
4816 "after `movprfx'");
4817 mismatch_detail->index = -1;
4818 mismatch_detail->non_fatal = TRUE;
4819 res = ERR_VFI;
4820 goto done;
4821 }
4822
4823 /* The instruction must have a merging predicate. */
4824 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
4825 {
4826 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4827 mismatch_detail->error = _("merging predicate expected due "
4828 "to preceding `movprfx'");
4829 mismatch_detail->index = inst_pred_idx;
4830 mismatch_detail->non_fatal = TRUE;
4831 res = ERR_VFI;
4832 goto done;
4833 }
4834
4835 /* The same register must be used in instruction. */
4836 if (blk_pred.reg.regno != inst_pred.reg.regno)
4837 {
4838 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4839 mismatch_detail->error = _("predicate register differs "
4840 "from that in preceding "
4841 "`movprfx'");
4842 mismatch_detail->index = inst_pred_idx;
4843 mismatch_detail->non_fatal = TRUE;
4844 res = ERR_VFI;
4845 goto done;
4846 }
4847 }
4848
4849 /* Destructive operations by definition must allow one usage of the
4850 same register. */
4851 int allowed_usage
4852 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
4853
4854 /* Operand is not used at all. */
4855 if (num_op_used == 0)
4856 {
4857 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4858 mismatch_detail->error = _("output register of preceding "
4859 "`movprfx' not used in current "
4860 "instruction");
4861 mismatch_detail->index = 0;
4862 mismatch_detail->non_fatal = TRUE;
4863 res = ERR_VFI;
4864 goto done;
4865 }
4866
4867 /* We now know it's used, now determine exactly where it's used. */
4868 if (blk_dest.reg.regno != inst_dest.reg.regno)
4869 {
4870 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4871 mismatch_detail->error = _("output register of preceding "
4872 "`movprfx' expected as output");
4873 mismatch_detail->index = 0;
4874 mismatch_detail->non_fatal = TRUE;
4875 res = ERR_VFI;
4876 goto done;
4877 }
4878
4879 /* Operand used more than allowed for the specific opcode type. */
4880 if (num_op_used > allowed_usage)
4881 {
4882 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4883 mismatch_detail->error = _("output register of preceding "
4884 "`movprfx' used as input");
4885 mismatch_detail->index = last_op_usage;
4886 mismatch_detail->non_fatal = TRUE;
4887 res = ERR_VFI;
4888 goto done;
4889 }
4890
4891 /* Now the only thing left is the qualifiers checks. The register
4892 must have the same maximum element size. */
4893 if (inst_dest.qualifier
4894 && blk_dest.qualifier
4895 && current_elem_size
4896 != aarch64_get_qualifier_esize (blk_dest.qualifier))
4897 {
4898 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4899 mismatch_detail->error = _("register size not compatible with "
4900 "previous `movprfx'");
4901 mismatch_detail->index = 0;
4902 mismatch_detail->non_fatal = TRUE;
4903 res = ERR_VFI;
4904 goto done;
4905 }
4906 }
4907
4908 done:
4909 /* Add the new instruction to the sequence. */
4910 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
4911 inst, sizeof (aarch64_inst));
4912
4913 /* Check if sequence is now full. */
4914 if (insn_sequence->next_insn >= insn_sequence->num_insns)
4915 {
4916 /* Sequence is full, but we don't have anything special to do for now,
4917 so clear and reset it. */
4918 init_insn_sequence (NULL, insn_sequence);
4919 }
4920 }
4921
4922 return res;
4923 }
4924
4925
4926 /* Return true if VALUE cannot be moved into an SVE register using DUP
4927 (with any element size, not just ESIZE) and if using DUPM would
4928 therefore be OK. ESIZE is the number of bytes in the immediate. */
4929
4930 bfd_boolean
4931 aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
4932 {
4933 int64_t svalue = uvalue;
4934 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
4935
4936 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
4937 return FALSE;
4938 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
4939 {
4940 svalue = (int32_t) uvalue;
4941 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
4942 {
4943 svalue = (int16_t) uvalue;
4944 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
4945 return FALSE;
4946 }
4947 }
4948 if ((svalue & 0xff) == 0)
4949 svalue /= 256;
4950 return svalue < -128 || svalue >= 128;
4951 }
4952
4953 /* Include the opcode description table as well as the operand description
4954 table. */
4955 #define VERIFIER(x) verify_##x
4956 #include "aarch64-tbl.h"
GDB Binutils - Deliverables
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