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AArch64: Replace C initializers with memset
[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c
1 /* aarch64-opc.c -- AArch64 opcode support.
2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21 #include "sysdep.h"
22 #include <assert.h>
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include <stdint.h>
26 #include <stdarg.h>
27 #include <inttypes.h>
28
29 #include "opintl.h"
30 #include "libiberty.h"
31
32 #include "aarch64-opc.h"
33
34 #ifdef DEBUG_AARCH64
35 int debug_dump = FALSE;
36 #endif /* DEBUG_AARCH64 */
37
38 /* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40 const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77 };
78
79 /* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81 const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100 };
101
102 /* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105 static inline bfd_boolean
106 vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107 {
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111 }
112
113 static inline bfd_boolean
114 fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115 {
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119 }
120
121 enum data_pattern
122 {
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128 };
129
130 static const char significant_operand_index [] =
131 {
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137 };
138
139 /* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144 static enum data_pattern
145 get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146 {
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185 }
186
187 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189 /* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195 int
196 aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197 {
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200 }
201 \f
202 const aarch64_field fields[] =
203 {
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
243 { 15, 6 }, /* imm6_2: in rmif instructions. */
244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
245 { 0, 4 }, /* imm4_2: in rmif instructions. */
246 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
247 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
248 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
249 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
250 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
251 { 5, 14 }, /* imm14: in test bit and branch instructions. */
252 { 5, 16 }, /* imm16: in exception instructions. */
253 { 0, 26 }, /* imm26: in unconditional branch instructions. */
254 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
255 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
256 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
257 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
258 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
259 { 22, 1 }, /* N: in logical (immediate) instructions. */
260 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
261 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
262 { 31, 1 }, /* sf: in integer data processing instructions. */
263 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
264 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
265 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
266 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
267 { 31, 1 }, /* b5: in the test bit and branch instructions. */
268 { 19, 5 }, /* b40: in the test bit and branch instructions. */
269 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
270 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
271 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
272 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
273 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
274 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
275 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
276 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
277 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
278 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
279 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
280 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
281 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
282 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
283 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
284 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
285 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
286 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
288 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
289 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
290 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
291 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
292 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
293 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
294 { 5, 1 }, /* SVE_i1: single-bit immediate. */
295 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
296 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
297 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
298 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
299 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
300 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
301 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
302 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
303 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
304 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
305 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
306 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
307 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
308 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
309 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
310 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
311 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
312 { 16, 4 }, /* SVE_tsz: triangular size select. */
313 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
314 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
315 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
316 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
317 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
318 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
319 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
320 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
321 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
322 };
323
324 enum aarch64_operand_class
325 aarch64_get_operand_class (enum aarch64_opnd type)
326 {
327 return aarch64_operands[type].op_class;
328 }
329
330 const char *
331 aarch64_get_operand_name (enum aarch64_opnd type)
332 {
333 return aarch64_operands[type].name;
334 }
335
336 /* Get operand description string.
337 This is usually for the diagnosis purpose. */
338 const char *
339 aarch64_get_operand_desc (enum aarch64_opnd type)
340 {
341 return aarch64_operands[type].desc;
342 }
343
344 /* Table of all conditional affixes. */
345 const aarch64_cond aarch64_conds[16] =
346 {
347 {{"eq", "none"}, 0x0},
348 {{"ne", "any"}, 0x1},
349 {{"cs", "hs", "nlast"}, 0x2},
350 {{"cc", "lo", "ul", "last"}, 0x3},
351 {{"mi", "first"}, 0x4},
352 {{"pl", "nfrst"}, 0x5},
353 {{"vs"}, 0x6},
354 {{"vc"}, 0x7},
355 {{"hi", "pmore"}, 0x8},
356 {{"ls", "plast"}, 0x9},
357 {{"ge", "tcont"}, 0xa},
358 {{"lt", "tstop"}, 0xb},
359 {{"gt"}, 0xc},
360 {{"le"}, 0xd},
361 {{"al"}, 0xe},
362 {{"nv"}, 0xf},
363 };
364
365 const aarch64_cond *
366 get_cond_from_value (aarch64_insn value)
367 {
368 assert (value < 16);
369 return &aarch64_conds[(unsigned int) value];
370 }
371
372 const aarch64_cond *
373 get_inverted_cond (const aarch64_cond *cond)
374 {
375 return &aarch64_conds[cond->value ^ 0x1];
376 }
377
378 /* Table describing the operand extension/shifting operators; indexed by
379 enum aarch64_modifier_kind.
380
381 The value column provides the most common values for encoding modifiers,
382 which enables table-driven encoding/decoding for the modifiers. */
383 const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
384 {
385 {"none", 0x0},
386 {"msl", 0x0},
387 {"ror", 0x3},
388 {"asr", 0x2},
389 {"lsr", 0x1},
390 {"lsl", 0x0},
391 {"uxtb", 0x0},
392 {"uxth", 0x1},
393 {"uxtw", 0x2},
394 {"uxtx", 0x3},
395 {"sxtb", 0x4},
396 {"sxth", 0x5},
397 {"sxtw", 0x6},
398 {"sxtx", 0x7},
399 {"mul", 0x0},
400 {"mul vl", 0x0},
401 {NULL, 0},
402 };
403
404 enum aarch64_modifier_kind
405 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
406 {
407 return desc - aarch64_operand_modifiers;
408 }
409
410 aarch64_insn
411 aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
412 {
413 return aarch64_operand_modifiers[kind].value;
414 }
415
416 enum aarch64_modifier_kind
417 aarch64_get_operand_modifier_from_value (aarch64_insn value,
418 bfd_boolean extend_p)
419 {
420 if (extend_p == TRUE)
421 return AARCH64_MOD_UXTB + value;
422 else
423 return AARCH64_MOD_LSL - value;
424 }
425
426 bfd_boolean
427 aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
428 {
429 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
430 ? TRUE : FALSE;
431 }
432
433 static inline bfd_boolean
434 aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
435 {
436 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
437 ? TRUE : FALSE;
438 }
439
440 const struct aarch64_name_value_pair aarch64_barrier_options[16] =
441 {
442 { "#0x00", 0x0 },
443 { "oshld", 0x1 },
444 { "oshst", 0x2 },
445 { "osh", 0x3 },
446 { "#0x04", 0x4 },
447 { "nshld", 0x5 },
448 { "nshst", 0x6 },
449 { "nsh", 0x7 },
450 { "#0x08", 0x8 },
451 { "ishld", 0x9 },
452 { "ishst", 0xa },
453 { "ish", 0xb },
454 { "#0x0c", 0xc },
455 { "ld", 0xd },
456 { "st", 0xe },
457 { "sy", 0xf },
458 };
459
460 /* Table describing the operands supported by the aliases of the HINT
461 instruction.
462
463 The name column is the operand that is accepted for the alias. The value
464 column is the hint number of the alias. The list of operands is terminated
465 by NULL in the name column. */
466
467 const struct aarch64_name_value_pair aarch64_hint_options[] =
468 {
469 { "csync", 0x11 }, /* PSB CSYNC. */
470 { NULL, 0x0 },
471 };
472
473 /* op -> op: load = 0 instruction = 1 store = 2
474 l -> level: 1-3
475 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
476 #define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
477 const struct aarch64_name_value_pair aarch64_prfops[32] =
478 {
479 { "pldl1keep", B(0, 1, 0) },
480 { "pldl1strm", B(0, 1, 1) },
481 { "pldl2keep", B(0, 2, 0) },
482 { "pldl2strm", B(0, 2, 1) },
483 { "pldl3keep", B(0, 3, 0) },
484 { "pldl3strm", B(0, 3, 1) },
485 { NULL, 0x06 },
486 { NULL, 0x07 },
487 { "plil1keep", B(1, 1, 0) },
488 { "plil1strm", B(1, 1, 1) },
489 { "plil2keep", B(1, 2, 0) },
490 { "plil2strm", B(1, 2, 1) },
491 { "plil3keep", B(1, 3, 0) },
492 { "plil3strm", B(1, 3, 1) },
493 { NULL, 0x0e },
494 { NULL, 0x0f },
495 { "pstl1keep", B(2, 1, 0) },
496 { "pstl1strm", B(2, 1, 1) },
497 { "pstl2keep", B(2, 2, 0) },
498 { "pstl2strm", B(2, 2, 1) },
499 { "pstl3keep", B(2, 3, 0) },
500 { "pstl3strm", B(2, 3, 1) },
501 { NULL, 0x16 },
502 { NULL, 0x17 },
503 { NULL, 0x18 },
504 { NULL, 0x19 },
505 { NULL, 0x1a },
506 { NULL, 0x1b },
507 { NULL, 0x1c },
508 { NULL, 0x1d },
509 { NULL, 0x1e },
510 { NULL, 0x1f },
511 };
512 #undef B
513 \f
514 /* Utilities on value constraint. */
515
516 static inline int
517 value_in_range_p (int64_t value, int low, int high)
518 {
519 return (value >= low && value <= high) ? 1 : 0;
520 }
521
522 /* Return true if VALUE is a multiple of ALIGN. */
523 static inline int
524 value_aligned_p (int64_t value, int align)
525 {
526 return (value % align) == 0;
527 }
528
529 /* A signed value fits in a field. */
530 static inline int
531 value_fit_signed_field_p (int64_t value, unsigned width)
532 {
533 assert (width < 32);
534 if (width < sizeof (value) * 8)
535 {
536 int64_t lim = (int64_t)1 << (width - 1);
537 if (value >= -lim && value < lim)
538 return 1;
539 }
540 return 0;
541 }
542
543 /* An unsigned value fits in a field. */
544 static inline int
545 value_fit_unsigned_field_p (int64_t value, unsigned width)
546 {
547 assert (width < 32);
548 if (width < sizeof (value) * 8)
549 {
550 int64_t lim = (int64_t)1 << width;
551 if (value >= 0 && value < lim)
552 return 1;
553 }
554 return 0;
555 }
556
557 /* Return 1 if OPERAND is SP or WSP. */
558 int
559 aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
560 {
561 return ((aarch64_get_operand_class (operand->type)
562 == AARCH64_OPND_CLASS_INT_REG)
563 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
564 && operand->reg.regno == 31);
565 }
566
567 /* Return 1 if OPERAND is XZR or WZP. */
568 int
569 aarch64_zero_register_p (const aarch64_opnd_info *operand)
570 {
571 return ((aarch64_get_operand_class (operand->type)
572 == AARCH64_OPND_CLASS_INT_REG)
573 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
574 && operand->reg.regno == 31);
575 }
576
577 /* Return true if the operand *OPERAND that has the operand code
578 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
579 qualified by the qualifier TARGET. */
580
581 static inline int
582 operand_also_qualified_p (const struct aarch64_opnd_info *operand,
583 aarch64_opnd_qualifier_t target)
584 {
585 switch (operand->qualifier)
586 {
587 case AARCH64_OPND_QLF_W:
588 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
589 return 1;
590 break;
591 case AARCH64_OPND_QLF_X:
592 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
593 return 1;
594 break;
595 case AARCH64_OPND_QLF_WSP:
596 if (target == AARCH64_OPND_QLF_W
597 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
598 return 1;
599 break;
600 case AARCH64_OPND_QLF_SP:
601 if (target == AARCH64_OPND_QLF_X
602 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
603 return 1;
604 break;
605 default:
606 break;
607 }
608
609 return 0;
610 }
611
612 /* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
613 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
614
615 Return NIL if more than one expected qualifiers are found. */
616
617 aarch64_opnd_qualifier_t
618 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
619 int idx,
620 const aarch64_opnd_qualifier_t known_qlf,
621 int known_idx)
622 {
623 int i, saved_i;
624
625 /* Special case.
626
627 When the known qualifier is NIL, we have to assume that there is only
628 one qualifier sequence in the *QSEQ_LIST and return the corresponding
629 qualifier directly. One scenario is that for instruction
630 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
631 which has only one possible valid qualifier sequence
632 NIL, S_D
633 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
634 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
635
636 Because the qualifier NIL has dual roles in the qualifier sequence:
637 it can mean no qualifier for the operand, or the qualifer sequence is
638 not in use (when all qualifiers in the sequence are NILs), we have to
639 handle this special case here. */
640 if (known_qlf == AARCH64_OPND_NIL)
641 {
642 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
643 return qseq_list[0][idx];
644 }
645
646 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
647 {
648 if (qseq_list[i][known_idx] == known_qlf)
649 {
650 if (saved_i != -1)
651 /* More than one sequences are found to have KNOWN_QLF at
652 KNOWN_IDX. */
653 return AARCH64_OPND_NIL;
654 saved_i = i;
655 }
656 }
657
658 return qseq_list[saved_i][idx];
659 }
660
661 enum operand_qualifier_kind
662 {
663 OQK_NIL,
664 OQK_OPD_VARIANT,
665 OQK_VALUE_IN_RANGE,
666 OQK_MISC,
667 };
668
669 /* Operand qualifier description. */
670 struct operand_qualifier_data
671 {
672 /* The usage of the three data fields depends on the qualifier kind. */
673 int data0;
674 int data1;
675 int data2;
676 /* Description. */
677 const char *desc;
678 /* Kind. */
679 enum operand_qualifier_kind kind;
680 };
681
682 /* Indexed by the operand qualifier enumerators. */
683 struct operand_qualifier_data aarch64_opnd_qualifiers[] =
684 {
685 {0, 0, 0, "NIL", OQK_NIL},
686
687 /* Operand variant qualifiers.
688 First 3 fields:
689 element size, number of elements and common value for encoding. */
690
691 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
692 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
693 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
694 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
695
696 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
697 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
698 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
699 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
700 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
701 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
702
703 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
704 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
705 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
706 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
707 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
708 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
709 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
710 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
711 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
712 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
713 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
714
715 {0, 0, 0, "z", OQK_OPD_VARIANT},
716 {0, 0, 0, "m", OQK_OPD_VARIANT},
717
718 /* Qualifiers constraining the value range.
719 First 3 fields:
720 Lower bound, higher bound, unused. */
721
722 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
723 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
724 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
725 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
726 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
727 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
728 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
729
730 /* Qualifiers for miscellaneous purpose.
731 First 3 fields:
732 unused, unused and unused. */
733
734 {0, 0, 0, "lsl", 0},
735 {0, 0, 0, "msl", 0},
736
737 {0, 0, 0, "retrieving", 0},
738 };
739
740 static inline bfd_boolean
741 operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
742 {
743 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
744 ? TRUE : FALSE;
745 }
746
747 static inline bfd_boolean
748 qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
749 {
750 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
751 ? TRUE : FALSE;
752 }
753
754 const char*
755 aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
756 {
757 return aarch64_opnd_qualifiers[qualifier].desc;
758 }
759
760 /* Given an operand qualifier, return the expected data element size
761 of a qualified operand. */
762 unsigned char
763 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
764 {
765 assert (operand_variant_qualifier_p (qualifier) == TRUE);
766 return aarch64_opnd_qualifiers[qualifier].data0;
767 }
768
769 unsigned char
770 aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
771 {
772 assert (operand_variant_qualifier_p (qualifier) == TRUE);
773 return aarch64_opnd_qualifiers[qualifier].data1;
774 }
775
776 aarch64_insn
777 aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
778 {
779 assert (operand_variant_qualifier_p (qualifier) == TRUE);
780 return aarch64_opnd_qualifiers[qualifier].data2;
781 }
782
783 static int
784 get_lower_bound (aarch64_opnd_qualifier_t qualifier)
785 {
786 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
787 return aarch64_opnd_qualifiers[qualifier].data0;
788 }
789
790 static int
791 get_upper_bound (aarch64_opnd_qualifier_t qualifier)
792 {
793 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
794 return aarch64_opnd_qualifiers[qualifier].data1;
795 }
796
797 #ifdef DEBUG_AARCH64
798 void
799 aarch64_verbose (const char *str, ...)
800 {
801 va_list ap;
802 va_start (ap, str);
803 printf ("#### ");
804 vprintf (str, ap);
805 printf ("\n");
806 va_end (ap);
807 }
808
809 static inline void
810 dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
811 {
812 int i;
813 printf ("#### \t");
814 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
815 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
816 printf ("\n");
817 }
818
819 static void
820 dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
821 const aarch64_opnd_qualifier_t *qualifier)
822 {
823 int i;
824 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
825
826 aarch64_verbose ("dump_match_qualifiers:");
827 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
828 curr[i] = opnd[i].qualifier;
829 dump_qualifier_sequence (curr);
830 aarch64_verbose ("against");
831 dump_qualifier_sequence (qualifier);
832 }
833 #endif /* DEBUG_AARCH64 */
834
835 /* This function checks if the given instruction INSN is a destructive
836 instruction based on the usage of the registers. It does not recognize
837 unary destructive instructions. */
838 bfd_boolean
839 aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
840 {
841 int i = 0;
842 const enum aarch64_opnd *opnds = opcode->operands;
843
844 if (opnds[0] == AARCH64_OPND_NIL)
845 return FALSE;
846
847 while (opnds[++i] != AARCH64_OPND_NIL)
848 if (opnds[i] == opnds[0])
849 return TRUE;
850
851 return FALSE;
852 }
853
854 /* TODO improve this, we can have an extra field at the runtime to
855 store the number of operands rather than calculating it every time. */
856
857 int
858 aarch64_num_of_operands (const aarch64_opcode *opcode)
859 {
860 int i = 0;
861 const enum aarch64_opnd *opnds = opcode->operands;
862 while (opnds[i++] != AARCH64_OPND_NIL)
863 ;
864 --i;
865 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
866 return i;
867 }
868
869 /* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
870 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
871
872 N.B. on the entry, it is very likely that only some operands in *INST
873 have had their qualifiers been established.
874
875 If STOP_AT is not -1, the function will only try to match
876 the qualifier sequence for operands before and including the operand
877 of index STOP_AT; and on success *RET will only be filled with the first
878 (STOP_AT+1) qualifiers.
879
880 A couple examples of the matching algorithm:
881
882 X,W,NIL should match
883 X,W,NIL
884
885 NIL,NIL should match
886 X ,NIL
887
888 Apart from serving the main encoding routine, this can also be called
889 during or after the operand decoding. */
890
891 int
892 aarch64_find_best_match (const aarch64_inst *inst,
893 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
894 int stop_at, aarch64_opnd_qualifier_t *ret)
895 {
896 int found = 0;
897 int i, num_opnds;
898 const aarch64_opnd_qualifier_t *qualifiers;
899
900 num_opnds = aarch64_num_of_operands (inst->opcode);
901 if (num_opnds == 0)
902 {
903 DEBUG_TRACE ("SUCCEED: no operand");
904 return 1;
905 }
906
907 if (stop_at < 0 || stop_at >= num_opnds)
908 stop_at = num_opnds - 1;
909
910 /* For each pattern. */
911 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
912 {
913 int j;
914 qualifiers = *qualifiers_list;
915
916 /* Start as positive. */
917 found = 1;
918
919 DEBUG_TRACE ("%d", i);
920 #ifdef DEBUG_AARCH64
921 if (debug_dump)
922 dump_match_qualifiers (inst->operands, qualifiers);
923 #endif
924
925 /* Most opcodes has much fewer patterns in the list.
926 First NIL qualifier indicates the end in the list. */
927 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
928 {
929 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
930 if (i)
931 found = 0;
932 break;
933 }
934
935 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
936 {
937 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
938 {
939 /* Either the operand does not have qualifier, or the qualifier
940 for the operand needs to be deduced from the qualifier
941 sequence.
942 In the latter case, any constraint checking related with
943 the obtained qualifier should be done later in
944 operand_general_constraint_met_p. */
945 continue;
946 }
947 else if (*qualifiers != inst->operands[j].qualifier)
948 {
949 /* Unless the target qualifier can also qualify the operand
950 (which has already had a non-nil qualifier), non-equal
951 qualifiers are generally un-matched. */
952 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
953 continue;
954 else
955 {
956 found = 0;
957 break;
958 }
959 }
960 else
961 continue; /* Equal qualifiers are certainly matched. */
962 }
963
964 /* Qualifiers established. */
965 if (found == 1)
966 break;
967 }
968
969 if (found == 1)
970 {
971 /* Fill the result in *RET. */
972 int j;
973 qualifiers = *qualifiers_list;
974
975 DEBUG_TRACE ("complete qualifiers using list %d", i);
976 #ifdef DEBUG_AARCH64
977 if (debug_dump)
978 dump_qualifier_sequence (qualifiers);
979 #endif
980
981 for (j = 0; j <= stop_at; ++j, ++qualifiers)
982 ret[j] = *qualifiers;
983 for (; j < AARCH64_MAX_OPND_NUM; ++j)
984 ret[j] = AARCH64_OPND_QLF_NIL;
985
986 DEBUG_TRACE ("SUCCESS");
987 return 1;
988 }
989
990 DEBUG_TRACE ("FAIL");
991 return 0;
992 }
993
994 /* Operand qualifier matching and resolving.
995
996 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
997 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
998
999 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1000 succeeds. */
1001
1002 static int
1003 match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1004 {
1005 int i, nops;
1006 aarch64_opnd_qualifier_seq_t qualifiers;
1007
1008 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1009 qualifiers))
1010 {
1011 DEBUG_TRACE ("matching FAIL");
1012 return 0;
1013 }
1014
1015 if (inst->opcode->flags & F_STRICT)
1016 {
1017 /* Require an exact qualifier match, even for NIL qualifiers. */
1018 nops = aarch64_num_of_operands (inst->opcode);
1019 for (i = 0; i < nops; ++i)
1020 if (inst->operands[i].qualifier != qualifiers[i])
1021 return FALSE;
1022 }
1023
1024 /* Update the qualifiers. */
1025 if (update_p == TRUE)
1026 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1027 {
1028 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1029 break;
1030 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1031 "update %s with %s for operand %d",
1032 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1033 aarch64_get_qualifier_name (qualifiers[i]), i);
1034 inst->operands[i].qualifier = qualifiers[i];
1035 }
1036
1037 DEBUG_TRACE ("matching SUCCESS");
1038 return 1;
1039 }
1040
1041 /* Return TRUE if VALUE is a wide constant that can be moved into a general
1042 register by MOVZ.
1043
1044 IS32 indicates whether value is a 32-bit immediate or not.
1045 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1046 amount will be returned in *SHIFT_AMOUNT. */
1047
1048 bfd_boolean
1049 aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1050 {
1051 int amount;
1052
1053 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1054
1055 if (is32)
1056 {
1057 /* Allow all zeros or all ones in top 32-bits, so that
1058 32-bit constant expressions like ~0x80000000 are
1059 permitted. */
1060 uint64_t ext = value;
1061 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1062 /* Immediate out of range. */
1063 return FALSE;
1064 value &= (int64_t) 0xffffffff;
1065 }
1066
1067 /* first, try movz then movn */
1068 amount = -1;
1069 if ((value & ((int64_t) 0xffff << 0)) == value)
1070 amount = 0;
1071 else if ((value & ((int64_t) 0xffff << 16)) == value)
1072 amount = 16;
1073 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1074 amount = 32;
1075 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1076 amount = 48;
1077
1078 if (amount == -1)
1079 {
1080 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1081 return FALSE;
1082 }
1083
1084 if (shift_amount != NULL)
1085 *shift_amount = amount;
1086
1087 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1088
1089 return TRUE;
1090 }
1091
1092 /* Build the accepted values for immediate logical SIMD instructions.
1093
1094 The standard encodings of the immediate value are:
1095 N imms immr SIMD size R S
1096 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1097 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1098 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1099 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1100 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1101 0 11110s 00000r 2 UInt(r) UInt(s)
1102 where all-ones value of S is reserved.
1103
1104 Let's call E the SIMD size.
1105
1106 The immediate value is: S+1 bits '1' rotated to the right by R.
1107
1108 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1109 (remember S != E - 1). */
1110
1111 #define TOTAL_IMM_NB 5334
1112
1113 typedef struct
1114 {
1115 uint64_t imm;
1116 aarch64_insn encoding;
1117 } simd_imm_encoding;
1118
1119 static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1120
1121 static int
1122 simd_imm_encoding_cmp(const void *i1, const void *i2)
1123 {
1124 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1125 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1126
1127 if (imm1->imm < imm2->imm)
1128 return -1;
1129 if (imm1->imm > imm2->imm)
1130 return +1;
1131 return 0;
1132 }
1133
1134 /* immediate bitfield standard encoding
1135 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1136 1 ssssss rrrrrr 64 rrrrrr ssssss
1137 0 0sssss 0rrrrr 32 rrrrr sssss
1138 0 10ssss 00rrrr 16 rrrr ssss
1139 0 110sss 000rrr 8 rrr sss
1140 0 1110ss 0000rr 4 rr ss
1141 0 11110s 00000r 2 r s */
1142 static inline int
1143 encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1144 {
1145 return (is64 << 12) | (r << 6) | s;
1146 }
1147
1148 static void
1149 build_immediate_table (void)
1150 {
1151 uint32_t log_e, e, s, r, s_mask;
1152 uint64_t mask, imm;
1153 int nb_imms;
1154 int is64;
1155
1156 nb_imms = 0;
1157 for (log_e = 1; log_e <= 6; log_e++)
1158 {
1159 /* Get element size. */
1160 e = 1u << log_e;
1161 if (log_e == 6)
1162 {
1163 is64 = 1;
1164 mask = 0xffffffffffffffffull;
1165 s_mask = 0;
1166 }
1167 else
1168 {
1169 is64 = 0;
1170 mask = (1ull << e) - 1;
1171 /* log_e s_mask
1172 1 ((1 << 4) - 1) << 2 = 111100
1173 2 ((1 << 3) - 1) << 3 = 111000
1174 3 ((1 << 2) - 1) << 4 = 110000
1175 4 ((1 << 1) - 1) << 5 = 100000
1176 5 ((1 << 0) - 1) << 6 = 000000 */
1177 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1178 }
1179 for (s = 0; s < e - 1; s++)
1180 for (r = 0; r < e; r++)
1181 {
1182 /* s+1 consecutive bits to 1 (s < 63) */
1183 imm = (1ull << (s + 1)) - 1;
1184 /* rotate right by r */
1185 if (r != 0)
1186 imm = (imm >> r) | ((imm << (e - r)) & mask);
1187 /* replicate the constant depending on SIMD size */
1188 switch (log_e)
1189 {
1190 case 1: imm = (imm << 2) | imm;
1191 /* Fall through. */
1192 case 2: imm = (imm << 4) | imm;
1193 /* Fall through. */
1194 case 3: imm = (imm << 8) | imm;
1195 /* Fall through. */
1196 case 4: imm = (imm << 16) | imm;
1197 /* Fall through. */
1198 case 5: imm = (imm << 32) | imm;
1199 /* Fall through. */
1200 case 6: break;
1201 default: abort ();
1202 }
1203 simd_immediates[nb_imms].imm = imm;
1204 simd_immediates[nb_imms].encoding =
1205 encode_immediate_bitfield(is64, s | s_mask, r);
1206 nb_imms++;
1207 }
1208 }
1209 assert (nb_imms == TOTAL_IMM_NB);
1210 qsort(simd_immediates, nb_imms,
1211 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1212 }
1213
1214 /* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1215 be accepted by logical (immediate) instructions
1216 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1217
1218 ESIZE is the number of bytes in the decoded immediate value.
1219 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1220 VALUE will be returned in *ENCODING. */
1221
1222 bfd_boolean
1223 aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
1224 {
1225 simd_imm_encoding imm_enc;
1226 const simd_imm_encoding *imm_encoding;
1227 static bfd_boolean initialized = FALSE;
1228 uint64_t upper;
1229 int i;
1230
1231 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1232 value, esize);
1233
1234 if (!initialized)
1235 {
1236 build_immediate_table ();
1237 initialized = TRUE;
1238 }
1239
1240 /* Allow all zeros or all ones in top bits, so that
1241 constant expressions like ~1 are permitted. */
1242 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1243 if ((value & ~upper) != value && (value | upper) != value)
1244 return FALSE;
1245
1246 /* Replicate to a full 64-bit value. */
1247 value &= ~upper;
1248 for (i = esize * 8; i < 64; i *= 2)
1249 value |= (value << i);
1250
1251 imm_enc.imm = value;
1252 imm_encoding = (const simd_imm_encoding *)
1253 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1254 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1255 if (imm_encoding == NULL)
1256 {
1257 DEBUG_TRACE ("exit with FALSE");
1258 return FALSE;
1259 }
1260 if (encoding != NULL)
1261 *encoding = imm_encoding->encoding;
1262 DEBUG_TRACE ("exit with TRUE");
1263 return TRUE;
1264 }
1265
1266 /* If 64-bit immediate IMM is in the format of
1267 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1268 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1269 of value "abcdefgh". Otherwise return -1. */
1270 int
1271 aarch64_shrink_expanded_imm8 (uint64_t imm)
1272 {
1273 int i, ret;
1274 uint32_t byte;
1275
1276 ret = 0;
1277 for (i = 0; i < 8; i++)
1278 {
1279 byte = (imm >> (8 * i)) & 0xff;
1280 if (byte == 0xff)
1281 ret |= 1 << i;
1282 else if (byte != 0x00)
1283 return -1;
1284 }
1285 return ret;
1286 }
1287
1288 /* Utility inline functions for operand_general_constraint_met_p. */
1289
1290 static inline void
1291 set_error (aarch64_operand_error *mismatch_detail,
1292 enum aarch64_operand_error_kind kind, int idx,
1293 const char* error)
1294 {
1295 if (mismatch_detail == NULL)
1296 return;
1297 mismatch_detail->kind = kind;
1298 mismatch_detail->index = idx;
1299 mismatch_detail->error = error;
1300 }
1301
1302 static inline void
1303 set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1304 const char* error)
1305 {
1306 if (mismatch_detail == NULL)
1307 return;
1308 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1309 }
1310
1311 static inline void
1312 set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1313 int idx, int lower_bound, int upper_bound,
1314 const char* error)
1315 {
1316 if (mismatch_detail == NULL)
1317 return;
1318 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1319 mismatch_detail->data[0] = lower_bound;
1320 mismatch_detail->data[1] = upper_bound;
1321 }
1322
1323 static inline void
1324 set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1325 int idx, int lower_bound, int upper_bound)
1326 {
1327 if (mismatch_detail == NULL)
1328 return;
1329 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1330 _("immediate value"));
1331 }
1332
1333 static inline void
1334 set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1335 int idx, int lower_bound, int upper_bound)
1336 {
1337 if (mismatch_detail == NULL)
1338 return;
1339 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1340 _("immediate offset"));
1341 }
1342
1343 static inline void
1344 set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1345 int idx, int lower_bound, int upper_bound)
1346 {
1347 if (mismatch_detail == NULL)
1348 return;
1349 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1350 _("register number"));
1351 }
1352
1353 static inline void
1354 set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1355 int idx, int lower_bound, int upper_bound)
1356 {
1357 if (mismatch_detail == NULL)
1358 return;
1359 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1360 _("register element index"));
1361 }
1362
1363 static inline void
1364 set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1365 int idx, int lower_bound, int upper_bound)
1366 {
1367 if (mismatch_detail == NULL)
1368 return;
1369 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1370 _("shift amount"));
1371 }
1372
1373 /* Report that the MUL modifier in operand IDX should be in the range
1374 [LOWER_BOUND, UPPER_BOUND]. */
1375 static inline void
1376 set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1377 int idx, int lower_bound, int upper_bound)
1378 {
1379 if (mismatch_detail == NULL)
1380 return;
1381 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1382 _("multiplier"));
1383 }
1384
1385 static inline void
1386 set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1387 int alignment)
1388 {
1389 if (mismatch_detail == NULL)
1390 return;
1391 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1392 mismatch_detail->data[0] = alignment;
1393 }
1394
1395 static inline void
1396 set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1397 int expected_num)
1398 {
1399 if (mismatch_detail == NULL)
1400 return;
1401 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1402 mismatch_detail->data[0] = expected_num;
1403 }
1404
1405 static inline void
1406 set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1407 const char* error)
1408 {
1409 if (mismatch_detail == NULL)
1410 return;
1411 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1412 }
1413
1414 /* General constraint checking based on operand code.
1415
1416 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1417 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1418
1419 This function has to be called after the qualifiers for all operands
1420 have been resolved.
1421
1422 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1423 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1424 of error message during the disassembling where error message is not
1425 wanted. We avoid the dynamic construction of strings of error messages
1426 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1427 use a combination of error code, static string and some integer data to
1428 represent an error. */
1429
1430 static int
1431 operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1432 enum aarch64_opnd type,
1433 const aarch64_opcode *opcode,
1434 aarch64_operand_error *mismatch_detail)
1435 {
1436 unsigned num, modifiers, shift;
1437 unsigned char size;
1438 int64_t imm, min_value, max_value;
1439 uint64_t uvalue, mask;
1440 const aarch64_opnd_info *opnd = opnds + idx;
1441 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1442
1443 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1444
1445 switch (aarch64_operands[type].op_class)
1446 {
1447 case AARCH64_OPND_CLASS_INT_REG:
1448 /* Check pair reg constraints for cas* instructions. */
1449 if (type == AARCH64_OPND_PAIRREG)
1450 {
1451 assert (idx == 1 || idx == 3);
1452 if (opnds[idx - 1].reg.regno % 2 != 0)
1453 {
1454 set_syntax_error (mismatch_detail, idx - 1,
1455 _("reg pair must start from even reg"));
1456 return 0;
1457 }
1458 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1459 {
1460 set_syntax_error (mismatch_detail, idx,
1461 _("reg pair must be contiguous"));
1462 return 0;
1463 }
1464 break;
1465 }
1466
1467 /* <Xt> may be optional in some IC and TLBI instructions. */
1468 if (type == AARCH64_OPND_Rt_SYS)
1469 {
1470 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1471 == AARCH64_OPND_CLASS_SYSTEM));
1472 if (opnds[1].present
1473 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1474 {
1475 set_other_error (mismatch_detail, idx, _("extraneous register"));
1476 return 0;
1477 }
1478 if (!opnds[1].present
1479 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1480 {
1481 set_other_error (mismatch_detail, idx, _("missing register"));
1482 return 0;
1483 }
1484 }
1485 switch (qualifier)
1486 {
1487 case AARCH64_OPND_QLF_WSP:
1488 case AARCH64_OPND_QLF_SP:
1489 if (!aarch64_stack_pointer_p (opnd))
1490 {
1491 set_other_error (mismatch_detail, idx,
1492 _("stack pointer register expected"));
1493 return 0;
1494 }
1495 break;
1496 default:
1497 break;
1498 }
1499 break;
1500
1501 case AARCH64_OPND_CLASS_SVE_REG:
1502 switch (type)
1503 {
1504 case AARCH64_OPND_SVE_Zm3_INDEX:
1505 case AARCH64_OPND_SVE_Zm3_22_INDEX:
1506 case AARCH64_OPND_SVE_Zm4_INDEX:
1507 size = get_operand_fields_width (get_operand_from_code (type));
1508 shift = get_operand_specific_data (&aarch64_operands[type]);
1509 mask = (1 << shift) - 1;
1510 if (opnd->reg.regno > mask)
1511 {
1512 assert (mask == 7 || mask == 15);
1513 set_other_error (mismatch_detail, idx,
1514 mask == 15
1515 ? _("z0-z15 expected")
1516 : _("z0-z7 expected"));
1517 return 0;
1518 }
1519 mask = (1 << (size - shift)) - 1;
1520 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1521 {
1522 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1523 return 0;
1524 }
1525 break;
1526
1527 case AARCH64_OPND_SVE_Zn_INDEX:
1528 size = aarch64_get_qualifier_esize (opnd->qualifier);
1529 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1530 {
1531 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1532 0, 64 / size - 1);
1533 return 0;
1534 }
1535 break;
1536
1537 case AARCH64_OPND_SVE_ZnxN:
1538 case AARCH64_OPND_SVE_ZtxN:
1539 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1540 {
1541 set_other_error (mismatch_detail, idx,
1542 _("invalid register list"));
1543 return 0;
1544 }
1545 break;
1546
1547 default:
1548 break;
1549 }
1550 break;
1551
1552 case AARCH64_OPND_CLASS_PRED_REG:
1553 if (opnd->reg.regno >= 8
1554 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1555 {
1556 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1557 return 0;
1558 }
1559 break;
1560
1561 case AARCH64_OPND_CLASS_COND:
1562 if (type == AARCH64_OPND_COND1
1563 && (opnds[idx].cond->value & 0xe) == 0xe)
1564 {
1565 /* Not allow AL or NV. */
1566 set_syntax_error (mismatch_detail, idx, NULL);
1567 }
1568 break;
1569
1570 case AARCH64_OPND_CLASS_ADDRESS:
1571 /* Check writeback. */
1572 switch (opcode->iclass)
1573 {
1574 case ldst_pos:
1575 case ldst_unscaled:
1576 case ldstnapair_offs:
1577 case ldstpair_off:
1578 case ldst_unpriv:
1579 if (opnd->addr.writeback == 1)
1580 {
1581 set_syntax_error (mismatch_detail, idx,
1582 _("unexpected address writeback"));
1583 return 0;
1584 }
1585 break;
1586 case ldst_imm10:
1587 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1588 {
1589 set_syntax_error (mismatch_detail, idx,
1590 _("unexpected address writeback"));
1591 return 0;
1592 }
1593 break;
1594 case ldst_imm9:
1595 case ldstpair_indexed:
1596 case asisdlsep:
1597 case asisdlsop:
1598 if (opnd->addr.writeback == 0)
1599 {
1600 set_syntax_error (mismatch_detail, idx,
1601 _("address writeback expected"));
1602 return 0;
1603 }
1604 break;
1605 default:
1606 assert (opnd->addr.writeback == 0);
1607 break;
1608 }
1609 switch (type)
1610 {
1611 case AARCH64_OPND_ADDR_SIMM7:
1612 /* Scaled signed 7 bits immediate offset. */
1613 /* Get the size of the data element that is accessed, which may be
1614 different from that of the source register size,
1615 e.g. in strb/ldrb. */
1616 size = aarch64_get_qualifier_esize (opnd->qualifier);
1617 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1618 {
1619 set_offset_out_of_range_error (mismatch_detail, idx,
1620 -64 * size, 63 * size);
1621 return 0;
1622 }
1623 if (!value_aligned_p (opnd->addr.offset.imm, size))
1624 {
1625 set_unaligned_error (mismatch_detail, idx, size);
1626 return 0;
1627 }
1628 break;
1629 case AARCH64_OPND_ADDR_OFFSET:
1630 case AARCH64_OPND_ADDR_SIMM9:
1631 /* Unscaled signed 9 bits immediate offset. */
1632 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1633 {
1634 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1635 return 0;
1636 }
1637 break;
1638
1639 case AARCH64_OPND_ADDR_SIMM9_2:
1640 /* Unscaled signed 9 bits immediate offset, which has to be negative
1641 or unaligned. */
1642 size = aarch64_get_qualifier_esize (qualifier);
1643 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1644 && !value_aligned_p (opnd->addr.offset.imm, size))
1645 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1646 return 1;
1647 set_other_error (mismatch_detail, idx,
1648 _("negative or unaligned offset expected"));
1649 return 0;
1650
1651 case AARCH64_OPND_ADDR_SIMM10:
1652 /* Scaled signed 10 bits immediate offset. */
1653 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1654 {
1655 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1656 return 0;
1657 }
1658 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1659 {
1660 set_unaligned_error (mismatch_detail, idx, 8);
1661 return 0;
1662 }
1663 break;
1664
1665 case AARCH64_OPND_SIMD_ADDR_POST:
1666 /* AdvSIMD load/store multiple structures, post-index. */
1667 assert (idx == 1);
1668 if (opnd->addr.offset.is_reg)
1669 {
1670 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1671 return 1;
1672 else
1673 {
1674 set_other_error (mismatch_detail, idx,
1675 _("invalid register offset"));
1676 return 0;
1677 }
1678 }
1679 else
1680 {
1681 const aarch64_opnd_info *prev = &opnds[idx-1];
1682 unsigned num_bytes; /* total number of bytes transferred. */
1683 /* The opcode dependent area stores the number of elements in
1684 each structure to be loaded/stored. */
1685 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1686 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1687 /* Special handling of loading single structure to all lane. */
1688 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1689 * aarch64_get_qualifier_esize (prev->qualifier);
1690 else
1691 num_bytes = prev->reglist.num_regs
1692 * aarch64_get_qualifier_esize (prev->qualifier)
1693 * aarch64_get_qualifier_nelem (prev->qualifier);
1694 if ((int) num_bytes != opnd->addr.offset.imm)
1695 {
1696 set_other_error (mismatch_detail, idx,
1697 _("invalid post-increment amount"));
1698 return 0;
1699 }
1700 }
1701 break;
1702
1703 case AARCH64_OPND_ADDR_REGOFF:
1704 /* Get the size of the data element that is accessed, which may be
1705 different from that of the source register size,
1706 e.g. in strb/ldrb. */
1707 size = aarch64_get_qualifier_esize (opnd->qualifier);
1708 /* It is either no shift or shift by the binary logarithm of SIZE. */
1709 if (opnd->shifter.amount != 0
1710 && opnd->shifter.amount != (int)get_logsz (size))
1711 {
1712 set_other_error (mismatch_detail, idx,
1713 _("invalid shift amount"));
1714 return 0;
1715 }
1716 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1717 operators. */
1718 switch (opnd->shifter.kind)
1719 {
1720 case AARCH64_MOD_UXTW:
1721 case AARCH64_MOD_LSL:
1722 case AARCH64_MOD_SXTW:
1723 case AARCH64_MOD_SXTX: break;
1724 default:
1725 set_other_error (mismatch_detail, idx,
1726 _("invalid extend/shift operator"));
1727 return 0;
1728 }
1729 break;
1730
1731 case AARCH64_OPND_ADDR_UIMM12:
1732 imm = opnd->addr.offset.imm;
1733 /* Get the size of the data element that is accessed, which may be
1734 different from that of the source register size,
1735 e.g. in strb/ldrb. */
1736 size = aarch64_get_qualifier_esize (qualifier);
1737 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1738 {
1739 set_offset_out_of_range_error (mismatch_detail, idx,
1740 0, 4095 * size);
1741 return 0;
1742 }
1743 if (!value_aligned_p (opnd->addr.offset.imm, size))
1744 {
1745 set_unaligned_error (mismatch_detail, idx, size);
1746 return 0;
1747 }
1748 break;
1749
1750 case AARCH64_OPND_ADDR_PCREL14:
1751 case AARCH64_OPND_ADDR_PCREL19:
1752 case AARCH64_OPND_ADDR_PCREL21:
1753 case AARCH64_OPND_ADDR_PCREL26:
1754 imm = opnd->imm.value;
1755 if (operand_need_shift_by_two (get_operand_from_code (type)))
1756 {
1757 /* The offset value in a PC-relative branch instruction is alway
1758 4-byte aligned and is encoded without the lowest 2 bits. */
1759 if (!value_aligned_p (imm, 4))
1760 {
1761 set_unaligned_error (mismatch_detail, idx, 4);
1762 return 0;
1763 }
1764 /* Right shift by 2 so that we can carry out the following check
1765 canonically. */
1766 imm >>= 2;
1767 }
1768 size = get_operand_fields_width (get_operand_from_code (type));
1769 if (!value_fit_signed_field_p (imm, size))
1770 {
1771 set_other_error (mismatch_detail, idx,
1772 _("immediate out of range"));
1773 return 0;
1774 }
1775 break;
1776
1777 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1778 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1779 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1780 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1781 min_value = -8;
1782 max_value = 7;
1783 sve_imm_offset_vl:
1784 assert (!opnd->addr.offset.is_reg);
1785 assert (opnd->addr.preind);
1786 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1787 min_value *= num;
1788 max_value *= num;
1789 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1790 || (opnd->shifter.operator_present
1791 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1792 {
1793 set_other_error (mismatch_detail, idx,
1794 _("invalid addressing mode"));
1795 return 0;
1796 }
1797 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1798 {
1799 set_offset_out_of_range_error (mismatch_detail, idx,
1800 min_value, max_value);
1801 return 0;
1802 }
1803 if (!value_aligned_p (opnd->addr.offset.imm, num))
1804 {
1805 set_unaligned_error (mismatch_detail, idx, num);
1806 return 0;
1807 }
1808 break;
1809
1810 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1811 min_value = -32;
1812 max_value = 31;
1813 goto sve_imm_offset_vl;
1814
1815 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1816 min_value = -256;
1817 max_value = 255;
1818 goto sve_imm_offset_vl;
1819
1820 case AARCH64_OPND_SVE_ADDR_RI_U6:
1821 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1822 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1823 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1824 min_value = 0;
1825 max_value = 63;
1826 sve_imm_offset:
1827 assert (!opnd->addr.offset.is_reg);
1828 assert (opnd->addr.preind);
1829 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1830 min_value *= num;
1831 max_value *= num;
1832 if (opnd->shifter.operator_present
1833 || opnd->shifter.amount_present)
1834 {
1835 set_other_error (mismatch_detail, idx,
1836 _("invalid addressing mode"));
1837 return 0;
1838 }
1839 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1840 {
1841 set_offset_out_of_range_error (mismatch_detail, idx,
1842 min_value, max_value);
1843 return 0;
1844 }
1845 if (!value_aligned_p (opnd->addr.offset.imm, num))
1846 {
1847 set_unaligned_error (mismatch_detail, idx, num);
1848 return 0;
1849 }
1850 break;
1851
1852 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
1853 min_value = -8;
1854 max_value = 7;
1855 goto sve_imm_offset;
1856
1857 case AARCH64_OPND_SVE_ADDR_R:
1858 case AARCH64_OPND_SVE_ADDR_RR:
1859 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1860 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1861 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1862 case AARCH64_OPND_SVE_ADDR_RX:
1863 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1864 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1865 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1866 case AARCH64_OPND_SVE_ADDR_RZ:
1867 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1868 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1869 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1870 modifiers = 1 << AARCH64_MOD_LSL;
1871 sve_rr_operand:
1872 assert (opnd->addr.offset.is_reg);
1873 assert (opnd->addr.preind);
1874 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1875 && opnd->addr.offset.regno == 31)
1876 {
1877 set_other_error (mismatch_detail, idx,
1878 _("index register xzr is not allowed"));
1879 return 0;
1880 }
1881 if (((1 << opnd->shifter.kind) & modifiers) == 0
1882 || (opnd->shifter.amount
1883 != get_operand_specific_data (&aarch64_operands[type])))
1884 {
1885 set_other_error (mismatch_detail, idx,
1886 _("invalid addressing mode"));
1887 return 0;
1888 }
1889 break;
1890
1891 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1892 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1893 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1894 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1895 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1896 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1897 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1898 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1899 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1900 goto sve_rr_operand;
1901
1902 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1903 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1904 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1905 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1906 min_value = 0;
1907 max_value = 31;
1908 goto sve_imm_offset;
1909
1910 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1911 modifiers = 1 << AARCH64_MOD_LSL;
1912 sve_zz_operand:
1913 assert (opnd->addr.offset.is_reg);
1914 assert (opnd->addr.preind);
1915 if (((1 << opnd->shifter.kind) & modifiers) == 0
1916 || opnd->shifter.amount < 0
1917 || opnd->shifter.amount > 3)
1918 {
1919 set_other_error (mismatch_detail, idx,
1920 _("invalid addressing mode"));
1921 return 0;
1922 }
1923 break;
1924
1925 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1926 modifiers = (1 << AARCH64_MOD_SXTW);
1927 goto sve_zz_operand;
1928
1929 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1930 modifiers = 1 << AARCH64_MOD_UXTW;
1931 goto sve_zz_operand;
1932
1933 default:
1934 break;
1935 }
1936 break;
1937
1938 case AARCH64_OPND_CLASS_SIMD_REGLIST:
1939 if (type == AARCH64_OPND_LEt)
1940 {
1941 /* Get the upper bound for the element index. */
1942 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
1943 if (!value_in_range_p (opnd->reglist.index, 0, num))
1944 {
1945 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
1946 return 0;
1947 }
1948 }
1949 /* The opcode dependent area stores the number of elements in
1950 each structure to be loaded/stored. */
1951 num = get_opcode_dependent_value (opcode);
1952 switch (type)
1953 {
1954 case AARCH64_OPND_LVt:
1955 assert (num >= 1 && num <= 4);
1956 /* Unless LD1/ST1, the number of registers should be equal to that
1957 of the structure elements. */
1958 if (num != 1 && opnd->reglist.num_regs != num)
1959 {
1960 set_reg_list_error (mismatch_detail, idx, num);
1961 return 0;
1962 }
1963 break;
1964 case AARCH64_OPND_LVt_AL:
1965 case AARCH64_OPND_LEt:
1966 assert (num >= 1 && num <= 4);
1967 /* The number of registers should be equal to that of the structure
1968 elements. */
1969 if (opnd->reglist.num_regs != num)
1970 {
1971 set_reg_list_error (mismatch_detail, idx, num);
1972 return 0;
1973 }
1974 break;
1975 default:
1976 break;
1977 }
1978 break;
1979
1980 case AARCH64_OPND_CLASS_IMMEDIATE:
1981 /* Constraint check on immediate operand. */
1982 imm = opnd->imm.value;
1983 /* E.g. imm_0_31 constrains value to be 0..31. */
1984 if (qualifier_value_in_range_constraint_p (qualifier)
1985 && !value_in_range_p (imm, get_lower_bound (qualifier),
1986 get_upper_bound (qualifier)))
1987 {
1988 set_imm_out_of_range_error (mismatch_detail, idx,
1989 get_lower_bound (qualifier),
1990 get_upper_bound (qualifier));
1991 return 0;
1992 }
1993
1994 switch (type)
1995 {
1996 case AARCH64_OPND_AIMM:
1997 if (opnd->shifter.kind != AARCH64_MOD_LSL)
1998 {
1999 set_other_error (mismatch_detail, idx,
2000 _("invalid shift operator"));
2001 return 0;
2002 }
2003 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2004 {
2005 set_other_error (mismatch_detail, idx,
2006 _("shift amount must be 0 or 12"));
2007 return 0;
2008 }
2009 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2010 {
2011 set_other_error (mismatch_detail, idx,
2012 _("immediate out of range"));
2013 return 0;
2014 }
2015 break;
2016
2017 case AARCH64_OPND_HALF:
2018 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2019 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2020 {
2021 set_other_error (mismatch_detail, idx,
2022 _("invalid shift operator"));
2023 return 0;
2024 }
2025 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2026 if (!value_aligned_p (opnd->shifter.amount, 16))
2027 {
2028 set_other_error (mismatch_detail, idx,
2029 _("shift amount must be a multiple of 16"));
2030 return 0;
2031 }
2032 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2033 {
2034 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2035 0, size * 8 - 16);
2036 return 0;
2037 }
2038 if (opnd->imm.value < 0)
2039 {
2040 set_other_error (mismatch_detail, idx,
2041 _("negative immediate value not allowed"));
2042 return 0;
2043 }
2044 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2045 {
2046 set_other_error (mismatch_detail, idx,
2047 _("immediate out of range"));
2048 return 0;
2049 }
2050 break;
2051
2052 case AARCH64_OPND_IMM_MOV:
2053 {
2054 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2055 imm = opnd->imm.value;
2056 assert (idx == 1);
2057 switch (opcode->op)
2058 {
2059 case OP_MOV_IMM_WIDEN:
2060 imm = ~imm;
2061 /* Fall through. */
2062 case OP_MOV_IMM_WIDE:
2063 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
2064 {
2065 set_other_error (mismatch_detail, idx,
2066 _("immediate out of range"));
2067 return 0;
2068 }
2069 break;
2070 case OP_MOV_IMM_LOG:
2071 if (!aarch64_logical_immediate_p (imm, esize, NULL))
2072 {
2073 set_other_error (mismatch_detail, idx,
2074 _("immediate out of range"));
2075 return 0;
2076 }
2077 break;
2078 default:
2079 assert (0);
2080 return 0;
2081 }
2082 }
2083 break;
2084
2085 case AARCH64_OPND_NZCV:
2086 case AARCH64_OPND_CCMP_IMM:
2087 case AARCH64_OPND_EXCEPTION:
2088 case AARCH64_OPND_UIMM4:
2089 case AARCH64_OPND_UIMM7:
2090 case AARCH64_OPND_UIMM3_OP1:
2091 case AARCH64_OPND_UIMM3_OP2:
2092 case AARCH64_OPND_SVE_UIMM3:
2093 case AARCH64_OPND_SVE_UIMM7:
2094 case AARCH64_OPND_SVE_UIMM8:
2095 case AARCH64_OPND_SVE_UIMM8_53:
2096 size = get_operand_fields_width (get_operand_from_code (type));
2097 assert (size < 32);
2098 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2099 {
2100 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2101 (1 << size) - 1);
2102 return 0;
2103 }
2104 break;
2105
2106 case AARCH64_OPND_SIMM5:
2107 case AARCH64_OPND_SVE_SIMM5:
2108 case AARCH64_OPND_SVE_SIMM5B:
2109 case AARCH64_OPND_SVE_SIMM6:
2110 case AARCH64_OPND_SVE_SIMM8:
2111 size = get_operand_fields_width (get_operand_from_code (type));
2112 assert (size < 32);
2113 if (!value_fit_signed_field_p (opnd->imm.value, size))
2114 {
2115 set_imm_out_of_range_error (mismatch_detail, idx,
2116 -(1 << (size - 1)),
2117 (1 << (size - 1)) - 1);
2118 return 0;
2119 }
2120 break;
2121
2122 case AARCH64_OPND_WIDTH:
2123 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
2124 && opnds[0].type == AARCH64_OPND_Rd);
2125 size = get_upper_bound (qualifier);
2126 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2127 /* lsb+width <= reg.size */
2128 {
2129 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2130 size - opnds[idx-1].imm.value);
2131 return 0;
2132 }
2133 break;
2134
2135 case AARCH64_OPND_LIMM:
2136 case AARCH64_OPND_SVE_LIMM:
2137 {
2138 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2139 uint64_t uimm = opnd->imm.value;
2140 if (opcode->op == OP_BIC)
2141 uimm = ~uimm;
2142 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2143 {
2144 set_other_error (mismatch_detail, idx,
2145 _("immediate out of range"));
2146 return 0;
2147 }
2148 }
2149 break;
2150
2151 case AARCH64_OPND_IMM0:
2152 case AARCH64_OPND_FPIMM0:
2153 if (opnd->imm.value != 0)
2154 {
2155 set_other_error (mismatch_detail, idx,
2156 _("immediate zero expected"));
2157 return 0;
2158 }
2159 break;
2160
2161 case AARCH64_OPND_IMM_ROT1:
2162 case AARCH64_OPND_IMM_ROT2:
2163 case AARCH64_OPND_SVE_IMM_ROT2:
2164 if (opnd->imm.value != 0
2165 && opnd->imm.value != 90
2166 && opnd->imm.value != 180
2167 && opnd->imm.value != 270)
2168 {
2169 set_other_error (mismatch_detail, idx,
2170 _("rotate expected to be 0, 90, 180 or 270"));
2171 return 0;
2172 }
2173 break;
2174
2175 case AARCH64_OPND_IMM_ROT3:
2176 case AARCH64_OPND_SVE_IMM_ROT1:
2177 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2178 {
2179 set_other_error (mismatch_detail, idx,
2180 _("rotate expected to be 90 or 270"));
2181 return 0;
2182 }
2183 break;
2184
2185 case AARCH64_OPND_SHLL_IMM:
2186 assert (idx == 2);
2187 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2188 if (opnd->imm.value != size)
2189 {
2190 set_other_error (mismatch_detail, idx,
2191 _("invalid shift amount"));
2192 return 0;
2193 }
2194 break;
2195
2196 case AARCH64_OPND_IMM_VLSL:
2197 size = aarch64_get_qualifier_esize (qualifier);
2198 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2199 {
2200 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2201 size * 8 - 1);
2202 return 0;
2203 }
2204 break;
2205
2206 case AARCH64_OPND_IMM_VLSR:
2207 size = aarch64_get_qualifier_esize (qualifier);
2208 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2209 {
2210 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2211 return 0;
2212 }
2213 break;
2214
2215 case AARCH64_OPND_SIMD_IMM:
2216 case AARCH64_OPND_SIMD_IMM_SFT:
2217 /* Qualifier check. */
2218 switch (qualifier)
2219 {
2220 case AARCH64_OPND_QLF_LSL:
2221 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2222 {
2223 set_other_error (mismatch_detail, idx,
2224 _("invalid shift operator"));
2225 return 0;
2226 }
2227 break;
2228 case AARCH64_OPND_QLF_MSL:
2229 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2230 {
2231 set_other_error (mismatch_detail, idx,
2232 _("invalid shift operator"));
2233 return 0;
2234 }
2235 break;
2236 case AARCH64_OPND_QLF_NIL:
2237 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2238 {
2239 set_other_error (mismatch_detail, idx,
2240 _("shift is not permitted"));
2241 return 0;
2242 }
2243 break;
2244 default:
2245 assert (0);
2246 return 0;
2247 }
2248 /* Is the immediate valid? */
2249 assert (idx == 1);
2250 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2251 {
2252 /* uimm8 or simm8 */
2253 if (!value_in_range_p (opnd->imm.value, -128, 255))
2254 {
2255 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
2256 return 0;
2257 }
2258 }
2259 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2260 {
2261 /* uimm64 is not
2262 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2263 ffffffffgggggggghhhhhhhh'. */
2264 set_other_error (mismatch_detail, idx,
2265 _("invalid value for immediate"));
2266 return 0;
2267 }
2268 /* Is the shift amount valid? */
2269 switch (opnd->shifter.kind)
2270 {
2271 case AARCH64_MOD_LSL:
2272 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2273 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
2274 {
2275 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2276 (size - 1) * 8);
2277 return 0;
2278 }
2279 if (!value_aligned_p (opnd->shifter.amount, 8))
2280 {
2281 set_unaligned_error (mismatch_detail, idx, 8);
2282 return 0;
2283 }
2284 break;
2285 case AARCH64_MOD_MSL:
2286 /* Only 8 and 16 are valid shift amount. */
2287 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2288 {
2289 set_other_error (mismatch_detail, idx,
2290 _("shift amount must be 0 or 16"));
2291 return 0;
2292 }
2293 break;
2294 default:
2295 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2296 {
2297 set_other_error (mismatch_detail, idx,
2298 _("invalid shift operator"));
2299 return 0;
2300 }
2301 break;
2302 }
2303 break;
2304
2305 case AARCH64_OPND_FPIMM:
2306 case AARCH64_OPND_SIMD_FPIMM:
2307 case AARCH64_OPND_SVE_FPIMM8:
2308 if (opnd->imm.is_fp == 0)
2309 {
2310 set_other_error (mismatch_detail, idx,
2311 _("floating-point immediate expected"));
2312 return 0;
2313 }
2314 /* The value is expected to be an 8-bit floating-point constant with
2315 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2316 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2317 instruction). */
2318 if (!value_in_range_p (opnd->imm.value, 0, 255))
2319 {
2320 set_other_error (mismatch_detail, idx,
2321 _("immediate out of range"));
2322 return 0;
2323 }
2324 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2325 {
2326 set_other_error (mismatch_detail, idx,
2327 _("invalid shift operator"));
2328 return 0;
2329 }
2330 break;
2331
2332 case AARCH64_OPND_SVE_AIMM:
2333 min_value = 0;
2334 sve_aimm:
2335 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2336 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2337 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2338 uvalue = opnd->imm.value;
2339 shift = opnd->shifter.amount;
2340 if (size == 1)
2341 {
2342 if (shift != 0)
2343 {
2344 set_other_error (mismatch_detail, idx,
2345 _("no shift amount allowed for"
2346 " 8-bit constants"));
2347 return 0;
2348 }
2349 }
2350 else
2351 {
2352 if (shift != 0 && shift != 8)
2353 {
2354 set_other_error (mismatch_detail, idx,
2355 _("shift amount must be 0 or 8"));
2356 return 0;
2357 }
2358 if (shift == 0 && (uvalue & 0xff) == 0)
2359 {
2360 shift = 8;
2361 uvalue = (int64_t) uvalue / 256;
2362 }
2363 }
2364 mask >>= shift;
2365 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2366 {
2367 set_other_error (mismatch_detail, idx,
2368 _("immediate too big for element size"));
2369 return 0;
2370 }
2371 uvalue = (uvalue - min_value) & mask;
2372 if (uvalue > 0xff)
2373 {
2374 set_other_error (mismatch_detail, idx,
2375 _("invalid arithmetic immediate"));
2376 return 0;
2377 }
2378 break;
2379
2380 case AARCH64_OPND_SVE_ASIMM:
2381 min_value = -128;
2382 goto sve_aimm;
2383
2384 case AARCH64_OPND_SVE_I1_HALF_ONE:
2385 assert (opnd->imm.is_fp);
2386 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2387 {
2388 set_other_error (mismatch_detail, idx,
2389 _("floating-point value must be 0.5 or 1.0"));
2390 return 0;
2391 }
2392 break;
2393
2394 case AARCH64_OPND_SVE_I1_HALF_TWO:
2395 assert (opnd->imm.is_fp);
2396 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2397 {
2398 set_other_error (mismatch_detail, idx,
2399 _("floating-point value must be 0.5 or 2.0"));
2400 return 0;
2401 }
2402 break;
2403
2404 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2405 assert (opnd->imm.is_fp);
2406 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2407 {
2408 set_other_error (mismatch_detail, idx,
2409 _("floating-point value must be 0.0 or 1.0"));
2410 return 0;
2411 }
2412 break;
2413
2414 case AARCH64_OPND_SVE_INV_LIMM:
2415 {
2416 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2417 uint64_t uimm = ~opnd->imm.value;
2418 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2419 {
2420 set_other_error (mismatch_detail, idx,
2421 _("immediate out of range"));
2422 return 0;
2423 }
2424 }
2425 break;
2426
2427 case AARCH64_OPND_SVE_LIMM_MOV:
2428 {
2429 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2430 uint64_t uimm = opnd->imm.value;
2431 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2432 {
2433 set_other_error (mismatch_detail, idx,
2434 _("immediate out of range"));
2435 return 0;
2436 }
2437 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2438 {
2439 set_other_error (mismatch_detail, idx,
2440 _("invalid replicated MOV immediate"));
2441 return 0;
2442 }
2443 }
2444 break;
2445
2446 case AARCH64_OPND_SVE_PATTERN_SCALED:
2447 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2448 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2449 {
2450 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2451 return 0;
2452 }
2453 break;
2454
2455 case AARCH64_OPND_SVE_SHLIMM_PRED:
2456 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
2457 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2458 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2459 {
2460 set_imm_out_of_range_error (mismatch_detail, idx,
2461 0, 8 * size - 1);
2462 return 0;
2463 }
2464 break;
2465
2466 case AARCH64_OPND_SVE_SHRIMM_PRED:
2467 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
2468 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2469 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2470 {
2471 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
2472 return 0;
2473 }
2474 break;
2475
2476 default:
2477 break;
2478 }
2479 break;
2480
2481 case AARCH64_OPND_CLASS_SYSTEM:
2482 switch (type)
2483 {
2484 case AARCH64_OPND_PSTATEFIELD:
2485 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
2486 /* MSR UAO, #uimm4
2487 MSR PAN, #uimm4
2488 The immediate must be #0 or #1. */
2489 if ((opnd->pstatefield == 0x03 /* UAO. */
2490 || opnd->pstatefield == 0x04 /* PAN. */
2491 || opnd->pstatefield == 0x1a) /* DIT. */
2492 && opnds[1].imm.value > 1)
2493 {
2494 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2495 return 0;
2496 }
2497 /* MSR SPSel, #uimm4
2498 Uses uimm4 as a control value to select the stack pointer: if
2499 bit 0 is set it selects the current exception level's stack
2500 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2501 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2502 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2503 {
2504 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2505 return 0;
2506 }
2507 break;
2508 default:
2509 break;
2510 }
2511 break;
2512
2513 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2514 /* Get the upper bound for the element index. */
2515 if (opcode->op == OP_FCMLA_ELEM)
2516 /* FCMLA index range depends on the vector size of other operands
2517 and is halfed because complex numbers take two elements. */
2518 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2519 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2520 else
2521 num = 16;
2522 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
2523
2524 /* Index out-of-range. */
2525 if (!value_in_range_p (opnd->reglane.index, 0, num))
2526 {
2527 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2528 return 0;
2529 }
2530 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2531 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2532 number is encoded in "size:M:Rm":
2533 size <Vm>
2534 00 RESERVED
2535 01 0:Rm
2536 10 M:Rm
2537 11 RESERVED */
2538 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
2539 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2540 {
2541 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2542 return 0;
2543 }
2544 break;
2545
2546 case AARCH64_OPND_CLASS_MODIFIED_REG:
2547 assert (idx == 1 || idx == 2);
2548 switch (type)
2549 {
2550 case AARCH64_OPND_Rm_EXT:
2551 if (!aarch64_extend_operator_p (opnd->shifter.kind)
2552 && opnd->shifter.kind != AARCH64_MOD_LSL)
2553 {
2554 set_other_error (mismatch_detail, idx,
2555 _("extend operator expected"));
2556 return 0;
2557 }
2558 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2559 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2560 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2561 case. */
2562 if (!aarch64_stack_pointer_p (opnds + 0)
2563 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2564 {
2565 if (!opnd->shifter.operator_present)
2566 {
2567 set_other_error (mismatch_detail, idx,
2568 _("missing extend operator"));
2569 return 0;
2570 }
2571 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2572 {
2573 set_other_error (mismatch_detail, idx,
2574 _("'LSL' operator not allowed"));
2575 return 0;
2576 }
2577 }
2578 assert (opnd->shifter.operator_present /* Default to LSL. */
2579 || opnd->shifter.kind == AARCH64_MOD_LSL);
2580 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2581 {
2582 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2583 return 0;
2584 }
2585 /* In the 64-bit form, the final register operand is written as Wm
2586 for all but the (possibly omitted) UXTX/LSL and SXTX
2587 operators.
2588 N.B. GAS allows X register to be used with any operator as a
2589 programming convenience. */
2590 if (qualifier == AARCH64_OPND_QLF_X
2591 && opnd->shifter.kind != AARCH64_MOD_LSL
2592 && opnd->shifter.kind != AARCH64_MOD_UXTX
2593 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2594 {
2595 set_other_error (mismatch_detail, idx, _("W register expected"));
2596 return 0;
2597 }
2598 break;
2599
2600 case AARCH64_OPND_Rm_SFT:
2601 /* ROR is not available to the shifted register operand in
2602 arithmetic instructions. */
2603 if (!aarch64_shift_operator_p (opnd->shifter.kind))
2604 {
2605 set_other_error (mismatch_detail, idx,
2606 _("shift operator expected"));
2607 return 0;
2608 }
2609 if (opnd->shifter.kind == AARCH64_MOD_ROR
2610 && opcode->iclass != log_shift)
2611 {
2612 set_other_error (mismatch_detail, idx,
2613 _("'ROR' operator not allowed"));
2614 return 0;
2615 }
2616 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2617 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2618 {
2619 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2620 return 0;
2621 }
2622 break;
2623
2624 default:
2625 break;
2626 }
2627 break;
2628
2629 default:
2630 break;
2631 }
2632
2633 return 1;
2634 }
2635
2636 /* Main entrypoint for the operand constraint checking.
2637
2638 Return 1 if operands of *INST meet the constraint applied by the operand
2639 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2640 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2641 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2642 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2643 error kind when it is notified that an instruction does not pass the check).
2644
2645 Un-determined operand qualifiers may get established during the process. */
2646
2647 int
2648 aarch64_match_operands_constraint (aarch64_inst *inst,
2649 aarch64_operand_error *mismatch_detail)
2650 {
2651 int i;
2652
2653 DEBUG_TRACE ("enter");
2654
2655 /* Check for cases where a source register needs to be the same as the
2656 destination register. Do this before matching qualifiers since if
2657 an instruction has both invalid tying and invalid qualifiers,
2658 the error about qualifiers would suggest several alternative
2659 instructions that also have invalid tying. */
2660 i = inst->opcode->tied_operand;
2661 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2662 {
2663 if (mismatch_detail)
2664 {
2665 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2666 mismatch_detail->index = i;
2667 mismatch_detail->error = NULL;
2668 }
2669 return 0;
2670 }
2671
2672 /* Match operands' qualifier.
2673 *INST has already had qualifier establish for some, if not all, of
2674 its operands; we need to find out whether these established
2675 qualifiers match one of the qualifier sequence in
2676 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2677 with the corresponding qualifier in such a sequence.
2678 Only basic operand constraint checking is done here; the more thorough
2679 constraint checking will carried out by operand_general_constraint_met_p,
2680 which has be to called after this in order to get all of the operands'
2681 qualifiers established. */
2682 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2683 {
2684 DEBUG_TRACE ("FAIL on operand qualifier matching");
2685 if (mismatch_detail)
2686 {
2687 /* Return an error type to indicate that it is the qualifier
2688 matching failure; we don't care about which operand as there
2689 are enough information in the opcode table to reproduce it. */
2690 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2691 mismatch_detail->index = -1;
2692 mismatch_detail->error = NULL;
2693 }
2694 return 0;
2695 }
2696
2697 /* Match operands' constraint. */
2698 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2699 {
2700 enum aarch64_opnd type = inst->opcode->operands[i];
2701 if (type == AARCH64_OPND_NIL)
2702 break;
2703 if (inst->operands[i].skip)
2704 {
2705 DEBUG_TRACE ("skip the incomplete operand %d", i);
2706 continue;
2707 }
2708 if (operand_general_constraint_met_p (inst->operands, i, type,
2709 inst->opcode, mismatch_detail) == 0)
2710 {
2711 DEBUG_TRACE ("FAIL on operand %d", i);
2712 return 0;
2713 }
2714 }
2715
2716 DEBUG_TRACE ("PASS");
2717
2718 return 1;
2719 }
2720
2721 /* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2722 Also updates the TYPE of each INST->OPERANDS with the corresponding
2723 value of OPCODE->OPERANDS.
2724
2725 Note that some operand qualifiers may need to be manually cleared by
2726 the caller before it further calls the aarch64_opcode_encode; by
2727 doing this, it helps the qualifier matching facilities work
2728 properly. */
2729
2730 const aarch64_opcode*
2731 aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2732 {
2733 int i;
2734 const aarch64_opcode *old = inst->opcode;
2735
2736 inst->opcode = opcode;
2737
2738 /* Update the operand types. */
2739 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2740 {
2741 inst->operands[i].type = opcode->operands[i];
2742 if (opcode->operands[i] == AARCH64_OPND_NIL)
2743 break;
2744 }
2745
2746 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2747
2748 return old;
2749 }
2750
2751 int
2752 aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2753 {
2754 int i;
2755 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2756 if (operands[i] == operand)
2757 return i;
2758 else if (operands[i] == AARCH64_OPND_NIL)
2759 break;
2760 return -1;
2761 }
2762 \f
2763 /* R0...R30, followed by FOR31. */
2764 #define BANK(R, FOR31) \
2765 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2766 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2767 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2768 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
2769 /* [0][0] 32-bit integer regs with sp Wn
2770 [0][1] 64-bit integer regs with sp Xn sf=1
2771 [1][0] 32-bit integer regs with #0 Wn
2772 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2773 static const char *int_reg[2][2][32] = {
2774 #define R32(X) "w" #X
2775 #define R64(X) "x" #X
2776 { BANK (R32, "wsp"), BANK (R64, "sp") },
2777 { BANK (R32, "wzr"), BANK (R64, "xzr") }
2778 #undef R64
2779 #undef R32
2780 };
2781
2782 /* Names of the SVE vector registers, first with .S suffixes,
2783 then with .D suffixes. */
2784
2785 static const char *sve_reg[2][32] = {
2786 #define ZS(X) "z" #X ".s"
2787 #define ZD(X) "z" #X ".d"
2788 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2789 #undef ZD
2790 #undef ZS
2791 };
2792 #undef BANK
2793
2794 /* Return the integer register name.
2795 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2796
2797 static inline const char *
2798 get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2799 {
2800 const int has_zr = sp_reg_p ? 0 : 1;
2801 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2802 return int_reg[has_zr][is_64][regno];
2803 }
2804
2805 /* Like get_int_reg_name, but IS_64 is always 1. */
2806
2807 static inline const char *
2808 get_64bit_int_reg_name (int regno, int sp_reg_p)
2809 {
2810 const int has_zr = sp_reg_p ? 0 : 1;
2811 return int_reg[has_zr][1][regno];
2812 }
2813
2814 /* Get the name of the integer offset register in OPND, using the shift type
2815 to decide whether it's a word or doubleword. */
2816
2817 static inline const char *
2818 get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2819 {
2820 switch (opnd->shifter.kind)
2821 {
2822 case AARCH64_MOD_UXTW:
2823 case AARCH64_MOD_SXTW:
2824 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2825
2826 case AARCH64_MOD_LSL:
2827 case AARCH64_MOD_SXTX:
2828 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2829
2830 default:
2831 abort ();
2832 }
2833 }
2834
2835 /* Get the name of the SVE vector offset register in OPND, using the operand
2836 qualifier to decide whether the suffix should be .S or .D. */
2837
2838 static inline const char *
2839 get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2840 {
2841 assert (qualifier == AARCH64_OPND_QLF_S_S
2842 || qualifier == AARCH64_OPND_QLF_S_D);
2843 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2844 }
2845
2846 /* Types for expanding an encoded 8-bit value to a floating-point value. */
2847
2848 typedef union
2849 {
2850 uint64_t i;
2851 double d;
2852 } double_conv_t;
2853
2854 typedef union
2855 {
2856 uint32_t i;
2857 float f;
2858 } single_conv_t;
2859
2860 typedef union
2861 {
2862 uint32_t i;
2863 float f;
2864 } half_conv_t;
2865
2866 /* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2867 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2868 (depending on the type of the instruction). IMM8 will be expanded to a
2869 single-precision floating-point value (SIZE == 4) or a double-precision
2870 floating-point value (SIZE == 8). A half-precision floating-point value
2871 (SIZE == 2) is expanded to a single-precision floating-point value. The
2872 expanded value is returned. */
2873
2874 static uint64_t
2875 expand_fp_imm (int size, uint32_t imm8)
2876 {
2877 uint64_t imm = 0;
2878 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2879
2880 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2881 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2882 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2883 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2884 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
2885 if (size == 8)
2886 {
2887 imm = (imm8_7 << (63-32)) /* imm8<7> */
2888 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2889 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2890 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2891 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2892 imm <<= 32;
2893 }
2894 else if (size == 4 || size == 2)
2895 {
2896 imm = (imm8_7 << 31) /* imm8<7> */
2897 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2898 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2899 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2900 }
2901 else
2902 {
2903 /* An unsupported size. */
2904 assert (0);
2905 }
2906
2907 return imm;
2908 }
2909
2910 /* Produce the string representation of the register list operand *OPND
2911 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2912 the register name that comes before the register number, such as "v". */
2913 static void
2914 print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
2915 const char *prefix)
2916 {
2917 const int num_regs = opnd->reglist.num_regs;
2918 const int first_reg = opnd->reglist.first_regno;
2919 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
2920 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
2921 char tb[8]; /* Temporary buffer. */
2922
2923 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
2924 assert (num_regs >= 1 && num_regs <= 4);
2925
2926 /* Prepare the index if any. */
2927 if (opnd->reglist.has_index)
2928 /* PR 21096: The %100 is to silence a warning about possible truncation. */
2929 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
2930 else
2931 tb[0] = '\0';
2932
2933 /* The hyphenated form is preferred for disassembly if there are
2934 more than two registers in the list, and the register numbers
2935 are monotonically increasing in increments of one. */
2936 if (num_regs > 2 && last_reg > first_reg)
2937 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
2938 prefix, last_reg, qlf_name, tb);
2939 else
2940 {
2941 const int reg0 = first_reg;
2942 const int reg1 = (first_reg + 1) & 0x1f;
2943 const int reg2 = (first_reg + 2) & 0x1f;
2944 const int reg3 = (first_reg + 3) & 0x1f;
2945
2946 switch (num_regs)
2947 {
2948 case 1:
2949 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
2950 break;
2951 case 2:
2952 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
2953 prefix, reg1, qlf_name, tb);
2954 break;
2955 case 3:
2956 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
2957 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
2958 prefix, reg2, qlf_name, tb);
2959 break;
2960 case 4:
2961 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
2962 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
2963 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
2964 break;
2965 }
2966 }
2967 }
2968
2969 /* Print the register+immediate address in OPND to BUF, which has SIZE
2970 characters. BASE is the name of the base register. */
2971
2972 static void
2973 print_immediate_offset_address (char *buf, size_t size,
2974 const aarch64_opnd_info *opnd,
2975 const char *base)
2976 {
2977 if (opnd->addr.writeback)
2978 {
2979 if (opnd->addr.preind)
2980 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
2981 else
2982 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
2983 }
2984 else
2985 {
2986 if (opnd->shifter.operator_present)
2987 {
2988 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
2989 snprintf (buf, size, "[%s, #%d, mul vl]",
2990 base, opnd->addr.offset.imm);
2991 }
2992 else if (opnd->addr.offset.imm)
2993 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
2994 else
2995 snprintf (buf, size, "[%s]", base);
2996 }
2997 }
2998
2999 /* Produce the string representation of the register offset address operand
3000 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3001 the names of the base and offset registers. */
3002 static void
3003 print_register_offset_address (char *buf, size_t size,
3004 const aarch64_opnd_info *opnd,
3005 const char *base, const char *offset)
3006 {
3007 char tb[16]; /* Temporary buffer. */
3008 bfd_boolean print_extend_p = TRUE;
3009 bfd_boolean print_amount_p = TRUE;
3010 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3011
3012 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3013 || !opnd->shifter.amount_present))
3014 {
3015 /* Not print the shift/extend amount when the amount is zero and
3016 when it is not the special case of 8-bit load/store instruction. */
3017 print_amount_p = FALSE;
3018 /* Likewise, no need to print the shift operator LSL in such a
3019 situation. */
3020 if (opnd->shifter.kind == AARCH64_MOD_LSL)
3021 print_extend_p = FALSE;
3022 }
3023
3024 /* Prepare for the extend/shift. */
3025 if (print_extend_p)
3026 {
3027 if (print_amount_p)
3028 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
3029 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3030 (opnd->shifter.amount % 100));
3031 else
3032 snprintf (tb, sizeof (tb), ", %s", shift_name);
3033 }
3034 else
3035 tb[0] = '\0';
3036
3037 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
3038 }
3039
3040 /* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3041 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3042 PC, PCREL_P and ADDRESS are used to pass in and return information about
3043 the PC-relative address calculation, where the PC value is passed in
3044 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3045 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3046 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3047
3048 The function serves both the disassembler and the assembler diagnostics
3049 issuer, which is the reason why it lives in this file. */
3050
3051 void
3052 aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3053 const aarch64_opcode *opcode,
3054 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
3055 bfd_vma *address, char** notes)
3056 {
3057 unsigned int i, num_conds;
3058 const char *name = NULL;
3059 const aarch64_opnd_info *opnd = opnds + idx;
3060 enum aarch64_modifier_kind kind;
3061 uint64_t addr, enum_value;
3062
3063 buf[0] = '\0';
3064 if (pcrel_p)
3065 *pcrel_p = 0;
3066
3067 switch (opnd->type)
3068 {
3069 case AARCH64_OPND_Rd:
3070 case AARCH64_OPND_Rn:
3071 case AARCH64_OPND_Rm:
3072 case AARCH64_OPND_Rt:
3073 case AARCH64_OPND_Rt2:
3074 case AARCH64_OPND_Rs:
3075 case AARCH64_OPND_Ra:
3076 case AARCH64_OPND_Rt_SYS:
3077 case AARCH64_OPND_PAIRREG:
3078 case AARCH64_OPND_SVE_Rm:
3079 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
3080 the <ic_op>, therefore we use opnd->present to override the
3081 generic optional-ness information. */
3082 if (opnd->type == AARCH64_OPND_Rt_SYS)
3083 {
3084 if (!opnd->present)
3085 break;
3086 }
3087 /* Omit the operand, e.g. RET. */
3088 else if (optional_operand_p (opcode, idx)
3089 && (opnd->reg.regno
3090 == get_optional_operand_default_value (opcode)))
3091 break;
3092 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3093 || opnd->qualifier == AARCH64_OPND_QLF_X);
3094 snprintf (buf, size, "%s",
3095 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3096 break;
3097
3098 case AARCH64_OPND_Rd_SP:
3099 case AARCH64_OPND_Rn_SP:
3100 case AARCH64_OPND_SVE_Rn_SP:
3101 case AARCH64_OPND_Rm_SP:
3102 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3103 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3104 || opnd->qualifier == AARCH64_OPND_QLF_X
3105 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3106 snprintf (buf, size, "%s",
3107 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3108 break;
3109
3110 case AARCH64_OPND_Rm_EXT:
3111 kind = opnd->shifter.kind;
3112 assert (idx == 1 || idx == 2);
3113 if ((aarch64_stack_pointer_p (opnds)
3114 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3115 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3116 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3117 && kind == AARCH64_MOD_UXTW)
3118 || (opnd->qualifier == AARCH64_OPND_QLF_X
3119 && kind == AARCH64_MOD_UXTX)))
3120 {
3121 /* 'LSL' is the preferred form in this case. */
3122 kind = AARCH64_MOD_LSL;
3123 if (opnd->shifter.amount == 0)
3124 {
3125 /* Shifter omitted. */
3126 snprintf (buf, size, "%s",
3127 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3128 break;
3129 }
3130 }
3131 if (opnd->shifter.amount)
3132 snprintf (buf, size, "%s, %s #%" PRIi64,
3133 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3134 aarch64_operand_modifiers[kind].name,
3135 opnd->shifter.amount);
3136 else
3137 snprintf (buf, size, "%s, %s",
3138 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3139 aarch64_operand_modifiers[kind].name);
3140 break;
3141
3142 case AARCH64_OPND_Rm_SFT:
3143 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3144 || opnd->qualifier == AARCH64_OPND_QLF_X);
3145 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3146 snprintf (buf, size, "%s",
3147 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3148 else
3149 snprintf (buf, size, "%s, %s #%" PRIi64,
3150 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3151 aarch64_operand_modifiers[opnd->shifter.kind].name,
3152 opnd->shifter.amount);
3153 break;
3154
3155 case AARCH64_OPND_Fd:
3156 case AARCH64_OPND_Fn:
3157 case AARCH64_OPND_Fm:
3158 case AARCH64_OPND_Fa:
3159 case AARCH64_OPND_Ft:
3160 case AARCH64_OPND_Ft2:
3161 case AARCH64_OPND_Sd:
3162 case AARCH64_OPND_Sn:
3163 case AARCH64_OPND_Sm:
3164 case AARCH64_OPND_SVE_VZn:
3165 case AARCH64_OPND_SVE_Vd:
3166 case AARCH64_OPND_SVE_Vm:
3167 case AARCH64_OPND_SVE_Vn:
3168 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3169 opnd->reg.regno);
3170 break;
3171
3172 case AARCH64_OPND_Va:
3173 case AARCH64_OPND_Vd:
3174 case AARCH64_OPND_Vn:
3175 case AARCH64_OPND_Vm:
3176 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3177 aarch64_get_qualifier_name (opnd->qualifier));
3178 break;
3179
3180 case AARCH64_OPND_Ed:
3181 case AARCH64_OPND_En:
3182 case AARCH64_OPND_Em:
3183 case AARCH64_OPND_Em16:
3184 case AARCH64_OPND_SM3_IMM2:
3185 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3186 aarch64_get_qualifier_name (opnd->qualifier),
3187 opnd->reglane.index);
3188 break;
3189
3190 case AARCH64_OPND_VdD1:
3191 case AARCH64_OPND_VnD1:
3192 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3193 break;
3194
3195 case AARCH64_OPND_LVn:
3196 case AARCH64_OPND_LVt:
3197 case AARCH64_OPND_LVt_AL:
3198 case AARCH64_OPND_LEt:
3199 print_register_list (buf, size, opnd, "v");
3200 break;
3201
3202 case AARCH64_OPND_SVE_Pd:
3203 case AARCH64_OPND_SVE_Pg3:
3204 case AARCH64_OPND_SVE_Pg4_5:
3205 case AARCH64_OPND_SVE_Pg4_10:
3206 case AARCH64_OPND_SVE_Pg4_16:
3207 case AARCH64_OPND_SVE_Pm:
3208 case AARCH64_OPND_SVE_Pn:
3209 case AARCH64_OPND_SVE_Pt:
3210 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3211 snprintf (buf, size, "p%d", opnd->reg.regno);
3212 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3213 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3214 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3215 aarch64_get_qualifier_name (opnd->qualifier));
3216 else
3217 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3218 aarch64_get_qualifier_name (opnd->qualifier));
3219 break;
3220
3221 case AARCH64_OPND_SVE_Za_5:
3222 case AARCH64_OPND_SVE_Za_16:
3223 case AARCH64_OPND_SVE_Zd:
3224 case AARCH64_OPND_SVE_Zm_5:
3225 case AARCH64_OPND_SVE_Zm_16:
3226 case AARCH64_OPND_SVE_Zn:
3227 case AARCH64_OPND_SVE_Zt:
3228 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3229 snprintf (buf, size, "z%d", opnd->reg.regno);
3230 else
3231 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3232 aarch64_get_qualifier_name (opnd->qualifier));
3233 break;
3234
3235 case AARCH64_OPND_SVE_ZnxN:
3236 case AARCH64_OPND_SVE_ZtxN:
3237 print_register_list (buf, size, opnd, "z");
3238 break;
3239
3240 case AARCH64_OPND_SVE_Zm3_INDEX:
3241 case AARCH64_OPND_SVE_Zm3_22_INDEX:
3242 case AARCH64_OPND_SVE_Zm4_INDEX:
3243 case AARCH64_OPND_SVE_Zn_INDEX:
3244 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3245 aarch64_get_qualifier_name (opnd->qualifier),
3246 opnd->reglane.index);
3247 break;
3248
3249 case AARCH64_OPND_CRn:
3250 case AARCH64_OPND_CRm:
3251 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
3252 break;
3253
3254 case AARCH64_OPND_IDX:
3255 case AARCH64_OPND_MASK:
3256 case AARCH64_OPND_IMM:
3257 case AARCH64_OPND_IMM_2:
3258 case AARCH64_OPND_WIDTH:
3259 case AARCH64_OPND_UIMM3_OP1:
3260 case AARCH64_OPND_UIMM3_OP2:
3261 case AARCH64_OPND_BIT_NUM:
3262 case AARCH64_OPND_IMM_VLSL:
3263 case AARCH64_OPND_IMM_VLSR:
3264 case AARCH64_OPND_SHLL_IMM:
3265 case AARCH64_OPND_IMM0:
3266 case AARCH64_OPND_IMMR:
3267 case AARCH64_OPND_IMMS:
3268 case AARCH64_OPND_FBITS:
3269 case AARCH64_OPND_SIMM5:
3270 case AARCH64_OPND_SVE_SHLIMM_PRED:
3271 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
3272 case AARCH64_OPND_SVE_SHRIMM_PRED:
3273 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3274 case AARCH64_OPND_SVE_SIMM5:
3275 case AARCH64_OPND_SVE_SIMM5B:
3276 case AARCH64_OPND_SVE_SIMM6:
3277 case AARCH64_OPND_SVE_SIMM8:
3278 case AARCH64_OPND_SVE_UIMM3:
3279 case AARCH64_OPND_SVE_UIMM7:
3280 case AARCH64_OPND_SVE_UIMM8:
3281 case AARCH64_OPND_SVE_UIMM8_53:
3282 case AARCH64_OPND_IMM_ROT1:
3283 case AARCH64_OPND_IMM_ROT2:
3284 case AARCH64_OPND_IMM_ROT3:
3285 case AARCH64_OPND_SVE_IMM_ROT1:
3286 case AARCH64_OPND_SVE_IMM_ROT2:
3287 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3288 break;
3289
3290 case AARCH64_OPND_SVE_I1_HALF_ONE:
3291 case AARCH64_OPND_SVE_I1_HALF_TWO:
3292 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3293 {
3294 single_conv_t c;
3295 c.i = opnd->imm.value;
3296 snprintf (buf, size, "#%.1f", c.f);
3297 break;
3298 }
3299
3300 case AARCH64_OPND_SVE_PATTERN:
3301 if (optional_operand_p (opcode, idx)
3302 && opnd->imm.value == get_optional_operand_default_value (opcode))
3303 break;
3304 enum_value = opnd->imm.value;
3305 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3306 if (aarch64_sve_pattern_array[enum_value])
3307 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3308 else
3309 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3310 break;
3311
3312 case AARCH64_OPND_SVE_PATTERN_SCALED:
3313 if (optional_operand_p (opcode, idx)
3314 && !opnd->shifter.operator_present
3315 && opnd->imm.value == get_optional_operand_default_value (opcode))
3316 break;
3317 enum_value = opnd->imm.value;
3318 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3319 if (aarch64_sve_pattern_array[opnd->imm.value])
3320 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3321 else
3322 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3323 if (opnd->shifter.operator_present)
3324 {
3325 size_t len = strlen (buf);
3326 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3327 aarch64_operand_modifiers[opnd->shifter.kind].name,
3328 opnd->shifter.amount);
3329 }
3330 break;
3331
3332 case AARCH64_OPND_SVE_PRFOP:
3333 enum_value = opnd->imm.value;
3334 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3335 if (aarch64_sve_prfop_array[enum_value])
3336 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3337 else
3338 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3339 break;
3340
3341 case AARCH64_OPND_IMM_MOV:
3342 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3343 {
3344 case 4: /* e.g. MOV Wd, #<imm32>. */
3345 {
3346 int imm32 = opnd->imm.value;
3347 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3348 }
3349 break;
3350 case 8: /* e.g. MOV Xd, #<imm64>. */
3351 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3352 opnd->imm.value, opnd->imm.value);
3353 break;
3354 default: assert (0);
3355 }
3356 break;
3357
3358 case AARCH64_OPND_FPIMM0:
3359 snprintf (buf, size, "#0.0");
3360 break;
3361
3362 case AARCH64_OPND_LIMM:
3363 case AARCH64_OPND_AIMM:
3364 case AARCH64_OPND_HALF:
3365 case AARCH64_OPND_SVE_INV_LIMM:
3366 case AARCH64_OPND_SVE_LIMM:
3367 case AARCH64_OPND_SVE_LIMM_MOV:
3368 if (opnd->shifter.amount)
3369 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
3370 opnd->shifter.amount);
3371 else
3372 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3373 break;
3374
3375 case AARCH64_OPND_SIMD_IMM:
3376 case AARCH64_OPND_SIMD_IMM_SFT:
3377 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3378 || opnd->shifter.kind == AARCH64_MOD_NONE)
3379 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3380 else
3381 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
3382 aarch64_operand_modifiers[opnd->shifter.kind].name,
3383 opnd->shifter.amount);
3384 break;
3385
3386 case AARCH64_OPND_SVE_AIMM:
3387 case AARCH64_OPND_SVE_ASIMM:
3388 if (opnd->shifter.amount)
3389 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3390 opnd->shifter.amount);
3391 else
3392 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3393 break;
3394
3395 case AARCH64_OPND_FPIMM:
3396 case AARCH64_OPND_SIMD_FPIMM:
3397 case AARCH64_OPND_SVE_FPIMM8:
3398 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3399 {
3400 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3401 {
3402 half_conv_t c;
3403 c.i = expand_fp_imm (2, opnd->imm.value);
3404 snprintf (buf, size, "#%.18e", c.f);
3405 }
3406 break;
3407 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3408 {
3409 single_conv_t c;
3410 c.i = expand_fp_imm (4, opnd->imm.value);
3411 snprintf (buf, size, "#%.18e", c.f);
3412 }
3413 break;
3414 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3415 {
3416 double_conv_t c;
3417 c.i = expand_fp_imm (8, opnd->imm.value);
3418 snprintf (buf, size, "#%.18e", c.d);
3419 }
3420 break;
3421 default: assert (0);
3422 }
3423 break;
3424
3425 case AARCH64_OPND_CCMP_IMM:
3426 case AARCH64_OPND_NZCV:
3427 case AARCH64_OPND_EXCEPTION:
3428 case AARCH64_OPND_UIMM4:
3429 case AARCH64_OPND_UIMM7:
3430 if (optional_operand_p (opcode, idx) == TRUE
3431 && (opnd->imm.value ==
3432 (int64_t) get_optional_operand_default_value (opcode)))
3433 /* Omit the operand, e.g. DCPS1. */
3434 break;
3435 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3436 break;
3437
3438 case AARCH64_OPND_COND:
3439 case AARCH64_OPND_COND1:
3440 snprintf (buf, size, "%s", opnd->cond->names[0]);
3441 num_conds = ARRAY_SIZE (opnd->cond->names);
3442 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3443 {
3444 size_t len = strlen (buf);
3445 if (i == 1)
3446 snprintf (buf + len, size - len, " // %s = %s",
3447 opnd->cond->names[0], opnd->cond->names[i]);
3448 else
3449 snprintf (buf + len, size - len, ", %s",
3450 opnd->cond->names[i]);
3451 }
3452 break;
3453
3454 case AARCH64_OPND_ADDR_ADRP:
3455 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3456 + opnd->imm.value;
3457 if (pcrel_p)
3458 *pcrel_p = 1;
3459 if (address)
3460 *address = addr;
3461 /* This is not necessary during the disassembling, as print_address_func
3462 in the disassemble_info will take care of the printing. But some
3463 other callers may be still interested in getting the string in *STR,
3464 so here we do snprintf regardless. */
3465 snprintf (buf, size, "#0x%" PRIx64, addr);
3466 break;
3467
3468 case AARCH64_OPND_ADDR_PCREL14:
3469 case AARCH64_OPND_ADDR_PCREL19:
3470 case AARCH64_OPND_ADDR_PCREL21:
3471 case AARCH64_OPND_ADDR_PCREL26:
3472 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3473 if (pcrel_p)
3474 *pcrel_p = 1;
3475 if (address)
3476 *address = addr;
3477 /* This is not necessary during the disassembling, as print_address_func
3478 in the disassemble_info will take care of the printing. But some
3479 other callers may be still interested in getting the string in *STR,
3480 so here we do snprintf regardless. */
3481 snprintf (buf, size, "#0x%" PRIx64, addr);
3482 break;
3483
3484 case AARCH64_OPND_ADDR_SIMPLE:
3485 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3486 case AARCH64_OPND_SIMD_ADDR_POST:
3487 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3488 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3489 {
3490 if (opnd->addr.offset.is_reg)
3491 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3492 else
3493 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3494 }
3495 else
3496 snprintf (buf, size, "[%s]", name);
3497 break;
3498
3499 case AARCH64_OPND_ADDR_REGOFF:
3500 case AARCH64_OPND_SVE_ADDR_R:
3501 case AARCH64_OPND_SVE_ADDR_RR:
3502 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3503 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3504 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3505 case AARCH64_OPND_SVE_ADDR_RX:
3506 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3507 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3508 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
3509 print_register_offset_address
3510 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3511 get_offset_int_reg_name (opnd));
3512 break;
3513
3514 case AARCH64_OPND_SVE_ADDR_RZ:
3515 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3516 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3517 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3518 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3519 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3520 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3521 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3522 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3523 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3524 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3525 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3526 print_register_offset_address
3527 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3528 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3529 break;
3530
3531 case AARCH64_OPND_ADDR_SIMM7:
3532 case AARCH64_OPND_ADDR_SIMM9:
3533 case AARCH64_OPND_ADDR_SIMM9_2:
3534 case AARCH64_OPND_ADDR_SIMM10:
3535 case AARCH64_OPND_ADDR_OFFSET:
3536 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
3537 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3538 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3539 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3540 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3541 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3542 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
3543 case AARCH64_OPND_SVE_ADDR_RI_U6:
3544 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3545 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3546 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
3547 print_immediate_offset_address
3548 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
3549 break;
3550
3551 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3552 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3553 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3554 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3555 print_immediate_offset_address
3556 (buf, size, opnd,
3557 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3558 break;
3559
3560 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3561 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3562 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3563 print_register_offset_address
3564 (buf, size, opnd,
3565 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3566 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3567 break;
3568
3569 case AARCH64_OPND_ADDR_UIMM12:
3570 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3571 if (opnd->addr.offset.imm)
3572 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
3573 else
3574 snprintf (buf, size, "[%s]", name);
3575 break;
3576
3577 case AARCH64_OPND_SYSREG:
3578 for (i = 0; aarch64_sys_regs[i].name; ++i)
3579 {
3580 bfd_boolean exact_match
3581 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3582 == opnd->sysreg.flags;
3583
3584 /* Try and find an exact match, But if that fails, return the first
3585 partial match that was found. */
3586 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3587 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3588 && (name == NULL || exact_match))
3589 {
3590 name = aarch64_sys_regs[i].name;
3591 if (exact_match)
3592 {
3593 if (notes)
3594 *notes = NULL;
3595 break;
3596 }
3597
3598 /* If we didn't match exactly, that means the presense of a flag
3599 indicates what we didn't want for this instruction. e.g. If
3600 F_REG_READ is there, that means we were looking for a write
3601 register. See aarch64_ext_sysreg. */
3602 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
3603 *notes = _("reading from a write-only register");
3604 else if (aarch64_sys_regs[i].flags & F_REG_READ)
3605 *notes = _("writing to a read-only register");
3606 }
3607 }
3608
3609 if (name)
3610 snprintf (buf, size, "%s", name);
3611 else
3612 {
3613 /* Implementation defined system register. */
3614 unsigned int value = opnd->sysreg.value;
3615 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3616 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3617 value & 0x7);
3618 }
3619 break;
3620
3621 case AARCH64_OPND_PSTATEFIELD:
3622 for (i = 0; aarch64_pstatefields[i].name; ++i)
3623 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3624 break;
3625 assert (aarch64_pstatefields[i].name);
3626 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3627 break;
3628
3629 case AARCH64_OPND_SYSREG_AT:
3630 case AARCH64_OPND_SYSREG_DC:
3631 case AARCH64_OPND_SYSREG_IC:
3632 case AARCH64_OPND_SYSREG_TLBI:
3633 snprintf (buf, size, "%s", opnd->sysins_op->name);
3634 break;
3635
3636 case AARCH64_OPND_BARRIER:
3637 snprintf (buf, size, "%s", opnd->barrier->name);
3638 break;
3639
3640 case AARCH64_OPND_BARRIER_ISB:
3641 /* Operand can be omitted, e.g. in DCPS1. */
3642 if (! optional_operand_p (opcode, idx)
3643 || (opnd->barrier->value
3644 != get_optional_operand_default_value (opcode)))
3645 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3646 break;
3647
3648 case AARCH64_OPND_PRFOP:
3649 if (opnd->prfop->name != NULL)
3650 snprintf (buf, size, "%s", opnd->prfop->name);
3651 else
3652 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
3653 break;
3654
3655 case AARCH64_OPND_BARRIER_PSB:
3656 snprintf (buf, size, "%s", opnd->hint_option->name);
3657 break;
3658
3659 default:
3660 assert (0);
3661 }
3662 }
3663 \f
3664 #define CPENC(op0,op1,crn,crm,op2) \
3665 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3666 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3667 #define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3668 /* for 3.9.10 System Instructions */
3669 #define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3670
3671 #define C0 0
3672 #define C1 1
3673 #define C2 2
3674 #define C3 3
3675 #define C4 4
3676 #define C5 5
3677 #define C6 6
3678 #define C7 7
3679 #define C8 8
3680 #define C9 9
3681 #define C10 10
3682 #define C11 11
3683 #define C12 12
3684 #define C13 13
3685 #define C14 14
3686 #define C15 15
3687
3688 /* TODO there is one more issues need to be resolved
3689 1. handle cpu-implementation-defined system registers. */
3690 const aarch64_sys_reg aarch64_sys_regs [] =
3691 {
3692 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
3693 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
3694 { "elr_el1", CPEN_(0,C0,1), 0 },
3695 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
3696 { "sp_el0", CPEN_(0,C1,0), 0 },
3697 { "spsel", CPEN_(0,C2,0), 0 },
3698 { "daif", CPEN_(3,C2,1), 0 },
3699 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
3700 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
3701 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
3702 { "nzcv", CPEN_(3,C2,0), 0 },
3703 { "fpcr", CPEN_(3,C4,0), 0 },
3704 { "fpsr", CPEN_(3,C4,1), 0 },
3705 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3706 { "dlr_el0", CPEN_(3,C5,1), 0 },
3707 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3708 { "elr_el2", CPEN_(4,C0,1), 0 },
3709 { "sp_el1", CPEN_(4,C1,0), 0 },
3710 { "spsr_irq", CPEN_(4,C3,0), 0 },
3711 { "spsr_abt", CPEN_(4,C3,1), 0 },
3712 { "spsr_und", CPEN_(4,C3,2), 0 },
3713 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3714 { "spsr_el3", CPEN_(6,C0,0), 0 },
3715 { "elr_el3", CPEN_(6,C0,1), 0 },
3716 { "sp_el2", CPEN_(6,C1,0), 0 },
3717 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3718 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
3719 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3720 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3721 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3722 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3723 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3724 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3725 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3726 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3727 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
3728 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3729 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3730 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3731 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3732 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3733 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3734 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3735 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3736 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3737 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3738 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3739 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3740 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3741 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3742 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3743 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3744 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3745 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3746 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3747 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3748 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3749 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3750 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3751 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3752 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3753 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3754 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3755 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3756 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
3757 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
3758 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3759 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3760 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3761 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3762 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
3763 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
3764 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3765 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3766 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3767 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
3768 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
3769 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3770 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3771 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3772 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3773 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3774 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3775 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3776 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
3777 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3778 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3779 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3780 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3781 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
3782 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3783 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3784 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
3785 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
3786 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
3787 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3788 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
3789 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3790 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3791 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3792 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
3793 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
3794 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
3795 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3796 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3797 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3798 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3799 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3800 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3801 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3802 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3803 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3804 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
3805 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3806 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3807 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3808 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3809 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
3810 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
3811 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
3812 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
3813 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3814 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3815 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
3816 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
3817 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
3818 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
3819 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
3820 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
3821 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
3822 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3823 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3824 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3825 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3826 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
3827 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3828 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3829 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
3830 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
3831 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3832 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3833 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3834 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3835 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
3836 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
3837 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3838 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3839 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
3840 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
3841 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3842 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3843 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
3844 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
3845 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3846 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3847 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
3848 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3849 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3850 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
3851 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
3852 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3853 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
3854 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
3855 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3856 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
3857 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
3858 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
3859 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3860 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3861 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
3862 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
3863 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3864 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3865 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
3866 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3867 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
3868 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
3869 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
3870 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
3871 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
3872 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
3873 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
3874 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
3875 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
3876 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
3877 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
3878 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
3879 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
3880 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
3881 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
3882 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
3883 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
3884 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
3885 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
3886 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
3887 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
3888 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
3889 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
3890 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
3891 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
3892 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
3893 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
3894 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
3895 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
3896 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
3897 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
3898 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
3899 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
3900 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
3901 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
3902 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
3903 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
3904 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
3905 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
3906 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
3907 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
3908 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
3909 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
3910 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
3911 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
3912 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
3913 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
3914 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
3915 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
3916 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
3917 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
3918 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
3919 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
3920 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
3921 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
3922 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
3923 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
3924 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
3925 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
3926 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
3927 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
3928 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
3929 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
3930 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
3931 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
3932 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
3933 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
3934 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
3935 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
3936 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
3937 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
3938 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
3939 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
3940 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
3941 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
3942 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
3943 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
3944 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
3945 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
3946 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
3947 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
3948 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
3949 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
3950 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
3951 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
3952 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
3953 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
3954 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
3955 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
3956 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
3957 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
3958 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
3959 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
3960 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
3961 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
3962 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
3963 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
3964 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
3965 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
3966 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
3967 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
3968 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
3969 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
3970 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
3971 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
3972 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
3973 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
3974 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
3975 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
3976 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
3977 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
3978 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
3979 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
3980 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
3981 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
3982 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
3983 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
3984 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
3985 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
3986 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
3987 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
3988 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
3989 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
3990 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
3991 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
3992 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
3993 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
3994 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
3995 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
3996 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
3997 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
3998 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
3999 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4000 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4001 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4002 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4003 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4004 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4005 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4006 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4007 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4008 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4009 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4010 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4011 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4012 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4013 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4014 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4015 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4016 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4017 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4018 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4019 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4020 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4021 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4022 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4023 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4024 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4025 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4026 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4027 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4028 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4029 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4030 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4031 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4032 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4033 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4034 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4035 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4036 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4037 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4038 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4039 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4040 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4041 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4042 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4043 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4044 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4045 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4046 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4047 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4048 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4049 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4050 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4051 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4052 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4053 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4054 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4055 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4056 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4057 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4058 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4059 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4060 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4061 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4062 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4063 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4064 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4065 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4066 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4067 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
4068
4069 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4070 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4071 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4072 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4073 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4074 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4075 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4076 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4077 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4078 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4079 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
4080 { 0, CPENC(0,0,0,0,0), 0 },
4081 };
4082
4083 bfd_boolean
4084 aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4085 {
4086 return (reg->flags & F_DEPRECATED) != 0;
4087 }
4088
4089 bfd_boolean
4090 aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4091 const aarch64_sys_reg *reg)
4092 {
4093 if (!(reg->flags & F_ARCHEXT))
4094 return TRUE;
4095
4096 /* PAN. Values are from aarch64_sys_regs. */
4097 if (reg->value == CPEN_(0,C2,3)
4098 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4099 return FALSE;
4100
4101 /* Virtualization host extensions: system registers. */
4102 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4103 || reg->value == CPENC (3, 4, C13, C0, 1)
4104 || reg->value == CPENC (3, 4, C14, C3, 0)
4105 || reg->value == CPENC (3, 4, C14, C3, 1)
4106 || reg->value == CPENC (3, 4, C14, C3, 2))
4107 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4108 return FALSE;
4109
4110 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4111 if ((reg->value == CPEN_ (5, C0, 0)
4112 || reg->value == CPEN_ (5, C0, 1)
4113 || reg->value == CPENC (3, 5, C1, C0, 0)
4114 || reg->value == CPENC (3, 5, C1, C0, 2)
4115 || reg->value == CPENC (3, 5, C2, C0, 0)
4116 || reg->value == CPENC (3, 5, C2, C0, 1)
4117 || reg->value == CPENC (3, 5, C2, C0, 2)
4118 || reg->value == CPENC (3, 5, C5, C1, 0)
4119 || reg->value == CPENC (3, 5, C5, C1, 1)
4120 || reg->value == CPENC (3, 5, C5, C2, 0)
4121 || reg->value == CPENC (3, 5, C6, C0, 0)
4122 || reg->value == CPENC (3, 5, C10, C2, 0)
4123 || reg->value == CPENC (3, 5, C10, C3, 0)
4124 || reg->value == CPENC (3, 5, C12, C0, 0)
4125 || reg->value == CPENC (3, 5, C13, C0, 1)
4126 || reg->value == CPENC (3, 5, C14, C1, 0))
4127 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4128 return FALSE;
4129
4130 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4131 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4132 || reg->value == CPENC (3, 5, C14, C2, 1)
4133 || reg->value == CPENC (3, 5, C14, C2, 2)
4134 || reg->value == CPENC (3, 5, C14, C3, 0)
4135 || reg->value == CPENC (3, 5, C14, C3, 1)
4136 || reg->value == CPENC (3, 5, C14, C3, 2))
4137 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4138 return FALSE;
4139
4140 /* ARMv8.2 features. */
4141
4142 /* ID_AA64MMFR2_EL1. */
4143 if (reg->value == CPENC (3, 0, C0, C7, 2)
4144 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4145 return FALSE;
4146
4147 /* PSTATE.UAO. */
4148 if (reg->value == CPEN_ (0, C2, 4)
4149 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4150 return FALSE;
4151
4152 /* RAS extension. */
4153
4154 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4155 ERXMISC0_EL1 AND ERXMISC1_EL1. */
4156 if ((reg->value == CPENC (3, 0, C5, C3, 0)
4157 || reg->value == CPENC (3, 0, C5, C3, 1)
4158 || reg->value == CPENC (3, 0, C5, C3, 2)
4159 || reg->value == CPENC (3, 0, C5, C3, 3)
4160 || reg->value == CPENC (3, 0, C5, C4, 0)
4161 || reg->value == CPENC (3, 0, C5, C4, 1)
4162 || reg->value == CPENC (3, 0, C5, C4, 2)
4163 || reg->value == CPENC (3, 0, C5, C4, 3)
4164 || reg->value == CPENC (3, 0, C5, C5, 0)
4165 || reg->value == CPENC (3, 0, C5, C5, 1))
4166 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4167 return FALSE;
4168
4169 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4170 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4171 || reg->value == CPENC (3, 0, C12, C1, 1)
4172 || reg->value == CPENC (3, 4, C12, C1, 1))
4173 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4174 return FALSE;
4175
4176 /* Statistical Profiling extension. */
4177 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4178 || reg->value == CPENC (3, 0, C9, C10, 1)
4179 || reg->value == CPENC (3, 0, C9, C10, 3)
4180 || reg->value == CPENC (3, 0, C9, C10, 7)
4181 || reg->value == CPENC (3, 0, C9, C9, 0)
4182 || reg->value == CPENC (3, 0, C9, C9, 2)
4183 || reg->value == CPENC (3, 0, C9, C9, 3)
4184 || reg->value == CPENC (3, 0, C9, C9, 4)
4185 || reg->value == CPENC (3, 0, C9, C9, 5)
4186 || reg->value == CPENC (3, 0, C9, C9, 6)
4187 || reg->value == CPENC (3, 0, C9, C9, 7)
4188 || reg->value == CPENC (3, 4, C9, C9, 0)
4189 || reg->value == CPENC (3, 5, C9, C9, 0))
4190 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4191 return FALSE;
4192
4193 /* ARMv8.3 Pointer authentication keys. */
4194 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4195 || reg->value == CPENC (3, 0, C2, C1, 1)
4196 || reg->value == CPENC (3, 0, C2, C1, 2)
4197 || reg->value == CPENC (3, 0, C2, C1, 3)
4198 || reg->value == CPENC (3, 0, C2, C2, 0)
4199 || reg->value == CPENC (3, 0, C2, C2, 1)
4200 || reg->value == CPENC (3, 0, C2, C2, 2)
4201 || reg->value == CPENC (3, 0, C2, C2, 3)
4202 || reg->value == CPENC (3, 0, C2, C3, 0)
4203 || reg->value == CPENC (3, 0, C2, C3, 1))
4204 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4205 return FALSE;
4206
4207 /* SVE. */
4208 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4209 || reg->value == CPENC (3, 0, C1, C2, 0)
4210 || reg->value == CPENC (3, 4, C1, C2, 0)
4211 || reg->value == CPENC (3, 6, C1, C2, 0)
4212 || reg->value == CPENC (3, 5, C1, C2, 0)
4213 || reg->value == CPENC (3, 0, C0, C0, 7))
4214 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4215 return FALSE;
4216
4217 /* ARMv8.4 features. */
4218
4219 /* PSTATE.DIT. */
4220 if (reg->value == CPEN_ (3, C2, 5)
4221 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4222 return FALSE;
4223
4224 /* Virtualization extensions. */
4225 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4226 || reg->value == CPENC(3, 4, C2, C6, 0)
4227 || reg->value == CPENC(3, 4, C14, C4, 0)
4228 || reg->value == CPENC(3, 4, C14, C4, 2)
4229 || reg->value == CPENC(3, 4, C14, C4, 1)
4230 || reg->value == CPENC(3, 4, C14, C5, 0)
4231 || reg->value == CPENC(3, 4, C14, C5, 2)
4232 || reg->value == CPENC(3, 4, C14, C5, 1)
4233 || reg->value == CPENC(3, 4, C1, C3, 1)
4234 || reg->value == CPENC(3, 4, C2, C2, 0))
4235 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4236 return FALSE;
4237
4238 /* ARMv8.4 TLB instructions. */
4239 if ((reg->value == CPENS (0, C8, C1, 0)
4240 || reg->value == CPENS (0, C8, C1, 1)
4241 || reg->value == CPENS (0, C8, C1, 2)
4242 || reg->value == CPENS (0, C8, C1, 3)
4243 || reg->value == CPENS (0, C8, C1, 5)
4244 || reg->value == CPENS (0, C8, C1, 7)
4245 || reg->value == CPENS (4, C8, C4, 0)
4246 || reg->value == CPENS (4, C8, C4, 4)
4247 || reg->value == CPENS (4, C8, C1, 1)
4248 || reg->value == CPENS (4, C8, C1, 5)
4249 || reg->value == CPENS (4, C8, C1, 6)
4250 || reg->value == CPENS (6, C8, C1, 1)
4251 || reg->value == CPENS (6, C8, C1, 5)
4252 || reg->value == CPENS (4, C8, C1, 0)
4253 || reg->value == CPENS (4, C8, C1, 4)
4254 || reg->value == CPENS (6, C8, C1, 0)
4255 || reg->value == CPENS (0, C8, C6, 1)
4256 || reg->value == CPENS (0, C8, C6, 3)
4257 || reg->value == CPENS (0, C8, C6, 5)
4258 || reg->value == CPENS (0, C8, C6, 7)
4259 || reg->value == CPENS (0, C8, C2, 1)
4260 || reg->value == CPENS (0, C8, C2, 3)
4261 || reg->value == CPENS (0, C8, C2, 5)
4262 || reg->value == CPENS (0, C8, C2, 7)
4263 || reg->value == CPENS (0, C8, C5, 1)
4264 || reg->value == CPENS (0, C8, C5, 3)
4265 || reg->value == CPENS (0, C8, C5, 5)
4266 || reg->value == CPENS (0, C8, C5, 7)
4267 || reg->value == CPENS (4, C8, C0, 2)
4268 || reg->value == CPENS (4, C8, C0, 6)
4269 || reg->value == CPENS (4, C8, C4, 2)
4270 || reg->value == CPENS (4, C8, C4, 6)
4271 || reg->value == CPENS (4, C8, C4, 3)
4272 || reg->value == CPENS (4, C8, C4, 7)
4273 || reg->value == CPENS (4, C8, C6, 1)
4274 || reg->value == CPENS (4, C8, C6, 5)
4275 || reg->value == CPENS (4, C8, C2, 1)
4276 || reg->value == CPENS (4, C8, C2, 5)
4277 || reg->value == CPENS (4, C8, C5, 1)
4278 || reg->value == CPENS (4, C8, C5, 5)
4279 || reg->value == CPENS (6, C8, C6, 1)
4280 || reg->value == CPENS (6, C8, C6, 5)
4281 || reg->value == CPENS (6, C8, C2, 1)
4282 || reg->value == CPENS (6, C8, C2, 5)
4283 || reg->value == CPENS (6, C8, C5, 1)
4284 || reg->value == CPENS (6, C8, C5, 5))
4285 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4286 return FALSE;
4287
4288 return TRUE;
4289 }
4290
4291 /* The CPENC below is fairly misleading, the fields
4292 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4293 by ins_pstatefield, which just shifts the value by the width of the fields
4294 in a loop. So if you CPENC them only the first value will be set, the rest
4295 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4296 value of 0b110000000001000000 (0x30040) while what you want is
4297 0b011010 (0x1a). */
4298 const aarch64_sys_reg aarch64_pstatefields [] =
4299 {
4300 { "spsel", 0x05, 0 },
4301 { "daifset", 0x1e, 0 },
4302 { "daifclr", 0x1f, 0 },
4303 { "pan", 0x04, F_ARCHEXT },
4304 { "uao", 0x03, F_ARCHEXT },
4305 { "dit", 0x1a, F_ARCHEXT },
4306 { 0, CPENC(0,0,0,0,0), 0 },
4307 };
4308
4309 bfd_boolean
4310 aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4311 const aarch64_sys_reg *reg)
4312 {
4313 if (!(reg->flags & F_ARCHEXT))
4314 return TRUE;
4315
4316 /* PAN. Values are from aarch64_pstatefields. */
4317 if (reg->value == 0x04
4318 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4319 return FALSE;
4320
4321 /* UAO. Values are from aarch64_pstatefields. */
4322 if (reg->value == 0x03
4323 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4324 return FALSE;
4325
4326 /* DIT. Values are from aarch64_pstatefields. */
4327 if (reg->value == 0x1a
4328 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4329 return FALSE;
4330
4331 return TRUE;
4332 }
4333
4334 const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4335 {
4336 { "ialluis", CPENS(0,C7,C1,0), 0 },
4337 { "iallu", CPENS(0,C7,C5,0), 0 },
4338 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
4339 { 0, CPENS(0,0,0,0), 0 }
4340 };
4341
4342 const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4343 {
4344 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
4345 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
4346 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
4347 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
4348 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
4349 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
4350 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
4351 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
4352 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
4353 { 0, CPENS(0,0,0,0), 0 }
4354 };
4355
4356 const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4357 {
4358 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4359 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4360 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4361 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4362 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4363 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4364 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4365 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4366 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4367 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4368 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4369 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
4370 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4371 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
4372 { 0, CPENS(0,0,0,0), 0 }
4373 };
4374
4375 const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4376 {
4377 { "vmalle1", CPENS(0,C8,C7,0), 0 },
4378 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4379 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4380 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
4381 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
4382 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4383 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4384 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4385 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4386 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4387 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4388 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4389 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4390 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
4391 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4392 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
4393 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4394 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
4395 { "alle2", CPENS(4,C8,C7,0), 0 },
4396 { "alle2is", CPENS(4,C8,C3,0), 0 },
4397 { "alle1", CPENS(4,C8,C7,4), 0 },
4398 { "alle1is", CPENS(4,C8,C3,4), 0 },
4399 { "alle3", CPENS(6,C8,C7,0), 0 },
4400 { "alle3is", CPENS(6,C8,C3,0), 0 },
4401 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4402 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4403 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4404 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4405 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4406 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4407 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4408 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
4409
4410 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4411 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4412 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4413 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4414 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4415 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4416 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4417 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4418 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4419 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4420 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4421 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4422 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4423 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4424 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4425 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4426
4427 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4428 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4429 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4430 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4431 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4432 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4433 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4434 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4435 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4436 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4437 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4438 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4439 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4440 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4441 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4442 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4443 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4444 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4445 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4446 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4447 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4448 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4449 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4450 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4451 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4452 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4453 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4454 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4455 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4456 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4457
4458 { 0, CPENS(0,0,0,0), 0 }
4459 };
4460
4461 bfd_boolean
4462 aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4463 {
4464 return (sys_ins_reg->flags & F_HASXT) != 0;
4465 }
4466
4467 extern bfd_boolean
4468 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4469 const aarch64_sys_ins_reg *reg)
4470 {
4471 if (!(reg->flags & F_ARCHEXT))
4472 return TRUE;
4473
4474 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4475 if (reg->value == CPENS (3, C7, C12, 1)
4476 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4477 return FALSE;
4478
4479 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4480 if ((reg->value == CPENS (0, C7, C9, 0)
4481 || reg->value == CPENS (0, C7, C9, 1))
4482 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4483 return FALSE;
4484
4485 return TRUE;
4486 }
4487
4488 #undef C0
4489 #undef C1
4490 #undef C2
4491 #undef C3
4492 #undef C4
4493 #undef C5
4494 #undef C6
4495 #undef C7
4496 #undef C8
4497 #undef C9
4498 #undef C10
4499 #undef C11
4500 #undef C12
4501 #undef C13
4502 #undef C14
4503 #undef C15
4504
4505 #define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4506 #define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4507
4508 static enum err_type
4509 verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4510 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4511 bfd_boolean encoding ATTRIBUTE_UNUSED,
4512 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4513 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4514 {
4515 int t = BITS (insn, 4, 0);
4516 int n = BITS (insn, 9, 5);
4517 int t2 = BITS (insn, 14, 10);
4518
4519 if (BIT (insn, 23))
4520 {
4521 /* Write back enabled. */
4522 if ((t == n || t2 == n) && n != 31)
4523 return ERR_UND;
4524 }
4525
4526 if (BIT (insn, 22))
4527 {
4528 /* Load */
4529 if (t == t2)
4530 return ERR_UND;
4531 }
4532
4533 return ERR_OK;
4534 }
4535
4536 /* Initialize an instruction sequence insn_sequence with the instruction INST.
4537 If INST is NULL the given insn_sequence is cleared and the sequence is left
4538 uninitialized. */
4539
4540 void
4541 init_insn_sequence (const struct aarch64_inst *inst,
4542 aarch64_instr_sequence *insn_sequence)
4543 {
4544 int num_req_entries = 0;
4545 insn_sequence->next_insn = 0;
4546 insn_sequence->num_insns = num_req_entries;
4547 if (insn_sequence->instr)
4548 XDELETE (insn_sequence->instr);
4549 insn_sequence->instr = NULL;
4550
4551 if (inst)
4552 {
4553 insn_sequence->instr = XNEW (aarch64_inst);
4554 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4555 }
4556
4557 /* Handle all the cases here. May need to think of something smarter than
4558 a giant if/else chain if this grows. At that time, a lookup table may be
4559 best. */
4560 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4561 num_req_entries = 1;
4562
4563 if (insn_sequence->current_insns)
4564 XDELETEVEC (insn_sequence->current_insns);
4565 insn_sequence->current_insns = NULL;
4566
4567 if (num_req_entries != 0)
4568 {
4569 size_t size = num_req_entries * sizeof (aarch64_inst);
4570 insn_sequence->current_insns
4571 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4572 memset (insn_sequence->current_insns, 0, size);
4573 }
4574 }
4575
4576
4577 /* This function verifies that the instruction INST adheres to its specified
4578 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4579 returned and MISMATCH_DETAIL contains the reason why verification failed.
4580
4581 The function is called both during assembly and disassembly. If assembling
4582 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4583 and will contain the PC of the current instruction w.r.t to the section.
4584
4585 If ENCODING and PC=0 then you are at a start of a section. The constraints
4586 are verified against the given state insn_sequence which is updated as it
4587 transitions through the verification. */
4588
4589 enum err_type
4590 verify_constraints (const struct aarch64_inst *inst,
4591 const aarch64_insn insn ATTRIBUTE_UNUSED,
4592 bfd_vma pc,
4593 bfd_boolean encoding,
4594 aarch64_operand_error *mismatch_detail,
4595 aarch64_instr_sequence *insn_sequence)
4596 {
4597 assert (inst);
4598 assert (inst->opcode);
4599
4600 const struct aarch64_opcode *opcode = inst->opcode;
4601 if (!opcode->constraints && !insn_sequence->instr)
4602 return ERR_OK;
4603
4604 assert (insn_sequence);
4605
4606 enum err_type res = ERR_OK;
4607
4608 /* This instruction puts a constraint on the insn_sequence. */
4609 if (opcode->flags & F_SCAN)
4610 {
4611 if (insn_sequence->instr)
4612 {
4613 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4614 mismatch_detail->error = _("instruction opens new dependency "
4615 "sequence without ending previous one");
4616 mismatch_detail->index = -1;
4617 mismatch_detail->non_fatal = TRUE;
4618 res = ERR_VFI;
4619 }
4620
4621 init_insn_sequence (inst, insn_sequence);
4622 return res;
4623 }
4624
4625 /* Verify constraints on an existing sequence. */
4626 if (insn_sequence->instr)
4627 {
4628 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4629 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4630 closed a previous one that we should have. */
4631 if (!encoding && pc == 0)
4632 {
4633 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4634 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4635 mismatch_detail->index = -1;
4636 mismatch_detail->non_fatal = TRUE;
4637 res = ERR_VFI;
4638 /* Reset the sequence. */
4639 init_insn_sequence (NULL, insn_sequence);
4640 return res;
4641 }
4642
4643 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4644 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4645 {
4646 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4647 instruction for better error messages. */
4648 if (!opcode->avariant || !(*opcode->avariant & AARCH64_FEATURE_SVE))
4649 {
4650 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4651 mismatch_detail->error = _("SVE instruction expected after "
4652 "`movprfx'");
4653 mismatch_detail->index = -1;
4654 mismatch_detail->non_fatal = TRUE;
4655 res = ERR_VFI;
4656 goto done;
4657 }
4658
4659 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4660 instruction that is allowed to be used with a MOVPRFX. */
4661 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4662 {
4663 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4664 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4665 "expected");
4666 mismatch_detail->index = -1;
4667 mismatch_detail->non_fatal = TRUE;
4668 res = ERR_VFI;
4669 goto done;
4670 }
4671
4672 /* Next check for usage of the predicate register. */
4673 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
4674 aarch64_opnd_info blk_pred, inst_pred;
4675 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4676 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
4677 bfd_boolean predicated = FALSE;
4678 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4679
4680 /* Determine if the movprfx instruction used is predicated or not. */
4681 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4682 {
4683 predicated = TRUE;
4684 blk_pred = insn_sequence->instr->operands[1];
4685 }
4686
4687 unsigned char max_elem_size = 0;
4688 unsigned char current_elem_size;
4689 int num_op_used = 0, last_op_usage = 0;
4690 int i, inst_pred_idx = -1;
4691 int num_ops = aarch64_num_of_operands (opcode);
4692 for (i = 0; i < num_ops; i++)
4693 {
4694 aarch64_opnd_info inst_op = inst->operands[i];
4695 switch (inst_op.type)
4696 {
4697 case AARCH64_OPND_SVE_Zd:
4698 case AARCH64_OPND_SVE_Zm_5:
4699 case AARCH64_OPND_SVE_Zm_16:
4700 case AARCH64_OPND_SVE_Zn:
4701 case AARCH64_OPND_SVE_Zt:
4702 case AARCH64_OPND_SVE_Vm:
4703 case AARCH64_OPND_SVE_Vn:
4704 case AARCH64_OPND_Va:
4705 case AARCH64_OPND_Vn:
4706 case AARCH64_OPND_Vm:
4707 case AARCH64_OPND_Sn:
4708 case AARCH64_OPND_Sm:
4709 case AARCH64_OPND_Rn:
4710 case AARCH64_OPND_Rm:
4711 case AARCH64_OPND_Rn_SP:
4712 case AARCH64_OPND_Rm_SP:
4713 if (inst_op.reg.regno == blk_dest.reg.regno)
4714 {
4715 num_op_used++;
4716 last_op_usage = i;
4717 }
4718 current_elem_size
4719 = aarch64_get_qualifier_esize (inst_op.qualifier);
4720 if (current_elem_size > max_elem_size)
4721 max_elem_size = current_elem_size;
4722 break;
4723 case AARCH64_OPND_SVE_Pd:
4724 case AARCH64_OPND_SVE_Pg3:
4725 case AARCH64_OPND_SVE_Pg4_5:
4726 case AARCH64_OPND_SVE_Pg4_10:
4727 case AARCH64_OPND_SVE_Pg4_16:
4728 case AARCH64_OPND_SVE_Pm:
4729 case AARCH64_OPND_SVE_Pn:
4730 case AARCH64_OPND_SVE_Pt:
4731 inst_pred = inst_op;
4732 inst_pred_idx = i;
4733 break;
4734 default:
4735 break;
4736 }
4737 }
4738
4739 assert (max_elem_size != 0);
4740 aarch64_opnd_info inst_dest = inst->operands[0];
4741 /* Determine the size that should be used to compare against the
4742 movprfx size. */
4743 current_elem_size
4744 = opcode->constraints & C_MAX_ELEM
4745 ? max_elem_size
4746 : aarch64_get_qualifier_esize (inst_dest.qualifier);
4747
4748 /* If movprfx is predicated do some extra checks. */
4749 if (predicated)
4750 {
4751 /* The instruction must be predicated. */
4752 if (inst_pred_idx < 0)
4753 {
4754 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4755 mismatch_detail->error = _("predicated instruction expected "
4756 "after `movprfx'");
4757 mismatch_detail->index = -1;
4758 mismatch_detail->non_fatal = TRUE;
4759 res = ERR_VFI;
4760 goto done;
4761 }
4762
4763 /* The instruction must have a merging predicate. */
4764 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
4765 {
4766 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4767 mismatch_detail->error = _("merging predicate expected due "
4768 "to preceding `movprfx'");
4769 mismatch_detail->index = inst_pred_idx;
4770 mismatch_detail->non_fatal = TRUE;
4771 res = ERR_VFI;
4772 goto done;
4773 }
4774
4775 /* The same register must be used in instruction. */
4776 if (blk_pred.reg.regno != inst_pred.reg.regno)
4777 {
4778 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4779 mismatch_detail->error = _("predicate register differs "
4780 "from that in preceding "
4781 "`movprfx'");
4782 mismatch_detail->index = inst_pred_idx;
4783 mismatch_detail->non_fatal = TRUE;
4784 res = ERR_VFI;
4785 goto done;
4786 }
4787 }
4788
4789 /* Destructive operations by definition must allow one usage of the
4790 same register. */
4791 int allowed_usage
4792 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
4793
4794 /* Operand is not used at all. */
4795 if (num_op_used == 0)
4796 {
4797 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4798 mismatch_detail->error = _("output register of preceding "
4799 "`movprfx' not used in current "
4800 "instruction");
4801 mismatch_detail->index = 0;
4802 mismatch_detail->non_fatal = TRUE;
4803 res = ERR_VFI;
4804 goto done;
4805 }
4806
4807 /* We now know it's used, now determine exactly where it's used. */
4808 if (blk_dest.reg.regno != inst_dest.reg.regno)
4809 {
4810 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4811 mismatch_detail->error = _("output register of preceding "
4812 "`movprfx' expected as output");
4813 mismatch_detail->index = 0;
4814 mismatch_detail->non_fatal = TRUE;
4815 res = ERR_VFI;
4816 goto done;
4817 }
4818
4819 /* Operand used more than allowed for the specific opcode type. */
4820 if (num_op_used > allowed_usage)
4821 {
4822 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4823 mismatch_detail->error = _("output register of preceding "
4824 "`movprfx' used as input");
4825 mismatch_detail->index = last_op_usage;
4826 mismatch_detail->non_fatal = TRUE;
4827 res = ERR_VFI;
4828 goto done;
4829 }
4830
4831 /* Now the only thing left is the qualifiers checks. The register
4832 must have the same maximum element size. */
4833 if (inst_dest.qualifier
4834 && blk_dest.qualifier
4835 && current_elem_size
4836 != aarch64_get_qualifier_esize (blk_dest.qualifier))
4837 {
4838 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4839 mismatch_detail->error = _("register size not compatible with "
4840 "previous `movprfx'");
4841 mismatch_detail->index = 0;
4842 mismatch_detail->non_fatal = TRUE;
4843 res = ERR_VFI;
4844 goto done;
4845 }
4846 }
4847
4848 done:
4849 /* Add the new instruction to the sequence. */
4850 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
4851 inst, sizeof (aarch64_inst));
4852
4853 /* Check if sequence is now full. */
4854 if (insn_sequence->next_insn >= insn_sequence->num_insns)
4855 {
4856 /* Sequence is full, but we don't have anything special to do for now,
4857 so clear and reset it. */
4858 init_insn_sequence (NULL, insn_sequence);
4859 }
4860 }
4861
4862 return res;
4863 }
4864
4865
4866 /* Return true if VALUE cannot be moved into an SVE register using DUP
4867 (with any element size, not just ESIZE) and if using DUPM would
4868 therefore be OK. ESIZE is the number of bytes in the immediate. */
4869
4870 bfd_boolean
4871 aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
4872 {
4873 int64_t svalue = uvalue;
4874 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
4875
4876 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
4877 return FALSE;
4878 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
4879 {
4880 svalue = (int32_t) uvalue;
4881 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
4882 {
4883 svalue = (int16_t) uvalue;
4884 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
4885 return FALSE;
4886 }
4887 }
4888 if ((svalue & 0xff) == 0)
4889 svalue /= 256;
4890 return svalue < -128 || svalue >= 128;
4891 }
4892
4893 /* Include the opcode description table as well as the operand description
4894 table. */
4895 #define VERIFIER(x) verify_##x
4896 #include "aarch64-tbl.h"
GDB Binutils - Deliverables
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