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[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c
1 /* aarch64-opc.c -- AArch64 opcode support.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21 #include "sysdep.h"
22 #include <assert.h>
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include <stdint.h>
26 #include <stdarg.h>
27 #include <inttypes.h>
28
29 #include "opintl.h"
30 #include "libiberty.h"
31
32 #include "aarch64-opc.h"
33
34 #ifdef DEBUG_AARCH64
35 int debug_dump = FALSE;
36 #endif /* DEBUG_AARCH64 */
37
38 /* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40 const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77 };
78
79 /* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81 const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100 };
101
102 /* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105 static inline bfd_boolean
106 vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107 {
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111 }
112
113 static inline bfd_boolean
114 fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115 {
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119 }
120
121 enum data_pattern
122 {
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128 };
129
130 static const char significant_operand_index [] =
131 {
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137 };
138
139 /* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144 static enum data_pattern
145 get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146 {
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185 }
186
187 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189 /* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195 int
196 aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197 {
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200 }
201 \f
202 const aarch64_field fields[] =
203 {
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
243 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
244 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
245 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
246 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
247 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
248 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
249 { 5, 14 }, /* imm14: in test bit and branch instructions. */
250 { 5, 16 }, /* imm16: in exception instructions. */
251 { 0, 26 }, /* imm26: in unconditional branch instructions. */
252 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
253 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
254 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
255 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
256 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
257 { 22, 1 }, /* N: in logical (immediate) instructions. */
258 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
259 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
260 { 31, 1 }, /* sf: in integer data processing instructions. */
261 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
262 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
263 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
264 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
265 { 31, 1 }, /* b5: in the test bit and branch instructions. */
266 { 19, 5 }, /* b40: in the test bit and branch instructions. */
267 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
268 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
269 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
270 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
271 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
272 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
273 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
274 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
275 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
276 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
277 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
278 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
279 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
280 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
281 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
282 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
283 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
284 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
285 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
286 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
287 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
288 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
290 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
291 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
292 { 5, 1 }, /* SVE_i1: single-bit immediate. */
293 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
294 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
295 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
296 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
297 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
298 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
299 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
300 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
301 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
302 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
303 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
304 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
305 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
306 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
307 { 16, 4 }, /* SVE_tsz: triangular size select. */
308 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
309 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
310 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
311 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
312 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
313 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
314 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
315 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
316 };
317
318 enum aarch64_operand_class
319 aarch64_get_operand_class (enum aarch64_opnd type)
320 {
321 return aarch64_operands[type].op_class;
322 }
323
324 const char *
325 aarch64_get_operand_name (enum aarch64_opnd type)
326 {
327 return aarch64_operands[type].name;
328 }
329
330 /* Get operand description string.
331 This is usually for the diagnosis purpose. */
332 const char *
333 aarch64_get_operand_desc (enum aarch64_opnd type)
334 {
335 return aarch64_operands[type].desc;
336 }
337
338 /* Table of all conditional affixes. */
339 const aarch64_cond aarch64_conds[16] =
340 {
341 {{"eq", "none"}, 0x0},
342 {{"ne", "any"}, 0x1},
343 {{"cs", "hs", "nlast"}, 0x2},
344 {{"cc", "lo", "ul", "last"}, 0x3},
345 {{"mi", "first"}, 0x4},
346 {{"pl", "nfrst"}, 0x5},
347 {{"vs"}, 0x6},
348 {{"vc"}, 0x7},
349 {{"hi", "pmore"}, 0x8},
350 {{"ls", "plast"}, 0x9},
351 {{"ge", "tcont"}, 0xa},
352 {{"lt", "tstop"}, 0xb},
353 {{"gt"}, 0xc},
354 {{"le"}, 0xd},
355 {{"al"}, 0xe},
356 {{"nv"}, 0xf},
357 };
358
359 const aarch64_cond *
360 get_cond_from_value (aarch64_insn value)
361 {
362 assert (value < 16);
363 return &aarch64_conds[(unsigned int) value];
364 }
365
366 const aarch64_cond *
367 get_inverted_cond (const aarch64_cond *cond)
368 {
369 return &aarch64_conds[cond->value ^ 0x1];
370 }
371
372 /* Table describing the operand extension/shifting operators; indexed by
373 enum aarch64_modifier_kind.
374
375 The value column provides the most common values for encoding modifiers,
376 which enables table-driven encoding/decoding for the modifiers. */
377 const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
378 {
379 {"none", 0x0},
380 {"msl", 0x0},
381 {"ror", 0x3},
382 {"asr", 0x2},
383 {"lsr", 0x1},
384 {"lsl", 0x0},
385 {"uxtb", 0x0},
386 {"uxth", 0x1},
387 {"uxtw", 0x2},
388 {"uxtx", 0x3},
389 {"sxtb", 0x4},
390 {"sxth", 0x5},
391 {"sxtw", 0x6},
392 {"sxtx", 0x7},
393 {"mul", 0x0},
394 {"mul vl", 0x0},
395 {NULL, 0},
396 };
397
398 enum aarch64_modifier_kind
399 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
400 {
401 return desc - aarch64_operand_modifiers;
402 }
403
404 aarch64_insn
405 aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
406 {
407 return aarch64_operand_modifiers[kind].value;
408 }
409
410 enum aarch64_modifier_kind
411 aarch64_get_operand_modifier_from_value (aarch64_insn value,
412 bfd_boolean extend_p)
413 {
414 if (extend_p == TRUE)
415 return AARCH64_MOD_UXTB + value;
416 else
417 return AARCH64_MOD_LSL - value;
418 }
419
420 bfd_boolean
421 aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
422 {
423 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
424 ? TRUE : FALSE;
425 }
426
427 static inline bfd_boolean
428 aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
429 {
430 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
431 ? TRUE : FALSE;
432 }
433
434 const struct aarch64_name_value_pair aarch64_barrier_options[16] =
435 {
436 { "#0x00", 0x0 },
437 { "oshld", 0x1 },
438 { "oshst", 0x2 },
439 { "osh", 0x3 },
440 { "#0x04", 0x4 },
441 { "nshld", 0x5 },
442 { "nshst", 0x6 },
443 { "nsh", 0x7 },
444 { "#0x08", 0x8 },
445 { "ishld", 0x9 },
446 { "ishst", 0xa },
447 { "ish", 0xb },
448 { "#0x0c", 0xc },
449 { "ld", 0xd },
450 { "st", 0xe },
451 { "sy", 0xf },
452 };
453
454 /* Table describing the operands supported by the aliases of the HINT
455 instruction.
456
457 The name column is the operand that is accepted for the alias. The value
458 column is the hint number of the alias. The list of operands is terminated
459 by NULL in the name column. */
460
461 const struct aarch64_name_value_pair aarch64_hint_options[] =
462 {
463 { "csync", 0x11 }, /* PSB CSYNC. */
464 { NULL, 0x0 },
465 };
466
467 /* op -> op: load = 0 instruction = 1 store = 2
468 l -> level: 1-3
469 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
470 #define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
471 const struct aarch64_name_value_pair aarch64_prfops[32] =
472 {
473 { "pldl1keep", B(0, 1, 0) },
474 { "pldl1strm", B(0, 1, 1) },
475 { "pldl2keep", B(0, 2, 0) },
476 { "pldl2strm", B(0, 2, 1) },
477 { "pldl3keep", B(0, 3, 0) },
478 { "pldl3strm", B(0, 3, 1) },
479 { NULL, 0x06 },
480 { NULL, 0x07 },
481 { "plil1keep", B(1, 1, 0) },
482 { "plil1strm", B(1, 1, 1) },
483 { "plil2keep", B(1, 2, 0) },
484 { "plil2strm", B(1, 2, 1) },
485 { "plil3keep", B(1, 3, 0) },
486 { "plil3strm", B(1, 3, 1) },
487 { NULL, 0x0e },
488 { NULL, 0x0f },
489 { "pstl1keep", B(2, 1, 0) },
490 { "pstl1strm", B(2, 1, 1) },
491 { "pstl2keep", B(2, 2, 0) },
492 { "pstl2strm", B(2, 2, 1) },
493 { "pstl3keep", B(2, 3, 0) },
494 { "pstl3strm", B(2, 3, 1) },
495 { NULL, 0x16 },
496 { NULL, 0x17 },
497 { NULL, 0x18 },
498 { NULL, 0x19 },
499 { NULL, 0x1a },
500 { NULL, 0x1b },
501 { NULL, 0x1c },
502 { NULL, 0x1d },
503 { NULL, 0x1e },
504 { NULL, 0x1f },
505 };
506 #undef B
507 \f
508 /* Utilities on value constraint. */
509
510 static inline int
511 value_in_range_p (int64_t value, int low, int high)
512 {
513 return (value >= low && value <= high) ? 1 : 0;
514 }
515
516 /* Return true if VALUE is a multiple of ALIGN. */
517 static inline int
518 value_aligned_p (int64_t value, int align)
519 {
520 return (value % align) == 0;
521 }
522
523 /* A signed value fits in a field. */
524 static inline int
525 value_fit_signed_field_p (int64_t value, unsigned width)
526 {
527 assert (width < 32);
528 if (width < sizeof (value) * 8)
529 {
530 int64_t lim = (int64_t)1 << (width - 1);
531 if (value >= -lim && value < lim)
532 return 1;
533 }
534 return 0;
535 }
536
537 /* An unsigned value fits in a field. */
538 static inline int
539 value_fit_unsigned_field_p (int64_t value, unsigned width)
540 {
541 assert (width < 32);
542 if (width < sizeof (value) * 8)
543 {
544 int64_t lim = (int64_t)1 << width;
545 if (value >= 0 && value < lim)
546 return 1;
547 }
548 return 0;
549 }
550
551 /* Return 1 if OPERAND is SP or WSP. */
552 int
553 aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
554 {
555 return ((aarch64_get_operand_class (operand->type)
556 == AARCH64_OPND_CLASS_INT_REG)
557 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
558 && operand->reg.regno == 31);
559 }
560
561 /* Return 1 if OPERAND is XZR or WZP. */
562 int
563 aarch64_zero_register_p (const aarch64_opnd_info *operand)
564 {
565 return ((aarch64_get_operand_class (operand->type)
566 == AARCH64_OPND_CLASS_INT_REG)
567 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
568 && operand->reg.regno == 31);
569 }
570
571 /* Return true if the operand *OPERAND that has the operand code
572 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
573 qualified by the qualifier TARGET. */
574
575 static inline int
576 operand_also_qualified_p (const struct aarch64_opnd_info *operand,
577 aarch64_opnd_qualifier_t target)
578 {
579 switch (operand->qualifier)
580 {
581 case AARCH64_OPND_QLF_W:
582 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
583 return 1;
584 break;
585 case AARCH64_OPND_QLF_X:
586 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
587 return 1;
588 break;
589 case AARCH64_OPND_QLF_WSP:
590 if (target == AARCH64_OPND_QLF_W
591 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
592 return 1;
593 break;
594 case AARCH64_OPND_QLF_SP:
595 if (target == AARCH64_OPND_QLF_X
596 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
597 return 1;
598 break;
599 default:
600 break;
601 }
602
603 return 0;
604 }
605
606 /* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
607 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
608
609 Return NIL if more than one expected qualifiers are found. */
610
611 aarch64_opnd_qualifier_t
612 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
613 int idx,
614 const aarch64_opnd_qualifier_t known_qlf,
615 int known_idx)
616 {
617 int i, saved_i;
618
619 /* Special case.
620
621 When the known qualifier is NIL, we have to assume that there is only
622 one qualifier sequence in the *QSEQ_LIST and return the corresponding
623 qualifier directly. One scenario is that for instruction
624 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
625 which has only one possible valid qualifier sequence
626 NIL, S_D
627 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
628 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
629
630 Because the qualifier NIL has dual roles in the qualifier sequence:
631 it can mean no qualifier for the operand, or the qualifer sequence is
632 not in use (when all qualifiers in the sequence are NILs), we have to
633 handle this special case here. */
634 if (known_qlf == AARCH64_OPND_NIL)
635 {
636 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
637 return qseq_list[0][idx];
638 }
639
640 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
641 {
642 if (qseq_list[i][known_idx] == known_qlf)
643 {
644 if (saved_i != -1)
645 /* More than one sequences are found to have KNOWN_QLF at
646 KNOWN_IDX. */
647 return AARCH64_OPND_NIL;
648 saved_i = i;
649 }
650 }
651
652 return qseq_list[saved_i][idx];
653 }
654
655 enum operand_qualifier_kind
656 {
657 OQK_NIL,
658 OQK_OPD_VARIANT,
659 OQK_VALUE_IN_RANGE,
660 OQK_MISC,
661 };
662
663 /* Operand qualifier description. */
664 struct operand_qualifier_data
665 {
666 /* The usage of the three data fields depends on the qualifier kind. */
667 int data0;
668 int data1;
669 int data2;
670 /* Description. */
671 const char *desc;
672 /* Kind. */
673 enum operand_qualifier_kind kind;
674 };
675
676 /* Indexed by the operand qualifier enumerators. */
677 struct operand_qualifier_data aarch64_opnd_qualifiers[] =
678 {
679 {0, 0, 0, "NIL", OQK_NIL},
680
681 /* Operand variant qualifiers.
682 First 3 fields:
683 element size, number of elements and common value for encoding. */
684
685 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
686 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
687 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
688 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
689
690 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
691 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
692 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
693 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
694 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
695
696 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
697 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
698 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
699 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
700 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
701 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
702 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
703 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
704 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
705 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
706
707 {0, 0, 0, "z", OQK_OPD_VARIANT},
708 {0, 0, 0, "m", OQK_OPD_VARIANT},
709
710 /* Qualifiers constraining the value range.
711 First 3 fields:
712 Lower bound, higher bound, unused. */
713
714 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
715 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
716 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
717 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
718 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
719 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
720
721 /* Qualifiers for miscellaneous purpose.
722 First 3 fields:
723 unused, unused and unused. */
724
725 {0, 0, 0, "lsl", 0},
726 {0, 0, 0, "msl", 0},
727
728 {0, 0, 0, "retrieving", 0},
729 };
730
731 static inline bfd_boolean
732 operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
733 {
734 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
735 ? TRUE : FALSE;
736 }
737
738 static inline bfd_boolean
739 qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
740 {
741 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
742 ? TRUE : FALSE;
743 }
744
745 const char*
746 aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
747 {
748 return aarch64_opnd_qualifiers[qualifier].desc;
749 }
750
751 /* Given an operand qualifier, return the expected data element size
752 of a qualified operand. */
753 unsigned char
754 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
755 {
756 assert (operand_variant_qualifier_p (qualifier) == TRUE);
757 return aarch64_opnd_qualifiers[qualifier].data0;
758 }
759
760 unsigned char
761 aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
762 {
763 assert (operand_variant_qualifier_p (qualifier) == TRUE);
764 return aarch64_opnd_qualifiers[qualifier].data1;
765 }
766
767 aarch64_insn
768 aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
769 {
770 assert (operand_variant_qualifier_p (qualifier) == TRUE);
771 return aarch64_opnd_qualifiers[qualifier].data2;
772 }
773
774 static int
775 get_lower_bound (aarch64_opnd_qualifier_t qualifier)
776 {
777 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
778 return aarch64_opnd_qualifiers[qualifier].data0;
779 }
780
781 static int
782 get_upper_bound (aarch64_opnd_qualifier_t qualifier)
783 {
784 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
785 return aarch64_opnd_qualifiers[qualifier].data1;
786 }
787
788 #ifdef DEBUG_AARCH64
789 void
790 aarch64_verbose (const char *str, ...)
791 {
792 va_list ap;
793 va_start (ap, str);
794 printf ("#### ");
795 vprintf (str, ap);
796 printf ("\n");
797 va_end (ap);
798 }
799
800 static inline void
801 dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
802 {
803 int i;
804 printf ("#### \t");
805 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
806 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
807 printf ("\n");
808 }
809
810 static void
811 dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
812 const aarch64_opnd_qualifier_t *qualifier)
813 {
814 int i;
815 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
816
817 aarch64_verbose ("dump_match_qualifiers:");
818 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
819 curr[i] = opnd[i].qualifier;
820 dump_qualifier_sequence (curr);
821 aarch64_verbose ("against");
822 dump_qualifier_sequence (qualifier);
823 }
824 #endif /* DEBUG_AARCH64 */
825
826 /* TODO improve this, we can have an extra field at the runtime to
827 store the number of operands rather than calculating it every time. */
828
829 int
830 aarch64_num_of_operands (const aarch64_opcode *opcode)
831 {
832 int i = 0;
833 const enum aarch64_opnd *opnds = opcode->operands;
834 while (opnds[i++] != AARCH64_OPND_NIL)
835 ;
836 --i;
837 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
838 return i;
839 }
840
841 /* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
842 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
843
844 N.B. on the entry, it is very likely that only some operands in *INST
845 have had their qualifiers been established.
846
847 If STOP_AT is not -1, the function will only try to match
848 the qualifier sequence for operands before and including the operand
849 of index STOP_AT; and on success *RET will only be filled with the first
850 (STOP_AT+1) qualifiers.
851
852 A couple examples of the matching algorithm:
853
854 X,W,NIL should match
855 X,W,NIL
856
857 NIL,NIL should match
858 X ,NIL
859
860 Apart from serving the main encoding routine, this can also be called
861 during or after the operand decoding. */
862
863 int
864 aarch64_find_best_match (const aarch64_inst *inst,
865 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
866 int stop_at, aarch64_opnd_qualifier_t *ret)
867 {
868 int found = 0;
869 int i, num_opnds;
870 const aarch64_opnd_qualifier_t *qualifiers;
871
872 num_opnds = aarch64_num_of_operands (inst->opcode);
873 if (num_opnds == 0)
874 {
875 DEBUG_TRACE ("SUCCEED: no operand");
876 return 1;
877 }
878
879 if (stop_at < 0 || stop_at >= num_opnds)
880 stop_at = num_opnds - 1;
881
882 /* For each pattern. */
883 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
884 {
885 int j;
886 qualifiers = *qualifiers_list;
887
888 /* Start as positive. */
889 found = 1;
890
891 DEBUG_TRACE ("%d", i);
892 #ifdef DEBUG_AARCH64
893 if (debug_dump)
894 dump_match_qualifiers (inst->operands, qualifiers);
895 #endif
896
897 /* Most opcodes has much fewer patterns in the list.
898 First NIL qualifier indicates the end in the list. */
899 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
900 {
901 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
902 if (i)
903 found = 0;
904 break;
905 }
906
907 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
908 {
909 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
910 {
911 /* Either the operand does not have qualifier, or the qualifier
912 for the operand needs to be deduced from the qualifier
913 sequence.
914 In the latter case, any constraint checking related with
915 the obtained qualifier should be done later in
916 operand_general_constraint_met_p. */
917 continue;
918 }
919 else if (*qualifiers != inst->operands[j].qualifier)
920 {
921 /* Unless the target qualifier can also qualify the operand
922 (which has already had a non-nil qualifier), non-equal
923 qualifiers are generally un-matched. */
924 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
925 continue;
926 else
927 {
928 found = 0;
929 break;
930 }
931 }
932 else
933 continue; /* Equal qualifiers are certainly matched. */
934 }
935
936 /* Qualifiers established. */
937 if (found == 1)
938 break;
939 }
940
941 if (found == 1)
942 {
943 /* Fill the result in *RET. */
944 int j;
945 qualifiers = *qualifiers_list;
946
947 DEBUG_TRACE ("complete qualifiers using list %d", i);
948 #ifdef DEBUG_AARCH64
949 if (debug_dump)
950 dump_qualifier_sequence (qualifiers);
951 #endif
952
953 for (j = 0; j <= stop_at; ++j, ++qualifiers)
954 ret[j] = *qualifiers;
955 for (; j < AARCH64_MAX_OPND_NUM; ++j)
956 ret[j] = AARCH64_OPND_QLF_NIL;
957
958 DEBUG_TRACE ("SUCCESS");
959 return 1;
960 }
961
962 DEBUG_TRACE ("FAIL");
963 return 0;
964 }
965
966 /* Operand qualifier matching and resolving.
967
968 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
969 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
970
971 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
972 succeeds. */
973
974 static int
975 match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
976 {
977 int i, nops;
978 aarch64_opnd_qualifier_seq_t qualifiers;
979
980 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
981 qualifiers))
982 {
983 DEBUG_TRACE ("matching FAIL");
984 return 0;
985 }
986
987 if (inst->opcode->flags & F_STRICT)
988 {
989 /* Require an exact qualifier match, even for NIL qualifiers. */
990 nops = aarch64_num_of_operands (inst->opcode);
991 for (i = 0; i < nops; ++i)
992 if (inst->operands[i].qualifier != qualifiers[i])
993 return FALSE;
994 }
995
996 /* Update the qualifiers. */
997 if (update_p == TRUE)
998 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
999 {
1000 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1001 break;
1002 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1003 "update %s with %s for operand %d",
1004 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1005 aarch64_get_qualifier_name (qualifiers[i]), i);
1006 inst->operands[i].qualifier = qualifiers[i];
1007 }
1008
1009 DEBUG_TRACE ("matching SUCCESS");
1010 return 1;
1011 }
1012
1013 /* Return TRUE if VALUE is a wide constant that can be moved into a general
1014 register by MOVZ.
1015
1016 IS32 indicates whether value is a 32-bit immediate or not.
1017 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1018 amount will be returned in *SHIFT_AMOUNT. */
1019
1020 bfd_boolean
1021 aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1022 {
1023 int amount;
1024
1025 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1026
1027 if (is32)
1028 {
1029 /* Allow all zeros or all ones in top 32-bits, so that
1030 32-bit constant expressions like ~0x80000000 are
1031 permitted. */
1032 uint64_t ext = value;
1033 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1034 /* Immediate out of range. */
1035 return FALSE;
1036 value &= (int64_t) 0xffffffff;
1037 }
1038
1039 /* first, try movz then movn */
1040 amount = -1;
1041 if ((value & ((int64_t) 0xffff << 0)) == value)
1042 amount = 0;
1043 else if ((value & ((int64_t) 0xffff << 16)) == value)
1044 amount = 16;
1045 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1046 amount = 32;
1047 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1048 amount = 48;
1049
1050 if (amount == -1)
1051 {
1052 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1053 return FALSE;
1054 }
1055
1056 if (shift_amount != NULL)
1057 *shift_amount = amount;
1058
1059 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1060
1061 return TRUE;
1062 }
1063
1064 /* Build the accepted values for immediate logical SIMD instructions.
1065
1066 The standard encodings of the immediate value are:
1067 N imms immr SIMD size R S
1068 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1069 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1070 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1071 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1072 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1073 0 11110s 00000r 2 UInt(r) UInt(s)
1074 where all-ones value of S is reserved.
1075
1076 Let's call E the SIMD size.
1077
1078 The immediate value is: S+1 bits '1' rotated to the right by R.
1079
1080 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1081 (remember S != E - 1). */
1082
1083 #define TOTAL_IMM_NB 5334
1084
1085 typedef struct
1086 {
1087 uint64_t imm;
1088 aarch64_insn encoding;
1089 } simd_imm_encoding;
1090
1091 static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1092
1093 static int
1094 simd_imm_encoding_cmp(const void *i1, const void *i2)
1095 {
1096 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1097 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1098
1099 if (imm1->imm < imm2->imm)
1100 return -1;
1101 if (imm1->imm > imm2->imm)
1102 return +1;
1103 return 0;
1104 }
1105
1106 /* immediate bitfield standard encoding
1107 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1108 1 ssssss rrrrrr 64 rrrrrr ssssss
1109 0 0sssss 0rrrrr 32 rrrrr sssss
1110 0 10ssss 00rrrr 16 rrrr ssss
1111 0 110sss 000rrr 8 rrr sss
1112 0 1110ss 0000rr 4 rr ss
1113 0 11110s 00000r 2 r s */
1114 static inline int
1115 encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1116 {
1117 return (is64 << 12) | (r << 6) | s;
1118 }
1119
1120 static void
1121 build_immediate_table (void)
1122 {
1123 uint32_t log_e, e, s, r, s_mask;
1124 uint64_t mask, imm;
1125 int nb_imms;
1126 int is64;
1127
1128 nb_imms = 0;
1129 for (log_e = 1; log_e <= 6; log_e++)
1130 {
1131 /* Get element size. */
1132 e = 1u << log_e;
1133 if (log_e == 6)
1134 {
1135 is64 = 1;
1136 mask = 0xffffffffffffffffull;
1137 s_mask = 0;
1138 }
1139 else
1140 {
1141 is64 = 0;
1142 mask = (1ull << e) - 1;
1143 /* log_e s_mask
1144 1 ((1 << 4) - 1) << 2 = 111100
1145 2 ((1 << 3) - 1) << 3 = 111000
1146 3 ((1 << 2) - 1) << 4 = 110000
1147 4 ((1 << 1) - 1) << 5 = 100000
1148 5 ((1 << 0) - 1) << 6 = 000000 */
1149 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1150 }
1151 for (s = 0; s < e - 1; s++)
1152 for (r = 0; r < e; r++)
1153 {
1154 /* s+1 consecutive bits to 1 (s < 63) */
1155 imm = (1ull << (s + 1)) - 1;
1156 /* rotate right by r */
1157 if (r != 0)
1158 imm = (imm >> r) | ((imm << (e - r)) & mask);
1159 /* replicate the constant depending on SIMD size */
1160 switch (log_e)
1161 {
1162 case 1: imm = (imm << 2) | imm;
1163 /* Fall through. */
1164 case 2: imm = (imm << 4) | imm;
1165 /* Fall through. */
1166 case 3: imm = (imm << 8) | imm;
1167 /* Fall through. */
1168 case 4: imm = (imm << 16) | imm;
1169 /* Fall through. */
1170 case 5: imm = (imm << 32) | imm;
1171 /* Fall through. */
1172 case 6: break;
1173 default: abort ();
1174 }
1175 simd_immediates[nb_imms].imm = imm;
1176 simd_immediates[nb_imms].encoding =
1177 encode_immediate_bitfield(is64, s | s_mask, r);
1178 nb_imms++;
1179 }
1180 }
1181 assert (nb_imms == TOTAL_IMM_NB);
1182 qsort(simd_immediates, nb_imms,
1183 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1184 }
1185
1186 /* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1187 be accepted by logical (immediate) instructions
1188 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1189
1190 ESIZE is the number of bytes in the decoded immediate value.
1191 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1192 VALUE will be returned in *ENCODING. */
1193
1194 bfd_boolean
1195 aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
1196 {
1197 simd_imm_encoding imm_enc;
1198 const simd_imm_encoding *imm_encoding;
1199 static bfd_boolean initialized = FALSE;
1200 uint64_t upper;
1201 int i;
1202
1203 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), is32: %d", value,
1204 value, is32);
1205
1206 if (initialized == FALSE)
1207 {
1208 build_immediate_table ();
1209 initialized = TRUE;
1210 }
1211
1212 /* Allow all zeros or all ones in top bits, so that
1213 constant expressions like ~1 are permitted. */
1214 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1215 if ((value & ~upper) != value && (value | upper) != value)
1216 return FALSE;
1217
1218 /* Replicate to a full 64-bit value. */
1219 value &= ~upper;
1220 for (i = esize * 8; i < 64; i *= 2)
1221 value |= (value << i);
1222
1223 imm_enc.imm = value;
1224 imm_encoding = (const simd_imm_encoding *)
1225 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1226 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1227 if (imm_encoding == NULL)
1228 {
1229 DEBUG_TRACE ("exit with FALSE");
1230 return FALSE;
1231 }
1232 if (encoding != NULL)
1233 *encoding = imm_encoding->encoding;
1234 DEBUG_TRACE ("exit with TRUE");
1235 return TRUE;
1236 }
1237
1238 /* If 64-bit immediate IMM is in the format of
1239 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1240 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1241 of value "abcdefgh". Otherwise return -1. */
1242 int
1243 aarch64_shrink_expanded_imm8 (uint64_t imm)
1244 {
1245 int i, ret;
1246 uint32_t byte;
1247
1248 ret = 0;
1249 for (i = 0; i < 8; i++)
1250 {
1251 byte = (imm >> (8 * i)) & 0xff;
1252 if (byte == 0xff)
1253 ret |= 1 << i;
1254 else if (byte != 0x00)
1255 return -1;
1256 }
1257 return ret;
1258 }
1259
1260 /* Utility inline functions for operand_general_constraint_met_p. */
1261
1262 static inline void
1263 set_error (aarch64_operand_error *mismatch_detail,
1264 enum aarch64_operand_error_kind kind, int idx,
1265 const char* error)
1266 {
1267 if (mismatch_detail == NULL)
1268 return;
1269 mismatch_detail->kind = kind;
1270 mismatch_detail->index = idx;
1271 mismatch_detail->error = error;
1272 }
1273
1274 static inline void
1275 set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1276 const char* error)
1277 {
1278 if (mismatch_detail == NULL)
1279 return;
1280 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1281 }
1282
1283 static inline void
1284 set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1285 int idx, int lower_bound, int upper_bound,
1286 const char* error)
1287 {
1288 if (mismatch_detail == NULL)
1289 return;
1290 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1291 mismatch_detail->data[0] = lower_bound;
1292 mismatch_detail->data[1] = upper_bound;
1293 }
1294
1295 static inline void
1296 set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1297 int idx, int lower_bound, int upper_bound)
1298 {
1299 if (mismatch_detail == NULL)
1300 return;
1301 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1302 _("immediate value"));
1303 }
1304
1305 static inline void
1306 set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1307 int idx, int lower_bound, int upper_bound)
1308 {
1309 if (mismatch_detail == NULL)
1310 return;
1311 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1312 _("immediate offset"));
1313 }
1314
1315 static inline void
1316 set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1317 int idx, int lower_bound, int upper_bound)
1318 {
1319 if (mismatch_detail == NULL)
1320 return;
1321 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1322 _("register number"));
1323 }
1324
1325 static inline void
1326 set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1327 int idx, int lower_bound, int upper_bound)
1328 {
1329 if (mismatch_detail == NULL)
1330 return;
1331 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1332 _("register element index"));
1333 }
1334
1335 static inline void
1336 set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1337 int idx, int lower_bound, int upper_bound)
1338 {
1339 if (mismatch_detail == NULL)
1340 return;
1341 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1342 _("shift amount"));
1343 }
1344
1345 /* Report that the MUL modifier in operand IDX should be in the range
1346 [LOWER_BOUND, UPPER_BOUND]. */
1347 static inline void
1348 set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1349 int idx, int lower_bound, int upper_bound)
1350 {
1351 if (mismatch_detail == NULL)
1352 return;
1353 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1354 _("multiplier"));
1355 }
1356
1357 static inline void
1358 set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1359 int alignment)
1360 {
1361 if (mismatch_detail == NULL)
1362 return;
1363 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1364 mismatch_detail->data[0] = alignment;
1365 }
1366
1367 static inline void
1368 set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1369 int expected_num)
1370 {
1371 if (mismatch_detail == NULL)
1372 return;
1373 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1374 mismatch_detail->data[0] = expected_num;
1375 }
1376
1377 static inline void
1378 set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1379 const char* error)
1380 {
1381 if (mismatch_detail == NULL)
1382 return;
1383 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1384 }
1385
1386 /* General constraint checking based on operand code.
1387
1388 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1389 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1390
1391 This function has to be called after the qualifiers for all operands
1392 have been resolved.
1393
1394 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1395 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1396 of error message during the disassembling where error message is not
1397 wanted. We avoid the dynamic construction of strings of error messages
1398 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1399 use a combination of error code, static string and some integer data to
1400 represent an error. */
1401
1402 static int
1403 operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1404 enum aarch64_opnd type,
1405 const aarch64_opcode *opcode,
1406 aarch64_operand_error *mismatch_detail)
1407 {
1408 unsigned num, modifiers, shift;
1409 unsigned char size;
1410 int64_t imm, min_value, max_value;
1411 uint64_t uvalue, mask;
1412 const aarch64_opnd_info *opnd = opnds + idx;
1413 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1414
1415 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1416
1417 switch (aarch64_operands[type].op_class)
1418 {
1419 case AARCH64_OPND_CLASS_INT_REG:
1420 /* Check pair reg constraints for cas* instructions. */
1421 if (type == AARCH64_OPND_PAIRREG)
1422 {
1423 assert (idx == 1 || idx == 3);
1424 if (opnds[idx - 1].reg.regno % 2 != 0)
1425 {
1426 set_syntax_error (mismatch_detail, idx - 1,
1427 _("reg pair must start from even reg"));
1428 return 0;
1429 }
1430 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1431 {
1432 set_syntax_error (mismatch_detail, idx,
1433 _("reg pair must be contiguous"));
1434 return 0;
1435 }
1436 break;
1437 }
1438
1439 /* <Xt> may be optional in some IC and TLBI instructions. */
1440 if (type == AARCH64_OPND_Rt_SYS)
1441 {
1442 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1443 == AARCH64_OPND_CLASS_SYSTEM));
1444 if (opnds[1].present
1445 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1446 {
1447 set_other_error (mismatch_detail, idx, _("extraneous register"));
1448 return 0;
1449 }
1450 if (!opnds[1].present
1451 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1452 {
1453 set_other_error (mismatch_detail, idx, _("missing register"));
1454 return 0;
1455 }
1456 }
1457 switch (qualifier)
1458 {
1459 case AARCH64_OPND_QLF_WSP:
1460 case AARCH64_OPND_QLF_SP:
1461 if (!aarch64_stack_pointer_p (opnd))
1462 {
1463 set_other_error (mismatch_detail, idx,
1464 _("stack pointer register expected"));
1465 return 0;
1466 }
1467 break;
1468 default:
1469 break;
1470 }
1471 break;
1472
1473 case AARCH64_OPND_CLASS_SVE_REG:
1474 switch (type)
1475 {
1476 case AARCH64_OPND_SVE_Zn_INDEX:
1477 size = aarch64_get_qualifier_esize (opnd->qualifier);
1478 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1479 {
1480 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1481 0, 64 / size - 1);
1482 return 0;
1483 }
1484 break;
1485
1486 case AARCH64_OPND_SVE_ZnxN:
1487 case AARCH64_OPND_SVE_ZtxN:
1488 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1489 {
1490 set_other_error (mismatch_detail, idx,
1491 _("invalid register list"));
1492 return 0;
1493 }
1494 break;
1495
1496 default:
1497 break;
1498 }
1499 break;
1500
1501 case AARCH64_OPND_CLASS_PRED_REG:
1502 if (opnd->reg.regno >= 8
1503 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1504 {
1505 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1506 return 0;
1507 }
1508 break;
1509
1510 case AARCH64_OPND_CLASS_COND:
1511 if (type == AARCH64_OPND_COND1
1512 && (opnds[idx].cond->value & 0xe) == 0xe)
1513 {
1514 /* Not allow AL or NV. */
1515 set_syntax_error (mismatch_detail, idx, NULL);
1516 }
1517 break;
1518
1519 case AARCH64_OPND_CLASS_ADDRESS:
1520 /* Check writeback. */
1521 switch (opcode->iclass)
1522 {
1523 case ldst_pos:
1524 case ldst_unscaled:
1525 case ldstnapair_offs:
1526 case ldstpair_off:
1527 case ldst_unpriv:
1528 if (opnd->addr.writeback == 1)
1529 {
1530 set_syntax_error (mismatch_detail, idx,
1531 _("unexpected address writeback"));
1532 return 0;
1533 }
1534 break;
1535 case ldst_imm10:
1536 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1537 {
1538 set_syntax_error (mismatch_detail, idx,
1539 _("unexpected address writeback"));
1540 return 0;
1541 }
1542 break;
1543 case ldst_imm9:
1544 case ldstpair_indexed:
1545 case asisdlsep:
1546 case asisdlsop:
1547 if (opnd->addr.writeback == 0)
1548 {
1549 set_syntax_error (mismatch_detail, idx,
1550 _("address writeback expected"));
1551 return 0;
1552 }
1553 break;
1554 default:
1555 assert (opnd->addr.writeback == 0);
1556 break;
1557 }
1558 switch (type)
1559 {
1560 case AARCH64_OPND_ADDR_SIMM7:
1561 /* Scaled signed 7 bits immediate offset. */
1562 /* Get the size of the data element that is accessed, which may be
1563 different from that of the source register size,
1564 e.g. in strb/ldrb. */
1565 size = aarch64_get_qualifier_esize (opnd->qualifier);
1566 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1567 {
1568 set_offset_out_of_range_error (mismatch_detail, idx,
1569 -64 * size, 63 * size);
1570 return 0;
1571 }
1572 if (!value_aligned_p (opnd->addr.offset.imm, size))
1573 {
1574 set_unaligned_error (mismatch_detail, idx, size);
1575 return 0;
1576 }
1577 break;
1578 case AARCH64_OPND_ADDR_SIMM9:
1579 /* Unscaled signed 9 bits immediate offset. */
1580 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1581 {
1582 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1583 return 0;
1584 }
1585 break;
1586
1587 case AARCH64_OPND_ADDR_SIMM9_2:
1588 /* Unscaled signed 9 bits immediate offset, which has to be negative
1589 or unaligned. */
1590 size = aarch64_get_qualifier_esize (qualifier);
1591 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1592 && !value_aligned_p (opnd->addr.offset.imm, size))
1593 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1594 return 1;
1595 set_other_error (mismatch_detail, idx,
1596 _("negative or unaligned offset expected"));
1597 return 0;
1598
1599 case AARCH64_OPND_ADDR_SIMM10:
1600 /* Scaled signed 10 bits immediate offset. */
1601 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1602 {
1603 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1604 return 0;
1605 }
1606 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1607 {
1608 set_unaligned_error (mismatch_detail, idx, 8);
1609 return 0;
1610 }
1611 break;
1612
1613 case AARCH64_OPND_SIMD_ADDR_POST:
1614 /* AdvSIMD load/store multiple structures, post-index. */
1615 assert (idx == 1);
1616 if (opnd->addr.offset.is_reg)
1617 {
1618 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1619 return 1;
1620 else
1621 {
1622 set_other_error (mismatch_detail, idx,
1623 _("invalid register offset"));
1624 return 0;
1625 }
1626 }
1627 else
1628 {
1629 const aarch64_opnd_info *prev = &opnds[idx-1];
1630 unsigned num_bytes; /* total number of bytes transferred. */
1631 /* The opcode dependent area stores the number of elements in
1632 each structure to be loaded/stored. */
1633 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1634 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1635 /* Special handling of loading single structure to all lane. */
1636 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1637 * aarch64_get_qualifier_esize (prev->qualifier);
1638 else
1639 num_bytes = prev->reglist.num_regs
1640 * aarch64_get_qualifier_esize (prev->qualifier)
1641 * aarch64_get_qualifier_nelem (prev->qualifier);
1642 if ((int) num_bytes != opnd->addr.offset.imm)
1643 {
1644 set_other_error (mismatch_detail, idx,
1645 _("invalid post-increment amount"));
1646 return 0;
1647 }
1648 }
1649 break;
1650
1651 case AARCH64_OPND_ADDR_REGOFF:
1652 /* Get the size of the data element that is accessed, which may be
1653 different from that of the source register size,
1654 e.g. in strb/ldrb. */
1655 size = aarch64_get_qualifier_esize (opnd->qualifier);
1656 /* It is either no shift or shift by the binary logarithm of SIZE. */
1657 if (opnd->shifter.amount != 0
1658 && opnd->shifter.amount != (int)get_logsz (size))
1659 {
1660 set_other_error (mismatch_detail, idx,
1661 _("invalid shift amount"));
1662 return 0;
1663 }
1664 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1665 operators. */
1666 switch (opnd->shifter.kind)
1667 {
1668 case AARCH64_MOD_UXTW:
1669 case AARCH64_MOD_LSL:
1670 case AARCH64_MOD_SXTW:
1671 case AARCH64_MOD_SXTX: break;
1672 default:
1673 set_other_error (mismatch_detail, idx,
1674 _("invalid extend/shift operator"));
1675 return 0;
1676 }
1677 break;
1678
1679 case AARCH64_OPND_ADDR_UIMM12:
1680 imm = opnd->addr.offset.imm;
1681 /* Get the size of the data element that is accessed, which may be
1682 different from that of the source register size,
1683 e.g. in strb/ldrb. */
1684 size = aarch64_get_qualifier_esize (qualifier);
1685 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1686 {
1687 set_offset_out_of_range_error (mismatch_detail, idx,
1688 0, 4095 * size);
1689 return 0;
1690 }
1691 if (!value_aligned_p (opnd->addr.offset.imm, size))
1692 {
1693 set_unaligned_error (mismatch_detail, idx, size);
1694 return 0;
1695 }
1696 break;
1697
1698 case AARCH64_OPND_ADDR_PCREL14:
1699 case AARCH64_OPND_ADDR_PCREL19:
1700 case AARCH64_OPND_ADDR_PCREL21:
1701 case AARCH64_OPND_ADDR_PCREL26:
1702 imm = opnd->imm.value;
1703 if (operand_need_shift_by_two (get_operand_from_code (type)))
1704 {
1705 /* The offset value in a PC-relative branch instruction is alway
1706 4-byte aligned and is encoded without the lowest 2 bits. */
1707 if (!value_aligned_p (imm, 4))
1708 {
1709 set_unaligned_error (mismatch_detail, idx, 4);
1710 return 0;
1711 }
1712 /* Right shift by 2 so that we can carry out the following check
1713 canonically. */
1714 imm >>= 2;
1715 }
1716 size = get_operand_fields_width (get_operand_from_code (type));
1717 if (!value_fit_signed_field_p (imm, size))
1718 {
1719 set_other_error (mismatch_detail, idx,
1720 _("immediate out of range"));
1721 return 0;
1722 }
1723 break;
1724
1725 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1726 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1727 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1728 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1729 min_value = -8;
1730 max_value = 7;
1731 sve_imm_offset_vl:
1732 assert (!opnd->addr.offset.is_reg);
1733 assert (opnd->addr.preind);
1734 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1735 min_value *= num;
1736 max_value *= num;
1737 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1738 || (opnd->shifter.operator_present
1739 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1740 {
1741 set_other_error (mismatch_detail, idx,
1742 _("invalid addressing mode"));
1743 return 0;
1744 }
1745 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1746 {
1747 set_offset_out_of_range_error (mismatch_detail, idx,
1748 min_value, max_value);
1749 return 0;
1750 }
1751 if (!value_aligned_p (opnd->addr.offset.imm, num))
1752 {
1753 set_unaligned_error (mismatch_detail, idx, num);
1754 return 0;
1755 }
1756 break;
1757
1758 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1759 min_value = -32;
1760 max_value = 31;
1761 goto sve_imm_offset_vl;
1762
1763 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1764 min_value = -256;
1765 max_value = 255;
1766 goto sve_imm_offset_vl;
1767
1768 case AARCH64_OPND_SVE_ADDR_RI_U6:
1769 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1770 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1771 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1772 min_value = 0;
1773 max_value = 63;
1774 sve_imm_offset:
1775 assert (!opnd->addr.offset.is_reg);
1776 assert (opnd->addr.preind);
1777 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1778 min_value *= num;
1779 max_value *= num;
1780 if (opnd->shifter.operator_present
1781 || opnd->shifter.amount_present)
1782 {
1783 set_other_error (mismatch_detail, idx,
1784 _("invalid addressing mode"));
1785 return 0;
1786 }
1787 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1788 {
1789 set_offset_out_of_range_error (mismatch_detail, idx,
1790 min_value, max_value);
1791 return 0;
1792 }
1793 if (!value_aligned_p (opnd->addr.offset.imm, num))
1794 {
1795 set_unaligned_error (mismatch_detail, idx, num);
1796 return 0;
1797 }
1798 break;
1799
1800 case AARCH64_OPND_SVE_ADDR_RR:
1801 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1802 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1803 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1804 case AARCH64_OPND_SVE_ADDR_RX:
1805 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1806 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1807 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1808 case AARCH64_OPND_SVE_ADDR_RZ:
1809 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1810 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1811 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1812 modifiers = 1 << AARCH64_MOD_LSL;
1813 sve_rr_operand:
1814 assert (opnd->addr.offset.is_reg);
1815 assert (opnd->addr.preind);
1816 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1817 && opnd->addr.offset.regno == 31)
1818 {
1819 set_other_error (mismatch_detail, idx,
1820 _("index register xzr is not allowed"));
1821 return 0;
1822 }
1823 if (((1 << opnd->shifter.kind) & modifiers) == 0
1824 || (opnd->shifter.amount
1825 != get_operand_specific_data (&aarch64_operands[type])))
1826 {
1827 set_other_error (mismatch_detail, idx,
1828 _("invalid addressing mode"));
1829 return 0;
1830 }
1831 break;
1832
1833 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1834 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1835 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1836 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1837 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1838 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1839 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1840 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1841 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1842 goto sve_rr_operand;
1843
1844 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1845 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1846 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1847 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1848 min_value = 0;
1849 max_value = 31;
1850 goto sve_imm_offset;
1851
1852 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1853 modifiers = 1 << AARCH64_MOD_LSL;
1854 sve_zz_operand:
1855 assert (opnd->addr.offset.is_reg);
1856 assert (opnd->addr.preind);
1857 if (((1 << opnd->shifter.kind) & modifiers) == 0
1858 || opnd->shifter.amount < 0
1859 || opnd->shifter.amount > 3)
1860 {
1861 set_other_error (mismatch_detail, idx,
1862 _("invalid addressing mode"));
1863 return 0;
1864 }
1865 break;
1866
1867 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1868 modifiers = (1 << AARCH64_MOD_SXTW);
1869 goto sve_zz_operand;
1870
1871 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1872 modifiers = 1 << AARCH64_MOD_UXTW;
1873 goto sve_zz_operand;
1874
1875 default:
1876 break;
1877 }
1878 break;
1879
1880 case AARCH64_OPND_CLASS_SIMD_REGLIST:
1881 if (type == AARCH64_OPND_LEt)
1882 {
1883 /* Get the upper bound for the element index. */
1884 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
1885 if (!value_in_range_p (opnd->reglist.index, 0, num))
1886 {
1887 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
1888 return 0;
1889 }
1890 }
1891 /* The opcode dependent area stores the number of elements in
1892 each structure to be loaded/stored. */
1893 num = get_opcode_dependent_value (opcode);
1894 switch (type)
1895 {
1896 case AARCH64_OPND_LVt:
1897 assert (num >= 1 && num <= 4);
1898 /* Unless LD1/ST1, the number of registers should be equal to that
1899 of the structure elements. */
1900 if (num != 1 && opnd->reglist.num_regs != num)
1901 {
1902 set_reg_list_error (mismatch_detail, idx, num);
1903 return 0;
1904 }
1905 break;
1906 case AARCH64_OPND_LVt_AL:
1907 case AARCH64_OPND_LEt:
1908 assert (num >= 1 && num <= 4);
1909 /* The number of registers should be equal to that of the structure
1910 elements. */
1911 if (opnd->reglist.num_regs != num)
1912 {
1913 set_reg_list_error (mismatch_detail, idx, num);
1914 return 0;
1915 }
1916 break;
1917 default:
1918 break;
1919 }
1920 break;
1921
1922 case AARCH64_OPND_CLASS_IMMEDIATE:
1923 /* Constraint check on immediate operand. */
1924 imm = opnd->imm.value;
1925 /* E.g. imm_0_31 constrains value to be 0..31. */
1926 if (qualifier_value_in_range_constraint_p (qualifier)
1927 && !value_in_range_p (imm, get_lower_bound (qualifier),
1928 get_upper_bound (qualifier)))
1929 {
1930 set_imm_out_of_range_error (mismatch_detail, idx,
1931 get_lower_bound (qualifier),
1932 get_upper_bound (qualifier));
1933 return 0;
1934 }
1935
1936 switch (type)
1937 {
1938 case AARCH64_OPND_AIMM:
1939 if (opnd->shifter.kind != AARCH64_MOD_LSL)
1940 {
1941 set_other_error (mismatch_detail, idx,
1942 _("invalid shift operator"));
1943 return 0;
1944 }
1945 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
1946 {
1947 set_other_error (mismatch_detail, idx,
1948 _("shift amount must be 0 or 12"));
1949 return 0;
1950 }
1951 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
1952 {
1953 set_other_error (mismatch_detail, idx,
1954 _("immediate out of range"));
1955 return 0;
1956 }
1957 break;
1958
1959 case AARCH64_OPND_HALF:
1960 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
1961 if (opnd->shifter.kind != AARCH64_MOD_LSL)
1962 {
1963 set_other_error (mismatch_detail, idx,
1964 _("invalid shift operator"));
1965 return 0;
1966 }
1967 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
1968 if (!value_aligned_p (opnd->shifter.amount, 16))
1969 {
1970 set_other_error (mismatch_detail, idx,
1971 _("shift amount must be a multiple of 16"));
1972 return 0;
1973 }
1974 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
1975 {
1976 set_sft_amount_out_of_range_error (mismatch_detail, idx,
1977 0, size * 8 - 16);
1978 return 0;
1979 }
1980 if (opnd->imm.value < 0)
1981 {
1982 set_other_error (mismatch_detail, idx,
1983 _("negative immediate value not allowed"));
1984 return 0;
1985 }
1986 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
1987 {
1988 set_other_error (mismatch_detail, idx,
1989 _("immediate out of range"));
1990 return 0;
1991 }
1992 break;
1993
1994 case AARCH64_OPND_IMM_MOV:
1995 {
1996 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
1997 imm = opnd->imm.value;
1998 assert (idx == 1);
1999 switch (opcode->op)
2000 {
2001 case OP_MOV_IMM_WIDEN:
2002 imm = ~imm;
2003 /* Fall through. */
2004 case OP_MOV_IMM_WIDE:
2005 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
2006 {
2007 set_other_error (mismatch_detail, idx,
2008 _("immediate out of range"));
2009 return 0;
2010 }
2011 break;
2012 case OP_MOV_IMM_LOG:
2013 if (!aarch64_logical_immediate_p (imm, esize, NULL))
2014 {
2015 set_other_error (mismatch_detail, idx,
2016 _("immediate out of range"));
2017 return 0;
2018 }
2019 break;
2020 default:
2021 assert (0);
2022 return 0;
2023 }
2024 }
2025 break;
2026
2027 case AARCH64_OPND_NZCV:
2028 case AARCH64_OPND_CCMP_IMM:
2029 case AARCH64_OPND_EXCEPTION:
2030 case AARCH64_OPND_UIMM4:
2031 case AARCH64_OPND_UIMM7:
2032 case AARCH64_OPND_UIMM3_OP1:
2033 case AARCH64_OPND_UIMM3_OP2:
2034 case AARCH64_OPND_SVE_UIMM3:
2035 case AARCH64_OPND_SVE_UIMM7:
2036 case AARCH64_OPND_SVE_UIMM8:
2037 case AARCH64_OPND_SVE_UIMM8_53:
2038 size = get_operand_fields_width (get_operand_from_code (type));
2039 assert (size < 32);
2040 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2041 {
2042 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2043 (1 << size) - 1);
2044 return 0;
2045 }
2046 break;
2047
2048 case AARCH64_OPND_SIMM5:
2049 case AARCH64_OPND_SVE_SIMM5:
2050 case AARCH64_OPND_SVE_SIMM5B:
2051 case AARCH64_OPND_SVE_SIMM6:
2052 case AARCH64_OPND_SVE_SIMM8:
2053 size = get_operand_fields_width (get_operand_from_code (type));
2054 assert (size < 32);
2055 if (!value_fit_signed_field_p (opnd->imm.value, size))
2056 {
2057 set_imm_out_of_range_error (mismatch_detail, idx,
2058 -(1 << (size - 1)),
2059 (1 << (size - 1)) - 1);
2060 return 0;
2061 }
2062 break;
2063
2064 case AARCH64_OPND_WIDTH:
2065 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
2066 && opnds[0].type == AARCH64_OPND_Rd);
2067 size = get_upper_bound (qualifier);
2068 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2069 /* lsb+width <= reg.size */
2070 {
2071 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2072 size - opnds[idx-1].imm.value);
2073 return 0;
2074 }
2075 break;
2076
2077 case AARCH64_OPND_LIMM:
2078 case AARCH64_OPND_SVE_LIMM:
2079 {
2080 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2081 uint64_t uimm = opnd->imm.value;
2082 if (opcode->op == OP_BIC)
2083 uimm = ~uimm;
2084 if (aarch64_logical_immediate_p (uimm, esize, NULL) == FALSE)
2085 {
2086 set_other_error (mismatch_detail, idx,
2087 _("immediate out of range"));
2088 return 0;
2089 }
2090 }
2091 break;
2092
2093 case AARCH64_OPND_IMM0:
2094 case AARCH64_OPND_FPIMM0:
2095 if (opnd->imm.value != 0)
2096 {
2097 set_other_error (mismatch_detail, idx,
2098 _("immediate zero expected"));
2099 return 0;
2100 }
2101 break;
2102
2103 case AARCH64_OPND_IMM_ROT1:
2104 case AARCH64_OPND_IMM_ROT2:
2105 if (opnd->imm.value != 0
2106 && opnd->imm.value != 90
2107 && opnd->imm.value != 180
2108 && opnd->imm.value != 270)
2109 {
2110 set_other_error (mismatch_detail, idx,
2111 _("rotate expected to be 0, 90, 180 or 270"));
2112 return 0;
2113 }
2114 break;
2115
2116 case AARCH64_OPND_IMM_ROT3:
2117 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2118 {
2119 set_other_error (mismatch_detail, idx,
2120 _("rotate expected to be 90 or 270"));
2121 return 0;
2122 }
2123 break;
2124
2125 case AARCH64_OPND_SHLL_IMM:
2126 assert (idx == 2);
2127 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2128 if (opnd->imm.value != size)
2129 {
2130 set_other_error (mismatch_detail, idx,
2131 _("invalid shift amount"));
2132 return 0;
2133 }
2134 break;
2135
2136 case AARCH64_OPND_IMM_VLSL:
2137 size = aarch64_get_qualifier_esize (qualifier);
2138 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2139 {
2140 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2141 size * 8 - 1);
2142 return 0;
2143 }
2144 break;
2145
2146 case AARCH64_OPND_IMM_VLSR:
2147 size = aarch64_get_qualifier_esize (qualifier);
2148 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2149 {
2150 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2151 return 0;
2152 }
2153 break;
2154
2155 case AARCH64_OPND_SIMD_IMM:
2156 case AARCH64_OPND_SIMD_IMM_SFT:
2157 /* Qualifier check. */
2158 switch (qualifier)
2159 {
2160 case AARCH64_OPND_QLF_LSL:
2161 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2162 {
2163 set_other_error (mismatch_detail, idx,
2164 _("invalid shift operator"));
2165 return 0;
2166 }
2167 break;
2168 case AARCH64_OPND_QLF_MSL:
2169 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2170 {
2171 set_other_error (mismatch_detail, idx,
2172 _("invalid shift operator"));
2173 return 0;
2174 }
2175 break;
2176 case AARCH64_OPND_QLF_NIL:
2177 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2178 {
2179 set_other_error (mismatch_detail, idx,
2180 _("shift is not permitted"));
2181 return 0;
2182 }
2183 break;
2184 default:
2185 assert (0);
2186 return 0;
2187 }
2188 /* Is the immediate valid? */
2189 assert (idx == 1);
2190 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2191 {
2192 /* uimm8 or simm8 */
2193 if (!value_in_range_p (opnd->imm.value, -128, 255))
2194 {
2195 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
2196 return 0;
2197 }
2198 }
2199 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2200 {
2201 /* uimm64 is not
2202 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2203 ffffffffgggggggghhhhhhhh'. */
2204 set_other_error (mismatch_detail, idx,
2205 _("invalid value for immediate"));
2206 return 0;
2207 }
2208 /* Is the shift amount valid? */
2209 switch (opnd->shifter.kind)
2210 {
2211 case AARCH64_MOD_LSL:
2212 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2213 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
2214 {
2215 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2216 (size - 1) * 8);
2217 return 0;
2218 }
2219 if (!value_aligned_p (opnd->shifter.amount, 8))
2220 {
2221 set_unaligned_error (mismatch_detail, idx, 8);
2222 return 0;
2223 }
2224 break;
2225 case AARCH64_MOD_MSL:
2226 /* Only 8 and 16 are valid shift amount. */
2227 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2228 {
2229 set_other_error (mismatch_detail, idx,
2230 _("shift amount must be 0 or 16"));
2231 return 0;
2232 }
2233 break;
2234 default:
2235 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2236 {
2237 set_other_error (mismatch_detail, idx,
2238 _("invalid shift operator"));
2239 return 0;
2240 }
2241 break;
2242 }
2243 break;
2244
2245 case AARCH64_OPND_FPIMM:
2246 case AARCH64_OPND_SIMD_FPIMM:
2247 case AARCH64_OPND_SVE_FPIMM8:
2248 if (opnd->imm.is_fp == 0)
2249 {
2250 set_other_error (mismatch_detail, idx,
2251 _("floating-point immediate expected"));
2252 return 0;
2253 }
2254 /* The value is expected to be an 8-bit floating-point constant with
2255 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2256 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2257 instruction). */
2258 if (!value_in_range_p (opnd->imm.value, 0, 255))
2259 {
2260 set_other_error (mismatch_detail, idx,
2261 _("immediate out of range"));
2262 return 0;
2263 }
2264 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2265 {
2266 set_other_error (mismatch_detail, idx,
2267 _("invalid shift operator"));
2268 return 0;
2269 }
2270 break;
2271
2272 case AARCH64_OPND_SVE_AIMM:
2273 min_value = 0;
2274 sve_aimm:
2275 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2276 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2277 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2278 uvalue = opnd->imm.value;
2279 shift = opnd->shifter.amount;
2280 if (size == 1)
2281 {
2282 if (shift != 0)
2283 {
2284 set_other_error (mismatch_detail, idx,
2285 _("no shift amount allowed for"
2286 " 8-bit constants"));
2287 return 0;
2288 }
2289 }
2290 else
2291 {
2292 if (shift != 0 && shift != 8)
2293 {
2294 set_other_error (mismatch_detail, idx,
2295 _("shift amount must be 0 or 8"));
2296 return 0;
2297 }
2298 if (shift == 0 && (uvalue & 0xff) == 0)
2299 {
2300 shift = 8;
2301 uvalue = (int64_t) uvalue / 256;
2302 }
2303 }
2304 mask >>= shift;
2305 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2306 {
2307 set_other_error (mismatch_detail, idx,
2308 _("immediate too big for element size"));
2309 return 0;
2310 }
2311 uvalue = (uvalue - min_value) & mask;
2312 if (uvalue > 0xff)
2313 {
2314 set_other_error (mismatch_detail, idx,
2315 _("invalid arithmetic immediate"));
2316 return 0;
2317 }
2318 break;
2319
2320 case AARCH64_OPND_SVE_ASIMM:
2321 min_value = -128;
2322 goto sve_aimm;
2323
2324 case AARCH64_OPND_SVE_I1_HALF_ONE:
2325 assert (opnd->imm.is_fp);
2326 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2327 {
2328 set_other_error (mismatch_detail, idx,
2329 _("floating-point value must be 0.5 or 1.0"));
2330 return 0;
2331 }
2332 break;
2333
2334 case AARCH64_OPND_SVE_I1_HALF_TWO:
2335 assert (opnd->imm.is_fp);
2336 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2337 {
2338 set_other_error (mismatch_detail, idx,
2339 _("floating-point value must be 0.5 or 2.0"));
2340 return 0;
2341 }
2342 break;
2343
2344 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2345 assert (opnd->imm.is_fp);
2346 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2347 {
2348 set_other_error (mismatch_detail, idx,
2349 _("floating-point value must be 0.0 or 1.0"));
2350 return 0;
2351 }
2352 break;
2353
2354 case AARCH64_OPND_SVE_INV_LIMM:
2355 {
2356 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2357 uint64_t uimm = ~opnd->imm.value;
2358 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2359 {
2360 set_other_error (mismatch_detail, idx,
2361 _("immediate out of range"));
2362 return 0;
2363 }
2364 }
2365 break;
2366
2367 case AARCH64_OPND_SVE_LIMM_MOV:
2368 {
2369 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2370 uint64_t uimm = opnd->imm.value;
2371 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2372 {
2373 set_other_error (mismatch_detail, idx,
2374 _("immediate out of range"));
2375 return 0;
2376 }
2377 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2378 {
2379 set_other_error (mismatch_detail, idx,
2380 _("invalid replicated MOV immediate"));
2381 return 0;
2382 }
2383 }
2384 break;
2385
2386 case AARCH64_OPND_SVE_PATTERN_SCALED:
2387 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2388 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2389 {
2390 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2391 return 0;
2392 }
2393 break;
2394
2395 case AARCH64_OPND_SVE_SHLIMM_PRED:
2396 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
2397 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2398 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2399 {
2400 set_imm_out_of_range_error (mismatch_detail, idx,
2401 0, 8 * size - 1);
2402 return 0;
2403 }
2404 break;
2405
2406 case AARCH64_OPND_SVE_SHRIMM_PRED:
2407 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
2408 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2409 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2410 {
2411 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
2412 return 0;
2413 }
2414 break;
2415
2416 default:
2417 break;
2418 }
2419 break;
2420
2421 case AARCH64_OPND_CLASS_CP_REG:
2422 /* Cn or Cm: 4-bit opcode field named for historical reasons.
2423 valid range: C0 - C15. */
2424 if (opnd->reg.regno > 15)
2425 {
2426 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2427 return 0;
2428 }
2429 break;
2430
2431 case AARCH64_OPND_CLASS_SYSTEM:
2432 switch (type)
2433 {
2434 case AARCH64_OPND_PSTATEFIELD:
2435 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
2436 /* MSR UAO, #uimm4
2437 MSR PAN, #uimm4
2438 The immediate must be #0 or #1. */
2439 if ((opnd->pstatefield == 0x03 /* UAO. */
2440 || opnd->pstatefield == 0x04) /* PAN. */
2441 && opnds[1].imm.value > 1)
2442 {
2443 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2444 return 0;
2445 }
2446 /* MSR SPSel, #uimm4
2447 Uses uimm4 as a control value to select the stack pointer: if
2448 bit 0 is set it selects the current exception level's stack
2449 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2450 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2451 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2452 {
2453 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2454 return 0;
2455 }
2456 break;
2457 default:
2458 break;
2459 }
2460 break;
2461
2462 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2463 /* Get the upper bound for the element index. */
2464 if (opcode->op == OP_FCMLA_ELEM)
2465 /* FCMLA index range depends on the vector size of other operands
2466 and is halfed because complex numbers take two elements. */
2467 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2468 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2469 else
2470 num = 16;
2471 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
2472
2473 /* Index out-of-range. */
2474 if (!value_in_range_p (opnd->reglane.index, 0, num))
2475 {
2476 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2477 return 0;
2478 }
2479 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2480 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2481 number is encoded in "size:M:Rm":
2482 size <Vm>
2483 00 RESERVED
2484 01 0:Rm
2485 10 M:Rm
2486 11 RESERVED */
2487 if (type == AARCH64_OPND_Em && qualifier == AARCH64_OPND_QLF_S_H
2488 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2489 {
2490 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2491 return 0;
2492 }
2493 break;
2494
2495 case AARCH64_OPND_CLASS_MODIFIED_REG:
2496 assert (idx == 1 || idx == 2);
2497 switch (type)
2498 {
2499 case AARCH64_OPND_Rm_EXT:
2500 if (aarch64_extend_operator_p (opnd->shifter.kind) == FALSE
2501 && opnd->shifter.kind != AARCH64_MOD_LSL)
2502 {
2503 set_other_error (mismatch_detail, idx,
2504 _("extend operator expected"));
2505 return 0;
2506 }
2507 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2508 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2509 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2510 case. */
2511 if (!aarch64_stack_pointer_p (opnds + 0)
2512 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2513 {
2514 if (!opnd->shifter.operator_present)
2515 {
2516 set_other_error (mismatch_detail, idx,
2517 _("missing extend operator"));
2518 return 0;
2519 }
2520 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2521 {
2522 set_other_error (mismatch_detail, idx,
2523 _("'LSL' operator not allowed"));
2524 return 0;
2525 }
2526 }
2527 assert (opnd->shifter.operator_present /* Default to LSL. */
2528 || opnd->shifter.kind == AARCH64_MOD_LSL);
2529 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2530 {
2531 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2532 return 0;
2533 }
2534 /* In the 64-bit form, the final register operand is written as Wm
2535 for all but the (possibly omitted) UXTX/LSL and SXTX
2536 operators.
2537 N.B. GAS allows X register to be used with any operator as a
2538 programming convenience. */
2539 if (qualifier == AARCH64_OPND_QLF_X
2540 && opnd->shifter.kind != AARCH64_MOD_LSL
2541 && opnd->shifter.kind != AARCH64_MOD_UXTX
2542 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2543 {
2544 set_other_error (mismatch_detail, idx, _("W register expected"));
2545 return 0;
2546 }
2547 break;
2548
2549 case AARCH64_OPND_Rm_SFT:
2550 /* ROR is not available to the shifted register operand in
2551 arithmetic instructions. */
2552 if (aarch64_shift_operator_p (opnd->shifter.kind) == FALSE)
2553 {
2554 set_other_error (mismatch_detail, idx,
2555 _("shift operator expected"));
2556 return 0;
2557 }
2558 if (opnd->shifter.kind == AARCH64_MOD_ROR
2559 && opcode->iclass != log_shift)
2560 {
2561 set_other_error (mismatch_detail, idx,
2562 _("'ROR' operator not allowed"));
2563 return 0;
2564 }
2565 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2566 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2567 {
2568 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2569 return 0;
2570 }
2571 break;
2572
2573 default:
2574 break;
2575 }
2576 break;
2577
2578 default:
2579 break;
2580 }
2581
2582 return 1;
2583 }
2584
2585 /* Main entrypoint for the operand constraint checking.
2586
2587 Return 1 if operands of *INST meet the constraint applied by the operand
2588 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2589 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2590 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2591 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2592 error kind when it is notified that an instruction does not pass the check).
2593
2594 Un-determined operand qualifiers may get established during the process. */
2595
2596 int
2597 aarch64_match_operands_constraint (aarch64_inst *inst,
2598 aarch64_operand_error *mismatch_detail)
2599 {
2600 int i;
2601
2602 DEBUG_TRACE ("enter");
2603
2604 /* Check for cases where a source register needs to be the same as the
2605 destination register. Do this before matching qualifiers since if
2606 an instruction has both invalid tying and invalid qualifiers,
2607 the error about qualifiers would suggest several alternative
2608 instructions that also have invalid tying. */
2609 i = inst->opcode->tied_operand;
2610 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2611 {
2612 if (mismatch_detail)
2613 {
2614 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2615 mismatch_detail->index = i;
2616 mismatch_detail->error = NULL;
2617 }
2618 return 0;
2619 }
2620
2621 /* Match operands' qualifier.
2622 *INST has already had qualifier establish for some, if not all, of
2623 its operands; we need to find out whether these established
2624 qualifiers match one of the qualifier sequence in
2625 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2626 with the corresponding qualifier in such a sequence.
2627 Only basic operand constraint checking is done here; the more thorough
2628 constraint checking will carried out by operand_general_constraint_met_p,
2629 which has be to called after this in order to get all of the operands'
2630 qualifiers established. */
2631 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2632 {
2633 DEBUG_TRACE ("FAIL on operand qualifier matching");
2634 if (mismatch_detail)
2635 {
2636 /* Return an error type to indicate that it is the qualifier
2637 matching failure; we don't care about which operand as there
2638 are enough information in the opcode table to reproduce it. */
2639 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2640 mismatch_detail->index = -1;
2641 mismatch_detail->error = NULL;
2642 }
2643 return 0;
2644 }
2645
2646 /* Match operands' constraint. */
2647 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2648 {
2649 enum aarch64_opnd type = inst->opcode->operands[i];
2650 if (type == AARCH64_OPND_NIL)
2651 break;
2652 if (inst->operands[i].skip)
2653 {
2654 DEBUG_TRACE ("skip the incomplete operand %d", i);
2655 continue;
2656 }
2657 if (operand_general_constraint_met_p (inst->operands, i, type,
2658 inst->opcode, mismatch_detail) == 0)
2659 {
2660 DEBUG_TRACE ("FAIL on operand %d", i);
2661 return 0;
2662 }
2663 }
2664
2665 DEBUG_TRACE ("PASS");
2666
2667 return 1;
2668 }
2669
2670 /* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2671 Also updates the TYPE of each INST->OPERANDS with the corresponding
2672 value of OPCODE->OPERANDS.
2673
2674 Note that some operand qualifiers may need to be manually cleared by
2675 the caller before it further calls the aarch64_opcode_encode; by
2676 doing this, it helps the qualifier matching facilities work
2677 properly. */
2678
2679 const aarch64_opcode*
2680 aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2681 {
2682 int i;
2683 const aarch64_opcode *old = inst->opcode;
2684
2685 inst->opcode = opcode;
2686
2687 /* Update the operand types. */
2688 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2689 {
2690 inst->operands[i].type = opcode->operands[i];
2691 if (opcode->operands[i] == AARCH64_OPND_NIL)
2692 break;
2693 }
2694
2695 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2696
2697 return old;
2698 }
2699
2700 int
2701 aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2702 {
2703 int i;
2704 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2705 if (operands[i] == operand)
2706 return i;
2707 else if (operands[i] == AARCH64_OPND_NIL)
2708 break;
2709 return -1;
2710 }
2711 \f
2712 /* R0...R30, followed by FOR31. */
2713 #define BANK(R, FOR31) \
2714 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2715 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2716 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2717 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
2718 /* [0][0] 32-bit integer regs with sp Wn
2719 [0][1] 64-bit integer regs with sp Xn sf=1
2720 [1][0] 32-bit integer regs with #0 Wn
2721 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2722 static const char *int_reg[2][2][32] = {
2723 #define R32(X) "w" #X
2724 #define R64(X) "x" #X
2725 { BANK (R32, "wsp"), BANK (R64, "sp") },
2726 { BANK (R32, "wzr"), BANK (R64, "xzr") }
2727 #undef R64
2728 #undef R32
2729 };
2730
2731 /* Names of the SVE vector registers, first with .S suffixes,
2732 then with .D suffixes. */
2733
2734 static const char *sve_reg[2][32] = {
2735 #define ZS(X) "z" #X ".s"
2736 #define ZD(X) "z" #X ".d"
2737 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2738 #undef ZD
2739 #undef ZS
2740 };
2741 #undef BANK
2742
2743 /* Return the integer register name.
2744 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2745
2746 static inline const char *
2747 get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2748 {
2749 const int has_zr = sp_reg_p ? 0 : 1;
2750 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2751 return int_reg[has_zr][is_64][regno];
2752 }
2753
2754 /* Like get_int_reg_name, but IS_64 is always 1. */
2755
2756 static inline const char *
2757 get_64bit_int_reg_name (int regno, int sp_reg_p)
2758 {
2759 const int has_zr = sp_reg_p ? 0 : 1;
2760 return int_reg[has_zr][1][regno];
2761 }
2762
2763 /* Get the name of the integer offset register in OPND, using the shift type
2764 to decide whether it's a word or doubleword. */
2765
2766 static inline const char *
2767 get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2768 {
2769 switch (opnd->shifter.kind)
2770 {
2771 case AARCH64_MOD_UXTW:
2772 case AARCH64_MOD_SXTW:
2773 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2774
2775 case AARCH64_MOD_LSL:
2776 case AARCH64_MOD_SXTX:
2777 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2778
2779 default:
2780 abort ();
2781 }
2782 }
2783
2784 /* Get the name of the SVE vector offset register in OPND, using the operand
2785 qualifier to decide whether the suffix should be .S or .D. */
2786
2787 static inline const char *
2788 get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2789 {
2790 assert (qualifier == AARCH64_OPND_QLF_S_S
2791 || qualifier == AARCH64_OPND_QLF_S_D);
2792 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2793 }
2794
2795 /* Types for expanding an encoded 8-bit value to a floating-point value. */
2796
2797 typedef union
2798 {
2799 uint64_t i;
2800 double d;
2801 } double_conv_t;
2802
2803 typedef union
2804 {
2805 uint32_t i;
2806 float f;
2807 } single_conv_t;
2808
2809 typedef union
2810 {
2811 uint32_t i;
2812 float f;
2813 } half_conv_t;
2814
2815 /* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2816 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2817 (depending on the type of the instruction). IMM8 will be expanded to a
2818 single-precision floating-point value (SIZE == 4) or a double-precision
2819 floating-point value (SIZE == 8). A half-precision floating-point value
2820 (SIZE == 2) is expanded to a single-precision floating-point value. The
2821 expanded value is returned. */
2822
2823 static uint64_t
2824 expand_fp_imm (int size, uint32_t imm8)
2825 {
2826 uint64_t imm;
2827 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2828
2829 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2830 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2831 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2832 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2833 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
2834 if (size == 8)
2835 {
2836 imm = (imm8_7 << (63-32)) /* imm8<7> */
2837 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2838 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2839 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2840 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2841 imm <<= 32;
2842 }
2843 else if (size == 4 || size == 2)
2844 {
2845 imm = (imm8_7 << 31) /* imm8<7> */
2846 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2847 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2848 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2849 }
2850 else
2851 {
2852 /* An unsupported size. */
2853 assert (0);
2854 }
2855
2856 return imm;
2857 }
2858
2859 /* Produce the string representation of the register list operand *OPND
2860 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2861 the register name that comes before the register number, such as "v". */
2862 static void
2863 print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
2864 const char *prefix)
2865 {
2866 const int num_regs = opnd->reglist.num_regs;
2867 const int first_reg = opnd->reglist.first_regno;
2868 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
2869 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
2870 char tb[8]; /* Temporary buffer. */
2871
2872 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
2873 assert (num_regs >= 1 && num_regs <= 4);
2874
2875 /* Prepare the index if any. */
2876 if (opnd->reglist.has_index)
2877 snprintf (tb, 8, "[%" PRIi64 "]", opnd->reglist.index);
2878 else
2879 tb[0] = '\0';
2880
2881 /* The hyphenated form is preferred for disassembly if there are
2882 more than two registers in the list, and the register numbers
2883 are monotonically increasing in increments of one. */
2884 if (num_regs > 2 && last_reg > first_reg)
2885 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
2886 prefix, last_reg, qlf_name, tb);
2887 else
2888 {
2889 const int reg0 = first_reg;
2890 const int reg1 = (first_reg + 1) & 0x1f;
2891 const int reg2 = (first_reg + 2) & 0x1f;
2892 const int reg3 = (first_reg + 3) & 0x1f;
2893
2894 switch (num_regs)
2895 {
2896 case 1:
2897 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
2898 break;
2899 case 2:
2900 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
2901 prefix, reg1, qlf_name, tb);
2902 break;
2903 case 3:
2904 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
2905 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
2906 prefix, reg2, qlf_name, tb);
2907 break;
2908 case 4:
2909 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
2910 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
2911 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
2912 break;
2913 }
2914 }
2915 }
2916
2917 /* Print the register+immediate address in OPND to BUF, which has SIZE
2918 characters. BASE is the name of the base register. */
2919
2920 static void
2921 print_immediate_offset_address (char *buf, size_t size,
2922 const aarch64_opnd_info *opnd,
2923 const char *base)
2924 {
2925 if (opnd->addr.writeback)
2926 {
2927 if (opnd->addr.preind)
2928 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
2929 else
2930 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
2931 }
2932 else
2933 {
2934 if (opnd->shifter.operator_present)
2935 {
2936 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
2937 snprintf (buf, size, "[%s, #%d, mul vl]",
2938 base, opnd->addr.offset.imm);
2939 }
2940 else if (opnd->addr.offset.imm)
2941 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
2942 else
2943 snprintf (buf, size, "[%s]", base);
2944 }
2945 }
2946
2947 /* Produce the string representation of the register offset address operand
2948 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
2949 the names of the base and offset registers. */
2950 static void
2951 print_register_offset_address (char *buf, size_t size,
2952 const aarch64_opnd_info *opnd,
2953 const char *base, const char *offset)
2954 {
2955 char tb[16]; /* Temporary buffer. */
2956 bfd_boolean print_extend_p = TRUE;
2957 bfd_boolean print_amount_p = TRUE;
2958 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
2959
2960 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
2961 || !opnd->shifter.amount_present))
2962 {
2963 /* Not print the shift/extend amount when the amount is zero and
2964 when it is not the special case of 8-bit load/store instruction. */
2965 print_amount_p = FALSE;
2966 /* Likewise, no need to print the shift operator LSL in such a
2967 situation. */
2968 if (opnd->shifter.kind == AARCH64_MOD_LSL)
2969 print_extend_p = FALSE;
2970 }
2971
2972 /* Prepare for the extend/shift. */
2973 if (print_extend_p)
2974 {
2975 if (print_amount_p)
2976 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
2977 opnd->shifter.amount);
2978 else
2979 snprintf (tb, sizeof (tb), ", %s", shift_name);
2980 }
2981 else
2982 tb[0] = '\0';
2983
2984 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
2985 }
2986
2987 /* Generate the string representation of the operand OPNDS[IDX] for OPCODE
2988 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
2989 PC, PCREL_P and ADDRESS are used to pass in and return information about
2990 the PC-relative address calculation, where the PC value is passed in
2991 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
2992 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
2993 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
2994
2995 The function serves both the disassembler and the assembler diagnostics
2996 issuer, which is the reason why it lives in this file. */
2997
2998 void
2999 aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3000 const aarch64_opcode *opcode,
3001 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
3002 bfd_vma *address)
3003 {
3004 unsigned int i, num_conds;
3005 const char *name = NULL;
3006 const aarch64_opnd_info *opnd = opnds + idx;
3007 enum aarch64_modifier_kind kind;
3008 uint64_t addr, enum_value;
3009
3010 buf[0] = '\0';
3011 if (pcrel_p)
3012 *pcrel_p = 0;
3013
3014 switch (opnd->type)
3015 {
3016 case AARCH64_OPND_Rd:
3017 case AARCH64_OPND_Rn:
3018 case AARCH64_OPND_Rm:
3019 case AARCH64_OPND_Rt:
3020 case AARCH64_OPND_Rt2:
3021 case AARCH64_OPND_Rs:
3022 case AARCH64_OPND_Ra:
3023 case AARCH64_OPND_Rt_SYS:
3024 case AARCH64_OPND_PAIRREG:
3025 case AARCH64_OPND_SVE_Rm:
3026 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
3027 the <ic_op>, therefore we we use opnd->present to override the
3028 generic optional-ness information. */
3029 if (opnd->type == AARCH64_OPND_Rt_SYS)
3030 {
3031 if (!opnd->present)
3032 break;
3033 }
3034 /* Omit the operand, e.g. RET. */
3035 else if (optional_operand_p (opcode, idx)
3036 && (opnd->reg.regno
3037 == get_optional_operand_default_value (opcode)))
3038 break;
3039 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3040 || opnd->qualifier == AARCH64_OPND_QLF_X);
3041 snprintf (buf, size, "%s",
3042 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3043 break;
3044
3045 case AARCH64_OPND_Rd_SP:
3046 case AARCH64_OPND_Rn_SP:
3047 case AARCH64_OPND_SVE_Rn_SP:
3048 case AARCH64_OPND_Rm_SP:
3049 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3050 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3051 || opnd->qualifier == AARCH64_OPND_QLF_X
3052 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3053 snprintf (buf, size, "%s",
3054 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3055 break;
3056
3057 case AARCH64_OPND_Rm_EXT:
3058 kind = opnd->shifter.kind;
3059 assert (idx == 1 || idx == 2);
3060 if ((aarch64_stack_pointer_p (opnds)
3061 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3062 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3063 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3064 && kind == AARCH64_MOD_UXTW)
3065 || (opnd->qualifier == AARCH64_OPND_QLF_X
3066 && kind == AARCH64_MOD_UXTX)))
3067 {
3068 /* 'LSL' is the preferred form in this case. */
3069 kind = AARCH64_MOD_LSL;
3070 if (opnd->shifter.amount == 0)
3071 {
3072 /* Shifter omitted. */
3073 snprintf (buf, size, "%s",
3074 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3075 break;
3076 }
3077 }
3078 if (opnd->shifter.amount)
3079 snprintf (buf, size, "%s, %s #%" PRIi64,
3080 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3081 aarch64_operand_modifiers[kind].name,
3082 opnd->shifter.amount);
3083 else
3084 snprintf (buf, size, "%s, %s",
3085 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3086 aarch64_operand_modifiers[kind].name);
3087 break;
3088
3089 case AARCH64_OPND_Rm_SFT:
3090 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3091 || opnd->qualifier == AARCH64_OPND_QLF_X);
3092 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3093 snprintf (buf, size, "%s",
3094 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3095 else
3096 snprintf (buf, size, "%s, %s #%" PRIi64,
3097 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3098 aarch64_operand_modifiers[opnd->shifter.kind].name,
3099 opnd->shifter.amount);
3100 break;
3101
3102 case AARCH64_OPND_Fd:
3103 case AARCH64_OPND_Fn:
3104 case AARCH64_OPND_Fm:
3105 case AARCH64_OPND_Fa:
3106 case AARCH64_OPND_Ft:
3107 case AARCH64_OPND_Ft2:
3108 case AARCH64_OPND_Sd:
3109 case AARCH64_OPND_Sn:
3110 case AARCH64_OPND_Sm:
3111 case AARCH64_OPND_SVE_VZn:
3112 case AARCH64_OPND_SVE_Vd:
3113 case AARCH64_OPND_SVE_Vm:
3114 case AARCH64_OPND_SVE_Vn:
3115 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3116 opnd->reg.regno);
3117 break;
3118
3119 case AARCH64_OPND_Vd:
3120 case AARCH64_OPND_Vn:
3121 case AARCH64_OPND_Vm:
3122 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3123 aarch64_get_qualifier_name (opnd->qualifier));
3124 break;
3125
3126 case AARCH64_OPND_Ed:
3127 case AARCH64_OPND_En:
3128 case AARCH64_OPND_Em:
3129 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3130 aarch64_get_qualifier_name (opnd->qualifier),
3131 opnd->reglane.index);
3132 break;
3133
3134 case AARCH64_OPND_VdD1:
3135 case AARCH64_OPND_VnD1:
3136 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3137 break;
3138
3139 case AARCH64_OPND_LVn:
3140 case AARCH64_OPND_LVt:
3141 case AARCH64_OPND_LVt_AL:
3142 case AARCH64_OPND_LEt:
3143 print_register_list (buf, size, opnd, "v");
3144 break;
3145
3146 case AARCH64_OPND_SVE_Pd:
3147 case AARCH64_OPND_SVE_Pg3:
3148 case AARCH64_OPND_SVE_Pg4_5:
3149 case AARCH64_OPND_SVE_Pg4_10:
3150 case AARCH64_OPND_SVE_Pg4_16:
3151 case AARCH64_OPND_SVE_Pm:
3152 case AARCH64_OPND_SVE_Pn:
3153 case AARCH64_OPND_SVE_Pt:
3154 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3155 snprintf (buf, size, "p%d", opnd->reg.regno);
3156 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3157 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3158 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3159 aarch64_get_qualifier_name (opnd->qualifier));
3160 else
3161 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3162 aarch64_get_qualifier_name (opnd->qualifier));
3163 break;
3164
3165 case AARCH64_OPND_SVE_Za_5:
3166 case AARCH64_OPND_SVE_Za_16:
3167 case AARCH64_OPND_SVE_Zd:
3168 case AARCH64_OPND_SVE_Zm_5:
3169 case AARCH64_OPND_SVE_Zm_16:
3170 case AARCH64_OPND_SVE_Zn:
3171 case AARCH64_OPND_SVE_Zt:
3172 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3173 snprintf (buf, size, "z%d", opnd->reg.regno);
3174 else
3175 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3176 aarch64_get_qualifier_name (opnd->qualifier));
3177 break;
3178
3179 case AARCH64_OPND_SVE_ZnxN:
3180 case AARCH64_OPND_SVE_ZtxN:
3181 print_register_list (buf, size, opnd, "z");
3182 break;
3183
3184 case AARCH64_OPND_SVE_Zn_INDEX:
3185 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3186 aarch64_get_qualifier_name (opnd->qualifier),
3187 opnd->reglane.index);
3188 break;
3189
3190 case AARCH64_OPND_Cn:
3191 case AARCH64_OPND_Cm:
3192 snprintf (buf, size, "C%d", opnd->reg.regno);
3193 break;
3194
3195 case AARCH64_OPND_IDX:
3196 case AARCH64_OPND_IMM:
3197 case AARCH64_OPND_WIDTH:
3198 case AARCH64_OPND_UIMM3_OP1:
3199 case AARCH64_OPND_UIMM3_OP2:
3200 case AARCH64_OPND_BIT_NUM:
3201 case AARCH64_OPND_IMM_VLSL:
3202 case AARCH64_OPND_IMM_VLSR:
3203 case AARCH64_OPND_SHLL_IMM:
3204 case AARCH64_OPND_IMM0:
3205 case AARCH64_OPND_IMMR:
3206 case AARCH64_OPND_IMMS:
3207 case AARCH64_OPND_FBITS:
3208 case AARCH64_OPND_SIMM5:
3209 case AARCH64_OPND_SVE_SHLIMM_PRED:
3210 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
3211 case AARCH64_OPND_SVE_SHRIMM_PRED:
3212 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3213 case AARCH64_OPND_SVE_SIMM5:
3214 case AARCH64_OPND_SVE_SIMM5B:
3215 case AARCH64_OPND_SVE_SIMM6:
3216 case AARCH64_OPND_SVE_SIMM8:
3217 case AARCH64_OPND_SVE_UIMM3:
3218 case AARCH64_OPND_SVE_UIMM7:
3219 case AARCH64_OPND_SVE_UIMM8:
3220 case AARCH64_OPND_SVE_UIMM8_53:
3221 case AARCH64_OPND_IMM_ROT1:
3222 case AARCH64_OPND_IMM_ROT2:
3223 case AARCH64_OPND_IMM_ROT3:
3224 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3225 break;
3226
3227 case AARCH64_OPND_SVE_I1_HALF_ONE:
3228 case AARCH64_OPND_SVE_I1_HALF_TWO:
3229 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3230 {
3231 single_conv_t c;
3232 c.i = opnd->imm.value;
3233 snprintf (buf, size, "#%.1f", c.f);
3234 break;
3235 }
3236
3237 case AARCH64_OPND_SVE_PATTERN:
3238 if (optional_operand_p (opcode, idx)
3239 && opnd->imm.value == get_optional_operand_default_value (opcode))
3240 break;
3241 enum_value = opnd->imm.value;
3242 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3243 if (aarch64_sve_pattern_array[enum_value])
3244 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3245 else
3246 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3247 break;
3248
3249 case AARCH64_OPND_SVE_PATTERN_SCALED:
3250 if (optional_operand_p (opcode, idx)
3251 && !opnd->shifter.operator_present
3252 && opnd->imm.value == get_optional_operand_default_value (opcode))
3253 break;
3254 enum_value = opnd->imm.value;
3255 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3256 if (aarch64_sve_pattern_array[opnd->imm.value])
3257 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3258 else
3259 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3260 if (opnd->shifter.operator_present)
3261 {
3262 size_t len = strlen (buf);
3263 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3264 aarch64_operand_modifiers[opnd->shifter.kind].name,
3265 opnd->shifter.amount);
3266 }
3267 break;
3268
3269 case AARCH64_OPND_SVE_PRFOP:
3270 enum_value = opnd->imm.value;
3271 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3272 if (aarch64_sve_prfop_array[enum_value])
3273 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3274 else
3275 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3276 break;
3277
3278 case AARCH64_OPND_IMM_MOV:
3279 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3280 {
3281 case 4: /* e.g. MOV Wd, #<imm32>. */
3282 {
3283 int imm32 = opnd->imm.value;
3284 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3285 }
3286 break;
3287 case 8: /* e.g. MOV Xd, #<imm64>. */
3288 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3289 opnd->imm.value, opnd->imm.value);
3290 break;
3291 default: assert (0);
3292 }
3293 break;
3294
3295 case AARCH64_OPND_FPIMM0:
3296 snprintf (buf, size, "#0.0");
3297 break;
3298
3299 case AARCH64_OPND_LIMM:
3300 case AARCH64_OPND_AIMM:
3301 case AARCH64_OPND_HALF:
3302 case AARCH64_OPND_SVE_INV_LIMM:
3303 case AARCH64_OPND_SVE_LIMM:
3304 case AARCH64_OPND_SVE_LIMM_MOV:
3305 if (opnd->shifter.amount)
3306 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
3307 opnd->shifter.amount);
3308 else
3309 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3310 break;
3311
3312 case AARCH64_OPND_SIMD_IMM:
3313 case AARCH64_OPND_SIMD_IMM_SFT:
3314 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3315 || opnd->shifter.kind == AARCH64_MOD_NONE)
3316 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3317 else
3318 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
3319 aarch64_operand_modifiers[opnd->shifter.kind].name,
3320 opnd->shifter.amount);
3321 break;
3322
3323 case AARCH64_OPND_SVE_AIMM:
3324 case AARCH64_OPND_SVE_ASIMM:
3325 if (opnd->shifter.amount)
3326 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3327 opnd->shifter.amount);
3328 else
3329 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3330 break;
3331
3332 case AARCH64_OPND_FPIMM:
3333 case AARCH64_OPND_SIMD_FPIMM:
3334 case AARCH64_OPND_SVE_FPIMM8:
3335 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3336 {
3337 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3338 {
3339 half_conv_t c;
3340 c.i = expand_fp_imm (2, opnd->imm.value);
3341 snprintf (buf, size, "#%.18e", c.f);
3342 }
3343 break;
3344 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3345 {
3346 single_conv_t c;
3347 c.i = expand_fp_imm (4, opnd->imm.value);
3348 snprintf (buf, size, "#%.18e", c.f);
3349 }
3350 break;
3351 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3352 {
3353 double_conv_t c;
3354 c.i = expand_fp_imm (8, opnd->imm.value);
3355 snprintf (buf, size, "#%.18e", c.d);
3356 }
3357 break;
3358 default: assert (0);
3359 }
3360 break;
3361
3362 case AARCH64_OPND_CCMP_IMM:
3363 case AARCH64_OPND_NZCV:
3364 case AARCH64_OPND_EXCEPTION:
3365 case AARCH64_OPND_UIMM4:
3366 case AARCH64_OPND_UIMM7:
3367 if (optional_operand_p (opcode, idx) == TRUE
3368 && (opnd->imm.value ==
3369 (int64_t) get_optional_operand_default_value (opcode)))
3370 /* Omit the operand, e.g. DCPS1. */
3371 break;
3372 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3373 break;
3374
3375 case AARCH64_OPND_COND:
3376 case AARCH64_OPND_COND1:
3377 snprintf (buf, size, "%s", opnd->cond->names[0]);
3378 num_conds = ARRAY_SIZE (opnd->cond->names);
3379 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3380 {
3381 size_t len = strlen (buf);
3382 if (i == 1)
3383 snprintf (buf + len, size - len, " // %s = %s",
3384 opnd->cond->names[0], opnd->cond->names[i]);
3385 else
3386 snprintf (buf + len, size - len, ", %s",
3387 opnd->cond->names[i]);
3388 }
3389 break;
3390
3391 case AARCH64_OPND_ADDR_ADRP:
3392 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3393 + opnd->imm.value;
3394 if (pcrel_p)
3395 *pcrel_p = 1;
3396 if (address)
3397 *address = addr;
3398 /* This is not necessary during the disassembling, as print_address_func
3399 in the disassemble_info will take care of the printing. But some
3400 other callers may be still interested in getting the string in *STR,
3401 so here we do snprintf regardless. */
3402 snprintf (buf, size, "#0x%" PRIx64, addr);
3403 break;
3404
3405 case AARCH64_OPND_ADDR_PCREL14:
3406 case AARCH64_OPND_ADDR_PCREL19:
3407 case AARCH64_OPND_ADDR_PCREL21:
3408 case AARCH64_OPND_ADDR_PCREL26:
3409 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3410 if (pcrel_p)
3411 *pcrel_p = 1;
3412 if (address)
3413 *address = addr;
3414 /* This is not necessary during the disassembling, as print_address_func
3415 in the disassemble_info will take care of the printing. But some
3416 other callers may be still interested in getting the string in *STR,
3417 so here we do snprintf regardless. */
3418 snprintf (buf, size, "#0x%" PRIx64, addr);
3419 break;
3420
3421 case AARCH64_OPND_ADDR_SIMPLE:
3422 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3423 case AARCH64_OPND_SIMD_ADDR_POST:
3424 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3425 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3426 {
3427 if (opnd->addr.offset.is_reg)
3428 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3429 else
3430 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3431 }
3432 else
3433 snprintf (buf, size, "[%s]", name);
3434 break;
3435
3436 case AARCH64_OPND_ADDR_REGOFF:
3437 case AARCH64_OPND_SVE_ADDR_RR:
3438 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3439 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3440 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3441 case AARCH64_OPND_SVE_ADDR_RX:
3442 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3443 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3444 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
3445 print_register_offset_address
3446 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3447 get_offset_int_reg_name (opnd));
3448 break;
3449
3450 case AARCH64_OPND_SVE_ADDR_RZ:
3451 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3452 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3453 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3454 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3455 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3456 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3457 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3458 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3459 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3460 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3461 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3462 print_register_offset_address
3463 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3464 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3465 break;
3466
3467 case AARCH64_OPND_ADDR_SIMM7:
3468 case AARCH64_OPND_ADDR_SIMM9:
3469 case AARCH64_OPND_ADDR_SIMM9_2:
3470 case AARCH64_OPND_ADDR_SIMM10:
3471 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3472 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3473 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3474 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3475 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3476 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
3477 case AARCH64_OPND_SVE_ADDR_RI_U6:
3478 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3479 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3480 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
3481 print_immediate_offset_address
3482 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
3483 break;
3484
3485 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3486 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3487 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3488 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3489 print_immediate_offset_address
3490 (buf, size, opnd,
3491 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3492 break;
3493
3494 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3495 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3496 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3497 print_register_offset_address
3498 (buf, size, opnd,
3499 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3500 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3501 break;
3502
3503 case AARCH64_OPND_ADDR_UIMM12:
3504 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3505 if (opnd->addr.offset.imm)
3506 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
3507 else
3508 snprintf (buf, size, "[%s]", name);
3509 break;
3510
3511 case AARCH64_OPND_SYSREG:
3512 for (i = 0; aarch64_sys_regs[i].name; ++i)
3513 if (aarch64_sys_regs[i].value == opnd->sysreg
3514 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i]))
3515 break;
3516 if (aarch64_sys_regs[i].name)
3517 snprintf (buf, size, "%s", aarch64_sys_regs[i].name);
3518 else
3519 {
3520 /* Implementation defined system register. */
3521 unsigned int value = opnd->sysreg;
3522 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3523 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3524 value & 0x7);
3525 }
3526 break;
3527
3528 case AARCH64_OPND_PSTATEFIELD:
3529 for (i = 0; aarch64_pstatefields[i].name; ++i)
3530 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3531 break;
3532 assert (aarch64_pstatefields[i].name);
3533 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3534 break;
3535
3536 case AARCH64_OPND_SYSREG_AT:
3537 case AARCH64_OPND_SYSREG_DC:
3538 case AARCH64_OPND_SYSREG_IC:
3539 case AARCH64_OPND_SYSREG_TLBI:
3540 snprintf (buf, size, "%s", opnd->sysins_op->name);
3541 break;
3542
3543 case AARCH64_OPND_BARRIER:
3544 snprintf (buf, size, "%s", opnd->barrier->name);
3545 break;
3546
3547 case AARCH64_OPND_BARRIER_ISB:
3548 /* Operand can be omitted, e.g. in DCPS1. */
3549 if (! optional_operand_p (opcode, idx)
3550 || (opnd->barrier->value
3551 != get_optional_operand_default_value (opcode)))
3552 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3553 break;
3554
3555 case AARCH64_OPND_PRFOP:
3556 if (opnd->prfop->name != NULL)
3557 snprintf (buf, size, "%s", opnd->prfop->name);
3558 else
3559 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
3560 break;
3561
3562 case AARCH64_OPND_BARRIER_PSB:
3563 snprintf (buf, size, "%s", opnd->hint_option->name);
3564 break;
3565
3566 default:
3567 assert (0);
3568 }
3569 }
3570 \f
3571 #define CPENC(op0,op1,crn,crm,op2) \
3572 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3573 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3574 #define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3575 /* for 3.9.10 System Instructions */
3576 #define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3577
3578 #define C0 0
3579 #define C1 1
3580 #define C2 2
3581 #define C3 3
3582 #define C4 4
3583 #define C5 5
3584 #define C6 6
3585 #define C7 7
3586 #define C8 8
3587 #define C9 9
3588 #define C10 10
3589 #define C11 11
3590 #define C12 12
3591 #define C13 13
3592 #define C14 14
3593 #define C15 15
3594
3595 #ifdef F_DEPRECATED
3596 #undef F_DEPRECATED
3597 #endif
3598 #define F_DEPRECATED 0x1 /* Deprecated system register. */
3599
3600 #ifdef F_ARCHEXT
3601 #undef F_ARCHEXT
3602 #endif
3603 #define F_ARCHEXT 0x2 /* Architecture dependent system register. */
3604
3605 #ifdef F_HASXT
3606 #undef F_HASXT
3607 #endif
3608 #define F_HASXT 0x4 /* System instruction register <Xt>
3609 operand. */
3610
3611
3612 /* TODO there are two more issues need to be resolved
3613 1. handle read-only and write-only system registers
3614 2. handle cpu-implementation-defined system registers. */
3615 const aarch64_sys_reg aarch64_sys_regs [] =
3616 {
3617 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
3618 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
3619 { "elr_el1", CPEN_(0,C0,1), 0 },
3620 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
3621 { "sp_el0", CPEN_(0,C1,0), 0 },
3622 { "spsel", CPEN_(0,C2,0), 0 },
3623 { "daif", CPEN_(3,C2,1), 0 },
3624 { "currentel", CPEN_(0,C2,2), 0 }, /* RO */
3625 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
3626 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
3627 { "nzcv", CPEN_(3,C2,0), 0 },
3628 { "fpcr", CPEN_(3,C4,0), 0 },
3629 { "fpsr", CPEN_(3,C4,1), 0 },
3630 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3631 { "dlr_el0", CPEN_(3,C5,1), 0 },
3632 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3633 { "elr_el2", CPEN_(4,C0,1), 0 },
3634 { "sp_el1", CPEN_(4,C1,0), 0 },
3635 { "spsr_irq", CPEN_(4,C3,0), 0 },
3636 { "spsr_abt", CPEN_(4,C3,1), 0 },
3637 { "spsr_und", CPEN_(4,C3,2), 0 },
3638 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3639 { "spsr_el3", CPEN_(6,C0,0), 0 },
3640 { "elr_el3", CPEN_(6,C0,1), 0 },
3641 { "sp_el2", CPEN_(6,C1,0), 0 },
3642 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3643 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
3644 { "midr_el1", CPENC(3,0,C0,C0,0), 0 }, /* RO */
3645 { "ctr_el0", CPENC(3,3,C0,C0,1), 0 }, /* RO */
3646 { "mpidr_el1", CPENC(3,0,C0,C0,5), 0 }, /* RO */
3647 { "revidr_el1", CPENC(3,0,C0,C0,6), 0 }, /* RO */
3648 { "aidr_el1", CPENC(3,1,C0,C0,7), 0 }, /* RO */
3649 { "dczid_el0", CPENC(3,3,C0,C0,7), 0 }, /* RO */
3650 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), 0 }, /* RO */
3651 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), 0 }, /* RO */
3652 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), 0 }, /* RO */
3653 { "id_afr0_el1", CPENC(3,0,C0,C1,3), 0 }, /* RO */
3654 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), 0 }, /* RO */
3655 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), 0 }, /* RO */
3656 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), 0 }, /* RO */
3657 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), 0 }, /* RO */
3658 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), 0 }, /* RO */
3659 { "id_isar0_el1", CPENC(3,0,C0,C2,0), 0 }, /* RO */
3660 { "id_isar1_el1", CPENC(3,0,C0,C2,1), 0 }, /* RO */
3661 { "id_isar2_el1", CPENC(3,0,C0,C2,2), 0 }, /* RO */
3662 { "id_isar3_el1", CPENC(3,0,C0,C2,3), 0 }, /* RO */
3663 { "id_isar4_el1", CPENC(3,0,C0,C2,4), 0 }, /* RO */
3664 { "id_isar5_el1", CPENC(3,0,C0,C2,5), 0 }, /* RO */
3665 { "mvfr0_el1", CPENC(3,0,C0,C3,0), 0 }, /* RO */
3666 { "mvfr1_el1", CPENC(3,0,C0,C3,1), 0 }, /* RO */
3667 { "mvfr2_el1", CPENC(3,0,C0,C3,2), 0 }, /* RO */
3668 { "ccsidr_el1", CPENC(3,1,C0,C0,0), 0 }, /* RO */
3669 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), 0 }, /* RO */
3670 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), 0 }, /* RO */
3671 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), 0 }, /* RO */
3672 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), 0 }, /* RO */
3673 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), 0 }, /* RO */
3674 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), 0 }, /* RO */
3675 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), 0 }, /* RO */
3676 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), 0 }, /* RO */
3677 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT }, /* RO */
3678 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), 0 }, /* RO */
3679 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), 0 }, /* RO */
3680 { "clidr_el1", CPENC(3,1,C0,C0,1), 0 }, /* RO */
3681 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 }, /* RO */
3682 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3683 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3684 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3685 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3686 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
3687 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
3688 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3689 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3690 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3691 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
3692 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
3693 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3694 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3695 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3696 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3697 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3698 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3699 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3700 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
3701 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3702 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3703 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
3704 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
3705 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
3706 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3707 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
3708 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3709 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3710 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3711 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
3712 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
3713 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
3714 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3715 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3716 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3717 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3718 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3719 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3720 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3721 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3722 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3723 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
3724 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3725 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3726 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3727 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3728 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
3729 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
3730 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
3731 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
3732 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3733 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3734 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
3735 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
3736 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT }, /* RO */
3737 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
3738 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT }, /* RO */
3739 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
3740 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT }, /* RO */
3741 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3742 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3743 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3744 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3745 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
3746 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3747 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3748 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
3749 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
3750 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3751 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3752 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3753 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3754 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
3755 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
3756 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3757 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3758 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
3759 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
3760 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3761 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3762 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
3763 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
3764 { "rvbar_el1", CPENC(3,0,C12,C0,1), 0 }, /* RO */
3765 { "rvbar_el2", CPENC(3,4,C12,C0,1), 0 }, /* RO */
3766 { "rvbar_el3", CPENC(3,6,C12,C0,1), 0 }, /* RO */
3767 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3768 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3769 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
3770 { "isr_el1", CPENC(3,0,C12,C1,0), 0 }, /* RO */
3771 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3772 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
3773 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
3774 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3775 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
3776 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
3777 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RO */
3778 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3779 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3780 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
3781 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
3782 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RO */
3783 { "cntpct_el0", CPENC(3,3,C14,C0,1), 0 }, /* RO */
3784 { "cntvct_el0", CPENC(3,3,C14,C0,2), 0 }, /* RO */
3785 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3786 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
3787 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
3788 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
3789 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
3790 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
3791 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
3792 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
3793 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
3794 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
3795 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
3796 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
3797 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
3798 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
3799 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
3800 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
3801 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
3802 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
3803 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
3804 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
3805 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
3806 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
3807 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
3808 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
3809 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
3810 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
3811 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
3812 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
3813 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
3814 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
3815 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), 0 }, /* r */
3816 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
3817 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
3818 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), 0 }, /* r */
3819 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), 0 }, /* w */
3820 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 }, /* r */
3821 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 }, /* w */
3822 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
3823 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
3824 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
3825 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
3826 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
3827 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
3828 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
3829 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
3830 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
3831 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
3832 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
3833 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
3834 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
3835 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
3836 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
3837 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
3838 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
3839 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
3840 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
3841 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
3842 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
3843 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
3844 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
3845 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
3846 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
3847 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
3848 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
3849 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
3850 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
3851 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
3852 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
3853 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
3854 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
3855 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
3856 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
3857 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
3858 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
3859 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
3860 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
3861 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
3862 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
3863 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
3864 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
3865 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
3866 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
3867 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
3868 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
3869 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
3870 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
3871 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
3872 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
3873 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
3874 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
3875 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
3876 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
3877 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
3878 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
3879 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
3880 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
3881 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
3882 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
3883 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
3884 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
3885 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
3886 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
3887 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
3888 { "mdrar_el1", CPENC(2,0,C1, C0, 0), 0 }, /* r */
3889 { "oslar_el1", CPENC(2,0,C1, C0, 4), 0 }, /* w */
3890 { "oslsr_el1", CPENC(2,0,C1, C1, 4), 0 }, /* r */
3891 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
3892 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
3893 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
3894 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
3895 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), 0 }, /* r */
3896 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
3897 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
3898 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
3899 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT }, /* ro */
3900 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
3901 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
3902 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
3903 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
3904 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
3905 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
3906 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* ro */
3907 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
3908 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
3909 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
3910 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
3911 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
3912 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
3913 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), 0 }, /* w */
3914 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
3915 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), 0 }, /* r */
3916 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), 0 }, /* r */
3917 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
3918 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
3919 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
3920 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
3921 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
3922 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
3923 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
3924 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
3925 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
3926 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
3927 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
3928 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
3929 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
3930 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
3931 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
3932 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
3933 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
3934 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
3935 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
3936 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
3937 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
3938 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
3939 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
3940 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
3941 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
3942 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
3943 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
3944 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
3945 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
3946 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
3947 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
3948 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
3949 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
3950 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
3951 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
3952 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
3953 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
3954 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
3955 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
3956 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
3957 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
3958 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
3959 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
3960 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
3961 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
3962 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
3963 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
3964 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
3965 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
3966 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
3967 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
3968 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
3969 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
3970 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
3971 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
3972 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
3973 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
3974 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
3975 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
3976 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
3977 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
3978 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
3979 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
3980 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
3981 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
3982 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
3983 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
3984 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
3985 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
3986 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
3987 { 0, CPENC(0,0,0,0,0), 0 },
3988 };
3989
3990 bfd_boolean
3991 aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
3992 {
3993 return (reg->flags & F_DEPRECATED) != 0;
3994 }
3995
3996 bfd_boolean
3997 aarch64_sys_reg_supported_p (const aarch64_feature_set features,
3998 const aarch64_sys_reg *reg)
3999 {
4000 if (!(reg->flags & F_ARCHEXT))
4001 return TRUE;
4002
4003 /* PAN. Values are from aarch64_sys_regs. */
4004 if (reg->value == CPEN_(0,C2,3)
4005 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4006 return FALSE;
4007
4008 /* Virtualization host extensions: system registers. */
4009 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4010 || reg->value == CPENC (3, 4, C13, C0, 1)
4011 || reg->value == CPENC (3, 4, C14, C3, 0)
4012 || reg->value == CPENC (3, 4, C14, C3, 1)
4013 || reg->value == CPENC (3, 4, C14, C3, 2))
4014 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4015 return FALSE;
4016
4017 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4018 if ((reg->value == CPEN_ (5, C0, 0)
4019 || reg->value == CPEN_ (5, C0, 1)
4020 || reg->value == CPENC (3, 5, C1, C0, 0)
4021 || reg->value == CPENC (3, 5, C1, C0, 2)
4022 || reg->value == CPENC (3, 5, C2, C0, 0)
4023 || reg->value == CPENC (3, 5, C2, C0, 1)
4024 || reg->value == CPENC (3, 5, C2, C0, 2)
4025 || reg->value == CPENC (3, 5, C5, C1, 0)
4026 || reg->value == CPENC (3, 5, C5, C1, 1)
4027 || reg->value == CPENC (3, 5, C5, C2, 0)
4028 || reg->value == CPENC (3, 5, C6, C0, 0)
4029 || reg->value == CPENC (3, 5, C10, C2, 0)
4030 || reg->value == CPENC (3, 5, C10, C3, 0)
4031 || reg->value == CPENC (3, 5, C12, C0, 0)
4032 || reg->value == CPENC (3, 5, C13, C0, 1)
4033 || reg->value == CPENC (3, 5, C14, C1, 0))
4034 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4035 return FALSE;
4036
4037 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4038 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4039 || reg->value == CPENC (3, 5, C14, C2, 1)
4040 || reg->value == CPENC (3, 5, C14, C2, 2)
4041 || reg->value == CPENC (3, 5, C14, C3, 0)
4042 || reg->value == CPENC (3, 5, C14, C3, 1)
4043 || reg->value == CPENC (3, 5, C14, C3, 2))
4044 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4045 return FALSE;
4046
4047 /* ARMv8.2 features. */
4048
4049 /* ID_AA64MMFR2_EL1. */
4050 if (reg->value == CPENC (3, 0, C0, C7, 2)
4051 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4052 return FALSE;
4053
4054 /* PSTATE.UAO. */
4055 if (reg->value == CPEN_ (0, C2, 4)
4056 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4057 return FALSE;
4058
4059 /* RAS extension. */
4060
4061 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4062 ERXMISC0_EL1 AND ERXMISC1_EL1. */
4063 if ((reg->value == CPENC (3, 0, C5, C3, 0)
4064 || reg->value == CPENC (3, 0, C5, C3, 1)
4065 || reg->value == CPENC (3, 0, C5, C3, 2)
4066 || reg->value == CPENC (3, 0, C5, C3, 3)
4067 || reg->value == CPENC (3, 0, C5, C4, 0)
4068 || reg->value == CPENC (3, 0, C5, C4, 1)
4069 || reg->value == CPENC (3, 0, C5, C4, 2)
4070 || reg->value == CPENC (3, 0, C5, C4, 3)
4071 || reg->value == CPENC (3, 0, C5, C5, 0)
4072 || reg->value == CPENC (3, 0, C5, C5, 1))
4073 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4074 return FALSE;
4075
4076 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4077 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4078 || reg->value == CPENC (3, 0, C12, C1, 1)
4079 || reg->value == CPENC (3, 4, C12, C1, 1))
4080 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4081 return FALSE;
4082
4083 /* Statistical Profiling extension. */
4084 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4085 || reg->value == CPENC (3, 0, C9, C10, 1)
4086 || reg->value == CPENC (3, 0, C9, C10, 3)
4087 || reg->value == CPENC (3, 0, C9, C10, 7)
4088 || reg->value == CPENC (3, 0, C9, C9, 0)
4089 || reg->value == CPENC (3, 0, C9, C9, 2)
4090 || reg->value == CPENC (3, 0, C9, C9, 3)
4091 || reg->value == CPENC (3, 0, C9, C9, 4)
4092 || reg->value == CPENC (3, 0, C9, C9, 5)
4093 || reg->value == CPENC (3, 0, C9, C9, 6)
4094 || reg->value == CPENC (3, 0, C9, C9, 7)
4095 || reg->value == CPENC (3, 4, C9, C9, 0)
4096 || reg->value == CPENC (3, 5, C9, C9, 0))
4097 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4098 return FALSE;
4099
4100 /* ARMv8.3 Pointer authentication keys. */
4101 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4102 || reg->value == CPENC (3, 0, C2, C1, 1)
4103 || reg->value == CPENC (3, 0, C2, C1, 2)
4104 || reg->value == CPENC (3, 0, C2, C1, 3)
4105 || reg->value == CPENC (3, 0, C2, C2, 0)
4106 || reg->value == CPENC (3, 0, C2, C2, 1)
4107 || reg->value == CPENC (3, 0, C2, C2, 2)
4108 || reg->value == CPENC (3, 0, C2, C2, 3)
4109 || reg->value == CPENC (3, 0, C2, C3, 0)
4110 || reg->value == CPENC (3, 0, C2, C3, 1))
4111 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4112 return FALSE;
4113
4114 return TRUE;
4115 }
4116
4117 const aarch64_sys_reg aarch64_pstatefields [] =
4118 {
4119 { "spsel", 0x05, 0 },
4120 { "daifset", 0x1e, 0 },
4121 { "daifclr", 0x1f, 0 },
4122 { "pan", 0x04, F_ARCHEXT },
4123 { "uao", 0x03, F_ARCHEXT },
4124 { 0, CPENC(0,0,0,0,0), 0 },
4125 };
4126
4127 bfd_boolean
4128 aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4129 const aarch64_sys_reg *reg)
4130 {
4131 if (!(reg->flags & F_ARCHEXT))
4132 return TRUE;
4133
4134 /* PAN. Values are from aarch64_pstatefields. */
4135 if (reg->value == 0x04
4136 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4137 return FALSE;
4138
4139 /* UAO. Values are from aarch64_pstatefields. */
4140 if (reg->value == 0x03
4141 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4142 return FALSE;
4143
4144 return TRUE;
4145 }
4146
4147 const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4148 {
4149 { "ialluis", CPENS(0,C7,C1,0), 0 },
4150 { "iallu", CPENS(0,C7,C5,0), 0 },
4151 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
4152 { 0, CPENS(0,0,0,0), 0 }
4153 };
4154
4155 const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4156 {
4157 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
4158 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
4159 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
4160 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
4161 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
4162 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
4163 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
4164 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
4165 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
4166 { 0, CPENS(0,0,0,0), 0 }
4167 };
4168
4169 const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4170 {
4171 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4172 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4173 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4174 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4175 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4176 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4177 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4178 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4179 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4180 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4181 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4182 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
4183 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4184 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
4185 { 0, CPENS(0,0,0,0), 0 }
4186 };
4187
4188 const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4189 {
4190 { "vmalle1", CPENS(0,C8,C7,0), 0 },
4191 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4192 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4193 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
4194 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
4195 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4196 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4197 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4198 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4199 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4200 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4201 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4202 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4203 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
4204 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4205 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
4206 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4207 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
4208 { "alle2", CPENS(4,C8,C7,0), 0 },
4209 { "alle2is", CPENS(4,C8,C3,0), 0 },
4210 { "alle1", CPENS(4,C8,C7,4), 0 },
4211 { "alle1is", CPENS(4,C8,C3,4), 0 },
4212 { "alle3", CPENS(6,C8,C7,0), 0 },
4213 { "alle3is", CPENS(6,C8,C3,0), 0 },
4214 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4215 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4216 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4217 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4218 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4219 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4220 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4221 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
4222 { 0, CPENS(0,0,0,0), 0 }
4223 };
4224
4225 bfd_boolean
4226 aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4227 {
4228 return (sys_ins_reg->flags & F_HASXT) != 0;
4229 }
4230
4231 extern bfd_boolean
4232 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4233 const aarch64_sys_ins_reg *reg)
4234 {
4235 if (!(reg->flags & F_ARCHEXT))
4236 return TRUE;
4237
4238 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4239 if (reg->value == CPENS (3, C7, C12, 1)
4240 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4241 return FALSE;
4242
4243 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4244 if ((reg->value == CPENS (0, C7, C9, 0)
4245 || reg->value == CPENS (0, C7, C9, 1))
4246 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4247 return FALSE;
4248
4249 return TRUE;
4250 }
4251
4252 #undef C0
4253 #undef C1
4254 #undef C2
4255 #undef C3
4256 #undef C4
4257 #undef C5
4258 #undef C6
4259 #undef C7
4260 #undef C8
4261 #undef C9
4262 #undef C10
4263 #undef C11
4264 #undef C12
4265 #undef C13
4266 #undef C14
4267 #undef C15
4268
4269 #define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4270 #define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4271
4272 static bfd_boolean
4273 verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
4274 const aarch64_insn insn)
4275 {
4276 int t = BITS (insn, 4, 0);
4277 int n = BITS (insn, 9, 5);
4278 int t2 = BITS (insn, 14, 10);
4279
4280 if (BIT (insn, 23))
4281 {
4282 /* Write back enabled. */
4283 if ((t == n || t2 == n) && n != 31)
4284 return FALSE;
4285 }
4286
4287 if (BIT (insn, 22))
4288 {
4289 /* Load */
4290 if (t == t2)
4291 return FALSE;
4292 }
4293
4294 return TRUE;
4295 }
4296
4297 /* Return true if VALUE cannot be moved into an SVE register using DUP
4298 (with any element size, not just ESIZE) and if using DUPM would
4299 therefore be OK. ESIZE is the number of bytes in the immediate. */
4300
4301 bfd_boolean
4302 aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
4303 {
4304 int64_t svalue = uvalue;
4305 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
4306
4307 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
4308 return FALSE;
4309 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
4310 {
4311 svalue = (int32_t) uvalue;
4312 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
4313 {
4314 svalue = (int16_t) uvalue;
4315 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
4316 return FALSE;
4317 }
4318 }
4319 if ((svalue & 0xff) == 0)
4320 svalue /= 256;
4321 return svalue < -128 || svalue >= 128;
4322 }
4323
4324 /* Include the opcode description table as well as the operand description
4325 table. */
4326 #define VERIFIER(x) verify_##x
4327 #include "aarch64-tbl.h"
GDB Binutils - Deliverables
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