opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2016 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm4,
  71   FLD_imm5,
  72   FLD_imm7,
  73   FLD_imm8,
  74   FLD_imm9,
  75   FLD_imm12,
  76   FLD_imm14,
  77   FLD_imm16,
  78   FLD_imm26,
  79   FLD_imms,
  80   FLD_immr,
  81   FLD_immb,
  82   FLD_immh,
  83   FLD_S_imm10,
  84   FLD_N,
  85   FLD_index,
  86   FLD_index2,
  87   FLD_sf,
  88   FLD_lse_sz,
  89   FLD_H,
  90   FLD_L,
  91   FLD_M,
  92   FLD_b5,
  93   FLD_b40,
  94   FLD_scale,
  95   FLD_SVE_M_4,
  96   FLD_SVE_M_14,
  97   FLD_SVE_M_16,
  98   FLD_SVE_N,
  99   FLD_SVE_Pd,
 100   FLD_SVE_Pg3,
 101   FLD_SVE_Pg4_5,
 102   FLD_SVE_Pg4_10,
 103   FLD_SVE_Pg4_16,
 104   FLD_SVE_Pm,
 105   FLD_SVE_Pn,
 106   FLD_SVE_Pt,
 107   FLD_SVE_Rm,
 108   FLD_SVE_Rn,
 109   FLD_SVE_Vd,
 110   FLD_SVE_Vm,
 111   FLD_SVE_Vn,
 112   FLD_SVE_Za_5,
 113   FLD_SVE_Za_16,
 114   FLD_SVE_Zd,
 115   FLD_SVE_Zm_5,
 116   FLD_SVE_Zm_16,
 117   FLD_SVE_Zn,
 118   FLD_SVE_Zt,
 119   FLD_SVE_i1,
 120   FLD_SVE_imm3,
 121   FLD_SVE_imm4,
 122   FLD_SVE_imm5,
 123   FLD_SVE_imm5b,
 124   FLD_SVE_imm6,
 125   FLD_SVE_imm7,
 126   FLD_SVE_imm8,
 127   FLD_SVE_imm9,
 128   FLD_SVE_immr,
 129   FLD_SVE_imms,
 130   FLD_SVE_msz,
 131   FLD_SVE_pattern,
 132   FLD_SVE_prfop,
 133   FLD_SVE_sz,
 134   FLD_SVE_tsz,
 135   FLD_SVE_tszh,
 136   FLD_SVE_tszl_8,
 137   FLD_SVE_tszl_19,
 138   FLD_SVE_xs_14,
 139   FLD_SVE_xs_22,
 140 };
 141
 142 /* Field description.  */
 143 struct aarch64_field
 144 {
 145   int lsb;
 146   int width;
 147 };
 148
 149 typedef struct aarch64_field aarch64_field;
 150
 151 extern const aarch64_field fields[];
 152 \f
 153 /* Operand description.  */
 154
 155 struct aarch64_operand
 156 {
 157   enum aarch64_operand_class op_class;
 158
 159   /* Name of the operand code; used mainly for the purpose of internal
 160      debugging.  */
 161   const char *name;
 162
 163   unsigned int flags;
 164
 165   /* The associated instruction bit-fields; no operand has more than 4
 166      bit-fields */
 167   enum aarch64_field_kind fields[4];
 168
 169   /* Brief description */
 170   const char *desc;
 171 };
 172
 173 typedef struct aarch64_operand aarch64_operand;
 174
 175 extern const aarch64_operand aarch64_operands[];
 176
 177 /* Operand flags.  */
 178
 179 #define OPD_F_HAS_INSERTER      0x00000001
 180 #define OPD_F_HAS_EXTRACTOR     0x00000002
 181 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 182 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 183                                                    value by 2 to get the value
 184                                                    of an immediate operand.  */
 185 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 186 #define OPD_F_OD_MASK           0x00000060      /* Operand-dependent data.  */
 187 #define OPD_F_OD_LSB            5
 188 #define OPD_F_NO_ZR             0x00000080      /* ZR index not allowed.  */
 189
 190 static inline bfd_boolean
 191 operand_has_inserter (const aarch64_operand *operand)
 192 {
 193   return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
 194 }
 195
 196 static inline bfd_boolean
 197 operand_has_extractor (const aarch64_operand *operand)
 198 {
 199   return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
 200 }
 201
 202 static inline bfd_boolean
 203 operand_need_sign_extension (const aarch64_operand *operand)
 204 {
 205   return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
 206 }
 207
 208 static inline bfd_boolean
 209 operand_need_shift_by_two (const aarch64_operand *operand)
 210 {
 211   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 212 }
 213
 214 static inline bfd_boolean
 215 operand_maybe_stack_pointer (const aarch64_operand *operand)
 216 {
 217   return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
 218 }
 219
 220 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 221 static inline unsigned int
 222 get_operand_specific_data (const aarch64_operand *operand)
 223 {
 224   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 225 }
 226
 227 /* Return the total width of the operand *OPERAND.  */
 228 static inline unsigned
 229 get_operand_fields_width (const aarch64_operand *operand)
 230 {
 231   int i = 0;
 232   unsigned width = 0;
 233   while (operand->fields[i] != FLD_NIL)
 234     width += fields[operand->fields[i++]].width;
 235   assert (width > 0 && width < 32);
 236   return width;
 237 }
 238
 239 static inline const aarch64_operand *
 240 get_operand_from_code (enum aarch64_opnd code)
 241 {
 242   return aarch64_operands + code;
 243 }
 244 \f
 245 /* Operand qualifier and operand constraint checking.  */
 246
 247 int aarch64_match_operands_constraint (aarch64_inst *,
 248                                        aarch64_operand_error *);
 249
 250 /* Operand qualifier related functions.  */
 251 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 252 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 253 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 254 int aarch64_find_best_match (const aarch64_inst *,
 255                              const aarch64_opnd_qualifier_seq_t *,
 256                              int, aarch64_opnd_qualifier_t *);
 257
 258 static inline void
 259 reset_operand_qualifier (aarch64_inst *inst, int idx)
 260 {
 261   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 262   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 263 }
 264 \f
 265 /* Inline functions operating on instruction bit-field(s).  */
 266
 267 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 268
 269 static inline aarch64_insn
 270 gen_mask (int width)
 271 {
 272   return ((aarch64_insn) 1 << width) - 1;
 273 }
 274
 275 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 276 static inline int
 277 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 278 {
 279   const aarch64_field *field = &fields[kind];
 280   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 281     return 0;
 282   ret->lsb = field->lsb + lsb_rel;
 283   ret->width = width;
 284   return 1;
 285 }
 286
 287 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 288    of the opcode.  */
 289
 290 static inline void
 291 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 292                 aarch64_insn value, aarch64_insn mask)
 293 {
 294   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 295           && field->lsb + field->width <= 32);
 296   value &= gen_mask (field->width);
 297   value <<= field->lsb;
 298   /* In some opcodes, field can be part of the base opcode, e.g. the size
 299      field in FADD.  The following helps avoid corrupt the base opcode.  */
 300   value &= ~mask;
 301   *code |= value;
 302 }
 303
 304 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 305    mask of the opcode.  */
 306
 307 static inline aarch64_insn
 308 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 309                  aarch64_insn mask)
 310 {
 311   aarch64_insn value;
 312   /* Clear any bit that is a part of the base opcode.  */
 313   code &= ~mask;
 314   value = (code >> field->lsb) & gen_mask (field->width);
 315   return value;
 316 }
 317
 318 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 319    of the opcode.  */
 320
 321 static inline void
 322 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 323               aarch64_insn value, aarch64_insn mask)
 324 {
 325   insert_field_2 (&fields[kind], code, value, mask);
 326 }
 327
 328 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 329    base mask of the opcode.  */
 330
 331 static inline aarch64_insn
 332 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 333                aarch64_insn mask)
 334 {
 335   return extract_field_2 (&fields[kind], code, mask);
 336 }
 337
 338 extern aarch64_insn
 339 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 340 \f
 341 /* Inline functions selecting operand to do the encoding/decoding for a
 342    certain instruction bit-field.  */
 343
 344 /* Select the operand to do the encoding/decoding of the 'sf' field.
 345    The heuristic-based rule is that the result operand is respected more.  */
 346
 347 static inline int
 348 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 349 {
 350   int idx = -1;
 351   if (aarch64_get_operand_class (opcode->operands[0])
 352       == AARCH64_OPND_CLASS_INT_REG)
 353     /* normal case.  */
 354     idx = 0;
 355   else if (aarch64_get_operand_class (opcode->operands[1])
 356            == AARCH64_OPND_CLASS_INT_REG)
 357     /* e.g. float2fix.  */
 358     idx = 1;
 359   else
 360     { assert (0); abort (); }
 361   return idx;
 362 }
 363
 364 /* Select the operand to do the encoding/decoding of the 'type' field in
 365    the floating-point instructions.
 366    The heuristic-based rule is that the source operand is respected more.  */
 367
 368 static inline int
 369 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 370 {
 371   int idx;
 372   if (aarch64_get_operand_class (opcode->operands[1])
 373       == AARCH64_OPND_CLASS_FP_REG)
 374     /* normal case.  */
 375     idx = 1;
 376   else if (aarch64_get_operand_class (opcode->operands[0])
 377            == AARCH64_OPND_CLASS_FP_REG)
 378     /* e.g. float2fix.  */
 379     idx = 0;
 380   else
 381     { assert (0); abort (); }
 382   return idx;
 383 }
 384
 385 /* Select the operand to do the encoding/decoding of the 'size' field in
 386    the AdvSIMD scalar instructions.
 387    The heuristic-based rule is that the destination operand is respected
 388    more.  */
 389
 390 static inline int
 391 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 392 {
 393   int src_size = 0, dst_size = 0;
 394   if (aarch64_get_operand_class (opcode->operands[0])
 395       == AARCH64_OPND_CLASS_SISD_REG)
 396     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 397   if (aarch64_get_operand_class (opcode->operands[1])
 398       == AARCH64_OPND_CLASS_SISD_REG)
 399     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 400   if (src_size == dst_size && src_size == 0)
 401     { assert (0); abort (); }
 402   /* When the result is not a sisd register or it is a long operantion.  */
 403   if (dst_size == 0 || dst_size == src_size << 1)
 404     return 1;
 405   else
 406     return 0;
 407 }
 408
 409 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 410    the AdvSIMD instructions.  */
 411
 412 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 413 \f
 414 /* Miscellaneous.  */
 415
 416 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 417 enum aarch64_modifier_kind
 418 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 419
 420
 421 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
 422 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 423 int aarch64_shrink_expanded_imm8 (uint64_t);
 424
 425 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 426 static inline void
 427 copy_operand_info (aarch64_inst *inst, int dst, int src)
 428 {
 429   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 430           && src < AARCH64_MAX_OPND_NUM);
 431   memcpy (&inst->operands[dst], &inst->operands[src],
 432           sizeof (aarch64_opnd_info));
 433   inst->operands[dst].idx = dst;
 434 }
 435
 436 /* A primitive log caculator.  */
 437
 438 static inline unsigned int
 439 get_logsz (unsigned int size)
 440 {
 441   const unsigned char ls[16] =
 442     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 443   if (size > 16)
 444     {
 445       assert (0);
 446       return -1;
 447     }
 448   assert (ls[size - 1] != (unsigned char)-1);
 449   return ls[size - 1];
 450 }
 451
 452 #endif /* OPCODES_AARCH64_OPC_H */