opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2016 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm4,
  71   FLD_imm5,
  72   FLD_imm7,
  73   FLD_imm8,
  74   FLD_imm9,
  75   FLD_imm12,
  76   FLD_imm14,
  77   FLD_imm16,
  78   FLD_imm26,
  79   FLD_imms,
  80   FLD_immr,
  81   FLD_immb,
  82   FLD_immh,
  83   FLD_N,
  84   FLD_index,
  85   FLD_index2,
  86   FLD_sf,
  87   FLD_lse_sz,
  88   FLD_H,
  89   FLD_L,
  90   FLD_M,
  91   FLD_b5,
  92   FLD_b40,
  93   FLD_scale,
  94   FLD_SVE_M_4,
  95   FLD_SVE_M_14,
  96   FLD_SVE_M_16,
  97   FLD_SVE_N,
  98   FLD_SVE_Pd,
  99   FLD_SVE_Pg3,
 100   FLD_SVE_Pg4_5,
 101   FLD_SVE_Pg4_10,
 102   FLD_SVE_Pg4_16,
 103   FLD_SVE_Pm,
 104   FLD_SVE_Pn,
 105   FLD_SVE_Pt,
 106   FLD_SVE_Rm,
 107   FLD_SVE_Rn,
 108   FLD_SVE_Vd,
 109   FLD_SVE_Vm,
 110   FLD_SVE_Vn,
 111   FLD_SVE_Za_5,
 112   FLD_SVE_Za_16,
 113   FLD_SVE_Zd,
 114   FLD_SVE_Zm_5,
 115   FLD_SVE_Zm_16,
 116   FLD_SVE_Zn,
 117   FLD_SVE_Zt,
 118   FLD_SVE_i1,
 119   FLD_SVE_imm3,
 120   FLD_SVE_imm4,
 121   FLD_SVE_imm5,
 122   FLD_SVE_imm5b,
 123   FLD_SVE_imm6,
 124   FLD_SVE_imm7,
 125   FLD_SVE_imm8,
 126   FLD_SVE_imm9,
 127   FLD_SVE_immr,
 128   FLD_SVE_imms,
 129   FLD_SVE_msz,
 130   FLD_SVE_pattern,
 131   FLD_SVE_prfop,
 132   FLD_SVE_sz,
 133   FLD_SVE_tsz,
 134   FLD_SVE_tszh,
 135   FLD_SVE_tszl_8,
 136   FLD_SVE_tszl_19,
 137   FLD_SVE_xs_14,
 138   FLD_SVE_xs_22,
 139 };
 140
 141 /* Field description.  */
 142 struct aarch64_field
 143 {
 144   int lsb;
 145   int width;
 146 };
 147
 148 typedef struct aarch64_field aarch64_field;
 149
 150 extern const aarch64_field fields[];
 151 \f
 152 /* Operand description.  */
 153
 154 struct aarch64_operand
 155 {
 156   enum aarch64_operand_class op_class;
 157
 158   /* Name of the operand code; used mainly for the purpose of internal
 159      debugging.  */
 160   const char *name;
 161
 162   unsigned int flags;
 163
 164   /* The associated instruction bit-fields; no operand has more than 4
 165      bit-fields */
 166   enum aarch64_field_kind fields[4];
 167
 168   /* Brief description */
 169   const char *desc;
 170 };
 171
 172 typedef struct aarch64_operand aarch64_operand;
 173
 174 extern const aarch64_operand aarch64_operands[];
 175
 176 /* Operand flags.  */
 177
 178 #define OPD_F_HAS_INSERTER      0x00000001
 179 #define OPD_F_HAS_EXTRACTOR     0x00000002
 180 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 181 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 182                                                    value by 2 to get the value
 183                                                    of an immediate operand.  */
 184 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 185 #define OPD_F_OD_MASK           0x00000060      /* Operand-dependent data.  */
 186 #define OPD_F_OD_LSB            5
 187 #define OPD_F_NO_ZR             0x00000080      /* ZR index not allowed.  */
 188
 189 static inline bfd_boolean
 190 operand_has_inserter (const aarch64_operand *operand)
 191 {
 192   return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
 193 }
 194
 195 static inline bfd_boolean
 196 operand_has_extractor (const aarch64_operand *operand)
 197 {
 198   return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
 199 }
 200
 201 static inline bfd_boolean
 202 operand_need_sign_extension (const aarch64_operand *operand)
 203 {
 204   return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
 205 }
 206
 207 static inline bfd_boolean
 208 operand_need_shift_by_two (const aarch64_operand *operand)
 209 {
 210   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 211 }
 212
 213 static inline bfd_boolean
 214 operand_maybe_stack_pointer (const aarch64_operand *operand)
 215 {
 216   return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
 217 }
 218
 219 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 220 static inline unsigned int
 221 get_operand_specific_data (const aarch64_operand *operand)
 222 {
 223   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 224 }
 225
 226 /* Return the total width of the operand *OPERAND.  */
 227 static inline unsigned
 228 get_operand_fields_width (const aarch64_operand *operand)
 229 {
 230   int i = 0;
 231   unsigned width = 0;
 232   while (operand->fields[i] != FLD_NIL)
 233     width += fields[operand->fields[i++]].width;
 234   assert (width > 0 && width < 32);
 235   return width;
 236 }
 237
 238 static inline const aarch64_operand *
 239 get_operand_from_code (enum aarch64_opnd code)
 240 {
 241   return aarch64_operands + code;
 242 }
 243 \f
 244 /* Operand qualifier and operand constraint checking.  */
 245
 246 int aarch64_match_operands_constraint (aarch64_inst *,
 247                                        aarch64_operand_error *);
 248
 249 /* Operand qualifier related functions.  */
 250 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 251 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 252 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 253 int aarch64_find_best_match (const aarch64_inst *,
 254                              const aarch64_opnd_qualifier_seq_t *,
 255                              int, aarch64_opnd_qualifier_t *);
 256
 257 static inline void
 258 reset_operand_qualifier (aarch64_inst *inst, int idx)
 259 {
 260   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 261   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 262 }
 263 \f
 264 /* Inline functions operating on instruction bit-field(s).  */
 265
 266 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 267
 268 static inline aarch64_insn
 269 gen_mask (int width)
 270 {
 271   return ((aarch64_insn) 1 << width) - 1;
 272 }
 273
 274 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 275 static inline int
 276 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 277 {
 278   const aarch64_field *field = &fields[kind];
 279   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 280     return 0;
 281   ret->lsb = field->lsb + lsb_rel;
 282   ret->width = width;
 283   return 1;
 284 }
 285
 286 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 287    of the opcode.  */
 288
 289 static inline void
 290 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 291                 aarch64_insn value, aarch64_insn mask)
 292 {
 293   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 294           && field->lsb + field->width <= 32);
 295   value &= gen_mask (field->width);
 296   value <<= field->lsb;
 297   /* In some opcodes, field can be part of the base opcode, e.g. the size
 298      field in FADD.  The following helps avoid corrupt the base opcode.  */
 299   value &= ~mask;
 300   *code |= value;
 301 }
 302
 303 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 304    mask of the opcode.  */
 305
 306 static inline aarch64_insn
 307 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 308                  aarch64_insn mask)
 309 {
 310   aarch64_insn value;
 311   /* Clear any bit that is a part of the base opcode.  */
 312   code &= ~mask;
 313   value = (code >> field->lsb) & gen_mask (field->width);
 314   return value;
 315 }
 316
 317 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 318    of the opcode.  */
 319
 320 static inline void
 321 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 322               aarch64_insn value, aarch64_insn mask)
 323 {
 324   insert_field_2 (&fields[kind], code, value, mask);
 325 }
 326
 327 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 328    base mask of the opcode.  */
 329
 330 static inline aarch64_insn
 331 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 332                aarch64_insn mask)
 333 {
 334   return extract_field_2 (&fields[kind], code, mask);
 335 }
 336
 337 extern aarch64_insn
 338 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 339 \f
 340 /* Inline functions selecting operand to do the encoding/decoding for a
 341    certain instruction bit-field.  */
 342
 343 /* Select the operand to do the encoding/decoding of the 'sf' field.
 344    The heuristic-based rule is that the result operand is respected more.  */
 345
 346 static inline int
 347 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 348 {
 349   int idx = -1;
 350   if (aarch64_get_operand_class (opcode->operands[0])
 351       == AARCH64_OPND_CLASS_INT_REG)
 352     /* normal case.  */
 353     idx = 0;
 354   else if (aarch64_get_operand_class (opcode->operands[1])
 355            == AARCH64_OPND_CLASS_INT_REG)
 356     /* e.g. float2fix.  */
 357     idx = 1;
 358   else
 359     { assert (0); abort (); }
 360   return idx;
 361 }
 362
 363 /* Select the operand to do the encoding/decoding of the 'type' field in
 364    the floating-point instructions.
 365    The heuristic-based rule is that the source operand is respected more.  */
 366
 367 static inline int
 368 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 369 {
 370   int idx;
 371   if (aarch64_get_operand_class (opcode->operands[1])
 372       == AARCH64_OPND_CLASS_FP_REG)
 373     /* normal case.  */
 374     idx = 1;
 375   else if (aarch64_get_operand_class (opcode->operands[0])
 376            == AARCH64_OPND_CLASS_FP_REG)
 377     /* e.g. float2fix.  */
 378     idx = 0;
 379   else
 380     { assert (0); abort (); }
 381   return idx;
 382 }
 383
 384 /* Select the operand to do the encoding/decoding of the 'size' field in
 385    the AdvSIMD scalar instructions.
 386    The heuristic-based rule is that the destination operand is respected
 387    more.  */
 388
 389 static inline int
 390 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 391 {
 392   int src_size = 0, dst_size = 0;
 393   if (aarch64_get_operand_class (opcode->operands[0])
 394       == AARCH64_OPND_CLASS_SISD_REG)
 395     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 396   if (aarch64_get_operand_class (opcode->operands[1])
 397       == AARCH64_OPND_CLASS_SISD_REG)
 398     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 399   if (src_size == dst_size && src_size == 0)
 400     { assert (0); abort (); }
 401   /* When the result is not a sisd register or it is a long operantion.  */
 402   if (dst_size == 0 || dst_size == src_size << 1)
 403     return 1;
 404   else
 405     return 0;
 406 }
 407
 408 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 409    the AdvSIMD instructions.  */
 410
 411 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 412 \f
 413 /* Miscellaneous.  */
 414
 415 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 416 enum aarch64_modifier_kind
 417 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 418
 419
 420 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
 421 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 422 int aarch64_shrink_expanded_imm8 (uint64_t);
 423
 424 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 425 static inline void
 426 copy_operand_info (aarch64_inst *inst, int dst, int src)
 427 {
 428   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 429           && src < AARCH64_MAX_OPND_NUM);
 430   memcpy (&inst->operands[dst], &inst->operands[src],
 431           sizeof (aarch64_opnd_info));
 432   inst->operands[dst].idx = dst;
 433 }
 434
 435 /* A primitive log caculator.  */
 436
 437 static inline unsigned int
 438 get_logsz (unsigned int size)
 439 {
 440   const unsigned char ls[16] =
 441     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 442   if (size > 16)
 443     {
 444       assert (0);
 445       return -1;
 446     }
 447   assert (ls[size - 1] != (unsigned char)-1);
 448   return ls[size - 1];
 449 }
 450
 451 #endif /* OPCODES_AARCH64_OPC_H */