opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2016 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm4,
  71   FLD_imm5,
  72   FLD_imm7,
  73   FLD_imm8,
  74   FLD_imm9,
  75   FLD_imm12,
  76   FLD_imm14,
  77   FLD_imm16,
  78   FLD_imm26,
  79   FLD_imms,
  80   FLD_immr,
  81   FLD_immb,
  82   FLD_immh,
  83   FLD_N,
  84   FLD_index,
  85   FLD_index2,
  86   FLD_sf,
  87   FLD_lse_sz,
  88   FLD_H,
  89   FLD_L,
  90   FLD_M,
  91   FLD_b5,
  92   FLD_b40,
  93   FLD_scale,
  94   FLD_SVE_N,
  95   FLD_SVE_Pd,
  96   FLD_SVE_Pg3,
  97   FLD_SVE_Pg4_5,
  98   FLD_SVE_Pg4_10,
  99   FLD_SVE_Pg4_16,
 100   FLD_SVE_Pm,
 101   FLD_SVE_Pn,
 102   FLD_SVE_Pt,
 103   FLD_SVE_Rm,
 104   FLD_SVE_Rn,
 105   FLD_SVE_Vd,
 106   FLD_SVE_Vm,
 107   FLD_SVE_Vn,
 108   FLD_SVE_Za_5,
 109   FLD_SVE_Za_16,
 110   FLD_SVE_Zd,
 111   FLD_SVE_Zm_5,
 112   FLD_SVE_Zm_16,
 113   FLD_SVE_Zn,
 114   FLD_SVE_Zt,
 115   FLD_SVE_i1,
 116   FLD_SVE_imm3,
 117   FLD_SVE_imm4,
 118   FLD_SVE_imm5,
 119   FLD_SVE_imm5b,
 120   FLD_SVE_imm6,
 121   FLD_SVE_imm7,
 122   FLD_SVE_imm8,
 123   FLD_SVE_imm9,
 124   FLD_SVE_immr,
 125   FLD_SVE_imms,
 126   FLD_SVE_msz,
 127   FLD_SVE_pattern,
 128   FLD_SVE_prfop,
 129   FLD_SVE_tszh,
 130   FLD_SVE_xs_14,
 131   FLD_SVE_xs_22,
 132 };
 133
 134 /* Field description.  */
 135 struct aarch64_field
 136 {
 137   int lsb;
 138   int width;
 139 };
 140
 141 typedef struct aarch64_field aarch64_field;
 142
 143 extern const aarch64_field fields[];
 144 \f
 145 /* Operand description.  */
 146
 147 struct aarch64_operand
 148 {
 149   enum aarch64_operand_class op_class;
 150
 151   /* Name of the operand code; used mainly for the purpose of internal
 152      debugging.  */
 153   const char *name;
 154
 155   unsigned int flags;
 156
 157   /* The associated instruction bit-fields; no operand has more than 4
 158      bit-fields */
 159   enum aarch64_field_kind fields[4];
 160
 161   /* Brief description */
 162   const char *desc;
 163 };
 164
 165 typedef struct aarch64_operand aarch64_operand;
 166
 167 extern const aarch64_operand aarch64_operands[];
 168
 169 /* Operand flags.  */
 170
 171 #define OPD_F_HAS_INSERTER      0x00000001
 172 #define OPD_F_HAS_EXTRACTOR     0x00000002
 173 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 174 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 175                                                    value by 2 to get the value
 176                                                    of an immediate operand.  */
 177 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 178 #define OPD_F_OD_MASK           0x00000060      /* Operand-dependent data.  */
 179 #define OPD_F_OD_LSB            5
 180 #define OPD_F_NO_ZR             0x00000080      /* ZR index not allowed.  */
 181
 182 static inline bfd_boolean
 183 operand_has_inserter (const aarch64_operand *operand)
 184 {
 185   return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
 186 }
 187
 188 static inline bfd_boolean
 189 operand_has_extractor (const aarch64_operand *operand)
 190 {
 191   return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
 192 }
 193
 194 static inline bfd_boolean
 195 operand_need_sign_extension (const aarch64_operand *operand)
 196 {
 197   return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
 198 }
 199
 200 static inline bfd_boolean
 201 operand_need_shift_by_two (const aarch64_operand *operand)
 202 {
 203   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 204 }
 205
 206 static inline bfd_boolean
 207 operand_maybe_stack_pointer (const aarch64_operand *operand)
 208 {
 209   return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
 210 }
 211
 212 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 213 static inline unsigned int
 214 get_operand_specific_data (const aarch64_operand *operand)
 215 {
 216   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 217 }
 218
 219 /* Return the total width of the operand *OPERAND.  */
 220 static inline unsigned
 221 get_operand_fields_width (const aarch64_operand *operand)
 222 {
 223   int i = 0;
 224   unsigned width = 0;
 225   while (operand->fields[i] != FLD_NIL)
 226     width += fields[operand->fields[i++]].width;
 227   assert (width > 0 && width < 32);
 228   return width;
 229 }
 230
 231 static inline const aarch64_operand *
 232 get_operand_from_code (enum aarch64_opnd code)
 233 {
 234   return aarch64_operands + code;
 235 }
 236 \f
 237 /* Operand qualifier and operand constraint checking.  */
 238
 239 int aarch64_match_operands_constraint (aarch64_inst *,
 240                                        aarch64_operand_error *);
 241
 242 /* Operand qualifier related functions.  */
 243 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 244 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 245 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 246 int aarch64_find_best_match (const aarch64_inst *,
 247                              const aarch64_opnd_qualifier_seq_t *,
 248                              int, aarch64_opnd_qualifier_t *);
 249
 250 static inline void
 251 reset_operand_qualifier (aarch64_inst *inst, int idx)
 252 {
 253   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 254   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 255 }
 256 \f
 257 /* Inline functions operating on instruction bit-field(s).  */
 258
 259 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 260
 261 static inline aarch64_insn
 262 gen_mask (int width)
 263 {
 264   return ((aarch64_insn) 1 << width) - 1;
 265 }
 266
 267 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 268 static inline int
 269 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 270 {
 271   const aarch64_field *field = &fields[kind];
 272   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 273     return 0;
 274   ret->lsb = field->lsb + lsb_rel;
 275   ret->width = width;
 276   return 1;
 277 }
 278
 279 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 280    of the opcode.  */
 281
 282 static inline void
 283 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 284                 aarch64_insn value, aarch64_insn mask)
 285 {
 286   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 287           && field->lsb + field->width <= 32);
 288   value &= gen_mask (field->width);
 289   value <<= field->lsb;
 290   /* In some opcodes, field can be part of the base opcode, e.g. the size
 291      field in FADD.  The following helps avoid corrupt the base opcode.  */
 292   value &= ~mask;
 293   *code |= value;
 294 }
 295
 296 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 297    mask of the opcode.  */
 298
 299 static inline aarch64_insn
 300 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 301                  aarch64_insn mask)
 302 {
 303   aarch64_insn value;
 304   /* Clear any bit that is a part of the base opcode.  */
 305   code &= ~mask;
 306   value = (code >> field->lsb) & gen_mask (field->width);
 307   return value;
 308 }
 309
 310 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 311    of the opcode.  */
 312
 313 static inline void
 314 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 315               aarch64_insn value, aarch64_insn mask)
 316 {
 317   insert_field_2 (&fields[kind], code, value, mask);
 318 }
 319
 320 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 321    base mask of the opcode.  */
 322
 323 static inline aarch64_insn
 324 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 325                aarch64_insn mask)
 326 {
 327   return extract_field_2 (&fields[kind], code, mask);
 328 }
 329 \f
 330 /* Inline functions selecting operand to do the encoding/decoding for a
 331    certain instruction bit-field.  */
 332
 333 /* Select the operand to do the encoding/decoding of the 'sf' field.
 334    The heuristic-based rule is that the result operand is respected more.  */
 335
 336 static inline int
 337 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 338 {
 339   int idx = -1;
 340   if (aarch64_get_operand_class (opcode->operands[0])
 341       == AARCH64_OPND_CLASS_INT_REG)
 342     /* normal case.  */
 343     idx = 0;
 344   else if (aarch64_get_operand_class (opcode->operands[1])
 345            == AARCH64_OPND_CLASS_INT_REG)
 346     /* e.g. float2fix.  */
 347     idx = 1;
 348   else
 349     { assert (0); abort (); }
 350   return idx;
 351 }
 352
 353 /* Select the operand to do the encoding/decoding of the 'type' field in
 354    the floating-point instructions.
 355    The heuristic-based rule is that the source operand is respected more.  */
 356
 357 static inline int
 358 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 359 {
 360   int idx;
 361   if (aarch64_get_operand_class (opcode->operands[1])
 362       == AARCH64_OPND_CLASS_FP_REG)
 363     /* normal case.  */
 364     idx = 1;
 365   else if (aarch64_get_operand_class (opcode->operands[0])
 366            == AARCH64_OPND_CLASS_FP_REG)
 367     /* e.g. float2fix.  */
 368     idx = 0;
 369   else
 370     { assert (0); abort (); }
 371   return idx;
 372 }
 373
 374 /* Select the operand to do the encoding/decoding of the 'size' field in
 375    the AdvSIMD scalar instructions.
 376    The heuristic-based rule is that the destination operand is respected
 377    more.  */
 378
 379 static inline int
 380 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 381 {
 382   int src_size = 0, dst_size = 0;
 383   if (aarch64_get_operand_class (opcode->operands[0])
 384       == AARCH64_OPND_CLASS_SISD_REG)
 385     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 386   if (aarch64_get_operand_class (opcode->operands[1])
 387       == AARCH64_OPND_CLASS_SISD_REG)
 388     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 389   if (src_size == dst_size && src_size == 0)
 390     { assert (0); abort (); }
 391   /* When the result is not a sisd register or it is a long operantion.  */
 392   if (dst_size == 0 || dst_size == src_size << 1)
 393     return 1;
 394   else
 395     return 0;
 396 }
 397
 398 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 399    the AdvSIMD instructions.  */
 400
 401 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 402 \f
 403 /* Miscellaneous.  */
 404
 405 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 406 enum aarch64_modifier_kind
 407 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 408
 409
 410 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
 411 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 412 int aarch64_shrink_expanded_imm8 (uint64_t);
 413
 414 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 415 static inline void
 416 copy_operand_info (aarch64_inst *inst, int dst, int src)
 417 {
 418   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 419           && src < AARCH64_MAX_OPND_NUM);
 420   memcpy (&inst->operands[dst], &inst->operands[src],
 421           sizeof (aarch64_opnd_info));
 422   inst->operands[dst].idx = dst;
 423 }
 424
 425 /* A primitive log caculator.  */
 426
 427 static inline unsigned int
 428 get_logsz (unsigned int size)
 429 {
 430   const unsigned char ls[16] =
 431     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 432   if (size > 16)
 433     {
 434       assert (0);
 435       return -1;
 436     }
 437   assert (ls[size - 1] != (unsigned char)-1);
 438   return ls[size - 1];
 439 }
 440
 441 #endif /* OPCODES_AARCH64_OPC_H */