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[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "bfd.h"
25 #include "opcode/arc.h"
26 #include "opintl.h"
27 #include "libiberty.h"
28
29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. Support for this target is available when binutils is
31 configured and built for the 'arc*-mellanox-*-*' target. As far as
32 possible all ARC NPS400 features are built into all ARC target builds as
33 this reduces the chances that regressions might creep in. */
34
35 /* Insert RB register into a 32-bit opcode. */
36 static unsigned
37 insert_rb (unsigned insn,
38 int value,
39 const char **errmsg ATTRIBUTE_UNUSED)
40 {
41 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
42 }
43
44 static int
45 extract_rb (unsigned insn ATTRIBUTE_UNUSED,
46 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47 {
48 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
49
50 if (value == 0x3e && invalid)
51 *invalid = TRUE; /* A limm operand, it should be extracted in a
52 different way. */
53
54 return value;
55 }
56
57 static unsigned
58 insert_rad (unsigned insn,
59 int value,
60 const char **errmsg ATTRIBUTE_UNUSED)
61 {
62 if (value & 0x01)
63 *errmsg = _("Improper register value.");
64
65 return insn | (value & 0x3F);
66 }
67
68 static unsigned
69 insert_rcd (unsigned insn,
70 int value,
71 const char **errmsg ATTRIBUTE_UNUSED)
72 {
73 if (value & 0x01)
74 *errmsg = _("Improper register value.");
75
76 return insn | ((value & 0x3F) << 6);
77 }
78
79 /* Dummy insert ZERO operand function. */
80
81 static unsigned
82 insert_za (unsigned insn,
83 int value,
84 const char **errmsg)
85 {
86 if (value)
87 *errmsg = _("operand is not zero");
88 return insn;
89 }
90
91 /* Insert Y-bit in bbit/br instructions. This function is called only
92 when solving fixups. */
93
94 static unsigned
95 insert_Ybit (unsigned insn,
96 int value,
97 const char **errmsg ATTRIBUTE_UNUSED)
98 {
99 if (value > 0)
100 insn |= 0x08;
101
102 return insn;
103 }
104
105 /* Insert Y-bit in bbit/br instructions. This function is called only
106 when solving fixups. */
107
108 static unsigned
109 insert_NYbit (unsigned insn,
110 int value,
111 const char **errmsg ATTRIBUTE_UNUSED)
112 {
113 if (value < 0)
114 insn |= 0x08;
115
116 return insn;
117 }
118
119 /* Insert H register into a 16-bit opcode. */
120
121 static unsigned
122 insert_rhv1 (unsigned insn,
123 int value,
124 const char **errmsg ATTRIBUTE_UNUSED)
125 {
126 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
127 }
128
129 static int
130 extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
131 bfd_boolean * invalid ATTRIBUTE_UNUSED)
132 {
133 int value = 0;
134
135 return value;
136 }
137
138 /* Insert H register into a 16-bit opcode. */
139
140 static unsigned
141 insert_rhv2 (unsigned insn,
142 int value,
143 const char **errmsg)
144 {
145 if (value == 0x1E)
146 *errmsg =
147 _("Register R30 is a limm indicator for this type of instruction.");
148 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
149 }
150
151 static int
152 extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
153 bfd_boolean * invalid ATTRIBUTE_UNUSED)
154 {
155 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
156
157 return value;
158 }
159
160 static unsigned
161 insert_r0 (unsigned insn,
162 int value,
163 const char **errmsg ATTRIBUTE_UNUSED)
164 {
165 if (value != 0)
166 *errmsg = _("Register must be R0.");
167 return insn;
168 }
169
170 static int
171 extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
172 bfd_boolean * invalid ATTRIBUTE_UNUSED)
173 {
174 return 0;
175 }
176
177
178 static unsigned
179 insert_r1 (unsigned insn,
180 int value,
181 const char **errmsg ATTRIBUTE_UNUSED)
182 {
183 if (value != 1)
184 *errmsg = _("Register must be R1.");
185 return insn;
186 }
187
188 static int
189 extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
190 bfd_boolean * invalid ATTRIBUTE_UNUSED)
191 {
192 return 1;
193 }
194
195 static unsigned
196 insert_r2 (unsigned insn,
197 int value,
198 const char **errmsg ATTRIBUTE_UNUSED)
199 {
200 if (value != 2)
201 *errmsg = _("Register must be R2.");
202 return insn;
203 }
204
205 static int
206 extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
207 bfd_boolean * invalid ATTRIBUTE_UNUSED)
208 {
209 return 2;
210 }
211
212 static unsigned
213 insert_r3 (unsigned insn,
214 int value,
215 const char **errmsg ATTRIBUTE_UNUSED)
216 {
217 if (value != 3)
218 *errmsg = _("Register must be R3.");
219 return insn;
220 }
221
222 static int
223 extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
224 bfd_boolean * invalid ATTRIBUTE_UNUSED)
225 {
226 return 3;
227 }
228
229 static unsigned
230 insert_sp (unsigned insn,
231 int value,
232 const char **errmsg ATTRIBUTE_UNUSED)
233 {
234 if (value != 28)
235 *errmsg = _("Register must be SP.");
236 return insn;
237 }
238
239 static int
240 extract_sp (unsigned insn ATTRIBUTE_UNUSED,
241 bfd_boolean * invalid ATTRIBUTE_UNUSED)
242 {
243 return 28;
244 }
245
246 static unsigned
247 insert_gp (unsigned insn,
248 int value,
249 const char **errmsg ATTRIBUTE_UNUSED)
250 {
251 if (value != 26)
252 *errmsg = _("Register must be GP.");
253 return insn;
254 }
255
256 static int
257 extract_gp (unsigned insn ATTRIBUTE_UNUSED,
258 bfd_boolean * invalid ATTRIBUTE_UNUSED)
259 {
260 return 26;
261 }
262
263 static unsigned
264 insert_pcl (unsigned insn,
265 int value,
266 const char **errmsg ATTRIBUTE_UNUSED)
267 {
268 if (value != 63)
269 *errmsg = _("Register must be PCL.");
270 return insn;
271 }
272
273 static int
274 extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
275 bfd_boolean * invalid ATTRIBUTE_UNUSED)
276 {
277 return 63;
278 }
279
280 static unsigned
281 insert_blink (unsigned insn,
282 int value,
283 const char **errmsg ATTRIBUTE_UNUSED)
284 {
285 if (value != 31)
286 *errmsg = _("Register must be BLINK.");
287 return insn;
288 }
289
290 static int
291 extract_blink (unsigned insn ATTRIBUTE_UNUSED,
292 bfd_boolean * invalid ATTRIBUTE_UNUSED)
293 {
294 return 31;
295 }
296
297 static unsigned
298 insert_ilink1 (unsigned insn,
299 int value,
300 const char **errmsg ATTRIBUTE_UNUSED)
301 {
302 if (value != 29)
303 *errmsg = _("Register must be ILINK1.");
304 return insn;
305 }
306
307 static int
308 extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
309 bfd_boolean * invalid ATTRIBUTE_UNUSED)
310 {
311 return 29;
312 }
313
314 static unsigned
315 insert_ilink2 (unsigned insn,
316 int value,
317 const char **errmsg ATTRIBUTE_UNUSED)
318 {
319 if (value != 30)
320 *errmsg = _("Register must be ILINK2.");
321 return insn;
322 }
323
324 static int
325 extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
326 bfd_boolean * invalid ATTRIBUTE_UNUSED)
327 {
328 return 30;
329 }
330
331 static unsigned
332 insert_ras (unsigned insn,
333 int value,
334 const char **errmsg ATTRIBUTE_UNUSED)
335 {
336 switch (value)
337 {
338 case 0:
339 case 1:
340 case 2:
341 case 3:
342 insn |= value;
343 break;
344 case 12:
345 case 13:
346 case 14:
347 case 15:
348 insn |= (value - 8);
349 break;
350 default:
351 *errmsg = _("Register must be either r0-r3 or r12-r15.");
352 break;
353 }
354 return insn;
355 }
356
357 static int
358 extract_ras (unsigned insn ATTRIBUTE_UNUSED,
359 bfd_boolean * invalid ATTRIBUTE_UNUSED)
360 {
361 int value = insn & 0x07;
362 if (value > 3)
363 return (value + 8);
364 else
365 return value;
366 }
367
368 static unsigned
369 insert_rbs (unsigned insn,
370 int value,
371 const char **errmsg ATTRIBUTE_UNUSED)
372 {
373 switch (value)
374 {
375 case 0:
376 case 1:
377 case 2:
378 case 3:
379 insn |= value << 8;
380 break;
381 case 12:
382 case 13:
383 case 14:
384 case 15:
385 insn |= ((value - 8)) << 8;
386 break;
387 default:
388 *errmsg = _("Register must be either r0-r3 or r12-r15.");
389 break;
390 }
391 return insn;
392 }
393
394 static int
395 extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
396 bfd_boolean * invalid ATTRIBUTE_UNUSED)
397 {
398 int value = (insn >> 8) & 0x07;
399 if (value > 3)
400 return (value + 8);
401 else
402 return value;
403 }
404
405 static unsigned
406 insert_rcs (unsigned insn,
407 int value,
408 const char **errmsg ATTRIBUTE_UNUSED)
409 {
410 switch (value)
411 {
412 case 0:
413 case 1:
414 case 2:
415 case 3:
416 insn |= value << 5;
417 break;
418 case 12:
419 case 13:
420 case 14:
421 case 15:
422 insn |= ((value - 8)) << 5;
423 break;
424 default:
425 *errmsg = _("Register must be either r0-r3 or r12-r15.");
426 break;
427 }
428 return insn;
429 }
430
431 static int
432 extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
433 bfd_boolean * invalid ATTRIBUTE_UNUSED)
434 {
435 int value = (insn >> 5) & 0x07;
436 if (value > 3)
437 return (value + 8);
438 else
439 return value;
440 }
441
442 static unsigned
443 insert_simm3s (unsigned insn,
444 int value,
445 const char **errmsg ATTRIBUTE_UNUSED)
446 {
447 int tmp = 0;
448 switch (value)
449 {
450 case -1:
451 tmp = 0x07;
452 break;
453 case 0:
454 tmp = 0x00;
455 break;
456 case 1:
457 tmp = 0x01;
458 break;
459 case 2:
460 tmp = 0x02;
461 break;
462 case 3:
463 tmp = 0x03;
464 break;
465 case 4:
466 tmp = 0x04;
467 break;
468 case 5:
469 tmp = 0x05;
470 break;
471 case 6:
472 tmp = 0x06;
473 break;
474 default:
475 *errmsg = _("Accepted values are from -1 to 6.");
476 break;
477 }
478
479 insn |= tmp << 8;
480 return insn;
481 }
482
483 static int
484 extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
485 bfd_boolean * invalid ATTRIBUTE_UNUSED)
486 {
487 int value = (insn >> 8) & 0x07;
488 if (value == 7)
489 return -1;
490 else
491 return value;
492 }
493
494 static unsigned
495 insert_rrange (unsigned insn,
496 int value,
497 const char **errmsg ATTRIBUTE_UNUSED)
498 {
499 int reg1 = (value >> 16) & 0xFFFF;
500 int reg2 = value & 0xFFFF;
501 if (reg1 != 13)
502 {
503 *errmsg = _("First register of the range should be r13.");
504 return insn;
505 }
506 if (reg2 < 13 || reg2 > 26)
507 {
508 *errmsg = _("Last register of the range doesn't fit.");
509 return insn;
510 }
511 insn |= ((reg2 - 12) & 0x0F) << 1;
512 return insn;
513 }
514
515 static int
516 extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
517 bfd_boolean * invalid ATTRIBUTE_UNUSED)
518 {
519 return (insn >> 1) & 0x0F;
520 }
521
522 static unsigned
523 insert_fpel (unsigned insn,
524 int value,
525 const char **errmsg ATTRIBUTE_UNUSED)
526 {
527 if (value != 27)
528 {
529 *errmsg = _("Invalid register number, should be fp.");
530 return insn;
531 }
532
533 insn |= 0x0100;
534 return insn;
535 }
536
537 static int
538 extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
539 bfd_boolean * invalid ATTRIBUTE_UNUSED)
540 {
541 return (insn & 0x0100) ? 27 : -1;
542 }
543
544 static unsigned
545 insert_blinkel (unsigned insn,
546 int value,
547 const char **errmsg ATTRIBUTE_UNUSED)
548 {
549 if (value != 31)
550 {
551 *errmsg = _("Invalid register number, should be blink.");
552 return insn;
553 }
554
555 insn |= 0x0200;
556 return insn;
557 }
558
559 static int
560 extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
561 bfd_boolean * invalid ATTRIBUTE_UNUSED)
562 {
563 return (insn & 0x0200) ? 31 : -1;
564 }
565
566 static unsigned
567 insert_pclel (unsigned insn,
568 int value,
569 const char **errmsg ATTRIBUTE_UNUSED)
570 {
571 if (value != 63)
572 {
573 *errmsg = _("Invalid register number, should be pcl.");
574 return insn;
575 }
576
577 insn |= 0x0400;
578 return insn;
579 }
580
581 static int
582 extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
583 bfd_boolean * invalid ATTRIBUTE_UNUSED)
584 {
585 return (insn & 0x0400) ? 63 : -1;
586 }
587
588 #define INSERT_W6
589 /* mask = 00000000000000000000111111000000
590 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
591 static unsigned
592 insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
593 int value ATTRIBUTE_UNUSED,
594 const char **errmsg ATTRIBUTE_UNUSED)
595 {
596 insn |= ((value >> 0) & 0x003f) << 6;
597
598 return insn;
599 }
600
601 #define EXTRACT_W6
602 /* mask = 00000000000000000000111111000000. */
603 static int
604 extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
605 bfd_boolean * invalid ATTRIBUTE_UNUSED)
606 {
607 unsigned value = 0;
608
609 value |= ((insn >> 6) & 0x003f) << 0;
610
611 return value;
612 }
613
614 #define INSERT_G_S
615 /* mask = 0000011100022000
616 insn = 01000ggghhhGG0HH. */
617 static unsigned
618 insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
619 int value ATTRIBUTE_UNUSED,
620 const char **errmsg ATTRIBUTE_UNUSED)
621 {
622 insn |= ((value >> 0) & 0x0007) << 8;
623 insn |= ((value >> 3) & 0x0003) << 3;
624
625 return insn;
626 }
627
628 #define EXTRACT_G_S
629 /* mask = 0000011100022000. */
630 static int
631 extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
632 bfd_boolean * invalid ATTRIBUTE_UNUSED)
633 {
634 int value = 0;
635
636 value |= ((insn >> 8) & 0x0007) << 0;
637 value |= ((insn >> 3) & 0x0003) << 3;
638
639 /* Extend the sign. */
640 int signbit = 1 << (6 - 1);
641 value = (value ^ signbit) - signbit;
642
643 return value;
644 }
645
646 /* ARC NPS400 Support: See comment near head of file. */
647 static unsigned
648 insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
649 int value ATTRIBUTE_UNUSED,
650 const char **errmsg ATTRIBUTE_UNUSED)
651 {
652 switch (value)
653 {
654 case 0:
655 case 1:
656 case 2:
657 case 3:
658 insn |= value << 24;
659 break;
660 case 12:
661 case 13:
662 case 14:
663 case 15:
664 insn |= (value - 8) << 24;
665 break;
666 default:
667 *errmsg = _("Register must be either r0-r3 or r12-r15.");
668 break;
669 }
670 return insn;
671 }
672
673 static int
674 extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
675 bfd_boolean * invalid ATTRIBUTE_UNUSED)
676 {
677 int value = (insn >> 24) & 0x07;
678 if (value > 3)
679 return (value + 8);
680 else
681 return value;
682 }
683
684 static unsigned
685 insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
686 int value ATTRIBUTE_UNUSED,
687 const char **errmsg ATTRIBUTE_UNUSED)
688 {
689 switch (value)
690 {
691 case 0:
692 case 1:
693 case 2:
694 case 3:
695 insn |= value << 21;
696 break;
697 case 12:
698 case 13:
699 case 14:
700 case 15:
701 insn |= (value - 8) << 21;
702 break;
703 default:
704 *errmsg = _("Register must be either r0-r3 or r12-r15.");
705 break;
706 }
707 return insn;
708 }
709
710 static int
711 extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
712 bfd_boolean * invalid ATTRIBUTE_UNUSED)
713 {
714 int value = (insn >> 21) & 0x07;
715 if (value > 3)
716 return (value + 8);
717 else
718 return value;
719 }
720
721 static unsigned
722 insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
723 int value ATTRIBUTE_UNUSED,
724 const char **errmsg ATTRIBUTE_UNUSED)
725 {
726 switch (value)
727 {
728 case 1:
729 value = 0;
730 break;
731 case 2:
732 value = 1;
733 break;
734 case 4:
735 value = 2;
736 break;
737 case 8:
738 value = 3;
739 break;
740 default:
741 value = 0;
742 *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
743 break;
744 }
745
746 insn |= value << 10;
747 return insn;
748 }
749
750 static int
751 extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
752 bfd_boolean * invalid ATTRIBUTE_UNUSED)
753 {
754 return 1 << ((insn >> 10) & 0x3);
755 }
756
757 static unsigned
758 insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
759 int value ATTRIBUTE_UNUSED,
760 const char **errmsg ATTRIBUTE_UNUSED)
761 {
762 insn |= ((value >> 5) & 7) << 12;
763 insn |= (value & 0x1f);
764 return insn;
765 }
766
767 static int
768 extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
769 bfd_boolean * invalid ATTRIBUTE_UNUSED)
770 {
771 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
772 }
773
774 static unsigned
775 insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
776 int value ATTRIBUTE_UNUSED,
777 const char **errmsg ATTRIBUTE_UNUSED)
778 {
779 switch (value)
780 {
781 case 1:
782 case 2:
783 case 4:
784 break;
785
786 default:
787 *errmsg = _("invalid immediate, must be 1, 2, or 4");
788 value = 0;
789 }
790
791 insn |= (value << 6);
792 return insn;
793 }
794
795 static int
796 extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
797 bfd_boolean * invalid ATTRIBUTE_UNUSED)
798 {
799 return (insn >> 6) & 0x3f;
800 }
801
802 static unsigned
803 insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
804 int value ATTRIBUTE_UNUSED,
805 const char **errmsg ATTRIBUTE_UNUSED)
806 {
807 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
808 return insn;
809 }
810
811 static int
812 extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
813 bfd_boolean * invalid ATTRIBUTE_UNUSED)
814 {
815 return (insn & 0x1f);
816 }
817
818 static unsigned
819 insert_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
820 int value ATTRIBUTE_UNUSED,
821 const char **errmsg ATTRIBUTE_UNUSED)
822 {
823 int top = (value >> 16) & 0xffff;
824 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
825 *errmsg = _("invalid value for CMEM ld/st immediate");
826 insn |= (value & 0xffff);
827 return insn;
828 }
829
830 static int
831 extract_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED,
832 bfd_boolean * invalid ATTRIBUTE_UNUSED)
833 {
834 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
835 }
836
837 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
838 static unsigned \
839 insert_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
840 int value ATTRIBUTE_UNUSED, \
841 const char **errmsg ATTRIBUTE_UNUSED) \
842 { \
843 switch (value) \
844 { \
845 case 0: \
846 case 8: \
847 case 16: \
848 case 24: \
849 value = value / 8; \
850 break; \
851 default: \
852 *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \
853 value = 0; \
854 } \
855 insn |= (value << SHIFT); \
856 return insn; \
857 } \
858 \
859 static int \
860 extract_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \
861 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
862 { \
863 return ((insn >> SHIFT) & 0x3) * 8; \
864 }
865
866 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
867 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
868
869 #define MAKE_SIZE_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
870 static unsigned \
871 insert_nps_##NAME##_size (unsigned insn ATTRIBUTE_UNUSED, \
872 int value ATTRIBUTE_UNUSED, \
873 const char **errmsg ATTRIBUTE_UNUSED) \
874 { \
875 if (value < LOWER || value > 32) \
876 { \
877 *errmsg = _("Invalid size, value must be " \
878 #LOWER " to " #UPPER "."); \
879 return insn; \
880 } \
881 value -= BIAS; \
882 insn |= (value << SHIFT); \
883 return insn; \
884 } \
885 \
886 static int \
887 extract_nps_##NAME##_size (unsigned insn ATTRIBUTE_UNUSED, \
888 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
889 { \
890 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
891 }
892
893 MAKE_SIZE_INSERT_EXTRACT_FUNCS(addb,2,32,5,1,5)
894 MAKE_SIZE_INSERT_EXTRACT_FUNCS(andb,1,32,5,1,5)
895 MAKE_SIZE_INSERT_EXTRACT_FUNCS(fxorb,8,32,5,8,5)
896 MAKE_SIZE_INSERT_EXTRACT_FUNCS(wxorb,16,32,5,16,5)
897 MAKE_SIZE_INSERT_EXTRACT_FUNCS(bitop,1,32,5,1,10)
898 MAKE_SIZE_INSERT_EXTRACT_FUNCS(qcmp,1,8,3,1,9)
899
900 static int
901 extract_nps_qcmp_m3 (unsigned insn ATTRIBUTE_UNUSED,
902 bfd_boolean * invalid ATTRIBUTE_UNUSED)
903 {
904 int m3 = (insn >> 5) & 0xf;
905 if (m3 == 0xf)
906 *invalid = TRUE;
907 return m3;
908 }
909
910 static int
911 extract_nps_qcmp_m2 (unsigned insn ATTRIBUTE_UNUSED,
912 bfd_boolean * invalid ATTRIBUTE_UNUSED)
913 {
914 bfd_boolean tmp_invalid = FALSE;
915 int m2 = (insn >> 15) & 0x1;
916 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
917
918 if (m2 == 0 && m3 == 0xf)
919 *invalid = TRUE;
920 return m2;
921 }
922
923 static int
924 extract_nps_qcmp_m1 (unsigned insn ATTRIBUTE_UNUSED,
925 bfd_boolean * invalid ATTRIBUTE_UNUSED)
926 {
927 bfd_boolean tmp_invalid = FALSE;
928 int m1 = (insn >> 14) & 0x1;
929 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
930 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
931
932 if (m1 == 0 && m2 == 0 && m3 == 0xf)
933 *invalid = TRUE;
934 return m1;
935 }
936
937 static unsigned
938 insert_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
939 int value ATTRIBUTE_UNUSED,
940 const char **errmsg ATTRIBUTE_UNUSED)
941 {
942 unsigned pwr;
943
944 if (value < 1 || value > 256)
945 {
946 *errmsg = _("value out of range 1 - 256");
947 return 0;
948 }
949
950 for (pwr = 0; (value & 1) == 0; value >>= 1)
951 ++pwr;
952
953 if (value != 1)
954 {
955 *errmsg = _("value must be power of 2");
956 return 0;
957 }
958
959 return insn | (pwr << 8);
960 }
961
962 static int
963 extract_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED,
964 bfd_boolean * invalid ATTRIBUTE_UNUSED)
965 {
966 unsigned entry_size = (insn >> 8) & 0xf;
967 return 1 << entry_size;
968 }
969
970 /* Include the generic extract/insert functions. Order is important
971 as some of the functions present in the .h may be disabled via
972 defines. */
973 #include "arc-fxi.h"
974
975 /* The flag operands table.
976
977 The format of the table is
978 NAME CODE BITS SHIFT FAVAIL. */
979 const struct arc_flag_operand arc_flag_operands[] =
980 {
981 #define F_NULL 0
982 { 0, 0, 0, 0, 0},
983 #define F_ALWAYS (F_NULL + 1)
984 { "al", 0, 0, 0, 0 },
985 #define F_RA (F_ALWAYS + 1)
986 { "ra", 0, 0, 0, 0 },
987 #define F_EQUAL (F_RA + 1)
988 { "eq", 1, 5, 0, 1 },
989 #define F_ZERO (F_EQUAL + 1)
990 { "z", 1, 5, 0, 0 },
991 #define F_NOTEQUAL (F_ZERO + 1)
992 { "ne", 2, 5, 0, 1 },
993 #define F_NOTZERO (F_NOTEQUAL + 1)
994 { "nz", 2, 5, 0, 0 },
995 #define F_POZITIVE (F_NOTZERO + 1)
996 { "p", 3, 5, 0, 1 },
997 #define F_PL (F_POZITIVE + 1)
998 { "pl", 3, 5, 0, 0 },
999 #define F_NEGATIVE (F_PL + 1)
1000 { "n", 4, 5, 0, 1 },
1001 #define F_MINUS (F_NEGATIVE + 1)
1002 { "mi", 4, 5, 0, 0 },
1003 #define F_CARRY (F_MINUS + 1)
1004 { "c", 5, 5, 0, 1 },
1005 #define F_CARRYSET (F_CARRY + 1)
1006 { "cs", 5, 5, 0, 0 },
1007 #define F_LOWER (F_CARRYSET + 1)
1008 { "lo", 5, 5, 0, 0 },
1009 #define F_CARRYCLR (F_LOWER + 1)
1010 { "cc", 6, 5, 0, 0 },
1011 #define F_NOTCARRY (F_CARRYCLR + 1)
1012 { "nc", 6, 5, 0, 1 },
1013 #define F_HIGHER (F_NOTCARRY + 1)
1014 { "hs", 6, 5, 0, 0 },
1015 #define F_OVERFLOWSET (F_HIGHER + 1)
1016 { "vs", 7, 5, 0, 0 },
1017 #define F_OVERFLOW (F_OVERFLOWSET + 1)
1018 { "v", 7, 5, 0, 1 },
1019 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
1020 { "nv", 8, 5, 0, 1 },
1021 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1022 { "vc", 8, 5, 0, 0 },
1023 #define F_GT (F_OVERFLOWCLR + 1)
1024 { "gt", 9, 5, 0, 1 },
1025 #define F_GE (F_GT + 1)
1026 { "ge", 10, 5, 0, 1 },
1027 #define F_LT (F_GE + 1)
1028 { "lt", 11, 5, 0, 1 },
1029 #define F_LE (F_LT + 1)
1030 { "le", 12, 5, 0, 1 },
1031 #define F_HI (F_LE + 1)
1032 { "hi", 13, 5, 0, 1 },
1033 #define F_LS (F_HI + 1)
1034 { "ls", 14, 5, 0, 1 },
1035 #define F_PNZ (F_LS + 1)
1036 { "pnz", 15, 5, 0, 1 },
1037
1038 /* FLAG. */
1039 #define F_FLAG (F_PNZ + 1)
1040 { "f", 1, 1, 15, 1 },
1041 #define F_FFAKE (F_FLAG + 1)
1042 { "f", 0, 0, 0, 1 },
1043
1044 /* Delay slot. */
1045 #define F_ND (F_FFAKE + 1)
1046 { "nd", 0, 1, 5, 0 },
1047 #define F_D (F_ND + 1)
1048 { "d", 1, 1, 5, 1 },
1049 #define F_DFAKE (F_D + 1)
1050 { "d", 0, 0, 0, 1 },
1051
1052 /* Data size. */
1053 #define F_SIZEB1 (F_DFAKE + 1)
1054 { "b", 1, 2, 1, 1 },
1055 #define F_SIZEB7 (F_SIZEB1 + 1)
1056 { "b", 1, 2, 7, 1 },
1057 #define F_SIZEB17 (F_SIZEB7 + 1)
1058 { "b", 1, 2, 17, 1 },
1059 #define F_SIZEW1 (F_SIZEB17 + 1)
1060 { "w", 2, 2, 1, 0 },
1061 #define F_SIZEW7 (F_SIZEW1 + 1)
1062 { "w", 2, 2, 7, 0 },
1063 #define F_SIZEW17 (F_SIZEW7 + 1)
1064 { "w", 2, 2, 17, 0 },
1065
1066 /* Sign extension. */
1067 #define F_SIGN6 (F_SIZEW17 + 1)
1068 { "x", 1, 1, 6, 1 },
1069 #define F_SIGN16 (F_SIGN6 + 1)
1070 { "x", 1, 1, 16, 1 },
1071 #define F_SIGNX (F_SIGN16 + 1)
1072 { "x", 0, 0, 0, 1 },
1073
1074 /* Address write-back modes. */
1075 #define F_A3 (F_SIGNX + 1)
1076 { "a", 1, 2, 3, 0 },
1077 #define F_A9 (F_A3 + 1)
1078 { "a", 1, 2, 9, 0 },
1079 #define F_A22 (F_A9 + 1)
1080 { "a", 1, 2, 22, 0 },
1081 #define F_AW3 (F_A22 + 1)
1082 { "aw", 1, 2, 3, 1 },
1083 #define F_AW9 (F_AW3 + 1)
1084 { "aw", 1, 2, 9, 1 },
1085 #define F_AW22 (F_AW9 + 1)
1086 { "aw", 1, 2, 22, 1 },
1087 #define F_AB3 (F_AW22 + 1)
1088 { "ab", 2, 2, 3, 1 },
1089 #define F_AB9 (F_AB3 + 1)
1090 { "ab", 2, 2, 9, 1 },
1091 #define F_AB22 (F_AB9 + 1)
1092 { "ab", 2, 2, 22, 1 },
1093 #define F_AS3 (F_AB22 + 1)
1094 { "as", 3, 2, 3, 1 },
1095 #define F_AS9 (F_AS3 + 1)
1096 { "as", 3, 2, 9, 1 },
1097 #define F_AS22 (F_AS9 + 1)
1098 { "as", 3, 2, 22, 1 },
1099 #define F_ASFAKE (F_AS22 + 1)
1100 { "as", 0, 0, 0, 1 },
1101
1102 /* Cache bypass. */
1103 #define F_DI5 (F_ASFAKE + 1)
1104 { "di", 1, 1, 5, 1 },
1105 #define F_DI11 (F_DI5 + 1)
1106 { "di", 1, 1, 11, 1 },
1107 #define F_DI15 (F_DI11 + 1)
1108 { "di", 1, 1, 15, 1 },
1109
1110 /* ARCv2 specific. */
1111 #define F_NT (F_DI15 + 1)
1112 { "nt", 0, 1, 3, 1},
1113 #define F_T (F_NT + 1)
1114 { "t", 1, 1, 3, 1},
1115 #define F_H1 (F_T + 1)
1116 { "h", 2, 2, 1, 1 },
1117 #define F_H7 (F_H1 + 1)
1118 { "h", 2, 2, 7, 1 },
1119 #define F_H17 (F_H7 + 1)
1120 { "h", 2, 2, 17, 1 },
1121
1122 /* Fake Flags. */
1123 #define F_NE (F_H17 + 1)
1124 { "ne", 0, 0, 0, 1 },
1125
1126 /* ARC NPS400 Support: See comment near head of file. */
1127 #define F_NPS_CL (F_NE + 1)
1128 { "cl", 0, 0, 0, 1 },
1129
1130 #define F_NPS_FLAG (F_NPS_CL + 1)
1131 { "f", 1, 1, 20, 1 },
1132
1133 #define F_NPS_R (F_NPS_FLAG + 1)
1134 { "r", 1, 1, 15, 1 },
1135
1136 #define F_NPS_RW (F_NPS_R + 1)
1137 { "rw", 0, 1, 7, 1 },
1138
1139 #define F_NPS_RD (F_NPS_RW + 1)
1140 { "rd", 1, 1, 7, 1 },
1141
1142 #define F_NPS_WFT (F_NPS_RD + 1)
1143 { "wft", 0, 0, 0, 1 },
1144
1145 #define F_NPS_IE1 (F_NPS_WFT + 1)
1146 { "ie1", 1, 2, 8, 1 },
1147
1148 #define F_NPS_IE2 (F_NPS_IE1 + 1)
1149 { "ie2", 2, 2, 8, 1 },
1150
1151 #define F_NPS_IE12 (F_NPS_IE2 + 1)
1152 { "ie12", 3, 2, 8, 1 },
1153
1154 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1155 { "rd", 0, 1, 6, 1 },
1156
1157 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1158 { "wr", 1, 1, 6, 1 },
1159
1160 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1161 { "off", 0, 0, 0, 1 },
1162
1163 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1164 { "restore", 0, 0, 0, 1 },
1165
1166 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1167 { "sx", 1, 1, 14, 1 },
1168
1169 #define F_NPS_AR (F_NPS_SX + 1)
1170 { "ar", 0, 1, 0, 1 },
1171
1172 #define F_NPS_AL (F_NPS_AR + 1)
1173 { "al", 1, 1, 0, 1 },
1174 };
1175
1176 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
1177
1178 /* Table of the flag classes.
1179
1180 The format of the table is
1181 CLASS {FLAG_CODE}. */
1182 const struct arc_flag_class arc_flag_classes[] =
1183 {
1184 #define C_EMPTY 0
1185 { F_CLASS_NONE, { F_NULL } },
1186
1187 #define C_CC (C_EMPTY + 1)
1188 { F_CLASS_OPTIONAL | F_CLASS_EXTEND,
1189 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1190 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1191 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1192 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1193 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1194 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1195
1196 #define C_AA_ADDR3 (C_CC + 1)
1197 #define C_AA27 (C_CC + 1)
1198 { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1199 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1200 #define C_AA21 (C_AA_ADDR3 + 1)
1201 { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1202 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1203 #define C_AA8 (C_AA_ADDR9 + 1)
1204 { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1205
1206 #define C_F (C_AA_ADDR22 + 1)
1207 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
1208 #define C_FHARD (C_F + 1)
1209 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
1210
1211 #define C_T (C_FHARD + 1)
1212 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
1213 #define C_D (C_T + 1)
1214 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
1215
1216 #define C_DHARD (C_D + 1)
1217 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
1218
1219 #define C_DI20 (C_DHARD + 1)
1220 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
1221 #define C_DI16 (C_DI20 + 1)
1222 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
1223 #define C_DI26 (C_DI16 + 1)
1224 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
1225
1226 #define C_X25 (C_DI26 + 1)
1227 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
1228 #define C_X15 (C_X25 + 1)
1229 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
1230 #define C_XHARD (C_X15 + 1)
1231 #define C_X (C_X15 + 1)
1232 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
1233
1234 #define C_ZZ13 (C_X + 1)
1235 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
1236 #define C_ZZ23 (C_ZZ13 + 1)
1237 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
1238 #define C_ZZ29 (C_ZZ23 + 1)
1239 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
1240
1241 #define C_AS (C_ZZ29 + 1)
1242 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
1243
1244 #define C_NE (C_AS + 1)
1245 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
1246
1247 /* ARC NPS400 Support: See comment near head of file. */
1248 #define C_NPS_CL (C_NE + 1)
1249 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1250
1251 #define C_NPS_F (C_NPS_CL + 1)
1252 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
1253
1254 #define C_NPS_R (C_NPS_F + 1)
1255 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
1256
1257 #define C_NPS_SCHD_RW (C_NPS_R + 1)
1258 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1259
1260 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1261 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1262
1263 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1264 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1265
1266 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1267 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1268
1269 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1270 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1271
1272 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1273 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1274
1275 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1276 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1277
1278 #define C_NPS_AR_AL (C_NPS_SX + 1)
1279 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
1280 };
1281
1282 const unsigned char flags_none[] = { 0 };
1283 const unsigned char flags_f[] = { C_F };
1284 const unsigned char flags_cc[] = { C_CC };
1285 const unsigned char flags_ccf[] = { C_CC, C_F };
1286
1287 /* The operands table.
1288
1289 The format of the operands table is:
1290
1291 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1292 const struct arc_operand arc_operands[] =
1293 {
1294 /* The fields are bits, shift, insert, extract, flags. The zero
1295 index is used to indicate end-of-list. */
1296 #define UNUSED 0
1297 { 0, 0, 0, 0, 0, 0 },
1298 /* The plain integer register fields. Used by 32 bit
1299 instructions. */
1300 #define RA (UNUSED + 1)
1301 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1302 #define RB (RA + 1)
1303 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1304 #define RC (RB + 1)
1305 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1306 #define RBdup (RC + 1)
1307 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1308
1309 #define RAD (RBdup + 1)
1310 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1311 #define RCD (RAD + 1)
1312 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1313
1314 /* The plain integer register fields. Used by short
1315 instructions. */
1316 #define RA16 (RCD + 1)
1317 #define RA_S (RCD + 1)
1318 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1319 #define RB16 (RA16 + 1)
1320 #define RB_S (RA16 + 1)
1321 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1322 #define RB16dup (RB16 + 1)
1323 #define RB_Sdup (RB16 + 1)
1324 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1325 #define RC16 (RB16dup + 1)
1326 #define RC_S (RB16dup + 1)
1327 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1328 #define R6H (RC16 + 1) /* 6bit register field 'h' used
1329 by V1 cpus. */
1330 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1331 #define R5H (R6H + 1) /* 5bit register field 'h' used
1332 by V2 cpus. */
1333 #define RH_S (R6H + 1) /* 5bit register field 'h' used
1334 by V2 cpus. */
1335 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1336 #define R5Hdup (R5H + 1)
1337 #define RH_Sdup (R5H + 1)
1338 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1339 insert_rhv2, extract_rhv2 },
1340
1341 #define RG (R5Hdup + 1)
1342 #define G_S (R5Hdup + 1)
1343 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1344
1345 /* Fix registers. */
1346 #define R0 (RG + 1)
1347 #define R0_S (RG + 1)
1348 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1349 #define R1 (R0 + 1)
1350 #define R1_S (R0 + 1)
1351 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1352 #define R2 (R1 + 1)
1353 #define R2_S (R1 + 1)
1354 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1355 #define R3 (R2 + 1)
1356 #define R3_S (R2 + 1)
1357 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1358 #define RSP (R3 + 1)
1359 #define SP_S (R3 + 1)
1360 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1361 #define SPdup (RSP + 1)
1362 #define SP_Sdup (RSP + 1)
1363 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1364 #define GP (SPdup + 1)
1365 #define GP_S (SPdup + 1)
1366 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1367
1368 #define PCL_S (GP + 1)
1369 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1370
1371 #define BLINK (PCL_S + 1)
1372 #define BLINK_S (PCL_S + 1)
1373 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1374
1375 #define ILINK1 (BLINK + 1)
1376 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1377 #define ILINK2 (ILINK1 + 1)
1378 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1379
1380 /* Long immediate. */
1381 #define LIMM (ILINK2 + 1)
1382 #define LIMM_S (ILINK2 + 1)
1383 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1384 #define LIMMdup (LIMM + 1)
1385 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1386
1387 /* Special operands. */
1388 #define ZA (LIMMdup + 1)
1389 #define ZB (LIMMdup + 1)
1390 #define ZA_S (LIMMdup + 1)
1391 #define ZB_S (LIMMdup + 1)
1392 #define ZC_S (LIMMdup + 1)
1393 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1394
1395 #define RRANGE_EL (ZA + 1)
1396 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1397 insert_rrange, extract_rrange},
1398 #define FP_EL (RRANGE_EL + 1)
1399 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1400 insert_fpel, extract_fpel },
1401 #define BLINK_EL (FP_EL + 1)
1402 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1403 insert_blinkel, extract_blinkel },
1404 #define PCL_EL (BLINK_EL + 1)
1405 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1406 insert_pclel, extract_pclel },
1407
1408 /* Fake operand to handle the T flag. */
1409 #define BRAKET (PCL_EL + 1)
1410 #define BRAKETdup (PCL_EL + 1)
1411 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1412
1413 /* Fake operand to handle the T flag. */
1414 #define FKT_T (BRAKET + 1)
1415 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1416 /* Fake operand to handle the T flag. */
1417 #define FKT_NT (FKT_T + 1)
1418 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1419
1420 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1421 #define UIMM6_20 (FKT_NT + 1)
1422 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1423
1424 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1425 #define SIMM12_20 (UIMM6_20 + 1)
1426 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1427
1428 /* SIMM3_5_S mask = 0000011100000000. */
1429 #define SIMM3_5_S (SIMM12_20 + 1)
1430 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1431 insert_simm3s, extract_simm3s},
1432
1433 /* UIMM7_A32_11_S mask = 0000000000011111. */
1434 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1435 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1436 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1437 extract_uimm7_a32_11_s},
1438
1439 /* UIMM7_9_S mask = 0000000001111111. */
1440 #define UIMM7_9_S (UIMM7_A32_11_S + 1)
1441 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1442
1443 /* UIMM3_13_S mask = 0000000000000111. */
1444 #define UIMM3_13_S (UIMM7_9_S + 1)
1445 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1446
1447 /* SIMM11_A32_7_S mask = 0000000111111111. */
1448 #define SIMM11_A32_7_S (UIMM3_13_S + 1)
1449 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1450 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1451
1452 /* UIMM6_13_S mask = 0000000002220111. */
1453 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1454 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1455 /* UIMM5_11_S mask = 0000000000011111. */
1456 #define UIMM5_11_S (UIMM6_13_S + 1)
1457 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1458 extract_uimm5_11_s},
1459
1460 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1461 #define SIMM9_A16_8 (UIMM5_11_S + 1)
1462 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1463 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1464 extract_simm9_a16_8},
1465
1466 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1467 #define UIMM6_8 (SIMM9_A16_8 + 1)
1468 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1469
1470 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1471 #define SIMM21_A16_5 (UIMM6_8 + 1)
1472 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1473 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1474 insert_simm21_a16_5, extract_simm21_a16_5},
1475
1476 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1477 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1478 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1479 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1480 insert_simm25_a16_5, extract_simm25_a16_5},
1481
1482 /* SIMM10_A16_7_S mask = 0000000111111111. */
1483 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1484 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1485 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1486 extract_simm10_a16_7_s},
1487
1488 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1489 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1490 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1491
1492 /* SIMM7_A16_10_S mask = 0000000000111111. */
1493 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1494 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1495 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1496 extract_simm7_a16_10_s},
1497
1498 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1499 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1500 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1501 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1502 extract_simm21_a32_5},
1503
1504 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1505 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1506 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1507 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1508 extract_simm25_a32_5},
1509
1510 /* SIMM13_A32_5_S mask = 0000011111111111. */
1511 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1512 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1513 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1514 extract_simm13_a32_5_s},
1515
1516 /* SIMM8_A16_9_S mask = 0000000001111111. */
1517 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1518 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1519 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1520 extract_simm8_a16_9_s},
1521
1522 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1523 #define UIMM3_23 (SIMM8_A16_9_S + 1)
1524 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1525
1526 /* UIMM10_6_S mask = 0000001111111111. */
1527 #define UIMM10_6_S (UIMM3_23 + 1)
1528 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1529
1530 /* UIMM6_11_S mask = 0000002200011110. */
1531 #define UIMM6_11_S (UIMM10_6_S + 1)
1532 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1533
1534 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1535 #define SIMM9_8 (UIMM6_11_S + 1)
1536 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1537 insert_simm9_8, extract_simm9_8},
1538
1539 /* UIMM10_A32_8_S mask = 0000000011111111. */
1540 #define UIMM10_A32_8_S (SIMM9_8 + 1)
1541 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1542 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1543 extract_uimm10_a32_8_s},
1544
1545 /* SIMM9_7_S mask = 0000000111111111. */
1546 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
1547 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1548 extract_simm9_7_s},
1549
1550 /* UIMM6_A16_11_S mask = 0000000000011111. */
1551 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
1552 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1553 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1554 extract_uimm6_a16_11_s},
1555
1556 /* UIMM5_A32_11_S mask = 0000020000011000. */
1557 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1558 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1559 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1560 extract_uimm5_a32_11_s},
1561
1562 /* SIMM11_A32_13_S mask = 0000022222200111. */
1563 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1564 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1565 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1566
1567 /* UIMM7_13_S mask = 0000000022220111. */
1568 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
1569 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1570
1571 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1572 #define UIMM6_A16_21 (UIMM7_13_S + 1)
1573 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1574 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1575
1576 /* UIMM7_11_S mask = 0000022200011110. */
1577 #define UIMM7_11_S (UIMM6_A16_21 + 1)
1578 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1579
1580 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1581 #define UIMM7_A16_20 (UIMM7_11_S + 1)
1582 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1583 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1584 extract_uimm7_a16_20},
1585
1586 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1587 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1588 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1589 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1590 extract_simm13_a16_20},
1591
1592 /* UIMM8_8_S mask = 0000000011111111. */
1593 #define UIMM8_8_S (SIMM13_A16_20 + 1)
1594 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1595
1596 /* W6 mask = 00000000000000000000111111000000. */
1597 #define W6 (UIMM8_8_S + 1)
1598 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1599
1600 /* UIMM6_5_S mask = 0000011111100000. */
1601 #define UIMM6_5_S (W6 + 1)
1602 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
1603
1604 /* ARC NPS400 Support: See comment near head of file. */
1605 #define NPS_R_DST_3B (UIMM6_5_S + 1)
1606 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1607
1608 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1609 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
1610
1611 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1612 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
1613
1614 #define NPS_R_DST (NPS_R_SRC2_3B + 1)
1615 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
1616
1617 #define NPS_R_SRC1 (NPS_R_DST + 1)
1618 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
1619
1620 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1621 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1622
1623 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1624 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
1625
1626 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
1627 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
1628
1629 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1630 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
1631
1632 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1633 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
1634
1635 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1636 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
1637
1638 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
1639 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1640
1641 #define NPS_RFLT_UIMM6 (NPS_UIMM16 + 1)
1642 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
1643
1644 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
1645 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
1646
1647 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
1648 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos },
1649
1650 #define NPS_SRC1_POS (NPS_SRC2_POS + 1)
1651 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos },
1652
1653 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
1654 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size },
1655
1656 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
1657 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size },
1658
1659 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
1660 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size },
1661
1662 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
1663 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size },
1664
1665 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
1666 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
1667
1668 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
1669 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
1670
1671 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
1672 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size },
1673
1674 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
1675 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
1676
1677 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
1678 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
1679
1680 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
1681 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
1682
1683 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
1684 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size },
1685 };
1686
1687 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
1688
1689 const unsigned arc_Toperand = FKT_T;
1690 const unsigned arc_NToperand = FKT_NT;
1691
1692 const unsigned char arg_none[] = { 0 };
1693 const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
1694 const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
1695 const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
1696 const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
1697 const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
1698 const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
1699 const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
1700 const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
1701 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
1702 const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
1703 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
1704
1705 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
1706 const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
1707 const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
1708
1709 const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
1710 const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
1711 const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
1712
1713 const unsigned char arg_32bit_rbrc[] = { RB, RC };
1714 const unsigned char arg_32bit_zarc[] = { ZA, RC };
1715 const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
1716 const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
1717 const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
1718 const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
1719
1720 const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
1721 const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
1722 const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
1723 const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
1724
1725 /* The opcode table.
1726
1727 The format of the opcode table is:
1728
1729 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
1730
1731 The table is organised such that, where possible, all instructions with
1732 the same mnemonic are together in a block. When the assembler searches
1733 for a suitable instruction the entries are checked in table order, so
1734 more specific, or specialised cases should appear earlier in the table.
1735
1736 As an example, consider two instructions 'add a,b,u6' and 'add
1737 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
1738 32-bit instruction, while the second takes a 32-bit immediate that is
1739 encoded in a follow-on 32-bit, making the total instruction length
1740 64-bits. In this case the u6 variant must appear first in the table, as
1741 all u6 immediates could also be encoded using the 'limm' extension,
1742 however, we want to use the shorter instruction wherever possible.
1743
1744 It is possible though to split instructions with the same mnemonic into
1745 multiple groups. However, the instructions are still checked in table
1746 order, even across groups. The only time that instructions with the
1747 same mnemonic should be split into different groups is when different
1748 variants of the instruction appear in different architectures, in which
1749 case, grouping all instructions from a particular architecture together
1750 might be preferable to merging the instruction into the main instruction
1751 table.
1752
1753 An example of this split instruction groups can be found with the 'sync'
1754 instruction. The core arc architecture provides a 'sync' instruction,
1755 while the nps instruction set extension provides 'sync.rd' and
1756 'sync.wr'. The rd/wr flags are instruction flags, not part of the
1757 mnemonic, so we end up with two groups for the sync instruction, the
1758 first within the core arc instruction table, and the second within the
1759 nps extension instructions. */
1760 const struct arc_opcode arc_opcodes[] =
1761 {
1762 #include "arc-tbl.h"
1763 #include "arc-nps400-tbl.h"
1764 #include "arc-ext-tbl.h"
1765
1766 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
1767 };
1768
1769 /* List with special cases instructions and the applicable flags. */
1770 const struct arc_flag_special arc_flag_special_cases[] =
1771 {
1772 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1773 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1774 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1775 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1776 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1777 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1778 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1779 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1780 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1781 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1782 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1783 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1784 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1785 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1786 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1787 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1788 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1789 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1790 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1791 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1792 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1793 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1794 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1795 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1796 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1797 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1798 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1799 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1800 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
1801 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
1802 };
1803
1804 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
1805
1806 /* Relocations. */
1807 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
1808 {
1809 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
1810 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1811 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
1812 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1813 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
1814 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1815 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
1816 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1817
1818 /* Next two entries will cover the undefined behavior ldb/stb with
1819 address scaling. */
1820 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
1821 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1822 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
1823 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
1824
1825 { "sda", "ld", { F_ASFAKE, F_NULL },
1826 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1827 { "sda", "st", { F_ASFAKE, F_NULL },
1828 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1829 { "sda", "ldd", { F_ASFAKE, F_NULL },
1830 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1831 { "sda", "std", { F_ASFAKE, F_NULL },
1832 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1833
1834 /* Short instructions. */
1835 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
1836 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
1837 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
1838 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
1839
1840 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
1841 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1842
1843 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
1844 BFD_RELOC_ARC_S25H_PCREL_PLT },
1845 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
1846 BFD_RELOC_ARC_S21H_PCREL_PLT },
1847 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
1848 BFD_RELOC_ARC_S25W_PCREL_PLT },
1849 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
1850 BFD_RELOC_ARC_S21W_PCREL_PLT },
1851
1852 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
1853 };
1854
1855 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
1856
1857 const struct arc_pseudo_insn arc_pseudo_insns[] =
1858 {
1859 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1860 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
1861 { BRAKETdup, 1, 0, 4} } },
1862 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1863 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
1864 { BRAKETdup, 1, 0, 4} } },
1865
1866 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1867 { SIMM9_A16_8, 0, 0, 2 } } },
1868 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1869 { SIMM9_A16_8, 0, 0, 2 } } },
1870 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1871 { SIMM9_A16_8, 0, 0, 2 } } },
1872 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1873 { SIMM9_A16_8, 0, 0, 2 } } },
1874 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1875 { SIMM9_A16_8, 0, 0, 2 } } },
1876
1877 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1878 { SIMM9_A16_8, 0, 0, 2 } } },
1879 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1880 { SIMM9_A16_8, 0, 0, 2 } } },
1881 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1882 { SIMM9_A16_8, 0, 0, 2 } } },
1883 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1884 { SIMM9_A16_8, 0, 0, 2 } } },
1885 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1886 { SIMM9_A16_8, 0, 0, 2 } } },
1887
1888 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1889 { SIMM9_A16_8, 0, 0, 2 } } },
1890 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1891 { SIMM9_A16_8, 0, 0, 2 } } },
1892 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1893 { SIMM9_A16_8, 0, 0, 2 } } },
1894 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1895 { SIMM9_A16_8, 0, 0, 2 } } },
1896 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1897 { SIMM9_A16_8, 0, 0, 2 } } },
1898
1899 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1900 { SIMM9_A16_8, 0, 0, 2 } } },
1901 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1902 { SIMM9_A16_8, 0, 0, 2 } } },
1903 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1904 { SIMM9_A16_8, 0, 0, 2 } } },
1905 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1906 { SIMM9_A16_8, 0, 0, 2 } } },
1907 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1908 { SIMM9_A16_8, 0, 0, 2 } } },
1909 };
1910
1911 const unsigned arc_num_pseudo_insn =
1912 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
1913
1914 const struct arc_aux_reg arc_aux_regs[] =
1915 {
1916 #undef DEF
1917 #define DEF(ADDR, CPU, SUBCLASS, NAME) \
1918 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
1919
1920 #include "arc-regs.h"
1921
1922 #undef DEF
1923 };
1924
1925 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
1926
1927 /* NOTE: The order of this array MUST be consistent with 'enum
1928 arc_rlx_types' located in tc-arc.h! */
1929 const struct arc_opcode arc_relax_opcodes[] =
1930 {
1931 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
1932
1933 /* bl_s s13 11111sssssssssss. */
1934 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1935 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1936 { SIMM13_A32_5_S }, { 0 }},
1937
1938 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
1939 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1940 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1941 { SIMM25_A32_5 }, { C_D }},
1942
1943 /* b_s s10 1111000sssssssss. */
1944 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1945 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1946 { SIMM10_A16_7_S }, { 0 }},
1947
1948 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
1949 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1950 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1951 { SIMM25_A16_5 }, { C_D }},
1952
1953 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
1954 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1955 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1956 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1957
1958 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
1959 UIMM6_20_PCREL. */
1960 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1961 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1962 { RA, RB, UIMM6_20 }, { C_F }},
1963
1964 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
1965 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1966 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1967 { RA, RB, LIMM }, { C_F }},
1968
1969 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
1970 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1971 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1972 { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
1973
1974 /* ld<.di><.aa><.x><zz> a,b,s9
1975 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
1976 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1977 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1978 { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
1979 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
1980
1981 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
1982 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1983 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1984 { RA, BRAKET, RB, LIMM, BRAKETdup },
1985 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
1986
1987 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
1988 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1989 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1990 { RB_S, UIMM8_8_S }, { 0 }},
1991
1992 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
1993 SIMM12_20_PCREL. */
1994 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1995 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1996 { RB, SIMM12_20 }, { C_F }},
1997
1998 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
1999 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2000 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2001 { RB, LIMM }, { C_F }},
2002
2003 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
2004 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2005 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2006 { RC_S, RB_S, UIMM3_13_S }, { 0 }},
2007
2008 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
2009 UIMM6_20_PCREL. */
2010 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2011 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2012 { RA, RB, UIMM6_20 }, { C_F }},
2013
2014 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2015 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2016 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2017 { RA, RB, LIMM }, { C_F }},
2018
2019 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
2020 UIMM6_20_PCREL. */
2021 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2022 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
2023
2024 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2025 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2026 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2027
2028 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
2029 UIMM6_20_PCREL. */
2030 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2031 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2032 { RB, UIMM6_20 }, { C_F, C_CC }},
2033
2034 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2035 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2036 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2037 { RB, LIMM }, { C_F, C_CC }},
2038
2039 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
2040 UIMM6_20_PCREL. */
2041 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2042 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2043 { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
2044
2045 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2046 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2047 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2048 { RB, RBdup, LIMM }, { C_F, C_CC }}
2049 };
2050
2051 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
GDB Binutils - Deliverables
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