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167c6685c5ce24e2c2e4e8c46e8c5a92aa025c9f
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24
25 #include "dis-asm.h"
26 #include "opcode/arm.h"
27 #include "opintl.h"
28 #include "safe-ctype.h"
29 #include "floatformat.h"
30
31 /* FIXME: This shouldn't be done here. */
32 #include "coff/internal.h"
33 #include "libcoff.h"
34 #include "elf-bfd.h"
35 #include "elf/internal.h"
36 #include "elf/arm.h"
37 #include "mach-o.h"
38
39 /* FIXME: Belongs in global header. */
40 #ifndef strneq
41 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42 #endif
43
44 #ifndef NUM_ELEM
45 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
46 #endif
47
48 /* Cached mapping symbol state. */
49 enum map_type
50 {
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54 };
55
56 struct arm_private_data
57 {
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
71 };
72
73 struct opcode32
74 {
75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
78 const char * assembler; /* How to disassemble this insn. */
79 };
80
81 struct opcode16
82 {
83 arm_feature_set arch; /* Architecture defining this insn. */
84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
85 const char *assembler; /* How to disassemble this insn. */
86 };
87
88 /* print_insn_coprocessor recognizes the following format control codes:
89
90 %% %
91
92 %c print condition code (always bits 28-31 in ARM mode)
93 %q print shifter argument
94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
96 %A print address for ldc/stc/ldf/stf instruction
97 %B print vstm/vldm register list
98 %I print cirrus signed shift immediate: bits 0..3|4..6
99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
104 %<bitfield>c print as a condition code (for vsel)
105 %<bitfield>r print as an ARM register
106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
108 %<bitfield>d print the bitfield in decimal
109 %<bitfield>k print immediate for VFPv3 conversion instruction
110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
119 %<bitfield>V print as a NEON D or Q register
120 %<bitfield>E print a quarter-float immediate value
121
122 %y<code> print a single precision VFP reg.
123 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
124 %z<code> print a double precision VFP reg
125 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
126
127 %<bitfield>'c print specified char iff bitfield is all ones
128 %<bitfield>`c print specified char iff bitfield is all zeroes
129 %<bitfield>?ab... select from array of values in big endian order
130
131 %L print as an iWMMXt N/M width field.
132 %Z print the Immediate of a WSHUFH instruction.
133 %l like 'A' except use byte offsets for 'B' & 'H'
134 versions.
135 %i print 5-bit immediate in bits 8,3..0
136 (print "32" when 0)
137 %r print register offset address for wldt/wstr instruction. */
138
139 enum opcode_sentinel_enum
140 {
141 SENTINEL_IWMMXT_START = 1,
142 SENTINEL_IWMMXT_END,
143 SENTINEL_GENERIC_START
144 } opcode_sentinels;
145
146 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
147 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
148
149 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
150
151 static const struct opcode32 coprocessor_opcodes[] =
152 {
153 /* XScale instructions. */
154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
155 0x0e200010, 0x0fff0ff0,
156 "mia%c\tacc0, %0-3r, %12-15r"},
157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
158 0x0e280010, 0x0fff0ff0,
159 "miaph%c\tacc0, %0-3r, %12-15r"},
160 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
161 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
162 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
163 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
164 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
165 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
166
167 /* Intel Wireless MMX technology instructions. */
168 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
169 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
170 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
171 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
172 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
173 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
174 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
175 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
176 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
177 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
178 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
179 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
180 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
181 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
182 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
183 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
184 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
185 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
186 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
187 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
188 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
189 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
190 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
191 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
192 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
193 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
194 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
195 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
196 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
197 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
198 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
199 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
200 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
201 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
202 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
203 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
204 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
205 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
206 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
207 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
208 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
209 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
210 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
211 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
212 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
213 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
214 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
215 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
216 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
217 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
218 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
219 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
220 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
221 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
222 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
223 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
224 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
225 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
226 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
227 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
228 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
229 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
230 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
231 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
232 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
233 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
234 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
235 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
236 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
237 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
238 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
239 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
240 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
242 0x0e800120, 0x0f800ff0,
243 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
244 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
245 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
246 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
247 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
248 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
249 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
250 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
251 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
252 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
253 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
254 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
255 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
257 0x0e8000a0, 0x0f800ff0,
258 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
259 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
260 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
261 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
262 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
263 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
264 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
265 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
266 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
267 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
268 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
269 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
270 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
271 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
272 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
273 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
274 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
275 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
276 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
277 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
278 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
279 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
280 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
281 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
282 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
283 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
284 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
285 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
286 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
287 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
288 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
289 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
290 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
291 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
292 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
293 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
294 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
295 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
296 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
297 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
298 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
299 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
300 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
301 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
302 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
303 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
304 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
305 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
306 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
307 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
308 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
309 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
310 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
311 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
312 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
313 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
314 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
315 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
316 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
317 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
318 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
319 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
320 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
321 {ARM_FEATURE_CORE_LOW (0),
322 SENTINEL_IWMMXT_END, 0, "" },
323
324 /* Floating point coprocessor (FPA) instructions. */
325 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
326 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
327 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
328 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
329 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
330 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
331 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
332 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
333 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
334 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
335 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
336 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
337 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
338 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
339 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
340 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
341 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
342 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
343 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
344 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
345 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
346 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
347 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
348 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
349 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
350 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
351 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
352 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
353 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
354 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
355 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
356 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
357 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
358 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
359 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
360 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
361 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
362 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
363 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
364 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
365 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
366 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
367 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
368 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
369 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
370 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
371 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
372 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
373 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
374 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
375 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
376 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
377 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
378 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
379 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
380 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
381 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
382 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
383 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
384 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
385 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
386 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
387 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
388 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
389 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
390 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
391 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
392 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
393 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
394 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
395 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
396 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
397 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
398 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
399 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
400 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
401 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
402 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
403 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
404 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
405 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
406 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
407 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
408 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
409 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
410 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
411
412 /* ARMv8-M Mainline Security Extensions instructions. */
413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
414 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
416 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
417
418 /* Register load/store. */
419 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
420 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
421 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
422 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
423 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
424 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
425 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
426 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
427 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
428 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
429 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
430 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
431 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
432 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
433 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
434 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
435 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
436 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
437 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
438 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
439 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
440 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
441 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
442 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
443 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
444 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
451
452 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
453 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
454 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
455 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
456 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
457 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
458 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
459 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
460
461 /* Data transfer between ARM and NEON registers. */
462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
463 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
465 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
467 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
469 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
471 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
473 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
475 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
477 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
479 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
481 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
483 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
485 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
487 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
489 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
490 /* Half-precision conversion instructions. */
491 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
492 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
493 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
494 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
495 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
496 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
497 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
498 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
499
500 /* Floating point coprocessor (VFP) instructions. */
501 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
502 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
503 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
504 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
505 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
506 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
507 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
508 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
509 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
510 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
511 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
512 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
513 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
514 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
515 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
516 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
517 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
518 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
520 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
522 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
523 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
524 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
525 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
526 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
527 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
528 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
529 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
530 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
531 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
532 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
533 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
534 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
535 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
536 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
537 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
538 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
539 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
540 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
541 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
542 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
543 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
544 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
545 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
546 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
547 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
548 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
549 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
550 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
551 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
552 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
553 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
554 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
555 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
556 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
557 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
558 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
559 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
560 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
561 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
562 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
563 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
564 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
565 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
566 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
567 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
568 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
569 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
570 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
571 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
572 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
573 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
574 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
575 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
576 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
577 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
578 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
579 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
580 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
581 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
582 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
583 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
584 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
585 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
586 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
587 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
588 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
589 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
590 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
591 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
592 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
593 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
594 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
595 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
596 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
597 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
598 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
599 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
600 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
601 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
602 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
603 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
604 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
605 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
606 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
607 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
608 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
609 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
610 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
611 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
612 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
613 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
614 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
615 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
616 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
617 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
618 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
619 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
620 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
621 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
622 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
623 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
624 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
625 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
626 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
627 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
628 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
629 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
630 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
631 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
632 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
633 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
634 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
635
636 /* Cirrus coprocessor instructions. */
637 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
638 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
639 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
640 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
641 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
642 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
643 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
644 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
645 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
646 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
647 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
648 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
649 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
650 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
651 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
652 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
653 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
654 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
655 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
656 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
657 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
658 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
659 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
660 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
661 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
662 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
663 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
664 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
665 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
666 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
667 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
668 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
669 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
670 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
671 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
672 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
673 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
674 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
675 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
676 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
677 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
678 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
679 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
680 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
681 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
682 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
683 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
684 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
685 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
686 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
687 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
688 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
689 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
690 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
691 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
692 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
693 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
694 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
695 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
696 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
697 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
698 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
699 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
700 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
701 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
702 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
703 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
704 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
705 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
706 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
707 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
708 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
709 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
710 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
711 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
712 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
713 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
714 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
715 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
716 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
717 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
718 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
719 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
720 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
721 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
722 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
723 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
724 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
725 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
726 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
727 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
728 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
729 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
730 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
731 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
732 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
733 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
734 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
735 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
736 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
737 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
738 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
739 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
740 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
741 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
742 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
743 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
744 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
745 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
746 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
747 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
748 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
749 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
750 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
751 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
752 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
753 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
754 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
755 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
756 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
757 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
758 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
759 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
760 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
761 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
762 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
763 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
764 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
765 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
766 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
767 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
768 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
769 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
770 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
771 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
772 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
773 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
774 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
775 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
776 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
777 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
778 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
779 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
780 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
781 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
782 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
783 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
784 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
785 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
786 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
787 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
788 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
789 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
790 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
791 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
792 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
795 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
796 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
797 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
798 0x0e000600, 0x0ff00f10,
799 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
800 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
801 0x0e100600, 0x0ff00f10,
802 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
803 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
804 0x0e200600, 0x0ff00f10,
805 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
806 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
807 0x0e300600, 0x0ff00f10,
808 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
809
810 /* VFP Fused multiply add instructions. */
811 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
812 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
813 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
814 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
815 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
816 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
817 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
818 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
819 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
820 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
821 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
822 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
823 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
824 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
825 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
826 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
827
828 /* FP v5. */
829 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
830 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
831 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
832 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
833 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
834 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
835 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
836 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
837 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
838 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
839 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
840 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
841 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
842 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
843 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
844 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
845 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
846 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
847 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
848 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
849 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
850 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
851 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
852 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
853
854 /* Generic coprocessor instructions. */
855 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
857 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
859 0x0c500000, 0x0ff00000,
860 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
862 0x0e000000, 0x0f000010,
863 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
865 0x0e10f010, 0x0f10f010,
866 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
868 0x0e100010, 0x0f100010,
869 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
871 0x0e000010, 0x0f100010,
872 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
874 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
876 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
877
878 /* V6 coprocessor instructions. */
879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
880 0xfc500000, 0xfff00000,
881 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
883 0xfc400000, 0xfff00000,
884 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
885
886 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
887 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
888 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
890 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
891 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
892 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
893 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
894 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
895 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
896 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
898 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
900 0xfe000800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
901 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
902 0xfe200800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%23?780"},
903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
904 0xfe800800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
906 0xfea00800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%23?780"},
907
908 /* V5 coprocessor instructions. */
909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
910 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
912 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
914 0xfe000000, 0xff000010,
915 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
917 0xfe000010, 0xff100010,
918 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
920 0xfe100010, 0xff100010,
921 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
922
923 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
924 cp_num: bit <11:8> == 0b1001.
925 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
926 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
927 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
928 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
929 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
931 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
932 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
933 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
934 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
935 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
937 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
938 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
939 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
940 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
941 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
943 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
944 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
945 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
946 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
947 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
949 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
950 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
951 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
952 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
953 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
955 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
957 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
958 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
959 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
961 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
962 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
963 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
964 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
965 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
967 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
968 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
969 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
970 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
971 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
973 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
975 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
976 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
977 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
979 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
981 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
982 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
983 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
985 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
986 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
987 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
988 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
989 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
991 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
992 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
993 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
994 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
995 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
996
997 /* ARMv8.3 javascript conversion instruction. */
998 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
999 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1000
1001 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1002 };
1003
1004 /* Neon opcode table: This does not encode the top byte -- that is
1005 checked by the print_insn_neon routine, as it depends on whether we are
1006 doing thumb32 or arm32 disassembly. */
1007
1008 /* print_insn_neon recognizes the following format control codes:
1009
1010 %% %
1011
1012 %c print condition code
1013 %u print condition code (unconditional in ARM mode,
1014 UNPREDICTABLE if not AL in Thumb)
1015 %A print v{st,ld}[1234] operands
1016 %B print v{st,ld}[1234] any one operands
1017 %C print v{st,ld}[1234] single->all operands
1018 %D print scalar
1019 %E print vmov, vmvn, vorr, vbic encoded constant
1020 %F print vtbl,vtbx register list
1021
1022 %<bitfield>r print as an ARM register
1023 %<bitfield>d print the bitfield in decimal
1024 %<bitfield>e print the 2^N - bitfield in decimal
1025 %<bitfield>D print as a NEON D register
1026 %<bitfield>Q print as a NEON Q register
1027 %<bitfield>R print as a NEON D or Q register
1028 %<bitfield>Sn print byte scaled width limited by n
1029 %<bitfield>Tn print short scaled width limited by n
1030 %<bitfield>Un print long scaled width limited by n
1031
1032 %<bitfield>'c print specified char iff bitfield is all ones
1033 %<bitfield>`c print specified char iff bitfield is all zeroes
1034 %<bitfield>?ab... select from array of values in big endian order. */
1035
1036 static const struct opcode32 neon_opcodes[] =
1037 {
1038 /* Extract. */
1039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040 0xf2b00840, 0xffb00850,
1041 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1043 0xf2b00000, 0xffb00810,
1044 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1045
1046 /* Move data element to all lanes. */
1047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1048 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1050 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1052 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1053
1054 /* Table lookup. */
1055 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1056 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1058 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1059
1060 /* Half-precision conversions. */
1061 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1062 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1063 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1064 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1065
1066 /* NEON fused multiply add instructions. */
1067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1068 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1070 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1071 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1072 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1073 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1074 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1075
1076 /* Two registers, miscellaneous. */
1077 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1078 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1080 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1081 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1082 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1083 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1084 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1085 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1086 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1087 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1088 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1089 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1090 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1091 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1092 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1093 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1094 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1095 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1096 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1097 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1098 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1100 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1102 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1104 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1106 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1108 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1110 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1112 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1114 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1116 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1118 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1119 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1120 0xf3b20300, 0xffb30fd0,
1121 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1125 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1128 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1129 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1149 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1151 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1153 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1155 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1157 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1159 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1163 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1165 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1169 0xf3bb0600, 0xffbf0e10,
1170 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1171 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1172 0xf3b70600, 0xffbf0e10,
1173 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1174
1175 /* Three registers of the same length. */
1176 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1177 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1178 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1179 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1180 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1181 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1182 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1183 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1184 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1185 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1186 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1187 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1188 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1189 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1191 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1193 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1195 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1196 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1197 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1198 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1199 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1200 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1201 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1203 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1204 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1205 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1206 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1207 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1208 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1209 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1210 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1211 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1212 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1213 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1214 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1215 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1217 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1218 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1219 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1220 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1221 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1223 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1224 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1225 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1227 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1229 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1231 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1232 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1233 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1235 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1237 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1239 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1241 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1243 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1244 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1245 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1249 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1253 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1256 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1257 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1261 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1265 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1267 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1268 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1269 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1271 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1273 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1275 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1277 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1279 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1281 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1283 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1285 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1287 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1288 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1289 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1291 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1293 0xf2000b00, 0xff800f10,
1294 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2000b10, 0xff800f10,
1297 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1300 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1301 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1303 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1305 0xf3000b00, 0xff800f10,
1306 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2000000, 0xfe800f10,
1309 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311 0xf2000010, 0xfe800f10,
1312 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2000100, 0xfe800f10,
1315 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2000200, 0xfe800f10,
1318 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf2000210, 0xfe800f10,
1321 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2000300, 0xfe800f10,
1324 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf2000310, 0xfe800f10,
1327 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf2000400, 0xfe800f10,
1330 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332 0xf2000410, 0xfe800f10,
1333 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2000500, 0xfe800f10,
1336 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338 0xf2000510, 0xfe800f10,
1339 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf2000600, 0xfe800f10,
1342 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf2000610, 0xfe800f10,
1345 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2000700, 0xfe800f10,
1348 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf2000710, 0xfe800f10,
1351 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2000910, 0xfe800f10,
1354 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356 0xf2000a00, 0xfe800f10,
1357 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf2000a10, 0xfe800f10,
1360 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1362 0xf3000b10, 0xff800f10,
1363 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1365 0xf3000c10, 0xff800f10,
1366 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1367
1368 /* One register and an immediate value. */
1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1395
1396 /* Two registers and a shift amount. */
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1402 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1408 0xf2880950, 0xfeb80fd0,
1409 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2900950, 0xfeb00fd0,
1432 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf2a00950, 0xfea00fd0,
1477 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf2a00e10, 0xfea00e90,
1516 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1518 0xf2a00c10, 0xfea00e90,
1519 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1520
1521 /* Three registers of different lengths. */
1522 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1523 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2800400, 0xff800f50,
1528 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2800600, 0xff800f50,
1531 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf2800900, 0xff800f50,
1534 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2800b00, 0xff800f50,
1537 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf2800d00, 0xff800f50,
1540 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf3800400, 0xff800f50,
1543 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf3800600, 0xff800f50,
1546 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf2800000, 0xfe800f50,
1549 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf2800100, 0xfe800f50,
1552 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2800200, 0xfe800f50,
1555 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2800300, 0xfe800f50,
1558 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2800500, 0xfe800f50,
1561 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf2800700, 0xfe800f50,
1564 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2800800, 0xfe800f50,
1567 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf2800a00, 0xfe800f50,
1570 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2800c00, 0xfe800f50,
1573 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1574
1575 /* Two registers and a scalar. */
1576 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1577 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1580 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1581 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1582 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1583 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1588 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1589 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1596 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1597 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1608 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1609 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1614 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1615 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1620 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1621 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf2800240, 0xfe800f50,
1628 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf2800640, 0xfe800f50,
1631 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf2800a40, 0xfe800f50,
1634 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1636 0xf2800e40, 0xff800f50,
1637 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1639 0xf2800f40, 0xff800f50,
1640 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1642 0xf3800e40, 0xff800f50,
1643 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1645 0xf3800f40, 0xff800f50,
1646 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1647 },
1648
1649 /* Element and structure load/store. */
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1673 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1688
1689 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1690 };
1691
1692 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1693 ordered: they must be searched linearly from the top to obtain a correct
1694 match. */
1695
1696 /* print_insn_arm recognizes the following format control codes:
1697
1698 %% %
1699
1700 %a print address for ldr/str instruction
1701 %s print address for ldr/str halfword/signextend instruction
1702 %S like %s but allow UNPREDICTABLE addressing
1703 %b print branch destination
1704 %c print condition code (always bits 28-31)
1705 %m print register mask for ldm/stm instruction
1706 %o print operand2 (immediate or register + shift)
1707 %p print 'p' iff bits 12-15 are 15
1708 %t print 't' iff bit 21 set and bit 24 clear
1709 %B print arm BLX(1) destination
1710 %C print the PSR sub type.
1711 %U print barrier type.
1712 %P print address for pli instruction.
1713
1714 %<bitfield>r print as an ARM register
1715 %<bitfield>T print as an ARM register + 1
1716 %<bitfield>R as %r but r15 is UNPREDICTABLE
1717 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1718 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1719 %<bitfield>d print the bitfield in decimal
1720 %<bitfield>W print the bitfield plus one in decimal
1721 %<bitfield>x print the bitfield in hex
1722 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1723
1724 %<bitfield>'c print specified char iff bitfield is all ones
1725 %<bitfield>`c print specified char iff bitfield is all zeroes
1726 %<bitfield>?ab... select from array of values in big endian order
1727
1728 %e print arm SMI operand (bits 0..7,8..19).
1729 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1730 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1731 %R print the SPSR/CPSR or banked register of an MRS. */
1732
1733 static const struct opcode32 arm_opcodes[] =
1734 {
1735 /* ARM instructions. */
1736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1737 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1739 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1740
1741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1742 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1744 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1746 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1748 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1750 0x00800090, 0x0fa000f0,
1751 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1753 0x00a00090, 0x0fa000f0,
1754 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1755
1756 /* V8.2 RAS extension instructions. */
1757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
1758 0xe320f010, 0xffffffff, "esb"},
1759
1760 /* V8 instructions. */
1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1762 0x0320f005, 0x0fffffff, "sevl"},
1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1764 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1766 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1767 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1768 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1770 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1772 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1773 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1774 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1775 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1776 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1777 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1778 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1780 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1781 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1782 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1783 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1784 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1786 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1787 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1788 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1790 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1792 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1793 /* CRC32 instructions. */
1794 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1795 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1796 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1797 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1798 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1799 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1800 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1801 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1802 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1803 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1804 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1805 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1806
1807 /* Privileged Access Never extension instructions. */
1808 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1809 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1810
1811 /* Virtualization Extension instructions. */
1812 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1814
1815 /* Integer Divide Extension instructions. */
1816 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1817 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1818 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1819 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1820
1821 /* MP Extension instructions. */
1822 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1823
1824 /* V7 instructions. */
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1833 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1834
1835 /* ARM V6T2 instructions. */
1836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1837 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1839 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1841 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1843 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1844
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1846 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1848 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1849
1850 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1851 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1852 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1853 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1855 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1857 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1858
1859 /* ARM Security extension instructions. */
1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1861 0x01600070, 0x0ff000f0, "smc%c\t%e"},
1862
1863 /* ARM V6K instructions. */
1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1865 0xf57ff01f, 0xffffffff, "clrex"},
1866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1867 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1869 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1871 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1873 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1875 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1877 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1878
1879 /* ARM V6K NOP hints. */
1880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1881 0x0320f001, 0x0fffffff, "yield%c"},
1882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1883 0x0320f002, 0x0fffffff, "wfe%c"},
1884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1885 0x0320f003, 0x0fffffff, "wfi%c"},
1886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1887 0x0320f004, 0x0fffffff, "sev%c"},
1888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1889 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1890
1891 /* ARM V6 instructions. */
1892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1893 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1895 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1897 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1899 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1901 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1903 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1905 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1907 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1909 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1911 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1913 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1915 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1917 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1919 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1921 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1923 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1925 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1927 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1929 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1931 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1933 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1935 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1937 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1939 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1941 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1943 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1945 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1947 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1949 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1951 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1953 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1955 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1957 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1959 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1961 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1963 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1965 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1967 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1969 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1971 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1973 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1975 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1977 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1979 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1981 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1983 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1985 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1987 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1989 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1991 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1993 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1995 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1997 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1999 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2001 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2003 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2005 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2007 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2009 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2011 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2013 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2015 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2017 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2019 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2021 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2023 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2025 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2027 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2029 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2031 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2033 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2035 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2037 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2039 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2041 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2043 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2045 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2047 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2049 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2051 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2053 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2055 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2057 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2059 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2061 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2063 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2065 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2067 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2069 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2071 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2073 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2075 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2077 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2079 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2081 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2083 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2085 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2087 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2089 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2091 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2093 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2095 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2097 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2099 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2101 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2103 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2105 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2107 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2109 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2111 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2113 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2115 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2117 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2119 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2121 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2123 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2125 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2127 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2129 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2131 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2133 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2135 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2136
2137 /* V5J instruction. */
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2139 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2140
2141 /* V5 Instructions. */
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2143 0xe1200070, 0xfff000f0,
2144 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2146 0xfa000000, 0xfe000000, "blx\t%B"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2148 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2150 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2151
2152 /* V5E "El Segundo" Instructions. */
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2154 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2156 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2158 0xf450f000, 0xfc70f000, "pld\t%a"},
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2160 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2162 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2164 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2166 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2167
2168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2169 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2171 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2172
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2174 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2176 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2178 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2180 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2181
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2183 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2185 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2187 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2189 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2190
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2192 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2194 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2195
2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2197 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2199 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2201 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2203 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2204
2205 /* ARM Instructions. */
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2207 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2208
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2221
2222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2223 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2225 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2227 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2229 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2230
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2239
2240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2246
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2253
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2260
2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2264 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2266 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2267
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2274
2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2281
2282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2283 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2285 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2288
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2290 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2295
2296 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2297 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2299 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2301 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2302
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2304 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2306 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2308 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2309
2310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2313 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2317 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
2318
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2324 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2325
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2331 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2332
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2334 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2338 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2339
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2341 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2345 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2347 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2349 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2351 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2353 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2354
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2361
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2363 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2367 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2368
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2373
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2376
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2378 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2381
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2389 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2391 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2393 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2395 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2397 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2403 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2405 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2407 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2413 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2415 0x092d0000, 0x0fff0000, "push%c\t%m"},
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2419 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2420
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2422 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2424 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2426 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2428 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2430 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2432 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2434 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2438 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2440 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2442 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2444 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2446 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2448 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2450 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2452 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2454 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2456 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2458 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2459
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2464
2465 /* The rest. */
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2467 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2469 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2470 {ARM_FEATURE_CORE_LOW (0),
2471 0x00000000, 0x00000000, 0}
2472 };
2473
2474 /* print_insn_thumb16 recognizes the following format control codes:
2475
2476 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2477 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2478 %<bitfield>I print bitfield as a signed decimal
2479 (top bit of range being the sign bit)
2480 %N print Thumb register mask (with LR)
2481 %O print Thumb register mask (with PC)
2482 %M print Thumb register mask
2483 %b print CZB's 6-bit unsigned branch destination
2484 %s print Thumb right-shift immediate (6..10; 0 == 32).
2485 %c print the condition code
2486 %C print the condition code, or "s" if not conditional
2487 %x print warning if conditional an not at end of IT block"
2488 %X print "\t; unpredictable <IT:code>" if conditional
2489 %I print IT instruction suffix and operands
2490 %W print Thumb Writeback indicator for LDMIA
2491 %<bitfield>r print bitfield as an ARM register
2492 %<bitfield>d print bitfield as a decimal
2493 %<bitfield>H print (bitfield * 2) as a decimal
2494 %<bitfield>W print (bitfield * 4) as a decimal
2495 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2496 %<bitfield>B print Thumb branch destination (signed displacement)
2497 %<bitfield>c print bitfield as a condition code
2498 %<bitnum>'c print specified char iff bit is one
2499 %<bitnum>?ab print a if bit is one else print b. */
2500
2501 static const struct opcode16 thumb_opcodes[] =
2502 {
2503 /* Thumb instructions. */
2504
2505 /* ARMv8-M Security Extensions instructions. */
2506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
2508
2509 /* ARM V8 instructions. */
2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
2512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
2513
2514 /* ARM V6K no-argument instructions. */
2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2521
2522 /* ARM V6T2 instructions. */
2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2524 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2526 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2528
2529 /* ARM V6. */
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2541
2542 /* ARM V5 ISA extends Thumb. */
2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2544 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
2545 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2547 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
2548 /* ARM V4T ISA (Thumb v1). */
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2550 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2551 /* Format 4. */
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2568 /* format 13 */
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2571 /* format 5 */
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2576 /* format 14 */
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2579 /* format 2 */
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2581 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2583 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2585 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2587 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2588 /* format 8 */
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2590 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2592 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2594 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2595 /* format 7 */
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2597 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2599 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2600 /* format 1 */
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2603 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2606 /* format 3 */
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2611 /* format 6 */
2612 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2614 0x4800, 0xF800,
2615 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2616 /* format 9 */
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2618 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2620 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2622 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2624 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2625 /* format 10 */
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2627 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2629 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2630 /* format 11 */
2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2632 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2634 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2635 /* format 12 */
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2637 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2639 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2640 /* format 15 */
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2643 /* format 17 */
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2645 /* format 16 */
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2649 /* format 18 */
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2651
2652 /* The E800 .. FFFF range is unconditionally redirected to the
2653 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2654 are processed via that table. Thus, we can never encounter a
2655 bare "second half of BL/BLX(1)" instruction here. */
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2657 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2658 };
2659
2660 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2661 We adopt the convention that hw1 is the high 16 bits of .value and
2662 .mask, hw2 the low 16 bits.
2663
2664 print_insn_thumb32 recognizes the following format control codes:
2665
2666 %% %
2667
2668 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2669 %M print a modified 12-bit immediate (same location)
2670 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2671 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2672 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
2673 %S print a possibly-shifted Rm
2674
2675 %L print address for a ldrd/strd instruction
2676 %a print the address of a plain load/store
2677 %w print the width and signedness of a core load/store
2678 %m print register mask for ldm/stm
2679
2680 %E print the lsb and width fields of a bfc/bfi instruction
2681 %F print the lsb and width fields of a sbfx/ubfx instruction
2682 %b print a conditional branch offset
2683 %B print an unconditional branch offset
2684 %s print the shift field of an SSAT instruction
2685 %R print the rotation field of an SXT instruction
2686 %U print barrier type.
2687 %P print address for pli instruction.
2688 %c print the condition code
2689 %x print warning if conditional an not at end of IT block"
2690 %X print "\t; unpredictable <IT:code>" if conditional
2691
2692 %<bitfield>d print bitfield in decimal
2693 %<bitfield>D print bitfield plus one in decimal
2694 %<bitfield>W print bitfield*4 in decimal
2695 %<bitfield>r print bitfield as an ARM register
2696 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2697 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
2698 %<bitfield>c print bitfield as a condition code
2699
2700 %<bitfield>'c print specified char iff bitfield is all ones
2701 %<bitfield>`c print specified char iff bitfield is all zeroes
2702 %<bitfield>?ab... select from array of values in big endian order
2703
2704 With one exception at the bottom (done because BL and BLX(1) need
2705 to come dead last), this table was machine-sorted first in
2706 decreasing order of number of bits set in the mask, then in
2707 increasing numeric order of mask, then in increasing numeric order
2708 of opcode. This order is not the clearest for a human reader, but
2709 is guaranteed never to catch a special-case bit pattern with a more
2710 general mask, which is important, because this instruction encoding
2711 makes heavy use of special-case bit patterns. */
2712 static const struct opcode32 thumb32_opcodes[] =
2713 {
2714 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
2716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2717 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2719 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2721 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2723 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2724
2725 /* ARM V8.2 RAS extension instructions. */
2726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2727 0xf3af8010, 0xffffffff, "esb"},
2728
2729 /* V8 instructions. */
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2731 0xf3af8005, 0xffffffff, "sevl%c.w"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2733 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2735 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2737 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2739 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2741 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2743 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2745 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2747 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2749 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2751 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2753 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2755 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2757 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2759 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2761 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2762
2763 /* CRC32 instructions. */
2764 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2765 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2766 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2767 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2768 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2769 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2770 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2771 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2772 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2773 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2774 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2775 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
2776
2777 /* V7 instructions. */
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2786 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2788 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2789
2790 /* Virtualization Extension instructions. */
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2792 /* We skip ERET as that is SUBS pc, lr, #0. */
2793
2794 /* MP Extension instructions. */
2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
2796
2797 /* Security extension instructions. */
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2799
2800 /* Instructions defined in the basic V6T2 set. */
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2809
2810 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2811 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2838 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2839 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2840 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2841 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2858 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2859 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2967 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3034 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3035 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041 0xf810f000, 0xff70f000, "pld%c\t%a"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067 0xfb100000, 0xfff000c0,
3068 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0xfbc00080, 0xfff000c0,
3071 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3082 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3083 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3086 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3087 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3109 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3131 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3137 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143 0xe9400000, 0xff500000,
3144 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3146 0xe9500000, 0xff500000,
3147 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3149 0xe8600000, 0xff700000,
3150 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3152 0xe8700000, 0xff700000,
3153 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3157 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3158
3159 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3163 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3168
3169 /* These have been 32-bit since the invention of Thumb. */
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3171 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3173 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3174
3175 /* Fallback. */
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3177 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3178 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3179 };
3180
3181 static const char *const arm_conditional[] =
3182 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3183 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3184
3185 static const char *const arm_fp_const[] =
3186 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3187
3188 static const char *const arm_shift[] =
3189 {"lsl", "lsr", "asr", "ror"};
3190
3191 typedef struct
3192 {
3193 const char *name;
3194 const char *description;
3195 const char *reg_names[16];
3196 }
3197 arm_regname;
3198
3199 static const arm_regname regnames[] =
3200 {
3201 { "raw" , "Select raw register names",
3202 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3203 { "gcc", "Select register names used by GCC",
3204 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3205 { "std", "Select register names used in ARM's ISA documentation",
3206 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3207 { "apcs", "Select register names used in the APCS",
3208 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3209 { "atpcs", "Select register names used in the ATPCS",
3210 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3211 { "special-atpcs", "Select special register names used in the ATPCS",
3212 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3213 };
3214
3215 static const char *const iwmmxt_wwnames[] =
3216 {"b", "h", "w", "d"};
3217
3218 static const char *const iwmmxt_wwssnames[] =
3219 {"b", "bus", "bc", "bss",
3220 "h", "hus", "hc", "hss",
3221 "w", "wus", "wc", "wss",
3222 "d", "dus", "dc", "dss"
3223 };
3224
3225 static const char *const iwmmxt_regnames[] =
3226 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3227 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3228 };
3229
3230 static const char *const iwmmxt_cregnames[] =
3231 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3232 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3233 };
3234
3235 /* Default to GCC register name set. */
3236 static unsigned int regname_selected = 1;
3237
3238 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3239 #define arm_regnames regnames[regname_selected].reg_names
3240
3241 static bfd_boolean force_thumb = FALSE;
3242
3243 /* Current IT instruction state. This contains the same state as the IT
3244 bits in the CPSR. */
3245 static unsigned int ifthen_state;
3246 /* IT state for the next instruction. */
3247 static unsigned int ifthen_next_state;
3248 /* The address of the insn for which the IT state is valid. */
3249 static bfd_vma ifthen_address;
3250 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3251 /* Indicates that the current Conditional state is unconditional or outside
3252 an IT block. */
3253 #define COND_UNCOND 16
3254
3255 \f
3256 /* Functions. */
3257 int
3258 get_arm_regname_num_options (void)
3259 {
3260 return NUM_ARM_REGNAMES;
3261 }
3262
3263 int
3264 set_arm_regname_option (int option)
3265 {
3266 int old = regname_selected;
3267 regname_selected = option;
3268 return old;
3269 }
3270
3271 int
3272 get_arm_regnames (int option,
3273 const char **setname,
3274 const char **setdescription,
3275 const char *const **register_names)
3276 {
3277 *setname = regnames[option].name;
3278 *setdescription = regnames[option].description;
3279 *register_names = regnames[option].reg_names;
3280 return 16;
3281 }
3282
3283 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3284 Returns pointer to following character of the format string and
3285 fills in *VALUEP and *WIDTHP with the extracted value and number of
3286 bits extracted. WIDTHP can be NULL. */
3287
3288 static const char *
3289 arm_decode_bitfield (const char *ptr,
3290 unsigned long insn,
3291 unsigned long *valuep,
3292 int *widthp)
3293 {
3294 unsigned long value = 0;
3295 int width = 0;
3296
3297 do
3298 {
3299 int start, end;
3300 int bits;
3301
3302 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3303 start = start * 10 + *ptr - '0';
3304 if (*ptr == '-')
3305 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3306 end = end * 10 + *ptr - '0';
3307 else
3308 end = start;
3309 bits = end - start;
3310 if (bits < 0)
3311 abort ();
3312 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3313 width += bits + 1;
3314 }
3315 while (*ptr++ == ',');
3316 *valuep = value;
3317 if (widthp)
3318 *widthp = width;
3319 return ptr - 1;
3320 }
3321
3322 static void
3323 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3324 bfd_boolean print_shift)
3325 {
3326 func (stream, "%s", arm_regnames[given & 0xf]);
3327
3328 if ((given & 0xff0) != 0)
3329 {
3330 if ((given & 0x10) == 0)
3331 {
3332 int amount = (given & 0xf80) >> 7;
3333 int shift = (given & 0x60) >> 5;
3334
3335 if (amount == 0)
3336 {
3337 if (shift == 3)
3338 {
3339 func (stream, ", rrx");
3340 return;
3341 }
3342
3343 amount = 32;
3344 }
3345
3346 if (print_shift)
3347 func (stream, ", %s #%d", arm_shift[shift], amount);
3348 else
3349 func (stream, ", #%d", amount);
3350 }
3351 else if ((given & 0x80) == 0x80)
3352 func (stream, "\t; <illegal shifter operand>");
3353 else if (print_shift)
3354 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3355 arm_regnames[(given & 0xf00) >> 8]);
3356 else
3357 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3358 }
3359 }
3360
3361 #define W_BIT 21
3362 #define I_BIT 22
3363 #define U_BIT 23
3364 #define P_BIT 24
3365
3366 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3367 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3368 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3369 #define PRE_BIT_SET (given & (1 << P_BIT))
3370
3371 /* Print one coprocessor instruction on INFO->STREAM.
3372 Return TRUE if the instuction matched, FALSE if this is not a
3373 recognised coprocessor instruction. */
3374
3375 static bfd_boolean
3376 print_insn_coprocessor (bfd_vma pc,
3377 struct disassemble_info *info,
3378 long given,
3379 bfd_boolean thumb)
3380 {
3381 const struct opcode32 *insn;
3382 void *stream = info->stream;
3383 fprintf_ftype func = info->fprintf_func;
3384 unsigned long mask;
3385 unsigned long value = 0;
3386 int cond;
3387 int cp_num;
3388 struct arm_private_data *private_data = info->private_data;
3389 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3390
3391 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3392
3393 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3394 {
3395 unsigned long u_reg = 16;
3396 bfd_boolean is_unpredictable = FALSE;
3397 signed long value_in_comment = 0;
3398 const char *c;
3399
3400 if (ARM_FEATURE_ZERO (insn->arch))
3401 switch (insn->value)
3402 {
3403 case SENTINEL_IWMMXT_START:
3404 if (info->mach != bfd_mach_arm_XScale
3405 && info->mach != bfd_mach_arm_iWMMXt
3406 && info->mach != bfd_mach_arm_iWMMXt2)
3407 do
3408 insn++;
3409 while ((! ARM_FEATURE_ZERO (insn->arch))
3410 && insn->value != SENTINEL_IWMMXT_END);
3411 continue;
3412
3413 case SENTINEL_IWMMXT_END:
3414 continue;
3415
3416 case SENTINEL_GENERIC_START:
3417 ARM_FEATURE_COPY (allowed_arches, private_data->features);
3418 continue;
3419
3420 default:
3421 abort ();
3422 }
3423
3424 mask = insn->mask;
3425 value = insn->value;
3426 cp_num = (given >> 8) & 0xf;
3427
3428 if (thumb)
3429 {
3430 /* The high 4 bits are 0xe for Arm conditional instructions, and
3431 0xe for arm unconditional instructions. The rest of the
3432 encoding is the same. */
3433 mask |= 0xf0000000;
3434 value |= 0xe0000000;
3435 if (ifthen_state)
3436 cond = IFTHEN_COND;
3437 else
3438 cond = COND_UNCOND;
3439 }
3440 else
3441 {
3442 /* Only match unconditional instuctions against unconditional
3443 patterns. */
3444 if ((given & 0xf0000000) == 0xf0000000)
3445 {
3446 mask |= 0xf0000000;
3447 cond = COND_UNCOND;
3448 }
3449 else
3450 {
3451 cond = (given >> 28) & 0xf;
3452 if (cond == 0xe)
3453 cond = COND_UNCOND;
3454 }
3455 }
3456
3457 if ((given & mask) != value)
3458 continue;
3459
3460 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3461 continue;
3462
3463 if (insn->value == 0xfe000010 /* mcr2 */
3464 || insn->value == 0xfe100010 /* mrc2 */
3465 || insn->value == 0xfc100000 /* ldc2 */
3466 || insn->value == 0xfc000000) /* stc2 */
3467 {
3468 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3469 is_unpredictable = TRUE;
3470 }
3471 else if (insn->value == 0x0e000000 /* cdp */
3472 || insn->value == 0xfe000000 /* cdp2 */
3473 || insn->value == 0x0e000010 /* mcr */
3474 || insn->value == 0x0e100010 /* mrc */
3475 || insn->value == 0x0c100000 /* ldc */
3476 || insn->value == 0x0c000000) /* stc */
3477 {
3478 /* Floating-point instructions. */
3479 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3480 continue;
3481 }
3482
3483 for (c = insn->assembler; *c; c++)
3484 {
3485 if (*c == '%')
3486 {
3487 switch (*++c)
3488 {
3489 case '%':
3490 func (stream, "%%");
3491 break;
3492
3493 case 'A':
3494 {
3495 int rn = (given >> 16) & 0xf;
3496 bfd_vma offset = given & 0xff;
3497
3498 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3499
3500 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3501 {
3502 /* Not unindexed. The offset is scaled. */
3503 if (cp_num == 9)
3504 /* vldr.16/vstr.16 will shift the address
3505 left by 1 bit only. */
3506 offset = offset * 2;
3507 else
3508 offset = offset * 4;
3509
3510 if (NEGATIVE_BIT_SET)
3511 offset = - offset;
3512 if (rn != 15)
3513 value_in_comment = offset;
3514 }
3515
3516 if (PRE_BIT_SET)
3517 {
3518 if (offset)
3519 func (stream, ", #%d]%s",
3520 (int) offset,
3521 WRITEBACK_BIT_SET ? "!" : "");
3522 else if (NEGATIVE_BIT_SET)
3523 func (stream, ", #-0]");
3524 else
3525 func (stream, "]");
3526 }
3527 else
3528 {
3529 func (stream, "]");
3530
3531 if (WRITEBACK_BIT_SET)
3532 {
3533 if (offset)
3534 func (stream, ", #%d", (int) offset);
3535 else if (NEGATIVE_BIT_SET)
3536 func (stream, ", #-0");
3537 }
3538 else
3539 {
3540 func (stream, ", {%s%d}",
3541 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3542 (int) offset);
3543 value_in_comment = offset;
3544 }
3545 }
3546 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3547 {
3548 func (stream, "\t; ");
3549 /* For unaligned PCs, apply off-by-alignment
3550 correction. */
3551 info->print_address_func (offset + pc
3552 + info->bytes_per_chunk * 2
3553 - (pc & 3),
3554 info);
3555 }
3556 }
3557 break;
3558
3559 case 'B':
3560 {
3561 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3562 int offset = (given >> 1) & 0x3f;
3563
3564 if (offset == 1)
3565 func (stream, "{d%d}", regno);
3566 else if (regno + offset > 32)
3567 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3568 else
3569 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3570 }
3571 break;
3572
3573 case 'u':
3574 if (cond != COND_UNCOND)
3575 is_unpredictable = TRUE;
3576
3577 /* Fall through. */
3578 case 'c':
3579 if (cond != COND_UNCOND && cp_num == 9)
3580 is_unpredictable = TRUE;
3581
3582 func (stream, "%s", arm_conditional[cond]);
3583 break;
3584
3585 case 'I':
3586 /* Print a Cirrus/DSP shift immediate. */
3587 /* Immediates are 7bit signed ints with bits 0..3 in
3588 bits 0..3 of opcode and bits 4..6 in bits 5..7
3589 of opcode. */
3590 {
3591 int imm;
3592
3593 imm = (given & 0xf) | ((given & 0xe0) >> 1);
3594
3595 /* Is ``imm'' a negative number? */
3596 if (imm & 0x40)
3597 imm -= 0x80;
3598
3599 func (stream, "%d", imm);
3600 }
3601
3602 break;
3603
3604 case 'F':
3605 switch (given & 0x00408000)
3606 {
3607 case 0:
3608 func (stream, "4");
3609 break;
3610 case 0x8000:
3611 func (stream, "1");
3612 break;
3613 case 0x00400000:
3614 func (stream, "2");
3615 break;
3616 default:
3617 func (stream, "3");
3618 }
3619 break;
3620
3621 case 'P':
3622 switch (given & 0x00080080)
3623 {
3624 case 0:
3625 func (stream, "s");
3626 break;
3627 case 0x80:
3628 func (stream, "d");
3629 break;
3630 case 0x00080000:
3631 func (stream, "e");
3632 break;
3633 default:
3634 func (stream, _("<illegal precision>"));
3635 break;
3636 }
3637 break;
3638
3639 case 'Q':
3640 switch (given & 0x00408000)
3641 {
3642 case 0:
3643 func (stream, "s");
3644 break;
3645 case 0x8000:
3646 func (stream, "d");
3647 break;
3648 case 0x00400000:
3649 func (stream, "e");
3650 break;
3651 default:
3652 func (stream, "p");
3653 break;
3654 }
3655 break;
3656
3657 case 'R':
3658 switch (given & 0x60)
3659 {
3660 case 0:
3661 break;
3662 case 0x20:
3663 func (stream, "p");
3664 break;
3665 case 0x40:
3666 func (stream, "m");
3667 break;
3668 default:
3669 func (stream, "z");
3670 break;
3671 }
3672 break;
3673
3674 case '0': case '1': case '2': case '3': case '4':
3675 case '5': case '6': case '7': case '8': case '9':
3676 {
3677 int width;
3678
3679 c = arm_decode_bitfield (c, given, &value, &width);
3680
3681 switch (*c)
3682 {
3683 case 'R':
3684 if (value == 15)
3685 is_unpredictable = TRUE;
3686 /* Fall through. */
3687 case 'r':
3688 if (c[1] == 'u')
3689 {
3690 /* Eat the 'u' character. */
3691 ++ c;
3692
3693 if (u_reg == value)
3694 is_unpredictable = TRUE;
3695 u_reg = value;
3696 }
3697 func (stream, "%s", arm_regnames[value]);
3698 break;
3699 case 'V':
3700 if (given & (1 << 6))
3701 goto Q;
3702 /* FALLTHROUGH */
3703 case 'D':
3704 func (stream, "d%ld", value);
3705 break;
3706 case 'Q':
3707 Q:
3708 if (value & 1)
3709 func (stream, "<illegal reg q%ld.5>", value >> 1);
3710 else
3711 func (stream, "q%ld", value >> 1);
3712 break;
3713 case 'd':
3714 func (stream, "%ld", value);
3715 value_in_comment = value;
3716 break;
3717 case 'E':
3718 {
3719 /* Converts immediate 8 bit back to float value. */
3720 unsigned floatVal = (value & 0x80) << 24
3721 | (value & 0x3F) << 19
3722 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3723
3724 /* Quarter float have a maximum value of 31.0.
3725 Get floating point value multiplied by 1e7.
3726 The maximum value stays in limit of a 32-bit int. */
3727 unsigned decVal =
3728 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3729 (16 + (value & 0xF));
3730
3731 if (!(decVal % 1000000))
3732 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3733 floatVal, value & 0x80 ? '-' : ' ',
3734 decVal / 10000000,
3735 decVal % 10000000 / 1000000);
3736 else if (!(decVal % 10000))
3737 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3738 floatVal, value & 0x80 ? '-' : ' ',
3739 decVal / 10000000,
3740 decVal % 10000000 / 10000);
3741 else
3742 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3743 floatVal, value & 0x80 ? '-' : ' ',
3744 decVal / 10000000, decVal % 10000000);
3745 break;
3746 }
3747 case 'k':
3748 {
3749 int from = (given & (1 << 7)) ? 32 : 16;
3750 func (stream, "%ld", from - value);
3751 }
3752 break;
3753
3754 case 'f':
3755 if (value > 7)
3756 func (stream, "#%s", arm_fp_const[value & 7]);
3757 else
3758 func (stream, "f%ld", value);
3759 break;
3760
3761 case 'w':
3762 if (width == 2)
3763 func (stream, "%s", iwmmxt_wwnames[value]);
3764 else
3765 func (stream, "%s", iwmmxt_wwssnames[value]);
3766 break;
3767
3768 case 'g':
3769 func (stream, "%s", iwmmxt_regnames[value]);
3770 break;
3771 case 'G':
3772 func (stream, "%s", iwmmxt_cregnames[value]);
3773 break;
3774
3775 case 'x':
3776 func (stream, "0x%lx", (value & 0xffffffffUL));
3777 break;
3778
3779 case 'c':
3780 switch (value)
3781 {
3782 case 0:
3783 func (stream, "eq");
3784 break;
3785
3786 case 1:
3787 func (stream, "vs");
3788 break;
3789
3790 case 2:
3791 func (stream, "ge");
3792 break;
3793
3794 case 3:
3795 func (stream, "gt");
3796 break;
3797
3798 default:
3799 func (stream, "??");
3800 break;
3801 }
3802 break;
3803
3804 case '`':
3805 c++;
3806 if (value == 0)
3807 func (stream, "%c", *c);
3808 break;
3809 case '\'':
3810 c++;
3811 if (value == ((1ul << width) - 1))
3812 func (stream, "%c", *c);
3813 break;
3814 case '?':
3815 func (stream, "%c", c[(1 << width) - (int) value]);
3816 c += 1 << width;
3817 break;
3818 default:
3819 abort ();
3820 }
3821 break;
3822
3823 case 'y':
3824 case 'z':
3825 {
3826 int single = *c++ == 'y';
3827 int regno;
3828
3829 switch (*c)
3830 {
3831 case '4': /* Sm pair */
3832 case '0': /* Sm, Dm */
3833 regno = given & 0x0000000f;
3834 if (single)
3835 {
3836 regno <<= 1;
3837 regno += (given >> 5) & 1;
3838 }
3839 else
3840 regno += ((given >> 5) & 1) << 4;
3841 break;
3842
3843 case '1': /* Sd, Dd */
3844 regno = (given >> 12) & 0x0000000f;
3845 if (single)
3846 {
3847 regno <<= 1;
3848 regno += (given >> 22) & 1;
3849 }
3850 else
3851 regno += ((given >> 22) & 1) << 4;
3852 break;
3853
3854 case '2': /* Sn, Dn */
3855 regno = (given >> 16) & 0x0000000f;
3856 if (single)
3857 {
3858 regno <<= 1;
3859 regno += (given >> 7) & 1;
3860 }
3861 else
3862 regno += ((given >> 7) & 1) << 4;
3863 break;
3864
3865 case '3': /* List */
3866 func (stream, "{");
3867 regno = (given >> 12) & 0x0000000f;
3868 if (single)
3869 {
3870 regno <<= 1;
3871 regno += (given >> 22) & 1;
3872 }
3873 else
3874 regno += ((given >> 22) & 1) << 4;
3875 break;
3876
3877 default:
3878 abort ();
3879 }
3880
3881 func (stream, "%c%d", single ? 's' : 'd', regno);
3882
3883 if (*c == '3')
3884 {
3885 int count = given & 0xff;
3886
3887 if (single == 0)
3888 count >>= 1;
3889
3890 if (--count)
3891 {
3892 func (stream, "-%c%d",
3893 single ? 's' : 'd',
3894 regno + count);
3895 }
3896
3897 func (stream, "}");
3898 }
3899 else if (*c == '4')
3900 func (stream, ", %c%d", single ? 's' : 'd',
3901 regno + 1);
3902 }
3903 break;
3904
3905 case 'L':
3906 switch (given & 0x00400100)
3907 {
3908 case 0x00000000: func (stream, "b"); break;
3909 case 0x00400000: func (stream, "h"); break;
3910 case 0x00000100: func (stream, "w"); break;
3911 case 0x00400100: func (stream, "d"); break;
3912 default:
3913 break;
3914 }
3915 break;
3916
3917 case 'Z':
3918 {
3919 /* given (20, 23) | given (0, 3) */
3920 value = ((given >> 16) & 0xf0) | (given & 0xf);
3921 func (stream, "%d", (int) value);
3922 }
3923 break;
3924
3925 case 'l':
3926 /* This is like the 'A' operator, except that if
3927 the width field "M" is zero, then the offset is
3928 *not* multiplied by four. */
3929 {
3930 int offset = given & 0xff;
3931 int multiplier = (given & 0x00000100) ? 4 : 1;
3932
3933 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3934
3935 if (multiplier > 1)
3936 {
3937 value_in_comment = offset * multiplier;
3938 if (NEGATIVE_BIT_SET)
3939 value_in_comment = - value_in_comment;
3940 }
3941
3942 if (offset)
3943 {
3944 if (PRE_BIT_SET)
3945 func (stream, ", #%s%d]%s",
3946 NEGATIVE_BIT_SET ? "-" : "",
3947 offset * multiplier,
3948 WRITEBACK_BIT_SET ? "!" : "");
3949 else
3950 func (stream, "], #%s%d",
3951 NEGATIVE_BIT_SET ? "-" : "",
3952 offset * multiplier);
3953 }
3954 else
3955 func (stream, "]");
3956 }
3957 break;
3958
3959 case 'r':
3960 {
3961 int imm4 = (given >> 4) & 0xf;
3962 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3963 int ubit = ! NEGATIVE_BIT_SET;
3964 const char *rm = arm_regnames [given & 0xf];
3965 const char *rn = arm_regnames [(given >> 16) & 0xf];
3966
3967 switch (puw_bits)
3968 {
3969 case 1:
3970 case 3:
3971 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3972 if (imm4)
3973 func (stream, ", lsl #%d", imm4);
3974 break;
3975
3976 case 4:
3977 case 5:
3978 case 6:
3979 case 7:
3980 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3981 if (imm4 > 0)
3982 func (stream, ", lsl #%d", imm4);
3983 func (stream, "]");
3984 if (puw_bits == 5 || puw_bits == 7)
3985 func (stream, "!");
3986 break;
3987
3988 default:
3989 func (stream, "INVALID");
3990 }
3991 }
3992 break;
3993
3994 case 'i':
3995 {
3996 long imm5;
3997 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3998 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3999 }
4000 break;
4001
4002 default:
4003 abort ();
4004 }
4005 }
4006 }
4007 else
4008 func (stream, "%c", *c);
4009 }
4010
4011 if (value_in_comment > 32 || value_in_comment < -16)
4012 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
4013
4014 if (is_unpredictable)
4015 func (stream, UNPREDICTABLE_INSTRUCTION);
4016
4017 return TRUE;
4018 }
4019 return FALSE;
4020 }
4021
4022 /* Decodes and prints ARM addressing modes. Returns the offset
4023 used in the address, if any, if it is worthwhile printing the
4024 offset as a hexadecimal value in a comment at the end of the
4025 line of disassembly. */
4026
4027 static signed long
4028 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4029 {
4030 void *stream = info->stream;
4031 fprintf_ftype func = info->fprintf_func;
4032 bfd_vma offset = 0;
4033
4034 if (((given & 0x000f0000) == 0x000f0000)
4035 && ((given & 0x02000000) == 0))
4036 {
4037 offset = given & 0xfff;
4038
4039 func (stream, "[pc");
4040
4041 if (PRE_BIT_SET)
4042 {
4043 /* Pre-indexed. Elide offset of positive zero when
4044 non-writeback. */
4045 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4046 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4047
4048 if (NEGATIVE_BIT_SET)
4049 offset = -offset;
4050
4051 offset += pc + 8;
4052
4053 /* Cope with the possibility of write-back
4054 being used. Probably a very dangerous thing
4055 for the programmer to do, but who are we to
4056 argue ? */
4057 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4058 }
4059 else /* Post indexed. */
4060 {
4061 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4062
4063 /* Ie ignore the offset. */
4064 offset = pc + 8;
4065 }
4066
4067 func (stream, "\t; ");
4068 info->print_address_func (offset, info);
4069 offset = 0;
4070 }
4071 else
4072 {
4073 func (stream, "[%s",
4074 arm_regnames[(given >> 16) & 0xf]);
4075
4076 if (PRE_BIT_SET)
4077 {
4078 if ((given & 0x02000000) == 0)
4079 {
4080 /* Elide offset of positive zero when non-writeback. */
4081 offset = given & 0xfff;
4082 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4083 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4084 }
4085 else
4086 {
4087 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4088 arm_decode_shift (given, func, stream, TRUE);
4089 }
4090
4091 func (stream, "]%s",
4092 WRITEBACK_BIT_SET ? "!" : "");
4093 }
4094 else
4095 {
4096 if ((given & 0x02000000) == 0)
4097 {
4098 /* Always show offset. */
4099 offset = given & 0xfff;
4100 func (stream, "], #%s%d",
4101 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4102 }
4103 else
4104 {
4105 func (stream, "], %s",
4106 NEGATIVE_BIT_SET ? "-" : "");
4107 arm_decode_shift (given, func, stream, TRUE);
4108 }
4109 }
4110 if (NEGATIVE_BIT_SET)
4111 offset = -offset;
4112 }
4113
4114 return (signed long) offset;
4115 }
4116
4117 /* Print one neon instruction on INFO->STREAM.
4118 Return TRUE if the instuction matched, FALSE if this is not a
4119 recognised neon instruction. */
4120
4121 static bfd_boolean
4122 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4123 {
4124 const struct opcode32 *insn;
4125 void *stream = info->stream;
4126 fprintf_ftype func = info->fprintf_func;
4127
4128 if (thumb)
4129 {
4130 if ((given & 0xef000000) == 0xef000000)
4131 {
4132 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
4133 unsigned long bit28 = given & (1 << 28);
4134
4135 given &= 0x00ffffff;
4136 if (bit28)
4137 given |= 0xf3000000;
4138 else
4139 given |= 0xf2000000;
4140 }
4141 else if ((given & 0xff000000) == 0xf9000000)
4142 given ^= 0xf9000000 ^ 0xf4000000;
4143 else
4144 return FALSE;
4145 }
4146
4147 for (insn = neon_opcodes; insn->assembler; insn++)
4148 {
4149 if ((given & insn->mask) == insn->value)
4150 {
4151 signed long value_in_comment = 0;
4152 bfd_boolean is_unpredictable = FALSE;
4153 const char *c;
4154
4155 for (c = insn->assembler; *c; c++)
4156 {
4157 if (*c == '%')
4158 {
4159 switch (*++c)
4160 {
4161 case '%':
4162 func (stream, "%%");
4163 break;
4164
4165 case 'u':
4166 if (thumb && ifthen_state)
4167 is_unpredictable = TRUE;
4168
4169 /* Fall through. */
4170 case 'c':
4171 if (thumb && ifthen_state)
4172 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4173 break;
4174
4175 case 'A':
4176 {
4177 static const unsigned char enc[16] =
4178 {
4179 0x4, 0x14, /* st4 0,1 */
4180 0x4, /* st1 2 */
4181 0x4, /* st2 3 */
4182 0x3, /* st3 4 */
4183 0x13, /* st3 5 */
4184 0x3, /* st1 6 */
4185 0x1, /* st1 7 */
4186 0x2, /* st2 8 */
4187 0x12, /* st2 9 */
4188 0x2, /* st1 10 */
4189 0, 0, 0, 0, 0
4190 };
4191 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4192 int rn = ((given >> 16) & 0xf);
4193 int rm = ((given >> 0) & 0xf);
4194 int align = ((given >> 4) & 0x3);
4195 int type = ((given >> 8) & 0xf);
4196 int n = enc[type] & 0xf;
4197 int stride = (enc[type] >> 4) + 1;
4198 int ix;
4199
4200 func (stream, "{");
4201 if (stride > 1)
4202 for (ix = 0; ix != n; ix++)
4203 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4204 else if (n == 1)
4205 func (stream, "d%d", rd);
4206 else
4207 func (stream, "d%d-d%d", rd, rd + n - 1);
4208 func (stream, "}, [%s", arm_regnames[rn]);
4209 if (align)
4210 func (stream, " :%d", 32 << align);
4211 func (stream, "]");
4212 if (rm == 0xd)
4213 func (stream, "!");
4214 else if (rm != 0xf)
4215 func (stream, ", %s", arm_regnames[rm]);
4216 }
4217 break;
4218
4219 case 'B':
4220 {
4221 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4222 int rn = ((given >> 16) & 0xf);
4223 int rm = ((given >> 0) & 0xf);
4224 int idx_align = ((given >> 4) & 0xf);
4225 int align = 0;
4226 int size = ((given >> 10) & 0x3);
4227 int idx = idx_align >> (size + 1);
4228 int length = ((given >> 8) & 3) + 1;
4229 int stride = 1;
4230 int i;
4231
4232 if (length > 1 && size > 0)
4233 stride = (idx_align & (1 << size)) ? 2 : 1;
4234
4235 switch (length)
4236 {
4237 case 1:
4238 {
4239 int amask = (1 << size) - 1;
4240 if ((idx_align & (1 << size)) != 0)
4241 return FALSE;
4242 if (size > 0)
4243 {
4244 if ((idx_align & amask) == amask)
4245 align = 8 << size;
4246 else if ((idx_align & amask) != 0)
4247 return FALSE;
4248 }
4249 }
4250 break;
4251
4252 case 2:
4253 if (size == 2 && (idx_align & 2) != 0)
4254 return FALSE;
4255 align = (idx_align & 1) ? 16 << size : 0;
4256 break;
4257
4258 case 3:
4259 if ((size == 2 && (idx_align & 3) != 0)
4260 || (idx_align & 1) != 0)
4261 return FALSE;
4262 break;
4263
4264 case 4:
4265 if (size == 2)
4266 {
4267 if ((idx_align & 3) == 3)
4268 return FALSE;
4269 align = (idx_align & 3) * 64;
4270 }
4271 else
4272 align = (idx_align & 1) ? 32 << size : 0;
4273 break;
4274
4275 default:
4276 abort ();
4277 }
4278
4279 func (stream, "{");
4280 for (i = 0; i < length; i++)
4281 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4282 rd + i * stride, idx);
4283 func (stream, "}, [%s", arm_regnames[rn]);
4284 if (align)
4285 func (stream, " :%d", align);
4286 func (stream, "]");
4287 if (rm == 0xd)
4288 func (stream, "!");
4289 else if (rm != 0xf)
4290 func (stream, ", %s", arm_regnames[rm]);
4291 }
4292 break;
4293
4294 case 'C':
4295 {
4296 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4297 int rn = ((given >> 16) & 0xf);
4298 int rm = ((given >> 0) & 0xf);
4299 int align = ((given >> 4) & 0x1);
4300 int size = ((given >> 6) & 0x3);
4301 int type = ((given >> 8) & 0x3);
4302 int n = type + 1;
4303 int stride = ((given >> 5) & 0x1);
4304 int ix;
4305
4306 if (stride && (n == 1))
4307 n++;
4308 else
4309 stride++;
4310
4311 func (stream, "{");
4312 if (stride > 1)
4313 for (ix = 0; ix != n; ix++)
4314 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4315 else if (n == 1)
4316 func (stream, "d%d[]", rd);
4317 else
4318 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4319 func (stream, "}, [%s", arm_regnames[rn]);
4320 if (align)
4321 {
4322 align = (8 * (type + 1)) << size;
4323 if (type == 3)
4324 align = (size > 1) ? align >> 1 : align;
4325 if (type == 2 || (type == 0 && !size))
4326 func (stream, " :<bad align %d>", align);
4327 else
4328 func (stream, " :%d", align);
4329 }
4330 func (stream, "]");
4331 if (rm == 0xd)
4332 func (stream, "!");
4333 else if (rm != 0xf)
4334 func (stream, ", %s", arm_regnames[rm]);
4335 }
4336 break;
4337
4338 case 'D':
4339 {
4340 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4341 int size = (given >> 20) & 3;
4342 int reg = raw_reg & ((4 << size) - 1);
4343 int ix = raw_reg >> size >> 2;
4344
4345 func (stream, "d%d[%d]", reg, ix);
4346 }
4347 break;
4348
4349 case 'E':
4350 /* Neon encoded constant for mov, mvn, vorr, vbic. */
4351 {
4352 int bits = 0;
4353 int cmode = (given >> 8) & 0xf;
4354 int op = (given >> 5) & 0x1;
4355 unsigned long value = 0, hival = 0;
4356 unsigned shift;
4357 int size = 0;
4358 int isfloat = 0;
4359
4360 bits |= ((given >> 24) & 1) << 7;
4361 bits |= ((given >> 16) & 7) << 4;
4362 bits |= ((given >> 0) & 15) << 0;
4363
4364 if (cmode < 8)
4365 {
4366 shift = (cmode >> 1) & 3;
4367 value = (unsigned long) bits << (8 * shift);
4368 size = 32;
4369 }
4370 else if (cmode < 12)
4371 {
4372 shift = (cmode >> 1) & 1;
4373 value = (unsigned long) bits << (8 * shift);
4374 size = 16;
4375 }
4376 else if (cmode < 14)
4377 {
4378 shift = (cmode & 1) + 1;
4379 value = (unsigned long) bits << (8 * shift);
4380 value |= (1ul << (8 * shift)) - 1;
4381 size = 32;
4382 }
4383 else if (cmode == 14)
4384 {
4385 if (op)
4386 {
4387 /* Bit replication into bytes. */
4388 int ix;
4389 unsigned long mask;
4390
4391 value = 0;
4392 hival = 0;
4393 for (ix = 7; ix >= 0; ix--)
4394 {
4395 mask = ((bits >> ix) & 1) ? 0xff : 0;
4396 if (ix <= 3)
4397 value = (value << 8) | mask;
4398 else
4399 hival = (hival << 8) | mask;
4400 }
4401 size = 64;
4402 }
4403 else
4404 {
4405 /* Byte replication. */
4406 value = (unsigned long) bits;
4407 size = 8;
4408 }
4409 }
4410 else if (!op)
4411 {
4412 /* Floating point encoding. */
4413 int tmp;
4414
4415 value = (unsigned long) (bits & 0x7f) << 19;
4416 value |= (unsigned long) (bits & 0x80) << 24;
4417 tmp = bits & 0x40 ? 0x3c : 0x40;
4418 value |= (unsigned long) tmp << 24;
4419 size = 32;
4420 isfloat = 1;
4421 }
4422 else
4423 {
4424 func (stream, "<illegal constant %.8x:%x:%x>",
4425 bits, cmode, op);
4426 size = 32;
4427 break;
4428 }
4429 switch (size)
4430 {
4431 case 8:
4432 func (stream, "#%ld\t; 0x%.2lx", value, value);
4433 break;
4434
4435 case 16:
4436 func (stream, "#%ld\t; 0x%.4lx", value, value);
4437 break;
4438
4439 case 32:
4440 if (isfloat)
4441 {
4442 unsigned char valbytes[4];
4443 double fvalue;
4444
4445 /* Do this a byte at a time so we don't have to
4446 worry about the host's endianness. */
4447 valbytes[0] = value & 0xff;
4448 valbytes[1] = (value >> 8) & 0xff;
4449 valbytes[2] = (value >> 16) & 0xff;
4450 valbytes[3] = (value >> 24) & 0xff;
4451
4452 floatformat_to_double
4453 (& floatformat_ieee_single_little, valbytes,
4454 & fvalue);
4455
4456 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4457 value);
4458 }
4459 else
4460 func (stream, "#%ld\t; 0x%.8lx",
4461 (long) (((value & 0x80000000L) != 0)
4462 ? value | ~0xffffffffL : value),
4463 value);
4464 break;
4465
4466 case 64:
4467 func (stream, "#0x%.8lx%.8lx", hival, value);
4468 break;
4469
4470 default:
4471 abort ();
4472 }
4473 }
4474 break;
4475
4476 case 'F':
4477 {
4478 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4479 int num = (given >> 8) & 0x3;
4480
4481 if (!num)
4482 func (stream, "{d%d}", regno);
4483 else if (num + regno >= 32)
4484 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4485 else
4486 func (stream, "{d%d-d%d}", regno, regno + num);
4487 }
4488 break;
4489
4490
4491 case '0': case '1': case '2': case '3': case '4':
4492 case '5': case '6': case '7': case '8': case '9':
4493 {
4494 int width;
4495 unsigned long value;
4496
4497 c = arm_decode_bitfield (c, given, &value, &width);
4498
4499 switch (*c)
4500 {
4501 case 'r':
4502 func (stream, "%s", arm_regnames[value]);
4503 break;
4504 case 'd':
4505 func (stream, "%ld", value);
4506 value_in_comment = value;
4507 break;
4508 case 'e':
4509 func (stream, "%ld", (1ul << width) - value);
4510 break;
4511
4512 case 'S':
4513 case 'T':
4514 case 'U':
4515 /* Various width encodings. */
4516 {
4517 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4518 int limit;
4519 unsigned low, high;
4520
4521 c++;
4522 if (*c >= '0' && *c <= '9')
4523 limit = *c - '0';
4524 else if (*c >= 'a' && *c <= 'f')
4525 limit = *c - 'a' + 10;
4526 else
4527 abort ();
4528 low = limit >> 2;
4529 high = limit & 3;
4530
4531 if (value < low || value > high)
4532 func (stream, "<illegal width %d>", base << value);
4533 else
4534 func (stream, "%d", base << value);
4535 }
4536 break;
4537 case 'R':
4538 if (given & (1 << 6))
4539 goto Q;
4540 /* FALLTHROUGH */
4541 case 'D':
4542 func (stream, "d%ld", value);
4543 break;
4544 case 'Q':
4545 Q:
4546 if (value & 1)
4547 func (stream, "<illegal reg q%ld.5>", value >> 1);
4548 else
4549 func (stream, "q%ld", value >> 1);
4550 break;
4551
4552 case '`':
4553 c++;
4554 if (value == 0)
4555 func (stream, "%c", *c);
4556 break;
4557 case '\'':
4558 c++;
4559 if (value == ((1ul << width) - 1))
4560 func (stream, "%c", *c);
4561 break;
4562 case '?':
4563 func (stream, "%c", c[(1 << width) - (int) value]);
4564 c += 1 << width;
4565 break;
4566 default:
4567 abort ();
4568 }
4569 break;
4570
4571 default:
4572 abort ();
4573 }
4574 }
4575 }
4576 else
4577 func (stream, "%c", *c);
4578 }
4579
4580 if (value_in_comment > 32 || value_in_comment < -16)
4581 func (stream, "\t; 0x%lx", value_in_comment);
4582
4583 if (is_unpredictable)
4584 func (stream, UNPREDICTABLE_INSTRUCTION);
4585
4586 return TRUE;
4587 }
4588 }
4589 return FALSE;
4590 }
4591
4592 /* Return the name of a v7A special register. */
4593
4594 static const char *
4595 banked_regname (unsigned reg)
4596 {
4597 switch (reg)
4598 {
4599 case 15: return "CPSR";
4600 case 32: return "R8_usr";
4601 case 33: return "R9_usr";
4602 case 34: return "R10_usr";
4603 case 35: return "R11_usr";
4604 case 36: return "R12_usr";
4605 case 37: return "SP_usr";
4606 case 38: return "LR_usr";
4607 case 40: return "R8_fiq";
4608 case 41: return "R9_fiq";
4609 case 42: return "R10_fiq";
4610 case 43: return "R11_fiq";
4611 case 44: return "R12_fiq";
4612 case 45: return "SP_fiq";
4613 case 46: return "LR_fiq";
4614 case 48: return "LR_irq";
4615 case 49: return "SP_irq";
4616 case 50: return "LR_svc";
4617 case 51: return "SP_svc";
4618 case 52: return "LR_abt";
4619 case 53: return "SP_abt";
4620 case 54: return "LR_und";
4621 case 55: return "SP_und";
4622 case 60: return "LR_mon";
4623 case 61: return "SP_mon";
4624 case 62: return "ELR_hyp";
4625 case 63: return "SP_hyp";
4626 case 79: return "SPSR";
4627 case 110: return "SPSR_fiq";
4628 case 112: return "SPSR_irq";
4629 case 114: return "SPSR_svc";
4630 case 116: return "SPSR_abt";
4631 case 118: return "SPSR_und";
4632 case 124: return "SPSR_mon";
4633 case 126: return "SPSR_hyp";
4634 default: return NULL;
4635 }
4636 }
4637
4638 /* Return the name of the DMB/DSB option. */
4639 static const char *
4640 data_barrier_option (unsigned option)
4641 {
4642 switch (option & 0xf)
4643 {
4644 case 0xf: return "sy";
4645 case 0xe: return "st";
4646 case 0xd: return "ld";
4647 case 0xb: return "ish";
4648 case 0xa: return "ishst";
4649 case 0x9: return "ishld";
4650 case 0x7: return "un";
4651 case 0x6: return "unst";
4652 case 0x5: return "nshld";
4653 case 0x3: return "osh";
4654 case 0x2: return "oshst";
4655 case 0x1: return "oshld";
4656 default: return NULL;
4657 }
4658 }
4659
4660 /* Print one ARM instruction from PC on INFO->STREAM. */
4661
4662 static void
4663 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4664 {
4665 const struct opcode32 *insn;
4666 void *stream = info->stream;
4667 fprintf_ftype func = info->fprintf_func;
4668 struct arm_private_data *private_data = info->private_data;
4669
4670 if (print_insn_coprocessor (pc, info, given, FALSE))
4671 return;
4672
4673 if (print_insn_neon (info, given, FALSE))
4674 return;
4675
4676 for (insn = arm_opcodes; insn->assembler; insn++)
4677 {
4678 if ((given & insn->mask) != insn->value)
4679 continue;
4680
4681 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4682 continue;
4683
4684 /* Special case: an instruction with all bits set in the condition field
4685 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4686 or by the catchall at the end of the table. */
4687 if ((given & 0xF0000000) != 0xF0000000
4688 || (insn->mask & 0xF0000000) == 0xF0000000
4689 || (insn->mask == 0 && insn->value == 0))
4690 {
4691 unsigned long u_reg = 16;
4692 unsigned long U_reg = 16;
4693 bfd_boolean is_unpredictable = FALSE;
4694 signed long value_in_comment = 0;
4695 const char *c;
4696
4697 for (c = insn->assembler; *c; c++)
4698 {
4699 if (*c == '%')
4700 {
4701 bfd_boolean allow_unpredictable = FALSE;
4702
4703 switch (*++c)
4704 {
4705 case '%':
4706 func (stream, "%%");
4707 break;
4708
4709 case 'a':
4710 value_in_comment = print_arm_address (pc, info, given);
4711 break;
4712
4713 case 'P':
4714 /* Set P address bit and use normal address
4715 printing routine. */
4716 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4717 break;
4718
4719 case 'S':
4720 allow_unpredictable = TRUE;
4721 /* Fall through. */
4722 case 's':
4723 if ((given & 0x004f0000) == 0x004f0000)
4724 {
4725 /* PC relative with immediate offset. */
4726 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4727
4728 if (PRE_BIT_SET)
4729 {
4730 /* Elide positive zero offset. */
4731 if (offset || NEGATIVE_BIT_SET)
4732 func (stream, "[pc, #%s%d]\t; ",
4733 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4734 else
4735 func (stream, "[pc]\t; ");
4736 if (NEGATIVE_BIT_SET)
4737 offset = -offset;
4738 info->print_address_func (offset + pc + 8, info);
4739 }
4740 else
4741 {
4742 /* Always show the offset. */
4743 func (stream, "[pc], #%s%d",
4744 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4745 if (! allow_unpredictable)
4746 is_unpredictable = TRUE;
4747 }
4748 }
4749 else
4750 {
4751 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4752
4753 func (stream, "[%s",
4754 arm_regnames[(given >> 16) & 0xf]);
4755
4756 if (PRE_BIT_SET)
4757 {
4758 if (IMMEDIATE_BIT_SET)
4759 {
4760 /* Elide offset for non-writeback
4761 positive zero. */
4762 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4763 || offset)
4764 func (stream, ", #%s%d",
4765 NEGATIVE_BIT_SET ? "-" : "", offset);
4766
4767 if (NEGATIVE_BIT_SET)
4768 offset = -offset;
4769
4770 value_in_comment = offset;
4771 }
4772 else
4773 {
4774 /* Register Offset or Register Pre-Indexed. */
4775 func (stream, ", %s%s",
4776 NEGATIVE_BIT_SET ? "-" : "",
4777 arm_regnames[given & 0xf]);
4778
4779 /* Writing back to the register that is the source/
4780 destination of the load/store is unpredictable. */
4781 if (! allow_unpredictable
4782 && WRITEBACK_BIT_SET
4783 && ((given & 0xf) == ((given >> 12) & 0xf)))
4784 is_unpredictable = TRUE;
4785 }
4786
4787 func (stream, "]%s",
4788 WRITEBACK_BIT_SET ? "!" : "");
4789 }
4790 else
4791 {
4792 if (IMMEDIATE_BIT_SET)
4793 {
4794 /* Immediate Post-indexed. */
4795 /* PR 10924: Offset must be printed, even if it is zero. */
4796 func (stream, "], #%s%d",
4797 NEGATIVE_BIT_SET ? "-" : "", offset);
4798 if (NEGATIVE_BIT_SET)
4799 offset = -offset;
4800 value_in_comment = offset;
4801 }
4802 else
4803 {
4804 /* Register Post-indexed. */
4805 func (stream, "], %s%s",
4806 NEGATIVE_BIT_SET ? "-" : "",
4807 arm_regnames[given & 0xf]);
4808
4809 /* Writing back to the register that is the source/
4810 destination of the load/store is unpredictable. */
4811 if (! allow_unpredictable
4812 && (given & 0xf) == ((given >> 12) & 0xf))
4813 is_unpredictable = TRUE;
4814 }
4815
4816 if (! allow_unpredictable)
4817 {
4818 /* Writeback is automatically implied by post- addressing.
4819 Setting the W bit is unnecessary and ARM specify it as
4820 being unpredictable. */
4821 if (WRITEBACK_BIT_SET
4822 /* Specifying the PC register as the post-indexed
4823 registers is also unpredictable. */
4824 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4825 is_unpredictable = TRUE;
4826 }
4827 }
4828 }
4829 break;
4830
4831 case 'b':
4832 {
4833 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4834 info->print_address_func (disp * 4 + pc + 8, info);
4835 }
4836 break;
4837
4838 case 'c':
4839 if (((given >> 28) & 0xf) != 0xe)
4840 func (stream, "%s",
4841 arm_conditional [(given >> 28) & 0xf]);
4842 break;
4843
4844 case 'm':
4845 {
4846 int started = 0;
4847 int reg;
4848
4849 func (stream, "{");
4850 for (reg = 0; reg < 16; reg++)
4851 if ((given & (1 << reg)) != 0)
4852 {
4853 if (started)
4854 func (stream, ", ");
4855 started = 1;
4856 func (stream, "%s", arm_regnames[reg]);
4857 }
4858 func (stream, "}");
4859 if (! started)
4860 is_unpredictable = TRUE;
4861 }
4862 break;
4863
4864 case 'q':
4865 arm_decode_shift (given, func, stream, FALSE);
4866 break;
4867
4868 case 'o':
4869 if ((given & 0x02000000) != 0)
4870 {
4871 unsigned int rotate = (given & 0xf00) >> 7;
4872 unsigned int immed = (given & 0xff);
4873 unsigned int a, i;
4874
4875 a = (((immed << (32 - rotate))
4876 | (immed >> rotate)) & 0xffffffff);
4877 /* If there is another encoding with smaller rotate,
4878 the rotate should be specified directly. */
4879 for (i = 0; i < 32; i += 2)
4880 if ((a << i | a >> (32 - i)) <= 0xff)
4881 break;
4882
4883 if (i != rotate)
4884 func (stream, "#%d, %d", immed, rotate);
4885 else
4886 func (stream, "#%d", a);
4887 value_in_comment = a;
4888 }
4889 else
4890 arm_decode_shift (given, func, stream, TRUE);
4891 break;
4892
4893 case 'p':
4894 if ((given & 0x0000f000) == 0x0000f000)
4895 {
4896 arm_feature_set arm_ext_v6 =
4897 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4898
4899 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4900 mechanism for setting PSR flag bits. They are
4901 obsolete in V6 onwards. */
4902 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4903 arm_ext_v6))
4904 func (stream, "p");
4905 else
4906 is_unpredictable = TRUE;
4907 }
4908 break;
4909
4910 case 't':
4911 if ((given & 0x01200000) == 0x00200000)
4912 func (stream, "t");
4913 break;
4914
4915 case 'A':
4916 {
4917 int offset = given & 0xff;
4918
4919 value_in_comment = offset * 4;
4920 if (NEGATIVE_BIT_SET)
4921 value_in_comment = - value_in_comment;
4922
4923 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4924
4925 if (PRE_BIT_SET)
4926 {
4927 if (offset)
4928 func (stream, ", #%d]%s",
4929 (int) value_in_comment,
4930 WRITEBACK_BIT_SET ? "!" : "");
4931 else
4932 func (stream, "]");
4933 }
4934 else
4935 {
4936 func (stream, "]");
4937
4938 if (WRITEBACK_BIT_SET)
4939 {
4940 if (offset)
4941 func (stream, ", #%d", (int) value_in_comment);
4942 }
4943 else
4944 {
4945 func (stream, ", {%d}", (int) offset);
4946 value_in_comment = offset;
4947 }
4948 }
4949 }
4950 break;
4951
4952 case 'B':
4953 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4954 {
4955 bfd_vma address;
4956 bfd_vma offset = 0;
4957
4958 if (! NEGATIVE_BIT_SET)
4959 /* Is signed, hi bits should be ones. */
4960 offset = (-1) ^ 0x00ffffff;
4961
4962 /* Offset is (SignExtend(offset field)<<2). */
4963 offset += given & 0x00ffffff;
4964 offset <<= 2;
4965 address = offset + pc + 8;
4966
4967 if (given & 0x01000000)
4968 /* H bit allows addressing to 2-byte boundaries. */
4969 address += 2;
4970
4971 info->print_address_func (address, info);
4972 }
4973 break;
4974
4975 case 'C':
4976 if ((given & 0x02000200) == 0x200)
4977 {
4978 const char * name;
4979 unsigned sysm = (given & 0x004f0000) >> 16;
4980
4981 sysm |= (given & 0x300) >> 4;
4982 name = banked_regname (sysm);
4983
4984 if (name != NULL)
4985 func (stream, "%s", name);
4986 else
4987 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4988 }
4989 else
4990 {
4991 func (stream, "%cPSR_",
4992 (given & 0x00400000) ? 'S' : 'C');
4993 if (given & 0x80000)
4994 func (stream, "f");
4995 if (given & 0x40000)
4996 func (stream, "s");
4997 if (given & 0x20000)
4998 func (stream, "x");
4999 if (given & 0x10000)
5000 func (stream, "c");
5001 }
5002 break;
5003
5004 case 'U':
5005 if ((given & 0xf0) == 0x60)
5006 {
5007 switch (given & 0xf)
5008 {
5009 case 0xf: func (stream, "sy"); break;
5010 default:
5011 func (stream, "#%d", (int) given & 0xf);
5012 break;
5013 }
5014 }
5015 else
5016 {
5017 const char * opt = data_barrier_option (given & 0xf);
5018 if (opt != NULL)
5019 func (stream, "%s", opt);
5020 else
5021 func (stream, "#%d", (int) given & 0xf);
5022 }
5023 break;
5024
5025 case '0': case '1': case '2': case '3': case '4':
5026 case '5': case '6': case '7': case '8': case '9':
5027 {
5028 int width;
5029 unsigned long value;
5030
5031 c = arm_decode_bitfield (c, given, &value, &width);
5032
5033 switch (*c)
5034 {
5035 case 'R':
5036 if (value == 15)
5037 is_unpredictable = TRUE;
5038 /* Fall through. */
5039 case 'r':
5040 case 'T':
5041 /* We want register + 1 when decoding T. */
5042 if (*c == 'T')
5043 ++value;
5044
5045 if (c[1] == 'u')
5046 {
5047 /* Eat the 'u' character. */
5048 ++ c;
5049
5050 if (u_reg == value)
5051 is_unpredictable = TRUE;
5052 u_reg = value;
5053 }
5054 if (c[1] == 'U')
5055 {
5056 /* Eat the 'U' character. */
5057 ++ c;
5058
5059 if (U_reg == value)
5060 is_unpredictable = TRUE;
5061 U_reg = value;
5062 }
5063 func (stream, "%s", arm_regnames[value]);
5064 break;
5065 case 'd':
5066 func (stream, "%ld", value);
5067 value_in_comment = value;
5068 break;
5069 case 'b':
5070 func (stream, "%ld", value * 8);
5071 value_in_comment = value * 8;
5072 break;
5073 case 'W':
5074 func (stream, "%ld", value + 1);
5075 value_in_comment = value + 1;
5076 break;
5077 case 'x':
5078 func (stream, "0x%08lx", value);
5079
5080 /* Some SWI instructions have special
5081 meanings. */
5082 if ((given & 0x0fffffff) == 0x0FF00000)
5083 func (stream, "\t; IMB");
5084 else if ((given & 0x0fffffff) == 0x0FF00001)
5085 func (stream, "\t; IMBRange");
5086 break;
5087 case 'X':
5088 func (stream, "%01lx", value & 0xf);
5089 value_in_comment = value;
5090 break;
5091 case '`':
5092 c++;
5093 if (value == 0)
5094 func (stream, "%c", *c);
5095 break;
5096 case '\'':
5097 c++;
5098 if (value == ((1ul << width) - 1))
5099 func (stream, "%c", *c);
5100 break;
5101 case '?':
5102 func (stream, "%c", c[(1 << width) - (int) value]);
5103 c += 1 << width;
5104 break;
5105 default:
5106 abort ();
5107 }
5108 break;
5109
5110 case 'e':
5111 {
5112 int imm;
5113
5114 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5115 func (stream, "%d", imm);
5116 value_in_comment = imm;
5117 }
5118 break;
5119
5120 case 'E':
5121 /* LSB and WIDTH fields of BFI or BFC. The machine-
5122 language instruction encodes LSB and MSB. */
5123 {
5124 long msb = (given & 0x001f0000) >> 16;
5125 long lsb = (given & 0x00000f80) >> 7;
5126 long w = msb - lsb + 1;
5127
5128 if (w > 0)
5129 func (stream, "#%lu, #%lu", lsb, w);
5130 else
5131 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5132 }
5133 break;
5134
5135 case 'R':
5136 /* Get the PSR/banked register name. */
5137 {
5138 const char * name;
5139 unsigned sysm = (given & 0x004f0000) >> 16;
5140
5141 sysm |= (given & 0x300) >> 4;
5142 name = banked_regname (sysm);
5143
5144 if (name != NULL)
5145 func (stream, "%s", name);
5146 else
5147 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5148 }
5149 break;
5150
5151 case 'V':
5152 /* 16-bit unsigned immediate from a MOVT or MOVW
5153 instruction, encoded in bits 0:11 and 15:19. */
5154 {
5155 long hi = (given & 0x000f0000) >> 4;
5156 long lo = (given & 0x00000fff);
5157 long imm16 = hi | lo;
5158
5159 func (stream, "#%lu", imm16);
5160 value_in_comment = imm16;
5161 }
5162 break;
5163
5164 default:
5165 abort ();
5166 }
5167 }
5168 }
5169 else
5170 func (stream, "%c", *c);
5171 }
5172
5173 if (value_in_comment > 32 || value_in_comment < -16)
5174 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5175
5176 if (is_unpredictable)
5177 func (stream, UNPREDICTABLE_INSTRUCTION);
5178
5179 return;
5180 }
5181 }
5182 abort ();
5183 }
5184
5185 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
5186
5187 static void
5188 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5189 {
5190 const struct opcode16 *insn;
5191 void *stream = info->stream;
5192 fprintf_ftype func = info->fprintf_func;
5193
5194 for (insn = thumb_opcodes; insn->assembler; insn++)
5195 if ((given & insn->mask) == insn->value)
5196 {
5197 signed long value_in_comment = 0;
5198 const char *c = insn->assembler;
5199
5200 for (; *c; c++)
5201 {
5202 int domaskpc = 0;
5203 int domasklr = 0;
5204
5205 if (*c != '%')
5206 {
5207 func (stream, "%c", *c);
5208 continue;
5209 }
5210
5211 switch (*++c)
5212 {
5213 case '%':
5214 func (stream, "%%");
5215 break;
5216
5217 case 'c':
5218 if (ifthen_state)
5219 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5220 break;
5221
5222 case 'C':
5223 if (ifthen_state)
5224 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5225 else
5226 func (stream, "s");
5227 break;
5228
5229 case 'I':
5230 {
5231 unsigned int tmp;
5232
5233 ifthen_next_state = given & 0xff;
5234 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5235 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5236 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5237 }
5238 break;
5239
5240 case 'x':
5241 if (ifthen_next_state)
5242 func (stream, "\t; unpredictable branch in IT block\n");
5243 break;
5244
5245 case 'X':
5246 if (ifthen_state)
5247 func (stream, "\t; unpredictable <IT:%s>",
5248 arm_conditional[IFTHEN_COND]);
5249 break;
5250
5251 case 'S':
5252 {
5253 long reg;
5254
5255 reg = (given >> 3) & 0x7;
5256 if (given & (1 << 6))
5257 reg += 8;
5258
5259 func (stream, "%s", arm_regnames[reg]);
5260 }
5261 break;
5262
5263 case 'D':
5264 {
5265 long reg;
5266
5267 reg = given & 0x7;
5268 if (given & (1 << 7))
5269 reg += 8;
5270
5271 func (stream, "%s", arm_regnames[reg]);
5272 }
5273 break;
5274
5275 case 'N':
5276 if (given & (1 << 8))
5277 domasklr = 1;
5278 /* Fall through. */
5279 case 'O':
5280 if (*c == 'O' && (given & (1 << 8)))
5281 domaskpc = 1;
5282 /* Fall through. */
5283 case 'M':
5284 {
5285 int started = 0;
5286 int reg;
5287
5288 func (stream, "{");
5289
5290 /* It would be nice if we could spot
5291 ranges, and generate the rS-rE format: */
5292 for (reg = 0; (reg < 8); reg++)
5293 if ((given & (1 << reg)) != 0)
5294 {
5295 if (started)
5296 func (stream, ", ");
5297 started = 1;
5298 func (stream, "%s", arm_regnames[reg]);
5299 }
5300
5301 if (domasklr)
5302 {
5303 if (started)
5304 func (stream, ", ");
5305 started = 1;
5306 func (stream, "%s", arm_regnames[14] /* "lr" */);
5307 }
5308
5309 if (domaskpc)
5310 {
5311 if (started)
5312 func (stream, ", ");
5313 func (stream, "%s", arm_regnames[15] /* "pc" */);
5314 }
5315
5316 func (stream, "}");
5317 }
5318 break;
5319
5320 case 'W':
5321 /* Print writeback indicator for a LDMIA. We are doing a
5322 writeback if the base register is not in the register
5323 mask. */
5324 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5325 func (stream, "!");
5326 break;
5327
5328 case 'b':
5329 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5330 {
5331 bfd_vma address = (pc + 4
5332 + ((given & 0x00f8) >> 2)
5333 + ((given & 0x0200) >> 3));
5334 info->print_address_func (address, info);
5335 }
5336 break;
5337
5338 case 's':
5339 /* Right shift immediate -- bits 6..10; 1-31 print
5340 as themselves, 0 prints as 32. */
5341 {
5342 long imm = (given & 0x07c0) >> 6;
5343 if (imm == 0)
5344 imm = 32;
5345 func (stream, "#%ld", imm);
5346 }
5347 break;
5348
5349 case '0': case '1': case '2': case '3': case '4':
5350 case '5': case '6': case '7': case '8': case '9':
5351 {
5352 int bitstart = *c++ - '0';
5353 int bitend = 0;
5354
5355 while (*c >= '0' && *c <= '9')
5356 bitstart = (bitstart * 10) + *c++ - '0';
5357
5358 switch (*c)
5359 {
5360 case '-':
5361 {
5362 bfd_vma reg;
5363
5364 c++;
5365 while (*c >= '0' && *c <= '9')
5366 bitend = (bitend * 10) + *c++ - '0';
5367 if (!bitend)
5368 abort ();
5369 reg = given >> bitstart;
5370 reg &= (2 << (bitend - bitstart)) - 1;
5371
5372 switch (*c)
5373 {
5374 case 'r':
5375 func (stream, "%s", arm_regnames[reg]);
5376 break;
5377
5378 case 'd':
5379 func (stream, "%ld", (long) reg);
5380 value_in_comment = reg;
5381 break;
5382
5383 case 'H':
5384 func (stream, "%ld", (long) (reg << 1));
5385 value_in_comment = reg << 1;
5386 break;
5387
5388 case 'W':
5389 func (stream, "%ld", (long) (reg << 2));
5390 value_in_comment = reg << 2;
5391 break;
5392
5393 case 'a':
5394 /* PC-relative address -- the bottom two
5395 bits of the address are dropped
5396 before the calculation. */
5397 info->print_address_func
5398 (((pc + 4) & ~3) + (reg << 2), info);
5399 value_in_comment = 0;
5400 break;
5401
5402 case 'x':
5403 func (stream, "0x%04lx", (long) reg);
5404 break;
5405
5406 case 'B':
5407 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5408 info->print_address_func (reg * 2 + pc + 4, info);
5409 value_in_comment = 0;
5410 break;
5411
5412 case 'c':
5413 func (stream, "%s", arm_conditional [reg]);
5414 break;
5415
5416 default:
5417 abort ();
5418 }
5419 }
5420 break;
5421
5422 case '\'':
5423 c++;
5424 if ((given & (1 << bitstart)) != 0)
5425 func (stream, "%c", *c);
5426 break;
5427
5428 case '?':
5429 ++c;
5430 if ((given & (1 << bitstart)) != 0)
5431 func (stream, "%c", *c++);
5432 else
5433 func (stream, "%c", *++c);
5434 break;
5435
5436 default:
5437 abort ();
5438 }
5439 }
5440 break;
5441
5442 default:
5443 abort ();
5444 }
5445 }
5446
5447 if (value_in_comment > 32 || value_in_comment < -16)
5448 func (stream, "\t; 0x%lx", value_in_comment);
5449 return;
5450 }
5451
5452 /* No match. */
5453 abort ();
5454 }
5455
5456 /* Return the name of an V7M special register. */
5457
5458 static const char *
5459 psr_name (int regno)
5460 {
5461 switch (regno)
5462 {
5463 case 0x0: return "APSR";
5464 case 0x1: return "IAPSR";
5465 case 0x2: return "EAPSR";
5466 case 0x3: return "PSR";
5467 case 0x5: return "IPSR";
5468 case 0x6: return "EPSR";
5469 case 0x7: return "IEPSR";
5470 case 0x8: return "MSP";
5471 case 0x9: return "PSP";
5472 case 0xa: return "MSPLIM";
5473 case 0xb: return "PSPLIM";
5474 case 0x10: return "PRIMASK";
5475 case 0x11: return "BASEPRI";
5476 case 0x12: return "BASEPRI_MAX";
5477 case 0x13: return "FAULTMASK";
5478 case 0x14: return "CONTROL";
5479 case 0x88: return "MSP_NS";
5480 case 0x89: return "PSP_NS";
5481 case 0x8a: return "MSPLIM_NS";
5482 case 0x8b: return "PSPLIM_NS";
5483 case 0x90: return "PRIMASK_NS";
5484 case 0x91: return "BASEPRI_NS";
5485 case 0x93: return "FAULTMASK_NS";
5486 case 0x94: return "CONTROL_NS";
5487 case 0x98: return "SP_NS";
5488 default: return "<unknown>";
5489 }
5490 }
5491
5492 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5493
5494 static void
5495 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5496 {
5497 const struct opcode32 *insn;
5498 void *stream = info->stream;
5499 fprintf_ftype func = info->fprintf_func;
5500
5501 if (print_insn_coprocessor (pc, info, given, TRUE))
5502 return;
5503
5504 if (print_insn_neon (info, given, TRUE))
5505 return;
5506
5507 for (insn = thumb32_opcodes; insn->assembler; insn++)
5508 if ((given & insn->mask) == insn->value)
5509 {
5510 bfd_boolean is_unpredictable = FALSE;
5511 signed long value_in_comment = 0;
5512 const char *c = insn->assembler;
5513
5514 for (; *c; c++)
5515 {
5516 if (*c != '%')
5517 {
5518 func (stream, "%c", *c);
5519 continue;
5520 }
5521
5522 switch (*++c)
5523 {
5524 case '%':
5525 func (stream, "%%");
5526 break;
5527
5528 case 'c':
5529 if (ifthen_state)
5530 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5531 break;
5532
5533 case 'x':
5534 if (ifthen_next_state)
5535 func (stream, "\t; unpredictable branch in IT block\n");
5536 break;
5537
5538 case 'X':
5539 if (ifthen_state)
5540 func (stream, "\t; unpredictable <IT:%s>",
5541 arm_conditional[IFTHEN_COND]);
5542 break;
5543
5544 case 'I':
5545 {
5546 unsigned int imm12 = 0;
5547
5548 imm12 |= (given & 0x000000ffu);
5549 imm12 |= (given & 0x00007000u) >> 4;
5550 imm12 |= (given & 0x04000000u) >> 15;
5551 func (stream, "#%u", imm12);
5552 value_in_comment = imm12;
5553 }
5554 break;
5555
5556 case 'M':
5557 {
5558 unsigned int bits = 0, imm, imm8, mod;
5559
5560 bits |= (given & 0x000000ffu);
5561 bits |= (given & 0x00007000u) >> 4;
5562 bits |= (given & 0x04000000u) >> 15;
5563 imm8 = (bits & 0x0ff);
5564 mod = (bits & 0xf00) >> 8;
5565 switch (mod)
5566 {
5567 case 0: imm = imm8; break;
5568 case 1: imm = ((imm8 << 16) | imm8); break;
5569 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5570 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5571 default:
5572 mod = (bits & 0xf80) >> 7;
5573 imm8 = (bits & 0x07f) | 0x80;
5574 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5575 }
5576 func (stream, "#%u", imm);
5577 value_in_comment = imm;
5578 }
5579 break;
5580
5581 case 'J':
5582 {
5583 unsigned int imm = 0;
5584
5585 imm |= (given & 0x000000ffu);
5586 imm |= (given & 0x00007000u) >> 4;
5587 imm |= (given & 0x04000000u) >> 15;
5588 imm |= (given & 0x000f0000u) >> 4;
5589 func (stream, "#%u", imm);
5590 value_in_comment = imm;
5591 }
5592 break;
5593
5594 case 'K':
5595 {
5596 unsigned int imm = 0;
5597
5598 imm |= (given & 0x000f0000u) >> 16;
5599 imm |= (given & 0x00000ff0u) >> 0;
5600 imm |= (given & 0x0000000fu) << 12;
5601 func (stream, "#%u", imm);
5602 value_in_comment = imm;
5603 }
5604 break;
5605
5606 case 'H':
5607 {
5608 unsigned int imm = 0;
5609
5610 imm |= (given & 0x000f0000u) >> 4;
5611 imm |= (given & 0x00000fffu) >> 0;
5612 func (stream, "#%u", imm);
5613 value_in_comment = imm;
5614 }
5615 break;
5616
5617 case 'V':
5618 {
5619 unsigned int imm = 0;
5620
5621 imm |= (given & 0x00000fffu);
5622 imm |= (given & 0x000f0000u) >> 4;
5623 func (stream, "#%u", imm);
5624 value_in_comment = imm;
5625 }
5626 break;
5627
5628 case 'S':
5629 {
5630 unsigned int reg = (given & 0x0000000fu);
5631 unsigned int stp = (given & 0x00000030u) >> 4;
5632 unsigned int imm = 0;
5633 imm |= (given & 0x000000c0u) >> 6;
5634 imm |= (given & 0x00007000u) >> 10;
5635
5636 func (stream, "%s", arm_regnames[reg]);
5637 switch (stp)
5638 {
5639 case 0:
5640 if (imm > 0)
5641 func (stream, ", lsl #%u", imm);
5642 break;
5643
5644 case 1:
5645 if (imm == 0)
5646 imm = 32;
5647 func (stream, ", lsr #%u", imm);
5648 break;
5649
5650 case 2:
5651 if (imm == 0)
5652 imm = 32;
5653 func (stream, ", asr #%u", imm);
5654 break;
5655
5656 case 3:
5657 if (imm == 0)
5658 func (stream, ", rrx");
5659 else
5660 func (stream, ", ror #%u", imm);
5661 }
5662 }
5663 break;
5664
5665 case 'a':
5666 {
5667 unsigned int Rn = (given & 0x000f0000) >> 16;
5668 unsigned int U = ! NEGATIVE_BIT_SET;
5669 unsigned int op = (given & 0x00000f00) >> 8;
5670 unsigned int i12 = (given & 0x00000fff);
5671 unsigned int i8 = (given & 0x000000ff);
5672 bfd_boolean writeback = FALSE, postind = FALSE;
5673 bfd_vma offset = 0;
5674
5675 func (stream, "[%s", arm_regnames[Rn]);
5676 if (U) /* 12-bit positive immediate offset. */
5677 {
5678 offset = i12;
5679 if (Rn != 15)
5680 value_in_comment = offset;
5681 }
5682 else if (Rn == 15) /* 12-bit negative immediate offset. */
5683 offset = - (int) i12;
5684 else if (op == 0x0) /* Shifted register offset. */
5685 {
5686 unsigned int Rm = (i8 & 0x0f);
5687 unsigned int sh = (i8 & 0x30) >> 4;
5688
5689 func (stream, ", %s", arm_regnames[Rm]);
5690 if (sh)
5691 func (stream, ", lsl #%u", sh);
5692 func (stream, "]");
5693 break;
5694 }
5695 else switch (op)
5696 {
5697 case 0xE: /* 8-bit positive immediate offset. */
5698 offset = i8;
5699 break;
5700
5701 case 0xC: /* 8-bit negative immediate offset. */
5702 offset = -i8;
5703 break;
5704
5705 case 0xF: /* 8-bit + preindex with wb. */
5706 offset = i8;
5707 writeback = TRUE;
5708 break;
5709
5710 case 0xD: /* 8-bit - preindex with wb. */
5711 offset = -i8;
5712 writeback = TRUE;
5713 break;
5714
5715 case 0xB: /* 8-bit + postindex. */
5716 offset = i8;
5717 postind = TRUE;
5718 break;
5719
5720 case 0x9: /* 8-bit - postindex. */
5721 offset = -i8;
5722 postind = TRUE;
5723 break;
5724
5725 default:
5726 func (stream, ", <undefined>]");
5727 goto skip;
5728 }
5729
5730 if (postind)
5731 func (stream, "], #%d", (int) offset);
5732 else
5733 {
5734 if (offset)
5735 func (stream, ", #%d", (int) offset);
5736 func (stream, writeback ? "]!" : "]");
5737 }
5738
5739 if (Rn == 15)
5740 {
5741 func (stream, "\t; ");
5742 info->print_address_func (((pc + 4) & ~3) + offset, info);
5743 }
5744 }
5745 skip:
5746 break;
5747
5748 case 'A':
5749 {
5750 unsigned int U = ! NEGATIVE_BIT_SET;
5751 unsigned int W = WRITEBACK_BIT_SET;
5752 unsigned int Rn = (given & 0x000f0000) >> 16;
5753 unsigned int off = (given & 0x000000ff);
5754
5755 func (stream, "[%s", arm_regnames[Rn]);
5756
5757 if (PRE_BIT_SET)
5758 {
5759 if (off || !U)
5760 {
5761 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5762 value_in_comment = (off && U) ? 1 : -1;
5763 }
5764 func (stream, "]");
5765 if (W)
5766 func (stream, "!");
5767 }
5768 else
5769 {
5770 func (stream, "], ");
5771 if (W)
5772 {
5773 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5774 value_in_comment = (off && U) ? 1 : -1;
5775 }
5776 else
5777 {
5778 func (stream, "{%u}", off);
5779 value_in_comment = off;
5780 }
5781 }
5782 }
5783 break;
5784
5785 case 'w':
5786 {
5787 unsigned int Sbit = (given & 0x01000000) >> 24;
5788 unsigned int type = (given & 0x00600000) >> 21;
5789
5790 switch (type)
5791 {
5792 case 0: func (stream, Sbit ? "sb" : "b"); break;
5793 case 1: func (stream, Sbit ? "sh" : "h"); break;
5794 case 2:
5795 if (Sbit)
5796 func (stream, "??");
5797 break;
5798 case 3:
5799 func (stream, "??");
5800 break;
5801 }
5802 }
5803 break;
5804
5805 case 'm':
5806 {
5807 int started = 0;
5808 int reg;
5809
5810 func (stream, "{");
5811 for (reg = 0; reg < 16; reg++)
5812 if ((given & (1 << reg)) != 0)
5813 {
5814 if (started)
5815 func (stream, ", ");
5816 started = 1;
5817 func (stream, "%s", arm_regnames[reg]);
5818 }
5819 func (stream, "}");
5820 }
5821 break;
5822
5823 case 'E':
5824 {
5825 unsigned int msb = (given & 0x0000001f);
5826 unsigned int lsb = 0;
5827
5828 lsb |= (given & 0x000000c0u) >> 6;
5829 lsb |= (given & 0x00007000u) >> 10;
5830 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5831 }
5832 break;
5833
5834 case 'F':
5835 {
5836 unsigned int width = (given & 0x0000001f) + 1;
5837 unsigned int lsb = 0;
5838
5839 lsb |= (given & 0x000000c0u) >> 6;
5840 lsb |= (given & 0x00007000u) >> 10;
5841 func (stream, "#%u, #%u", lsb, width);
5842 }
5843 break;
5844
5845 case 'b':
5846 {
5847 unsigned int S = (given & 0x04000000u) >> 26;
5848 unsigned int J1 = (given & 0x00002000u) >> 13;
5849 unsigned int J2 = (given & 0x00000800u) >> 11;
5850 bfd_vma offset = 0;
5851
5852 offset |= !S << 20;
5853 offset |= J2 << 19;
5854 offset |= J1 << 18;
5855 offset |= (given & 0x003f0000) >> 4;
5856 offset |= (given & 0x000007ff) << 1;
5857 offset -= (1 << 20);
5858
5859 info->print_address_func (pc + 4 + offset, info);
5860 }
5861 break;
5862
5863 case 'B':
5864 {
5865 unsigned int S = (given & 0x04000000u) >> 26;
5866 unsigned int I1 = (given & 0x00002000u) >> 13;
5867 unsigned int I2 = (given & 0x00000800u) >> 11;
5868 bfd_vma offset = 0;
5869
5870 offset |= !S << 24;
5871 offset |= !(I1 ^ S) << 23;
5872 offset |= !(I2 ^ S) << 22;
5873 offset |= (given & 0x03ff0000u) >> 4;
5874 offset |= (given & 0x000007ffu) << 1;
5875 offset -= (1 << 24);
5876 offset += pc + 4;
5877
5878 /* BLX target addresses are always word aligned. */
5879 if ((given & 0x00001000u) == 0)
5880 offset &= ~2u;
5881
5882 info->print_address_func (offset, info);
5883 }
5884 break;
5885
5886 case 's':
5887 {
5888 unsigned int shift = 0;
5889
5890 shift |= (given & 0x000000c0u) >> 6;
5891 shift |= (given & 0x00007000u) >> 10;
5892 if (WRITEBACK_BIT_SET)
5893 func (stream, ", asr #%u", shift);
5894 else if (shift)
5895 func (stream, ", lsl #%u", shift);
5896 /* else print nothing - lsl #0 */
5897 }
5898 break;
5899
5900 case 'R':
5901 {
5902 unsigned int rot = (given & 0x00000030) >> 4;
5903
5904 if (rot)
5905 func (stream, ", ror #%u", rot * 8);
5906 }
5907 break;
5908
5909 case 'U':
5910 if ((given & 0xf0) == 0x60)
5911 {
5912 switch (given & 0xf)
5913 {
5914 case 0xf: func (stream, "sy"); break;
5915 default:
5916 func (stream, "#%d", (int) given & 0xf);
5917 break;
5918 }
5919 }
5920 else
5921 {
5922 const char * opt = data_barrier_option (given & 0xf);
5923 if (opt != NULL)
5924 func (stream, "%s", opt);
5925 else
5926 func (stream, "#%d", (int) given & 0xf);
5927 }
5928 break;
5929
5930 case 'C':
5931 if ((given & 0xff) == 0)
5932 {
5933 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5934 if (given & 0x800)
5935 func (stream, "f");
5936 if (given & 0x400)
5937 func (stream, "s");
5938 if (given & 0x200)
5939 func (stream, "x");
5940 if (given & 0x100)
5941 func (stream, "c");
5942 }
5943 else if ((given & 0x20) == 0x20)
5944 {
5945 char const* name;
5946 unsigned sysm = (given & 0xf00) >> 8;
5947
5948 sysm |= (given & 0x30);
5949 sysm |= (given & 0x00100000) >> 14;
5950 name = banked_regname (sysm);
5951
5952 if (name != NULL)
5953 func (stream, "%s", name);
5954 else
5955 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5956 }
5957 else
5958 {
5959 func (stream, "%s", psr_name (given & 0xff));
5960 }
5961 break;
5962
5963 case 'D':
5964 if (((given & 0xff) == 0)
5965 || ((given & 0x20) == 0x20))
5966 {
5967 char const* name;
5968 unsigned sm = (given & 0xf0000) >> 16;
5969
5970 sm |= (given & 0x30);
5971 sm |= (given & 0x00100000) >> 14;
5972 name = banked_regname (sm);
5973
5974 if (name != NULL)
5975 func (stream, "%s", name);
5976 else
5977 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5978 }
5979 else
5980 func (stream, "%s", psr_name (given & 0xff));
5981 break;
5982
5983 case '0': case '1': case '2': case '3': case '4':
5984 case '5': case '6': case '7': case '8': case '9':
5985 {
5986 int width;
5987 unsigned long val;
5988
5989 c = arm_decode_bitfield (c, given, &val, &width);
5990
5991 switch (*c)
5992 {
5993 case 'd':
5994 func (stream, "%lu", val);
5995 value_in_comment = val;
5996 break;
5997
5998 case 'D':
5999 func (stream, "%lu", val + 1);
6000 value_in_comment = val + 1;
6001 break;
6002
6003 case 'W':
6004 func (stream, "%lu", val * 4);
6005 value_in_comment = val * 4;
6006 break;
6007
6008 case 'S':
6009 if (val == 13)
6010 is_unpredictable = TRUE;
6011 /* Fall through. */
6012 case 'R':
6013 if (val == 15)
6014 is_unpredictable = TRUE;
6015 /* Fall through. */
6016 case 'r':
6017 func (stream, "%s", arm_regnames[val]);
6018 break;
6019
6020 case 'c':
6021 func (stream, "%s", arm_conditional[val]);
6022 break;
6023
6024 case '\'':
6025 c++;
6026 if (val == ((1ul << width) - 1))
6027 func (stream, "%c", *c);
6028 break;
6029
6030 case '`':
6031 c++;
6032 if (val == 0)
6033 func (stream, "%c", *c);
6034 break;
6035
6036 case '?':
6037 func (stream, "%c", c[(1 << width) - (int) val]);
6038 c += 1 << width;
6039 break;
6040
6041 case 'x':
6042 func (stream, "0x%lx", val & 0xffffffffUL);
6043 break;
6044
6045 default:
6046 abort ();
6047 }
6048 }
6049 break;
6050
6051 case 'L':
6052 /* PR binutils/12534
6053 If we have a PC relative offset in an LDRD or STRD
6054 instructions then display the decoded address. */
6055 if (((given >> 16) & 0xf) == 0xf)
6056 {
6057 bfd_vma offset = (given & 0xff) * 4;
6058
6059 if ((given & (1 << 23)) == 0)
6060 offset = - offset;
6061 func (stream, "\t; ");
6062 info->print_address_func ((pc & ~3) + 4 + offset, info);
6063 }
6064 break;
6065
6066 default:
6067 abort ();
6068 }
6069 }
6070
6071 if (value_in_comment > 32 || value_in_comment < -16)
6072 func (stream, "\t; 0x%lx", value_in_comment);
6073
6074 if (is_unpredictable)
6075 func (stream, UNPREDICTABLE_INSTRUCTION);
6076
6077 return;
6078 }
6079
6080 /* No match. */
6081 abort ();
6082 }
6083
6084 /* Print data bytes on INFO->STREAM. */
6085
6086 static void
6087 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6088 struct disassemble_info *info,
6089 long given)
6090 {
6091 switch (info->bytes_per_chunk)
6092 {
6093 case 1:
6094 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6095 break;
6096 case 2:
6097 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6098 break;
6099 case 4:
6100 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6101 break;
6102 default:
6103 abort ();
6104 }
6105 }
6106
6107 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6108 being displayed in symbol relative addresses.
6109
6110 Also disallow private symbol, with __tagsym$$ prefix,
6111 from ARM RVCT toolchain being displayed. */
6112
6113 bfd_boolean
6114 arm_symbol_is_valid (asymbol * sym,
6115 struct disassemble_info * info ATTRIBUTE_UNUSED)
6116 {
6117 const char * name;
6118
6119 if (sym == NULL)
6120 return FALSE;
6121
6122 name = bfd_asymbol_name (sym);
6123
6124 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6125 }
6126
6127 /* Parse an individual disassembler option. */
6128
6129 void
6130 parse_arm_disassembler_option (char *option)
6131 {
6132 if (option == NULL)
6133 return;
6134
6135 if (CONST_STRNEQ (option, "reg-names-"))
6136 {
6137 int i;
6138
6139 option += 10;
6140
6141 for (i = NUM_ARM_REGNAMES; i--;)
6142 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
6143 {
6144 regname_selected = i;
6145 break;
6146 }
6147
6148 if (i < 0)
6149 /* XXX - should break 'option' at following delimiter. */
6150 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
6151 }
6152 else if (CONST_STRNEQ (option, "force-thumb"))
6153 force_thumb = 1;
6154 else if (CONST_STRNEQ (option, "no-force-thumb"))
6155 force_thumb = 0;
6156 else
6157 /* XXX - should break 'option' at following delimiter. */
6158 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
6159
6160 return;
6161 }
6162
6163 /* Parse the string of disassembler options, spliting it at whitespaces
6164 or commas. (Whitespace separators supported for backwards compatibility). */
6165
6166 static void
6167 parse_disassembler_options (char *options)
6168 {
6169 if (options == NULL)
6170 return;
6171
6172 while (*options)
6173 {
6174 parse_arm_disassembler_option (options);
6175
6176 /* Skip forward to next seperator. */
6177 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
6178 ++ options;
6179 /* Skip forward past seperators. */
6180 while (ISSPACE (*options) || (*options == ','))
6181 ++ options;
6182 }
6183 }
6184
6185 static bfd_boolean
6186 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6187 enum map_type *map_symbol);
6188
6189 /* Search back through the insn stream to determine if this instruction is
6190 conditionally executed. */
6191
6192 static void
6193 find_ifthen_state (bfd_vma pc,
6194 struct disassemble_info *info,
6195 bfd_boolean little)
6196 {
6197 unsigned char b[2];
6198 unsigned int insn;
6199 int status;
6200 /* COUNT is twice the number of instructions seen. It will be odd if we
6201 just crossed an instruction boundary. */
6202 int count;
6203 int it_count;
6204 unsigned int seen_it;
6205 bfd_vma addr;
6206
6207 ifthen_address = pc;
6208 ifthen_state = 0;
6209
6210 addr = pc;
6211 count = 1;
6212 it_count = 0;
6213 seen_it = 0;
6214 /* Scan backwards looking for IT instructions, keeping track of where
6215 instruction boundaries are. We don't know if something is actually an
6216 IT instruction until we find a definite instruction boundary. */
6217 for (;;)
6218 {
6219 if (addr == 0 || info->symbol_at_address_func (addr, info))
6220 {
6221 /* A symbol must be on an instruction boundary, and will not
6222 be within an IT block. */
6223 if (seen_it && (count & 1))
6224 break;
6225
6226 return;
6227 }
6228 addr -= 2;
6229 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6230 if (status)
6231 return;
6232
6233 if (little)
6234 insn = (b[0]) | (b[1] << 8);
6235 else
6236 insn = (b[1]) | (b[0] << 8);
6237 if (seen_it)
6238 {
6239 if ((insn & 0xf800) < 0xe800)
6240 {
6241 /* Addr + 2 is an instruction boundary. See if this matches
6242 the expected boundary based on the position of the last
6243 IT candidate. */
6244 if (count & 1)
6245 break;
6246 seen_it = 0;
6247 }
6248 }
6249 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6250 {
6251 enum map_type type = MAP_ARM;
6252 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6253
6254 if (!found || (found && type == MAP_THUMB))
6255 {
6256 /* This could be an IT instruction. */
6257 seen_it = insn;
6258 it_count = count >> 1;
6259 }
6260 }
6261 if ((insn & 0xf800) >= 0xe800)
6262 count++;
6263 else
6264 count = (count + 2) | 1;
6265 /* IT blocks contain at most 4 instructions. */
6266 if (count >= 8 && !seen_it)
6267 return;
6268 }
6269 /* We found an IT instruction. */
6270 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6271 if ((ifthen_state & 0xf) == 0)
6272 ifthen_state = 0;
6273 }
6274
6275 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6276 mapping symbol. */
6277
6278 static int
6279 is_mapping_symbol (struct disassemble_info *info, int n,
6280 enum map_type *map_type)
6281 {
6282 const char *name;
6283
6284 name = bfd_asymbol_name (info->symtab[n]);
6285 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6286 && (name[2] == 0 || name[2] == '.'))
6287 {
6288 *map_type = ((name[1] == 'a') ? MAP_ARM
6289 : (name[1] == 't') ? MAP_THUMB
6290 : MAP_DATA);
6291 return TRUE;
6292 }
6293
6294 return FALSE;
6295 }
6296
6297 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6298 Returns nonzero if *MAP_TYPE was set. */
6299
6300 static int
6301 get_map_sym_type (struct disassemble_info *info,
6302 int n,
6303 enum map_type *map_type)
6304 {
6305 /* If the symbol is in a different section, ignore it. */
6306 if (info->section != NULL && info->section != info->symtab[n]->section)
6307 return FALSE;
6308
6309 return is_mapping_symbol (info, n, map_type);
6310 }
6311
6312 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6313 Returns nonzero if *MAP_TYPE was set. */
6314
6315 static int
6316 get_sym_code_type (struct disassemble_info *info,
6317 int n,
6318 enum map_type *map_type)
6319 {
6320 elf_symbol_type *es;
6321 unsigned int type;
6322
6323 /* If the symbol is in a different section, ignore it. */
6324 if (info->section != NULL && info->section != info->symtab[n]->section)
6325 return FALSE;
6326
6327 es = *(elf_symbol_type **)(info->symtab + n);
6328 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6329
6330 /* If the symbol has function type then use that. */
6331 if (type == STT_FUNC || type == STT_GNU_IFUNC)
6332 {
6333 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6334 == ST_BRANCH_TO_THUMB)
6335 *map_type = MAP_THUMB;
6336 else
6337 *map_type = MAP_ARM;
6338 return TRUE;
6339 }
6340
6341 return FALSE;
6342 }
6343
6344 /* Search the mapping symbol state for instruction at pc. This is only
6345 applicable for elf target.
6346
6347 There is an assumption Here, info->private_data contains the correct AND
6348 up-to-date information about current scan process. The information will be
6349 used to speed this search process.
6350
6351 Return TRUE if the mapping state can be determined, and map_symbol
6352 will be updated accordingly. Otherwise, return FALSE. */
6353
6354 static bfd_boolean
6355 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6356 enum map_type *map_symbol)
6357 {
6358 bfd_vma addr;
6359 int n, start = 0;
6360 bfd_boolean found = FALSE;
6361 enum map_type type = MAP_ARM;
6362 struct arm_private_data *private_data;
6363
6364 if (info->private_data == NULL || info->symtab_size == 0
6365 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6366 return FALSE;
6367
6368 private_data = info->private_data;
6369 if (pc == 0)
6370 start = 0;
6371 else
6372 start = private_data->last_mapping_sym;
6373
6374 start = (start == -1)? 0 : start;
6375 addr = bfd_asymbol_value (info->symtab[start]);
6376
6377 if (pc >= addr)
6378 {
6379 if (get_map_sym_type (info, start, &type))
6380 found = TRUE;
6381 }
6382 else
6383 {
6384 for (n = start - 1; n >= 0; n--)
6385 {
6386 if (get_map_sym_type (info, n, &type))
6387 {
6388 found = TRUE;
6389 break;
6390 }
6391 }
6392 }
6393
6394 /* No mapping symbols were found. A leading $d may be
6395 omitted for sections which start with data; but for
6396 compatibility with legacy and stripped binaries, only
6397 assume the leading $d if there is at least one mapping
6398 symbol in the file. */
6399 if (!found && private_data->has_mapping_symbols == 1)
6400 {
6401 type = MAP_DATA;
6402 found = TRUE;
6403 }
6404
6405 *map_symbol = type;
6406 return found;
6407 }
6408
6409 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6410 of the supplied arm_feature_set structure with bitmasks indicating
6411 the support base architectures and coprocessor extensions.
6412
6413 FIXME: This could more efficiently implemented as a constant array,
6414 although it would also be less robust. */
6415
6416 static void
6417 select_arm_features (unsigned long mach,
6418 arm_feature_set * features)
6419 {
6420 #undef ARM_SET_FEATURES
6421 #define ARM_SET_FEATURES(FSET) \
6422 { \
6423 const arm_feature_set fset = FSET; \
6424 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6425 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6426 }
6427
6428 switch (mach)
6429 {
6430 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6431 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6432 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6433 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6434 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6435 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6436 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6437 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6438 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6439 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6440 case bfd_mach_arm_ep9312:
6441 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6442 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6443 break;
6444 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6445 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6446 /* If the machine type is unknown allow all
6447 architecture types and all extensions. */
6448 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6449 default:
6450 abort ();
6451 }
6452
6453 #undef ARM_SET_FEATURES
6454 }
6455
6456
6457 /* NOTE: There are no checks in these routines that
6458 the relevant number of data bytes exist. */
6459
6460 static int
6461 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6462 {
6463 unsigned char b[4];
6464 long given;
6465 int status;
6466 int is_thumb = FALSE;
6467 int is_data = FALSE;
6468 int little_code;
6469 unsigned int size = 4;
6470 void (*printer) (bfd_vma, struct disassemble_info *, long);
6471 bfd_boolean found = FALSE;
6472 struct arm_private_data *private_data;
6473
6474 if (info->disassembler_options)
6475 {
6476 parse_disassembler_options (info->disassembler_options);
6477
6478 /* To avoid repeated parsing of these options, we remove them here. */
6479 info->disassembler_options = NULL;
6480 }
6481
6482 /* PR 10288: Control which instructions will be disassembled. */
6483 if (info->private_data == NULL)
6484 {
6485 static struct arm_private_data private;
6486
6487 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6488 /* If the user did not use the -m command line switch then default to
6489 disassembling all types of ARM instruction.
6490
6491 The info->mach value has to be ignored as this will be based on
6492 the default archictecture for the target and/or hints in the notes
6493 section, but it will never be greater than the current largest arm
6494 machine value (iWMMXt2), which is only equivalent to the V5TE
6495 architecture. ARM architectures have advanced beyond the machine
6496 value encoding, and these newer architectures would be ignored if
6497 the machine value was used.
6498
6499 Ie the -m switch is used to restrict which instructions will be
6500 disassembled. If it is necessary to use the -m switch to tell
6501 objdump that an ARM binary is being disassembled, eg because the
6502 input is a raw binary file, but it is also desired to disassemble
6503 all ARM instructions then use "-marm". This will select the
6504 "unknown" arm architecture which is compatible with any ARM
6505 instruction. */
6506 info->mach = bfd_mach_arm_unknown;
6507
6508 /* Compute the architecture bitmask from the machine number.
6509 Note: This assumes that the machine number will not change
6510 during disassembly.... */
6511 select_arm_features (info->mach, & private.features);
6512
6513 private.has_mapping_symbols = -1;
6514 private.last_mapping_sym = -1;
6515 private.last_mapping_addr = 0;
6516
6517 info->private_data = & private;
6518 }
6519
6520 private_data = info->private_data;
6521
6522 /* Decide if our code is going to be little-endian, despite what the
6523 function argument might say. */
6524 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6525
6526 /* For ELF, consult the symbol table to determine what kind of code
6527 or data we have. */
6528 if (info->symtab_size != 0
6529 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6530 {
6531 bfd_vma addr;
6532 int n, start;
6533 int last_sym = -1;
6534 enum map_type type = MAP_ARM;
6535
6536 /* Start scanning at the start of the function, or wherever
6537 we finished last time. */
6538 /* PR 14006. When the address is 0 we are either at the start of the
6539 very first function, or else the first function in a new, unlinked
6540 executable section (eg because of -ffunction-sections). Either way
6541 start scanning from the beginning of the symbol table, not where we
6542 left off last time. */
6543 if (pc == 0)
6544 start = 0;
6545 else
6546 {
6547 start = info->symtab_pos + 1;
6548 if (start < private_data->last_mapping_sym)
6549 start = private_data->last_mapping_sym;
6550 }
6551 found = FALSE;
6552
6553 /* First, look for mapping symbols. */
6554 if (private_data->has_mapping_symbols != 0)
6555 {
6556 /* Scan up to the location being disassembled. */
6557 for (n = start; n < info->symtab_size; n++)
6558 {
6559 addr = bfd_asymbol_value (info->symtab[n]);
6560 if (addr > pc)
6561 break;
6562 if (get_map_sym_type (info, n, &type))
6563 {
6564 last_sym = n;
6565 found = TRUE;
6566 }
6567 }
6568
6569 if (!found)
6570 {
6571 /* No mapping symbol found at this address. Look backwards
6572 for a preceding one. */
6573 for (n = start - 1; n >= 0; n--)
6574 {
6575 if (get_map_sym_type (info, n, &type))
6576 {
6577 last_sym = n;
6578 found = TRUE;
6579 break;
6580 }
6581 }
6582 }
6583
6584 if (found)
6585 private_data->has_mapping_symbols = 1;
6586
6587 /* No mapping symbols were found. A leading $d may be
6588 omitted for sections which start with data; but for
6589 compatibility with legacy and stripped binaries, only
6590 assume the leading $d if there is at least one mapping
6591 symbol in the file. */
6592 if (!found && private_data->has_mapping_symbols == -1)
6593 {
6594 /* Look for mapping symbols, in any section. */
6595 for (n = 0; n < info->symtab_size; n++)
6596 if (is_mapping_symbol (info, n, &type))
6597 {
6598 private_data->has_mapping_symbols = 1;
6599 break;
6600 }
6601 if (private_data->has_mapping_symbols == -1)
6602 private_data->has_mapping_symbols = 0;
6603 }
6604
6605 if (!found && private_data->has_mapping_symbols == 1)
6606 {
6607 type = MAP_DATA;
6608 found = TRUE;
6609 }
6610 }
6611
6612 /* Next search for function symbols to separate ARM from Thumb
6613 in binaries without mapping symbols. */
6614 if (!found)
6615 {
6616 /* Scan up to the location being disassembled. */
6617 for (n = start; n < info->symtab_size; n++)
6618 {
6619 addr = bfd_asymbol_value (info->symtab[n]);
6620 if (addr > pc)
6621 break;
6622 if (get_sym_code_type (info, n, &type))
6623 {
6624 last_sym = n;
6625 found = TRUE;
6626 }
6627 }
6628
6629 if (!found)
6630 {
6631 /* No mapping symbol found at this address. Look backwards
6632 for a preceding one. */
6633 for (n = start - 1; n >= 0; n--)
6634 {
6635 if (get_sym_code_type (info, n, &type))
6636 {
6637 last_sym = n;
6638 found = TRUE;
6639 break;
6640 }
6641 }
6642 }
6643 }
6644
6645 private_data->last_mapping_sym = last_sym;
6646 private_data->last_type = type;
6647 is_thumb = (private_data->last_type == MAP_THUMB);
6648 is_data = (private_data->last_type == MAP_DATA);
6649
6650 /* Look a little bit ahead to see if we should print out
6651 two or four bytes of data. If there's a symbol,
6652 mapping or otherwise, after two bytes then don't
6653 print more. */
6654 if (is_data)
6655 {
6656 size = 4 - (pc & 3);
6657 for (n = last_sym + 1; n < info->symtab_size; n++)
6658 {
6659 addr = bfd_asymbol_value (info->symtab[n]);
6660 if (addr > pc
6661 && (info->section == NULL
6662 || info->section == info->symtab[n]->section))
6663 {
6664 if (addr - pc < size)
6665 size = addr - pc;
6666 break;
6667 }
6668 }
6669 /* If the next symbol is after three bytes, we need to
6670 print only part of the data, so that we can use either
6671 .byte or .short. */
6672 if (size == 3)
6673 size = (pc & 1) ? 1 : 2;
6674 }
6675 }
6676
6677 if (info->symbols != NULL)
6678 {
6679 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6680 {
6681 coff_symbol_type * cs;
6682
6683 cs = coffsymbol (*info->symbols);
6684 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6685 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6686 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6687 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6688 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6689 }
6690 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6691 && !found)
6692 {
6693 /* If no mapping symbol has been found then fall back to the type
6694 of the function symbol. */
6695 elf_symbol_type * es;
6696 unsigned int type;
6697
6698 es = *(elf_symbol_type **)(info->symbols);
6699 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6700
6701 is_thumb =
6702 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6703 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
6704 }
6705 else if (bfd_asymbol_flavour (*info->symbols)
6706 == bfd_target_mach_o_flavour)
6707 {
6708 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6709
6710 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6711 }
6712 }
6713
6714 if (force_thumb)
6715 is_thumb = TRUE;
6716
6717 if (is_data)
6718 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6719 else
6720 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6721
6722 info->bytes_per_line = 4;
6723
6724 /* PR 10263: Disassemble data if requested to do so by the user. */
6725 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6726 {
6727 int i;
6728
6729 /* Size was already set above. */
6730 info->bytes_per_chunk = size;
6731 printer = print_insn_data;
6732
6733 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6734 given = 0;
6735 if (little)
6736 for (i = size - 1; i >= 0; i--)
6737 given = b[i] | (given << 8);
6738 else
6739 for (i = 0; i < (int) size; i++)
6740 given = b[i] | (given << 8);
6741 }
6742 else if (!is_thumb)
6743 {
6744 /* In ARM mode endianness is a straightforward issue: the instruction
6745 is four bytes long and is either ordered 0123 or 3210. */
6746 printer = print_insn_arm;
6747 info->bytes_per_chunk = 4;
6748 size = 4;
6749
6750 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6751 if (little_code)
6752 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6753 else
6754 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6755 }
6756 else
6757 {
6758 /* In Thumb mode we have the additional wrinkle of two
6759 instruction lengths. Fortunately, the bits that determine
6760 the length of the current instruction are always to be found
6761 in the first two bytes. */
6762 printer = print_insn_thumb16;
6763 info->bytes_per_chunk = 2;
6764 size = 2;
6765
6766 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6767 if (little_code)
6768 given = (b[0]) | (b[1] << 8);
6769 else
6770 given = (b[1]) | (b[0] << 8);
6771
6772 if (!status)
6773 {
6774 /* These bit patterns signal a four-byte Thumb
6775 instruction. */
6776 if ((given & 0xF800) == 0xF800
6777 || (given & 0xF800) == 0xF000
6778 || (given & 0xF800) == 0xE800)
6779 {
6780 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6781 if (little_code)
6782 given = (b[0]) | (b[1] << 8) | (given << 16);
6783 else
6784 given = (b[1]) | (b[0] << 8) | (given << 16);
6785
6786 printer = print_insn_thumb32;
6787 size = 4;
6788 }
6789 }
6790
6791 if (ifthen_address != pc)
6792 find_ifthen_state (pc, info, little_code);
6793
6794 if (ifthen_state)
6795 {
6796 if ((ifthen_state & 0xf) == 0x8)
6797 ifthen_next_state = 0;
6798 else
6799 ifthen_next_state = (ifthen_state & 0xe0)
6800 | ((ifthen_state & 0xf) << 1);
6801 }
6802 }
6803
6804 if (status)
6805 {
6806 info->memory_error_func (status, pc, info);
6807 return -1;
6808 }
6809 if (info->flags & INSN_HAS_RELOC)
6810 /* If the instruction has a reloc associated with it, then
6811 the offset field in the instruction will actually be the
6812 addend for the reloc. (We are using REL type relocs).
6813 In such cases, we can ignore the pc when computing
6814 addresses, since the addend is not currently pc-relative. */
6815 pc = 0;
6816
6817 printer (pc, info, given);
6818
6819 if (is_thumb)
6820 {
6821 ifthen_state = ifthen_next_state;
6822 ifthen_address += size;
6823 }
6824 return size;
6825 }
6826
6827 int
6828 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6829 {
6830 /* Detect BE8-ness and record it in the disassembler info. */
6831 if (info->flavour == bfd_target_elf_flavour
6832 && info->section != NULL
6833 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6834 info->endian_code = BFD_ENDIAN_LITTLE;
6835
6836 return print_insn (pc, info, FALSE);
6837 }
6838
6839 int
6840 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6841 {
6842 return print_insn (pc, info, TRUE);
6843 }
6844
6845 void
6846 print_arm_disassembler_options (FILE *stream)
6847 {
6848 int i;
6849
6850 fprintf (stream, _("\n\
6851 The following ARM specific disassembler options are supported for use with\n\
6852 the -M switch:\n"));
6853
6854 for (i = NUM_ARM_REGNAMES; i--;)
6855 fprintf (stream, " reg-names-%s %*c%s\n",
6856 regnames[i].name,
6857 (int)(14 - strlen (regnames[i].name)), ' ',
6858 regnames[i].description);
6859
6860 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
6861 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
6862 }
GDB Binutils - Deliverables
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