1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* Cached mapping symbol state. */
50 struct arm_private_data
52 /* The features to use when disassembling optional instructions. */
53 arm_feature_set features
;
55 /* Track the last type (although this doesn't seem to be useful) */
56 enum map_type last_type
;
58 /* Tracking symbol table information */
61 /* The end range of the current range being disassembled. */
62 bfd_vma last_stop_offset
;
63 bfd_vma last_mapping_addr
;
116 MVE_VSTRB_SCATTER_T1
,
117 MVE_VSTRH_SCATTER_T2
,
118 MVE_VSTRW_SCATTER_T3
,
119 MVE_VSTRD_SCATTER_T4
,
120 MVE_VSTRW_SCATTER_T5
,
121 MVE_VSTRD_SCATTER_T6
,
123 MVE_VCVT_BETWEEN_FP_INT
,
125 MVE_VCVT_FROM_FP_TO_INT
,
128 MVE_VMOV_GP_TO_VEC_LANE
,
131 MVE_VMOV2_VEC_LANE_TO_GP
,
132 MVE_VMOV2_GP_TO_VEC_LANE
,
133 MVE_VMOV_VEC_LANE_TO_GP
,
291 enum mve_unpredictable
293 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
295 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
297 UNPRED_R13
, /* Unpredictable because r13 (sp) or
299 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
300 UNPRED_Q_GT_4
, /* Unpredictable because
301 vec reg start > 4 (vld4/st4). */
302 UNPRED_Q_GT_6
, /* Unpredictable because
303 vec reg start > 6 (vld2/st2). */
304 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
306 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
308 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
309 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
311 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
313 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
315 UNPRED_NONE
/* No unpredictable behavior. */
320 UNDEF_SIZE
, /* undefined size. */
321 UNDEF_SIZE_0
, /* undefined because size == 0. */
322 UNDEF_SIZE_2
, /* undefined because size == 2. */
323 UNDEF_SIZE_3
, /* undefined because size == 3. */
324 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
325 UNDEF_SIZE_NOT_0
, /* undefined because size != 0. */
326 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
327 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
328 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
330 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
332 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
333 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
335 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
337 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
338 op2 == 0 and op1 == (0 or 1). */
339 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
341 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
342 UNDEF_NONE
/* no undefined behavior. */
347 arm_feature_set arch
; /* Architecture defining this insn. */
348 unsigned long value
; /* If arch is 0 then value is a sentinel. */
349 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
350 const char * assembler
; /* How to disassemble this insn. */
355 arm_feature_set arch
; /* Architecture defining this insn. */
356 uint8_t coproc_shift
; /* coproc is this far into op. */
357 uint16_t coproc_mask
; /* Length of coproc field in op. */
358 unsigned long value
; /* If arch is 0 then value is a sentinel. */
359 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
360 const char * assembler
; /* How to disassemble this insn. */
367 arm_feature_set arch
; /* Architecture defining this insn. */
368 enum mve_instructions mve_op
; /* Specific mve instruction for faster
370 unsigned long value
; /* If arch is 0 then value is a sentinel. */
371 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
372 const char * assembler
; /* How to disassemble this insn. */
382 /* Shared (between Arm and Thumb mode) opcode. */
385 enum isa isa
; /* Execution mode instruction availability. */
386 arm_feature_set arch
; /* Architecture defining this insn. */
387 unsigned long value
; /* If arch is 0 then value is a sentinel. */
388 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
389 const char * assembler
; /* How to disassemble this insn. */
394 arm_feature_set arch
; /* Architecture defining this insn. */
395 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
396 const char *assembler
; /* How to disassemble this insn. */
399 /* print_insn_coprocessor recognizes the following format control codes:
403 %c print condition code (always bits 28-31 in ARM mode)
404 %b print condition code allowing cp_num == 9
405 %q print shifter argument
406 %u print condition code (unconditional in ARM mode,
407 UNPREDICTABLE if not AL in Thumb)
408 %A print address for ldc/stc/ldf/stf instruction
409 %B print vstm/vldm register list
410 %C print vscclrm register list
411 %I print cirrus signed shift immediate: bits 0..3|4..6
412 %J print register for VLDR instruction
413 %K print address for VLDR instruction
414 %F print the COUNT field of a LFM/SFM instruction.
415 %P print floating point precision in arithmetic insn
416 %Q print floating point precision in ldf/stf insn
417 %R print floating point rounding mode
419 %<bitfield>c print as a condition code (for vsel)
420 %<bitfield>r print as an ARM register
421 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
422 %<bitfield>ru as %<>r but each u register must be unique.
423 %<bitfield>d print the bitfield in decimal
424 %<bitfield>k print immediate for VFPv3 conversion instruction
425 %<bitfield>x print the bitfield in hex
426 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
427 %<bitfield>f print a floating point constant if >7 else a
428 floating point register
429 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
430 %<bitfield>g print as an iWMMXt 64-bit register
431 %<bitfield>G print as an iWMMXt general purpose or control register
432 %<bitfield>D print as a NEON D register
433 %<bitfield>Q print as a NEON Q register
434 %<bitfield>V print as a NEON D or Q register
435 %<bitfield>E print a quarter-float immediate value
437 %y<code> print a single precision VFP reg.
438 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
439 %z<code> print a double precision VFP reg
440 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
442 %<bitfield>'c print specified char iff bitfield is all ones
443 %<bitfield>`c print specified char iff bitfield is all zeroes
444 %<bitfield>?ab... select from array of values in big endian order
446 %L print as an iWMMXt N/M width field.
447 %Z print the Immediate of a WSHUFH instruction.
448 %l like 'A' except use byte offsets for 'B' & 'H'
450 %i print 5-bit immediate in bits 8,3..0
452 %r print register offset address for wldt/wstr instruction. */
454 enum opcode_sentinel_enum
456 SENTINEL_IWMMXT_START
= 1,
458 SENTINEL_GENERIC_START
461 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
462 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
463 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
464 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
466 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
468 /* print_insn_cde recognizes the following format control codes:
472 %a print 'a' iff bit 28 is 1
473 %p print bits 8-10 as coprocessor
474 %<bitfield>d print as decimal
475 %<bitfield>r print as an ARM register
476 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
477 %<bitfield>T print as an ARM register + 1
478 %<bitfield>R as %r but r13 is UNPREDICTABLE
479 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
480 %j print immediate taken from bits (16..21,7,0..5)
481 %k print immediate taken from bits (20..21,7,0..5).
482 %l print immediate taken from bits (20..22,7,4..5). */
484 /* At the moment there is only one valid position for the coprocessor number,
485 and hence that's encoded in the macro below. */
486 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487 { ARCH, 8, 7, VALUE, MASK, ASM }
488 static const struct cdeopcode32 cde_opcodes
[] =
490 /* Custom Datapath Extension instructions. */
491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
492 0xee000000, 0xefc00840,
493 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
495 0xee000040, 0xefc00840,
496 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
499 0xee400000, 0xefc00840,
500 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
502 0xee400040, 0xefc00840,
503 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
506 0xee800000, 0xef800840,
507 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
509 0xee800040, 0xef800840,
510 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
513 0xec200000, 0xeeb00840,
514 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
516 0xec200040, 0xeeb00840,
517 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
520 0xec300000, 0xeeb00840,
521 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
523 0xec300040, 0xeeb00840,
524 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
526 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
527 0xec800000, 0xee800840,
528 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
529 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
530 0xec800040, 0xee800840,
531 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
533 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
537 static const struct sopcode32 coprocessor_opcodes
[] =
539 /* XScale instructions. */
540 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
541 0x0e200010, 0x0fff0ff0,
542 "mia%c\tacc0, %0-3r, %12-15r"},
543 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
544 0x0e280010, 0x0fff0ff0,
545 "miaph%c\tacc0, %0-3r, %12-15r"},
546 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
547 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
548 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
549 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
550 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
551 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
553 /* Intel Wireless MMX technology instructions. */
554 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
555 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
556 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
557 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
558 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
559 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
560 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
561 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
562 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
563 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
564 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
565 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
566 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
567 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
568 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
569 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
570 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
571 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
572 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
573 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
574 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
575 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
576 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
577 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
578 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
579 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
580 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
581 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
582 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
583 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
584 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
585 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
586 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
587 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
588 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
589 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
590 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
591 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
592 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
593 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
594 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
595 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
596 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
597 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
598 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
599 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
600 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
601 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
602 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
603 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
604 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
605 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
606 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
607 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
608 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
609 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
610 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
611 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
612 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
613 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
614 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
615 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
616 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
617 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
618 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
619 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
620 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
621 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
622 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
623 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
624 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
625 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
626 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
627 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
628 0x0e800120, 0x0f800ff0,
629 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
630 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
631 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
632 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
633 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
634 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
635 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
636 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
637 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
638 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
639 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
640 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
641 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
642 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
643 0x0e8000a0, 0x0f800ff0,
644 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
645 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
646 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
647 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
648 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
649 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
650 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
651 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
652 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
653 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
654 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
655 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
656 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
657 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
658 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
659 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
660 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
661 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
662 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
663 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
664 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
665 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
666 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
667 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
668 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
669 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
670 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
671 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
672 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
673 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
674 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
675 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
676 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
677 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
678 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
679 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
680 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
681 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
682 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
683 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
684 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
685 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
686 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
687 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
688 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
689 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
690 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
691 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
692 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
693 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
694 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
695 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
696 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
697 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
698 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
699 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
700 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
701 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
702 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
703 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
704 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
705 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
706 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
707 {ANY
, ARM_FEATURE_CORE_LOW (0),
708 SENTINEL_IWMMXT_END
, 0, "" },
710 /* Floating point coprocessor (FPA) instructions. */
711 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
712 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
713 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
714 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
715 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
716 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
717 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
718 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
719 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
720 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
721 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
722 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
723 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
724 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
725 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
726 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
727 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
728 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
729 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
730 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
731 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
732 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
733 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
734 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
735 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
736 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
737 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
738 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
739 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
740 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
741 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
742 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
743 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
744 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
745 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
746 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
747 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
748 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
749 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
750 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
751 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
752 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
753 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
754 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
755 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
756 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
757 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
758 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
759 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
760 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
761 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
762 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
763 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
764 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
765 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
766 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
767 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
768 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
769 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
770 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
771 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
772 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
773 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
774 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
775 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
776 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
777 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
778 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
779 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
780 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
781 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
782 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
783 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
784 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
785 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
786 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
787 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
788 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
789 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
790 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
791 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
792 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
793 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
794 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
795 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
796 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
798 /* Armv8.1-M Mainline instructions. */
799 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
800 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
802 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
804 /* ARMv8-M Mainline Security Extensions instructions. */
805 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
806 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
807 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
808 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
810 /* Register load/store. */
811 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
812 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
813 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
814 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
815 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
816 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
817 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
818 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
819 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
820 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
821 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
822 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
823 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
824 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
825 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
826 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
827 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
828 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
829 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
830 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
831 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
832 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
833 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
834 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
835 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
836 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
837 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
838 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
839 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
840 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
841 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
842 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
843 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
844 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
846 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
848 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
849 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
850 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
851 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
852 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
853 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
854 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
855 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
857 /* Data transfer between ARM and NEON registers. */
858 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
859 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
860 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
861 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
862 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
863 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
864 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
865 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
866 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
867 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
868 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
869 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
870 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
871 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
872 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
873 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
874 /* Half-precision conversion instructions. */
875 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
876 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
877 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
878 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
879 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
880 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
881 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
882 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
884 /* Floating point coprocessor (VFP) instructions. */
885 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
886 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
887 {ANY
, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN
, FPU_VFP_EXT_V1xD
),
888 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
889 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
890 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
891 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
892 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
893 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
894 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
895 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
896 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
897 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
898 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
899 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
900 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
901 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
902 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
903 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
904 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
905 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
906 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
907 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
908 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
909 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
910 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
911 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
912 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
913 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
914 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
915 {ANY
, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN
, FPU_VFP_EXT_V1xD
),
916 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
917 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
918 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
919 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
920 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
921 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
922 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
923 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
924 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
925 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
926 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
927 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
928 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
929 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
930 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
931 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
932 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
933 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
934 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
935 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
936 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
937 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
938 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
939 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
940 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
941 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
942 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
943 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
944 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
945 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
946 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
947 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
948 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
949 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
950 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
951 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
952 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
953 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
954 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
955 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
956 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
957 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
958 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
959 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
960 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
961 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
962 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
963 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
964 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
965 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
966 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
967 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
968 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
969 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
970 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
971 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
972 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
973 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
974 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
975 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
976 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
977 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
978 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
979 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
980 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
981 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
982 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
983 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
984 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
985 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
986 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
987 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
988 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
989 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
990 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
991 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
992 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
993 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
994 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
995 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
996 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
997 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
998 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
999 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
1000 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
1001 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
1002 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
1003 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
1004 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
1005 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
1006 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
1007 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1008 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
1009 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1010 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
1011 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1012 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
1013 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1014 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
1015 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1016 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1017 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1018 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1019 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1020 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1021 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1022 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1023 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1024 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1025 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1026 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1027 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1028 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1029 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1030 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1031 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1032 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1033 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1034 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1035 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1036 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1037 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1038 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1039 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1040 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1041 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1042 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1044 /* Cirrus coprocessor instructions. */
1045 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1046 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1047 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1048 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1049 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1050 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1051 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1052 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1053 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1054 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1055 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1056 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1057 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1058 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1059 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1060 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1061 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1062 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1063 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1064 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1065 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1066 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1067 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1068 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1069 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1070 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1071 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1072 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1073 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1074 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1075 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1076 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1077 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1078 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1079 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1080 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1081 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1082 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1083 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1084 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1085 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1086 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1087 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1088 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1089 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1090 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1091 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1092 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1093 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1094 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1095 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1096 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1097 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1098 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1099 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1100 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1101 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1102 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1103 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1104 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1105 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1106 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1107 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1108 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1109 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1110 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1111 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1112 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1113 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1114 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1115 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1116 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1117 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1118 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1119 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1120 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1121 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1122 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1123 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1124 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1125 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1126 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1127 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1128 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1129 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1130 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1131 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1132 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1133 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1134 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1135 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1136 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1137 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1138 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1139 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1140 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1141 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1142 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1143 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1144 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1145 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1146 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1147 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1148 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1149 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1150 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1151 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1152 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1153 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1154 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1155 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1156 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1157 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1158 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1159 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1160 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1161 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1162 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1163 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1164 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1165 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1166 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1167 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1168 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1169 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1170 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1171 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1172 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1173 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1174 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1175 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1176 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1177 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1178 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1179 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1180 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1181 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1182 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1183 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1184 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1185 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1186 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1187 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1188 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1189 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1190 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1191 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1192 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1193 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1194 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1195 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1196 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1197 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1198 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1199 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1200 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1201 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1202 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1203 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1204 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1205 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1206 0x0e000600, 0x0ff00f10,
1207 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1208 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1209 0x0e100600, 0x0ff00f10,
1210 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1211 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1212 0x0e200600, 0x0ff00f10,
1213 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1214 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1215 0x0e300600, 0x0ff00f10,
1216 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1218 /* VFP Fused multiply add instructions. */
1219 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1220 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1221 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1222 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1223 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1224 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1225 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1226 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1227 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1228 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1229 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1230 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1231 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1232 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1233 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1234 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1237 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1238 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1239 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1240 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1241 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1242 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1243 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1244 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1245 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1246 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1247 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1248 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1249 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1250 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1251 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1252 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1253 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1254 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1255 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1256 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1257 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1258 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1259 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1260 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1262 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1263 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1264 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1265 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1266 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1267 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1268 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1269 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1270 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1271 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1272 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1273 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1274 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1275 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1276 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1277 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1278 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1279 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1280 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1281 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1282 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1283 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1285 /* BFloat16 instructions. */
1286 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1287 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1289 /* Dot Product instructions in the space of coprocessor 13. */
1290 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1291 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1292 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1293 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1295 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1296 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1297 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1298 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1299 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1300 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1301 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1302 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1303 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1304 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1305 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1306 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1307 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1308 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1309 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1310 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1311 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1313 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314 cp_num: bit <11:8> == 0b1001.
1315 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1316 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1317 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1318 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1319 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1320 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1321 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1322 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1323 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1324 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1325 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1326 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1327 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1328 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1329 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1330 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1331 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1332 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1333 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1334 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1335 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1336 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1337 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1338 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1339 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1340 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1341 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1342 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1343 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1344 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1345 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1346 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1347 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1348 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1349 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1350 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1351 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1352 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1353 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1354 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1355 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1356 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1357 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1358 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1359 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1360 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1361 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1362 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1363 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1364 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1365 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1366 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1367 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1368 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1369 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1370 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1371 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1372 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1373 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1374 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1375 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1376 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1377 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1378 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1379 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1380 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1381 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1382 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1383 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1384 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1385 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1387 /* ARMv8.3 javascript conversion instruction. */
1388 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1389 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1391 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1394 /* Generic coprocessor instructions. These are only matched if a more specific
1395 SIMD or co-processor instruction does not match first. */
1397 static const struct sopcode32 generic_coprocessor_opcodes
[] =
1399 /* Generic coprocessor instructions. */
1400 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1401 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1402 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1403 0x0c500000, 0x0ff00000,
1404 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1405 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1406 0x0e000000, 0x0f000010,
1407 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1408 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1409 0x0e10f010, 0x0f10f010,
1410 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1411 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1412 0x0e100010, 0x0f100010,
1413 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1414 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1415 0x0e000010, 0x0f100010,
1416 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1417 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1418 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1419 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1420 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1422 /* V6 coprocessor instructions. */
1423 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1424 0xfc500000, 0xfff00000,
1425 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1426 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1427 0xfc400000, 0xfff00000,
1428 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1430 /* V5 coprocessor instructions. */
1431 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1432 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1433 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1434 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1435 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1436 0xfe000000, 0xff000010,
1437 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1438 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1439 0xfe000010, 0xff100010,
1440 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1441 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1442 0xfe100010, 0xff100010,
1443 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1445 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1448 /* Neon opcode table: This does not encode the top byte -- that is
1449 checked by the print_insn_neon routine, as it depends on whether we are
1450 doing thumb32 or arm32 disassembly. */
1452 /* print_insn_neon recognizes the following format control codes:
1456 %c print condition code
1457 %u print condition code (unconditional in ARM mode,
1458 UNPREDICTABLE if not AL in Thumb)
1459 %A print v{st,ld}[1234] operands
1460 %B print v{st,ld}[1234] any one operands
1461 %C print v{st,ld}[1234] single->all operands
1463 %E print vmov, vmvn, vorr, vbic encoded constant
1464 %F print vtbl,vtbx register list
1466 %<bitfield>r print as an ARM register
1467 %<bitfield>d print the bitfield in decimal
1468 %<bitfield>e print the 2^N - bitfield in decimal
1469 %<bitfield>D print as a NEON D register
1470 %<bitfield>Q print as a NEON Q register
1471 %<bitfield>R print as a NEON D or Q register
1472 %<bitfield>Sn print byte scaled width limited by n
1473 %<bitfield>Tn print short scaled width limited by n
1474 %<bitfield>Un print long scaled width limited by n
1476 %<bitfield>'c print specified char iff bitfield is all ones
1477 %<bitfield>`c print specified char iff bitfield is all zeroes
1478 %<bitfield>?ab... select from array of values in big endian order. */
1480 static const struct opcode32 neon_opcodes
[] =
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1484 0xf2b00840, 0xffb00850,
1485 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1487 0xf2b00000, 0xffb00810,
1488 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1490 /* Data transfer between ARM and NEON registers. */
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1492 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1494 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1496 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1498 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1500 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1502 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1504 /* Move data element to all lanes. */
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1506 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1508 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1510 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1514 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1516 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1518 /* Half-precision conversions. */
1519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1520 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1522 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1524 /* NEON fused multiply add instructions. */
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1526 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1528 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1530 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1532 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534 /* BFloat16 instructions. */
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1536 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1538 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1540 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1542 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1544 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1546 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1548 /* Matrix Multiply instructions. */
1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1550 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1552 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1554 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1556 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1558 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1560 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1562 /* Two registers, miscellaneous. */
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1564 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1566 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1568 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1570 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1572 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1574 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1576 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1578 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1580 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1582 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1584 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1586 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1590 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1592 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1596 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1598 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1600 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1602 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1604 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1606 0xf3b20300, 0xffb30fd0,
1607 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1609 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1611 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1615 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1617 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1623 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1625 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1629 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1631 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1633 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1635 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1637 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1639 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1641 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1643 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1645 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1647 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1649 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1651 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1653 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1655 0xf3bb0600, 0xffbf0e10,
1656 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1658 0xf3b70600, 0xffbf0e10,
1659 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1661 /* Three registers of the same length. */
1662 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1663 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1665 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1667 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1669 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1671 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1673 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1675 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1677 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1679 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1681 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1683 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1689 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1695 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1701 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1703 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1705 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1707 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1711 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1715 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1719 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1721 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1723 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1725 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1727 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1729 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1731 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1733 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1735 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1737 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1739 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1743 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1745 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1747 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1751 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1755 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1757 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1759 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1761 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1763 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1767 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1769 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1771 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1775 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1777 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1779 0xf2000b00, 0xff800f10,
1780 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1782 0xf2000b10, 0xff800f10,
1783 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1785 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1787 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1789 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1791 0xf3000b00, 0xff800f10,
1792 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf2000000, 0xfe800f10,
1795 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1797 0xf2000010, 0xfe800f10,
1798 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1800 0xf2000100, 0xfe800f10,
1801 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1803 0xf2000200, 0xfe800f10,
1804 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1806 0xf2000210, 0xfe800f10,
1807 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1809 0xf2000300, 0xfe800f10,
1810 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1812 0xf2000310, 0xfe800f10,
1813 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1815 0xf2000400, 0xfe800f10,
1816 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1818 0xf2000410, 0xfe800f10,
1819 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1821 0xf2000500, 0xfe800f10,
1822 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1824 0xf2000510, 0xfe800f10,
1825 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1827 0xf2000600, 0xfe800f10,
1828 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1830 0xf2000610, 0xfe800f10,
1831 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1833 0xf2000700, 0xfe800f10,
1834 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1836 0xf2000710, 0xfe800f10,
1837 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1839 0xf2000910, 0xfe800f10,
1840 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1842 0xf2000a00, 0xfe800f10,
1843 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1845 0xf2000a10, 0xfe800f10,
1846 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1848 0xf3000b10, 0xff800f10,
1849 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1851 0xf3000c10, 0xff800f10,
1852 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1854 /* One register and an immediate value. */
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1856 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1858 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1860 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1862 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1864 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1866 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1868 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1870 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1872 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1874 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1876 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1878 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1880 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1882 /* Two registers and a shift amount. */
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1884 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1886 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1888 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1890 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1892 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1894 0xf2880950, 0xfeb80fd0,
1895 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1897 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1899 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1901 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1903 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1905 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1907 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1909 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1911 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1913 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1915 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1917 0xf2900950, 0xfeb00fd0,
1918 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1920 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1922 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1924 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1926 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1928 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1930 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1932 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1934 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1936 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1938 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1940 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1942 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1944 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1946 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1948 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1950 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1952 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1954 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1956 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1958 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1960 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1962 0xf2a00950, 0xfea00fd0,
1963 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1965 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1967 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1969 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1971 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1973 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1975 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1977 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1979 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1981 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1983 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1985 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1987 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1989 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1991 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1993 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1995 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1997 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1999 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2001 0xf2a00e10, 0xfea00e90,
2002 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
2003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
2004 0xf2a00c10, 0xfea00e90,
2005 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
2007 /* Three registers of different lengths. */
2008 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
2009 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2011 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2013 0xf2800400, 0xff800f50,
2014 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2016 0xf2800600, 0xff800f50,
2017 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2019 0xf2800900, 0xff800f50,
2020 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2022 0xf2800b00, 0xff800f50,
2023 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2025 0xf2800d00, 0xff800f50,
2026 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2028 0xf3800400, 0xff800f50,
2029 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2031 0xf3800600, 0xff800f50,
2032 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2034 0xf2800000, 0xfe800f50,
2035 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2037 0xf2800100, 0xfe800f50,
2038 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2040 0xf2800200, 0xfe800f50,
2041 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2043 0xf2800300, 0xfe800f50,
2044 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2046 0xf2800500, 0xfe800f50,
2047 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2049 0xf2800700, 0xfe800f50,
2050 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2052 0xf2800800, 0xfe800f50,
2053 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2055 0xf2800a00, 0xfe800f50,
2056 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2058 0xf2800c00, 0xfe800f50,
2059 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2061 /* Two registers and a scalar. */
2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2063 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2065 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2067 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2069 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2071 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2073 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2075 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2077 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2079 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2081 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2083 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2085 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2087 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2089 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2091 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2093 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2095 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2097 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2099 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2101 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2103 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2105 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2107 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2109 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2111 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2113 0xf2800240, 0xfe800f50,
2114 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2116 0xf2800640, 0xfe800f50,
2117 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2119 0xf2800a40, 0xfe800f50,
2120 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2122 0xf2800e40, 0xff800f50,
2123 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2125 0xf2800f40, 0xff800f50,
2126 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2128 0xf3800e40, 0xff800f50,
2129 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2131 0xf3800f40, 0xff800f50,
2132 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2135 /* Element and structure load/store. */
2136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2137 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2139 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2141 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2143 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2145 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2147 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2149 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2151 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2153 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2155 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2157 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2159 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2161 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2163 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2165 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2167 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2169 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2171 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2173 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2175 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2178 /* mve opcode table. */
2180 /* print_insn_mve recognizes the following format control codes:
2184 %a print '+' or '-' or imm offset in vldr[bhwd] and
2186 %c print condition code
2187 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2188 %u print 'U' (unsigned) or 'S' for various mve instructions
2189 %i print MVE predicate(s) for vpt and vpst
2190 %j print a 5-bit immediate from hw2[14:12,7:6]
2191 %k print 48 if the 7th position bit is set else print 64.
2192 %m print rounding mode for vcvt and vrint
2193 %n print vector comparison code for predicated instruction
2194 %s print size for various vcvt instructions
2195 %v print vector predicate for instruction in predicated
2197 %o print offset scaled for vldr[hwd] and vstr[hwd]
2198 %w print writeback mode for MVE v{st,ld}[24]
2199 %B print v{st,ld}[24] any one operands
2200 %E print vmov, vmvn, vorr, vbic encoded constant
2201 %N print generic index for vmov
2202 %T print bottom ('b') or top ('t') of source register
2203 %X print exchange field in vmla* instructions
2205 %<bitfield>r print as an ARM register
2206 %<bitfield>d print the bitfield in decimal
2207 %<bitfield>A print accumulate or not
2208 %<bitfield>c print bitfield as a condition code
2209 %<bitfield>C print bitfield as an inverted condition code
2210 %<bitfield>Q print as a MVE Q register
2211 %<bitfield>F print as a MVE S register
2212 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2215 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2216 %<bitfield>s print size for vector predicate & non VMOV instructions
2217 %<bitfield>I print carry flag or not
2218 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2219 %<bitfield>h print high half of 64-bit destination reg
2220 %<bitfield>k print immediate for vector conversion instruction
2221 %<bitfield>l print low half of 64-bit destination reg
2222 %<bitfield>o print rotate value for vcmul
2223 %<bitfield>u print immediate value for vddup/vdwdup
2224 %<bitfield>x print the bitfield in hex.
2227 static const struct mopcode32 mve_opcodes
[] =
2231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2233 0xfe310f4d, 0xffbf1fff,
2237 /* Floating point VPT T1. */
2238 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2240 0xee310f00, 0xefb10f50,
2241 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242 /* Floating point VPT T2. */
2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2245 0xee310f40, 0xefb10f50,
2246 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2248 /* Vector VPT T1. */
2249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2251 0xfe010f00, 0xff811f51,
2252 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253 /* Vector VPT T2. */
2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2256 0xfe010f01, 0xff811f51,
2257 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258 /* Vector VPT T3. */
2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2261 0xfe011f00, 0xff811f50,
2262 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263 /* Vector VPT T4. */
2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2266 0xfe010f40, 0xff811f70,
2267 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268 /* Vector VPT T5. */
2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2271 0xfe010f60, 0xff811f70,
2272 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273 /* Vector VPT T6. */
2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2276 0xfe011f40, 0xff811f50,
2277 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2279 /* Vector VBIC immediate. */
2280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2282 0xef800070, 0xefb81070,
2283 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2285 /* Vector VBIC register. */
2286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2288 0xef100150, 0xffb11f51,
2289 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2294 0xee800f01, 0xefc10f51,
2295 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2297 /* Vector VABD floating point. */
2298 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2300 0xff200d40, 0xffa11f51,
2301 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2306 0xef000740, 0xef811f51,
2307 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2309 /* Vector VABS floating point. */
2310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2312 0xFFB10740, 0xFFB31FD1,
2313 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2317 0xffb10340, 0xffb31fd1,
2318 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2320 /* Vector VADD floating point T1. */
2321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2323 0xef000d40, 0xffa11f51,
2324 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325 /* Vector VADD floating point T2. */
2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2328 0xee300f40, 0xefb11f70,
2329 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330 /* Vector VADD T1. */
2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2333 0xef000840, 0xff811f51,
2334 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335 /* Vector VADD T2. */
2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2338 0xee010f40, 0xff811f70,
2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2341 /* Vector VADDLV. */
2342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2344 0xee890f00, 0xef8f1fd1,
2345 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2350 0xeef10f00, 0xeff31fd1,
2351 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2356 0xee300f00, 0xffb10f51,
2357 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2362 0xef000150, 0xffb11f51,
2363 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2365 /* Vector VBRSR register. */
2366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2368 0xfe011e60, 0xff811f70,
2369 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2371 /* Vector VCADD floating point. */
2372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2374 0xfc800840, 0xfea11f51,
2375 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2380 0xfe000f00, 0xff810f51,
2381 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2386 0xffb00440, 0xffb31fd1,
2387 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2392 0xffb004c0, 0xffb31fd1,
2393 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2398 0xfc200840, 0xfe211f51,
2399 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2401 /* Vector VCMP floating point T1. */
2402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2404 0xee310f00, 0xeff1ef50,
2405 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2407 /* Vector VCMP floating point T2. */
2408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2410 0xee310f40, 0xeff1ef50,
2411 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2413 /* Vector VCMP T1. */
2414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2416 0xfe010f00, 0xffc1ff51,
2417 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418 /* Vector VCMP T2. */
2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2421 0xfe010f01, 0xffc1ff51,
2422 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423 /* Vector VCMP T3. */
2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2426 0xfe011f00, 0xffc1ff50,
2427 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428 /* Vector VCMP T4. */
2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2431 0xfe010f40, 0xffc1ff70,
2432 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433 /* Vector VCMP T5. */
2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2436 0xfe010f60, 0xffc1ff70,
2437 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438 /* Vector VCMP T6. */
2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2441 0xfe011f40, 0xffc1ff50,
2442 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2447 0xeea00b10, 0xffb10f5f,
2448 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2453 0xff000150, 0xffd11f51,
2454 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2456 /* Vector VFMA, vector * scalar. */
2457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2459 0xee310e40, 0xefb11f70,
2460 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2462 /* Vector VFMA floating point. */
2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2465 0xef000c50, 0xffa11f51,
2466 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2468 /* Vector VFMS floating point. */
2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2471 0xef200c50, 0xffa11f51,
2472 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2474 /* Vector VFMAS, vector * scalar. */
2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2476 MVE_VFMAS_FP_SCALAR
,
2477 0xee311e40, 0xefb11f70,
2478 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2480 /* Vector VHADD T1. */
2481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2483 0xef000040, 0xef811f51,
2484 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2486 /* Vector VHADD T2. */
2487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2489 0xee000f40, 0xef811f70,
2490 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2492 /* Vector VHSUB T1. */
2493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2495 0xef000240, 0xef811f51,
2496 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2498 /* Vector VHSUB T2. */
2499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2501 0xee001f40, 0xef811f70,
2502 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2507 0xee300e00, 0xefb10f50,
2508 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2513 0xf000e801, 0xffc0ffff,
2514 "vctp%v.%20-21s\t%16-19r"},
2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2519 0xeea00b10, 0xffb10f5f,
2520 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2522 /* Vector VRHADD. */
2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2525 0xef000140, 0xef811f51,
2526 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2530 MVE_VCVT_FP_FIX_VEC
,
2531 0xef800c50, 0xef801cd1,
2532 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2536 MVE_VCVT_BETWEEN_FP_INT
,
2537 0xffb30640, 0xffb31e51,
2538 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2540 /* Vector VCVT between single and half-precision float, bottom half. */
2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2542 MVE_VCVT_FP_HALF_FP
,
2543 0xee3f0e01, 0xefbf1fd1,
2544 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2546 /* Vector VCVT between single and half-precision float, top half. */
2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2548 MVE_VCVT_FP_HALF_FP
,
2549 0xee3f1e01, 0xefbf1fd1,
2550 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2554 MVE_VCVT_FROM_FP_TO_INT
,
2555 0xffb30040, 0xffb31c51,
2556 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2561 0xee011f6e, 0xff811f7e,
2562 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2564 /* Vector VDWDUP. */
2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2567 0xee011f60, 0xff811f70,
2568 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2570 /* Vector VHCADD. */
2571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2573 0xee000f00, 0xff810f51,
2574 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2576 /* Vector VIWDUP. */
2577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2579 0xee010f60, 0xff811f70,
2580 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2585 0xee010f6e, 0xff811f7e,
2586 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2591 0xfc901e00, 0xff901e5f,
2592 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2597 0xfc901e01, 0xff901e1f,
2598 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2600 /* Vector VLDRB gather load. */
2601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2602 MVE_VLDRB_GATHER_T1
,
2603 0xec900e00, 0xefb01e50,
2604 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2606 /* Vector VLDRH gather load. */
2607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2608 MVE_VLDRH_GATHER_T2
,
2609 0xec900e10, 0xefb01e50,
2610 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2612 /* Vector VLDRW gather load. */
2613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2614 MVE_VLDRW_GATHER_T3
,
2615 0xfc900f40, 0xffb01fd0,
2616 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2618 /* Vector VLDRD gather load. */
2619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2620 MVE_VLDRD_GATHER_T4
,
2621 0xec900fd0, 0xefb01fd0,
2622 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2624 /* Vector VLDRW gather load. */
2625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2626 MVE_VLDRW_GATHER_T5
,
2627 0xfd101e00, 0xff111f00,
2628 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2630 /* Vector VLDRD gather load, variant T6. */
2631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2632 MVE_VLDRD_GATHER_T6
,
2633 0xfd101f00, 0xff111f00,
2634 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2639 0xec100e00, 0xee581e00,
2640 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2645 0xec180e00, 0xee581e00,
2646 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2648 /* Vector VLDRB unsigned, variant T5. */
2649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2651 0xec101e00, 0xfe101f80,
2652 "vldrb%v.u8\t%13-15,22Q, %d"},
2654 /* Vector VLDRH unsigned, variant T6. */
2655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2657 0xec101e80, 0xfe101f80,
2658 "vldrh%v.u16\t%13-15,22Q, %d"},
2660 /* Vector VLDRW unsigned, variant T7. */
2661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2663 0xec101f00, 0xfe101f80,
2664 "vldrw%v.u32\t%13-15,22Q, %d"},
2667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2669 0xef000640, 0xef811f51,
2670 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2675 0xee330e81, 0xffb31fd1,
2676 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2678 /* Vector VMAXNM floating point. */
2679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2681 0xff000f50, 0xffa11f51,
2682 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2684 /* Vector VMAXNMA floating point. */
2685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2687 0xee3f0e81, 0xefbf1fd1,
2688 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2690 /* Vector VMAXNMV floating point. */
2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2693 0xeeee0f00, 0xefff0fd1,
2694 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2696 /* Vector VMAXNMAV floating point. */
2697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2699 0xeeec0f00, 0xefff0fd1,
2700 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2703 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2705 0xeee20f00, 0xeff30fd1,
2706 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2708 /* Vector VMAXAV. */
2709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2711 0xeee00f00, 0xfff30fd1,
2712 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2717 0xef000650, 0xef811f51,
2718 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2721 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2723 0xee331e81, 0xffb31fd1,
2724 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2726 /* Vector VMINNM floating point. */
2727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2729 0xff200f50, 0xffa11f51,
2730 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2732 /* Vector VMINNMA floating point. */
2733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2735 0xee3f1e81, 0xefbf1fd1,
2736 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2738 /* Vector VMINNMV floating point. */
2739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2741 0xeeee0f80, 0xefff0fd1,
2742 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2744 /* Vector VMINNMAV floating point. */
2745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2747 0xeeec0f80, 0xefff0fd1,
2748 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2753 0xeee20f80, 0xeff30fd1,
2754 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2756 /* Vector VMINAV. */
2757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2759 0xeee00f80, 0xfff30fd1,
2760 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2765 0xee010e40, 0xef811f70,
2766 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2768 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2772 0xee801e00, 0xef801f51,
2773 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2777 0xee800e00, 0xef801f51,
2778 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2780 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2783 0xeef00e00, 0xeff01f51,
2784 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2786 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2787 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2789 0xeef00f00, 0xeff11f51,
2790 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2792 /* Vector VMLADAV T1 variant. */
2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2795 0xeef01e00, 0xeff01f51,
2796 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2798 /* Vector VMLADAV T2 variant. */
2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2801 0xeef01f00, 0xeff11f51,
2802 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2807 0xee011e40, 0xef811f70,
2808 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2810 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2812 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2814 0xfe800e01, 0xff810f51,
2815 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2817 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2819 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2821 0xee800e01, 0xff800f51,
2822 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2824 /* Vector VMLSDAV T1 Variant. */
2825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2827 0xeef00e01, 0xfff00f51,
2828 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2830 /* Vector VMLSDAV T2 Variant. */
2831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2833 0xfef00e01, 0xfff10f51,
2834 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2836 /* Vector VMOV between gpr and half precision register, op == 0. */
2837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2839 0xee000910, 0xfff00f7f,
2840 "vmov.f16\t%7,16-19F, %12-15r"},
2842 /* Vector VMOV between gpr and half precision register, op == 1. */
2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2845 0xee100910, 0xfff00f7f,
2846 "vmov.f16\t%12-15r, %7,16-19F"},
2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2849 MVE_VMOV_GP_TO_VEC_LANE
,
2850 0xee000b10, 0xff900f1f,
2851 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2853 /* Vector VORR immediate to vector.
2854 NOTE: MVE_VORR_IMM must appear in the table
2855 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2858 0xef800050, 0xefb810f0,
2859 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2861 /* Vector VQSHL T2 Variant.
2862 NOTE: MVE_VQSHL_T2 must appear in the table before
2863 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2866 0xef800750, 0xef801fd1,
2867 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2869 /* Vector VQSHLU T3 Variant
2870 NOTE: MVE_VQSHL_T2 must appear in the table before
2871 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2873 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2875 0xff800650, 0xff801fd1,
2876 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2879 NOTE: MVE_VRSHR must appear in the table before
2880 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2883 0xef800250, 0xef801fd1,
2884 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2887 NOTE: MVE_VSHL must appear in the table before
2888 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2891 0xef800550, 0xff801fd1,
2892 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2895 NOTE: MVE_VSHR must appear in the table before
2896 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2899 0xef800050, 0xef801fd1,
2900 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2903 NOTE: MVE_VSLI must appear in the table before
2904 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2907 0xff800550, 0xff801fd1,
2908 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2911 NOTE: MVE_VSRI must appear in the table before
2912 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2915 0xff800450, 0xff801fd1,
2916 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2918 /* Vector VMOV immediate to vector,
2919 undefinded for cmode == 1111 */
2920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2921 MVE_VMVN_IMM
, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION
},
2923 /* Vector VMOV immediate to vector,
2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2926 MVE_VMOV_IMM_TO_VEC
, 0xef800d50, 0xefb81fd0,
2927 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2929 /* Vector VMOV immediate to vector. */
2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2931 MVE_VMOV_IMM_TO_VEC
,
2932 0xef800050, 0xefb810d0,
2933 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2935 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2937 MVE_VMOV2_VEC_LANE_TO_GP
,
2938 0xec000f00, 0xffb01ff0,
2939 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2941 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2943 MVE_VMOV2_VEC_LANE_TO_GP
,
2944 0xec000f10, 0xffb01ff0,
2945 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2947 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2949 MVE_VMOV2_GP_TO_VEC_LANE
,
2950 0xec100f00, 0xffb01ff0,
2951 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2953 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2955 MVE_VMOV2_GP_TO_VEC_LANE
,
2956 0xec100f10, 0xffb01ff0,
2957 "vmov%c\t%13-15,22Q[3], %13-15,22Q[1], %0-3r, %16-19r"},
2959 /* Vector VMOV Vector lane to gpr. */
2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2961 MVE_VMOV_VEC_LANE_TO_GP
,
2962 0xee100b10, 0xff100f1f,
2963 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2965 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2966 to instruction opcode aliasing. */
2967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2969 0xeea00f40, 0xefa00fd1,
2970 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2972 /* Vector VMOVL long. */
2973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2975 0xeea00f40, 0xefa70fd1,
2976 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2978 /* Vector VMOV and narrow. */
2979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2981 0xfe310e81, 0xffb30fd1,
2982 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2984 /* Floating point move extract. */
2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2987 0xfeb00a40, 0xffbf0fd0,
2988 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2990 /* Vector VMUL floating-point T1 variant. */
2991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2993 0xff000d50, 0xffa11f51,
2994 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2996 /* Vector VMUL floating-point T2 variant. */
2997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2999 0xee310e60, 0xefb11f70,
3000 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3002 /* Vector VMUL T1 variant. */
3003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3005 0xef000950, 0xff811f51,
3006 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3008 /* Vector VMUL T2 variant. */
3009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3011 0xee011e60, 0xff811f70,
3012 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3017 0xee010e01, 0xef811f51,
3018 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3020 /* Vector VRMULH. */
3021 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3023 0xee011e01, 0xef811f51,
3024 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3026 /* Vector VMULL integer. */
3027 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3029 0xee010e00, 0xef810f51,
3030 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3032 /* Vector VMULL polynomial. */
3033 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3035 0xee310e00, 0xefb10f51,
3036 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3038 /* Vector VMVN immediate to vector. */
3039 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3041 0xef800070, 0xefb810f0,
3042 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3044 /* Vector VMVN register. */
3045 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3047 0xffb005c0, 0xffbf1fd1,
3048 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3050 /* Vector VNEG floating point. */
3051 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3053 0xffb107c0, 0xffb31fd1,
3054 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3059 0xffb103c0, 0xffb31fd1,
3060 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3062 /* Vector VORN, vector bitwise or not. */
3063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3065 0xef300150, 0xffb11f51,
3066 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3068 /* Vector VORR register. */
3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3071 0xef200150, 0xffb11f51,
3072 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3074 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3080 MVE_VMOV_VEC_TO_VEC
,
3081 0xef200150, 0xffb11f51,
3082 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3084 /* Vector VQDMULL T1 variant. */
3085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3087 0xee300f01, 0xefb10f51,
3088 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3093 0xfe310f4d, 0xffffffff,
3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3099 0xfe310f01, 0xffb11f51,
3100 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3105 0xffb00740, 0xffb31fd1,
3106 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3108 /* Vector VQADD T1 variant. */
3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3111 0xef000050, 0xef811f51,
3112 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3114 /* Vector VQADD T2 variant. */
3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3117 0xee000f60, 0xef811f70,
3118 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3120 /* Vector VQDMULL T2 variant. */
3121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3123 0xee300f60, 0xefb10f70,
3124 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3126 /* Vector VQMOVN. */
3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3129 0xee330e01, 0xefb30fd1,
3130 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3132 /* Vector VQMOVUN. */
3133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3135 0xee310e81, 0xffb30fd1,
3136 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3138 /* Vector VQDMLADH. */
3139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3141 0xee000e00, 0xff810f51,
3142 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3144 /* Vector VQRDMLADH. */
3145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3147 0xee000e01, 0xff810f51,
3148 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3150 /* Vector VQDMLAH. */
3151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3153 0xee000e60, 0xff811f70,
3154 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3156 /* Vector VQRDMLAH. */
3157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3159 0xee000e40, 0xff811f70,
3160 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3162 /* Vector VQDMLASH. */
3163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3165 0xee001e60, 0xff811f70,
3166 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3168 /* Vector VQRDMLASH. */
3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3171 0xee001e40, 0xff811f70,
3172 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3174 /* Vector VQDMLSDH. */
3175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3177 0xfe000e00, 0xff810f51,
3178 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3180 /* Vector VQRDMLSDH. */
3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3183 0xfe000e01, 0xff810f51,
3184 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3186 /* Vector VQDMULH T1 variant. */
3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3189 0xef000b40, 0xff811f51,
3190 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3192 /* Vector VQRDMULH T2 variant. */
3193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3195 0xff000b40, 0xff811f51,
3196 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3198 /* Vector VQDMULH T3 variant. */
3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3201 0xee010e60, 0xff811f70,
3202 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3204 /* Vector VQRDMULH T4 variant. */
3205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3207 0xfe010e60, 0xff811f70,
3208 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3213 0xffb007c0, 0xffb31fd1,
3214 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3216 /* Vector VQRSHL T1 variant. */
3217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3219 0xef000550, 0xef811f51,
3220 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3222 /* Vector VQRSHL T2 variant. */
3223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3225 0xee331ee0, 0xefb31ff0,
3226 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3228 /* Vector VQRSHRN. */
3229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3231 0xee800f41, 0xefa00fd1,
3232 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3234 /* Vector VQRSHRUN. */
3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3237 0xfe800fc0, 0xffa00fd1,
3238 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3240 /* Vector VQSHL T1 Variant. */
3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3243 0xee311ee0, 0xefb31ff0,
3244 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3246 /* Vector VQSHL T4 Variant. */
3247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3249 0xef000450, 0xef811f51,
3250 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3252 /* Vector VQSHRN. */
3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3255 0xee800f40, 0xefa00fd1,
3256 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3258 /* Vector VQSHRUN. */
3259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3261 0xee800fc0, 0xffa00fd1,
3262 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3264 /* Vector VQSUB T1 Variant. */
3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3267 0xef000250, 0xef811f51,
3268 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3270 /* Vector VQSUB T2 Variant. */
3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3273 0xee001f60, 0xef811f70,
3274 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3276 /* Vector VREV16. */
3277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3279 0xffb00140, 0xffb31fd1,
3280 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3282 /* Vector VREV32. */
3283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3285 0xffb000c0, 0xffb31fd1,
3286 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3288 /* Vector VREV64. */
3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3291 0xffb00040, 0xffb31fd1,
3292 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3294 /* Vector VRINT floating point. */
3295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3297 0xffb20440, 0xffb31c51,
3298 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3300 /* Vector VRMLALDAVH. */
3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3303 0xee800f00, 0xef811f51,
3304 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3306 /* Vector VRMLALDAVH. */
3307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3309 0xee801f00, 0xef811f51,
3310 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3312 /* Vector VRSHL T1 Variant. */
3313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3315 0xef000540, 0xef811f51,
3316 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3318 /* Vector VRSHL T2 Variant. */
3319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3321 0xee331e60, 0xefb31ff0,
3322 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3324 /* Vector VRSHRN. */
3325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3327 0xfe800fc1, 0xffa00fd1,
3328 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3333 0xfe300f00, 0xffb10f51,
3334 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3336 /* Vector VSHL T2 Variant. */
3337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3339 0xee311e60, 0xefb31ff0,
3340 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3342 /* Vector VSHL T3 Variant. */
3343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3345 0xef000440, 0xef811f51,
3346 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3351 0xeea00fc0, 0xffa01ff0,
3352 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3354 /* Vector VSHLL T2 Variant. */
3355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3357 0xee310e01, 0xefb30fd1,
3358 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3363 0xee800fc1, 0xffa00fd1,
3364 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3366 /* Vector VST2 no writeback. */
3367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3369 0xfc801e00, 0xffb01e5f,
3370 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3372 /* Vector VST2 writeback. */
3373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3375 0xfca01e00, 0xffb01e5f,
3376 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3378 /* Vector VST4 no writeback. */
3379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3381 0xfc801e01, 0xffb01e1f,
3382 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3384 /* Vector VST4 writeback. */
3385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3387 0xfca01e01, 0xffb01e1f,
3388 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3390 /* Vector VSTRB scatter store, T1 variant. */
3391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3392 MVE_VSTRB_SCATTER_T1
,
3393 0xec800e00, 0xffb01e50,
3394 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3396 /* Vector VSTRH scatter store, T2 variant. */
3397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3398 MVE_VSTRH_SCATTER_T2
,
3399 0xec800e10, 0xffb01e50,
3400 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3402 /* Vector VSTRW scatter store, T3 variant. */
3403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3404 MVE_VSTRW_SCATTER_T3
,
3405 0xec800e40, 0xffb01e50,
3406 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3408 /* Vector VSTRD scatter store, T4 variant. */
3409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3410 MVE_VSTRD_SCATTER_T4
,
3411 0xec800fd0, 0xffb01fd0,
3412 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3414 /* Vector VSTRW scatter store, T5 variant. */
3415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3416 MVE_VSTRW_SCATTER_T5
,
3417 0xfd001e00, 0xff111f00,
3418 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3420 /* Vector VSTRD scatter store, T6 variant. */
3421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3422 MVE_VSTRD_SCATTER_T6
,
3423 0xfd001f00, 0xff111f00,
3424 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3429 0xec000e00, 0xfe581e00,
3430 "vstrb%v.%7-8s\t%13-15Q, %d"},
3433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3435 0xec080e00, 0xfe581e00,
3436 "vstrh%v.%7-8s\t%13-15Q, %d"},
3438 /* Vector VSTRB variant T5. */
3439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3441 0xec001e00, 0xfe101f80,
3442 "vstrb%v.8\t%13-15,22Q, %d"},
3444 /* Vector VSTRH variant T6. */
3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3447 0xec001e80, 0xfe101f80,
3448 "vstrh%v.16\t%13-15,22Q, %d"},
3450 /* Vector VSTRW variant T7. */
3451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3453 0xec001f00, 0xfe101f80,
3454 "vstrw%v.32\t%13-15,22Q, %d"},
3456 /* Vector VSUB floating point T1 variant. */
3457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3459 0xef200d40, 0xffa11f51,
3460 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3462 /* Vector VSUB floating point T2 variant. */
3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3465 0xee301f40, 0xefb11f70,
3466 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3468 /* Vector VSUB T1 variant. */
3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3471 0xff000840, 0xff811f51,
3472 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3474 /* Vector VSUB T2 variant. */
3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3477 0xee011f40, 0xff811f70,
3478 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3482 0xea50012f, 0xfff1813f,
3483 "asrl%c\t%17-19l, %9-11h, %j"},
3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3487 0xea50012d, 0xfff101ff,
3488 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3492 0xea50010f, 0xfff1813f,
3493 "lsll%c\t%17-19l, %9-11h, %j"},
3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3497 0xea50010d, 0xfff101ff,
3498 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3502 0xea50011f, 0xfff1813f,
3503 "lsrl%c\t%17-19l, %9-11h, %j"},
3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3507 0xea51012d, 0xfff1017f,
3508 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3512 0xea500f2d, 0xfff00fff,
3513 "sqrshr%c\t%16-19S, %12-15S"},
3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3517 0xea51013f, 0xfff1813f,
3518 "sqshll%c\t%17-19l, %9-11h, %j"},
3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3522 0xea500f3f, 0xfff08f3f,
3523 "sqshl%c\t%16-19S, %j"},
3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3527 0xea51012f, 0xfff1813f,
3528 "srshrl%c\t%17-19l, %9-11h, %j"},
3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3532 0xea500f2f, 0xfff08f3f,
3533 "srshr%c\t%16-19S, %j"},
3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3537 0xea51010d, 0xfff1017f,
3538 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3542 0xea500f0d, 0xfff00fff,
3543 "uqrshl%c\t%16-19S, %12-15S"},
3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3547 0xea51010f, 0xfff1813f,
3548 "uqshll%c\t%17-19l, %9-11h, %j"},
3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3552 0xea500f0f, 0xfff08f3f,
3553 "uqshl%c\t%16-19S, %j"},
3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3557 0xea51011f, 0xfff1813f,
3558 "urshrl%c\t%17-19l, %9-11h, %j"},
3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3562 0xea500f1f, 0xfff08f3f,
3563 "urshr%c\t%16-19S, %j"},
3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3567 0xea509000, 0xfff0f000,
3568 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3572 0xea50a000, 0xfff0f000,
3573 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3577 0xea5f900f, 0xfffff00f,
3578 "cset\t%8-11S, %4-7C"},
3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3582 0xea5fa00f, 0xfffff00f,
3583 "csetm\t%8-11S, %4-7C"},
3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3587 0xea508000, 0xfff0f000,
3588 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3592 0xea50b000, 0xfff0f000,
3593 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3597 0xea509000, 0xfff0f000,
3598 "cinc\t%8-11S, %16-19Z, %4-7C"},
3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3602 0xea50a000, 0xfff0f000,
3603 "cinv\t%8-11S, %16-19Z, %4-7C"},
3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3607 0xea50b000, 0xfff0f000,
3608 "cneg\t%8-11S, %16-19Z, %4-7C"},
3610 {ARM_FEATURE_CORE_LOW (0),
3612 0x00000000, 0x00000000, 0}
3615 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3616 ordered: they must be searched linearly from the top to obtain a correct
3619 /* print_insn_arm recognizes the following format control codes:
3623 %a print address for ldr/str instruction
3624 %s print address for ldr/str halfword/signextend instruction
3625 %S like %s but allow UNPREDICTABLE addressing
3626 %b print branch destination
3627 %c print condition code (always bits 28-31)
3628 %m print register mask for ldm/stm instruction
3629 %o print operand2 (immediate or register + shift)
3630 %p print 'p' iff bits 12-15 are 15
3631 %t print 't' iff bit 21 set and bit 24 clear
3632 %B print arm BLX(1) destination
3633 %C print the PSR sub type.
3634 %U print barrier type.
3635 %P print address for pli instruction.
3637 %<bitfield>r print as an ARM register
3638 %<bitfield>T print as an ARM register + 1
3639 %<bitfield>R as %r but r15 is UNPREDICTABLE
3640 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3642 %<bitfield>d print the bitfield in decimal
3643 %<bitfield>W print the bitfield plus one in decimal
3644 %<bitfield>x print the bitfield in hex
3645 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3647 %<bitfield>'c print specified char iff bitfield is all ones
3648 %<bitfield>`c print specified char iff bitfield is all zeroes
3649 %<bitfield>?ab... select from array of values in big endian order
3651 %e print arm SMI operand (bits 0..7,8..19).
3652 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3653 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3654 %R print the SPSR/CPSR or banked register of an MRS. */
3656 static const struct opcode32 arm_opcodes
[] =
3658 /* ARM instructions. */
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3660 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3662 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
3665 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3667 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3669 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
3671 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3673 0x00800090, 0x0fa000f0,
3674 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3676 0x00a00090, 0x0fa000f0,
3677 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3679 /* V8.2 RAS extension instructions. */
3680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3681 0xe320f010, 0xffffffff, "esb"},
3683 /* V8-R instructions. */
3684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
),
3685 0xf57ff04c, 0xffffffff, "dfb"},
3687 /* V8 instructions. */
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3689 0x0320f005, 0x0fffffff, "sevl"},
3690 /* Defined in V8 but is in NOP space so available to all arch. */
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3692 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
3694 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3696 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3698 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3700 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3701 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3702 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3703 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3704 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3705 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3706 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3707 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3708 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3710 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3711 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3712 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3713 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3714 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3715 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3716 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3717 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3718 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3719 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3720 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3721 /* CRC32 instructions. */
3722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3723 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3725 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3727 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3729 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3731 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3733 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3735 /* Privileged Access Never extension instructions. */
3736 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
3737 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3739 /* Virtualization Extension instructions. */
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3743 /* Integer Divide Extension instructions. */
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3745 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3747 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3749 /* MP Extension instructions. */
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3752 /* Speculation Barriers. */
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
3757 /* V7 instructions. */
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3766 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3768 /* ARM V6T2 instructions. */
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3770 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3772 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3774 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3776 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3779 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3781 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3784 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3786 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3788 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3790 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3792 /* ARM Security extension instructions. */
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
3794 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3796 /* ARM V6K instructions. */
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3798 0xf57ff01f, 0xffffffff, "clrex"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3800 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3802 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3804 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3806 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3808 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3810 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3812 /* ARMv8.5-A instructions. */
3813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
3815 /* ARM V6K NOP hints. */
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3817 0x0320f001, 0x0fffffff, "yield%c"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3819 0x0320f002, 0x0fffffff, "wfe%c"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3821 0x0320f003, 0x0fffffff, "wfi%c"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3823 0x0320f004, 0x0fffffff, "sev%c"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3825 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3827 /* ARM V6 instructions. */
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3829 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3831 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3833 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3835 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3837 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3839 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3841 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3843 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3845 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3847 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3849 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3851 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3853 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3855 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3857 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3859 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3861 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3863 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3865 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3867 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3869 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3871 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3873 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3875 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3877 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3879 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3881 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3883 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3885 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3887 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3889 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3891 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3893 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3895 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3897 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3899 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3901 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3903 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3905 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3907 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3909 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3911 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3913 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3915 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3917 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3919 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3921 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3923 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3925 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3927 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3929 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3931 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3933 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3935 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3937 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3939 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3941 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3943 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3945 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3947 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3949 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3951 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3953 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3955 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3957 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3959 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3961 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3963 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3965 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3967 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3969 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3971 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3973 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3975 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3977 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3979 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3981 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3983 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3985 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3987 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3989 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3991 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3993 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3995 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3997 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3999 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4001 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4003 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4005 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4007 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4009 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4011 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4013 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4015 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4017 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4019 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4021 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4023 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4025 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4027 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4029 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4031 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4033 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4035 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4037 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4039 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4041 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4043 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4045 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4047 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4049 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4051 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4053 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4055 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4057 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4059 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4061 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4063 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4065 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4067 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4069 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4071 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
4073 /* V5J instruction. */
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
4075 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
4077 /* V5 Instructions. */
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4079 0xe1200070, 0xfff000f0,
4080 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4082 0xfa000000, 0xfe000000, "blx\t%B"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4084 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4086 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4088 /* V5E "El Segundo" Instructions. */
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4090 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4092 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4094 0xf450f000, 0xfc70f000, "pld\t%a"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4096 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4098 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4100 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4102 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4105 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4107 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4110 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4112 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4114 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4116 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4119 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4121 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4123 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4125 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4128 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4130 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4133 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4135 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4137 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4139 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4141 /* ARM Instructions. */
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4143 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4146 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4148 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4150 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4152 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4154 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4156 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4159 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4161 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4163 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4165 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4168 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4170 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4172 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4174 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4177 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4179 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4181 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4184 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4186 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4188 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4191 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4193 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4195 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4198 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4200 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4202 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4205 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4207 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4209 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4212 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4214 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4216 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4219 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4221 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4223 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4226 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4228 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4230 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
4233 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4235 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4237 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4240 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4242 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4244 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4247 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4249 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4251 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4254 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4256 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4258 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4261 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4263 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4265 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4268 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4270 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4272 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4275 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4277 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4279 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4281 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4283 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4285 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4287 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4290 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4292 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4294 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4297 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4299 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4301 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4304 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4306 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4309 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4312 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4314 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4317 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4319 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4321 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4323 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4325 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4327 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4329 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4331 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4333 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4335 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4337 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4339 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4341 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4343 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4345 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4347 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4349 0x092d0000, 0x0fff0000, "push%c\t%m"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4351 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4353 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4356 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4358 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4360 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4362 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4364 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4366 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4368 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4370 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4372 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4374 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4376 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4378 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4380 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4382 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4384 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4386 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4388 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4390 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4392 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4395 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4397 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
4401 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4403 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4404 {ARM_FEATURE_CORE_LOW (0),
4405 0x00000000, 0x00000000, 0}
4408 /* print_insn_thumb16 recognizes the following format control codes:
4410 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4411 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4412 %<bitfield>I print bitfield as a signed decimal
4413 (top bit of range being the sign bit)
4414 %N print Thumb register mask (with LR)
4415 %O print Thumb register mask (with PC)
4416 %M print Thumb register mask
4417 %b print CZB's 6-bit unsigned branch destination
4418 %s print Thumb right-shift immediate (6..10; 0 == 32).
4419 %c print the condition code
4420 %C print the condition code, or "s" if not conditional
4421 %x print warning if conditional an not at end of IT block"
4422 %X print "\t; unpredictable <IT:code>" if conditional
4423 %I print IT instruction suffix and operands
4424 %W print Thumb Writeback indicator for LDMIA
4425 %<bitfield>r print bitfield as an ARM register
4426 %<bitfield>d print bitfield as a decimal
4427 %<bitfield>H print (bitfield * 2) as a decimal
4428 %<bitfield>W print (bitfield * 4) as a decimal
4429 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4430 %<bitfield>B print Thumb branch destination (signed displacement)
4431 %<bitfield>c print bitfield as a condition code
4432 %<bitnum>'c print specified char iff bit is one
4433 %<bitnum>?ab print a if bit is one else print b. */
4435 static const struct opcode16 thumb_opcodes
[] =
4437 /* Thumb instructions. */
4439 /* ARMv8-M Security Extensions instructions. */
4440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
4441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
4443 /* ARM V8 instructions. */
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4448 /* ARM V6K no-argument instructions. */
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4456 /* ARM V6T2 instructions. */
4457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4458 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4460 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4476 /* ARM V5 ISA extends Thumb. */
4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4478 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4479 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4481 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4482 /* ARM V4T ISA (Thumb v1). */
4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4484 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4515 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4517 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4519 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4521 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4524 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4526 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4528 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4531 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4533 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4537 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4546 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4549 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4552 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4554 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4556 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4558 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4561 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4563 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4566 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4568 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4571 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4573 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4586 /* The E800 .. FFFF range is unconditionally redirected to the
4587 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588 are processed via that table. Thus, we can never encounter a
4589 bare "second half of BL/BLX(1)" instruction here. */
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
4591 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4594 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595 We adopt the convention that hw1 is the high 16 bits of .value and
4596 .mask, hw2 the low 16 bits.
4598 print_insn_thumb32 recognizes the following format control codes:
4602 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603 %M print a modified 12-bit immediate (same location)
4604 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4606 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4607 %S print a possibly-shifted Rm
4609 %L print address for a ldrd/strd instruction
4610 %a print the address of a plain load/store
4611 %w print the width and signedness of a core load/store
4612 %m print register mask for ldm/stm
4613 %n print register mask for clrm
4615 %E print the lsb and width fields of a bfc/bfi instruction
4616 %F print the lsb and width fields of a sbfx/ubfx instruction
4617 %G print a fallback offset for Branch Future instructions
4618 %W print an offset for BF instruction
4619 %Y print an offset for BFL instruction
4620 %Z print an offset for BFCSEL instruction
4621 %Q print an offset for Low Overhead Loop instructions
4622 %P print an offset for Low Overhead Loop end instructions
4623 %b print a conditional branch offset
4624 %B print an unconditional branch offset
4625 %s print the shift field of an SSAT instruction
4626 %R print the rotation field of an SXT instruction
4627 %U print barrier type.
4628 %P print address for pli instruction.
4629 %c print the condition code
4630 %x print warning if conditional an not at end of IT block"
4631 %X print "\t; unpredictable <IT:code>" if conditional
4633 %<bitfield>d print bitfield in decimal
4634 %<bitfield>D print bitfield plus one in decimal
4635 %<bitfield>W print bitfield*4 in decimal
4636 %<bitfield>r print bitfield as an ARM register
4637 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4638 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4639 %<bitfield>c print bitfield as a condition code
4641 %<bitfield>'c print specified char iff bitfield is all ones
4642 %<bitfield>`c print specified char iff bitfield is all zeroes
4643 %<bitfield>?ab... select from array of values in big endian order
4645 With one exception at the bottom (done because BL and BLX(1) need
4646 to come dead last), this table was machine-sorted first in
4647 decreasing order of number of bits set in the mask, then in
4648 increasing numeric order of mask, then in increasing numeric order
4649 of opcode. This order is not the clearest for a human reader, but
4650 is guaranteed never to catch a special-case bit pattern with a more
4651 general mask, which is important, because this instruction encoding
4652 makes heavy use of special-case bit patterns. */
4653 static const struct opcode32 thumb32_opcodes
[] =
4655 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4658 0xf00fe001, 0xffffffff, "lctp%c"},
4659 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4660 0xf02fc001, 0xfffff001, "le\t%P"},
4661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4662 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4663 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4664 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4666 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4668 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4670 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4671 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4672 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4675 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4677 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4679 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4681 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4683 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4686 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4688 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4689 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
4690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4691 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4692 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4693 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4694 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4695 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4697 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4699 /* ARM V8.2 RAS extension instructions. */
4700 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
4701 0xf3af8010, 0xffffffff, "esb"},
4703 /* V8 instructions. */
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4705 0xf3af8005, 0xffffffff, "sevl%c.w"},
4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4707 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4709 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4711 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4713 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4715 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4717 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4719 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4721 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4723 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4725 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4727 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4729 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4731 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4733 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4735 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4737 /* V8-R instructions. */
4738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
),
4739 0xf3bf8f4c, 0xffffffff, "dfb%c"},
4741 /* CRC32 instructions. */
4742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4743 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4744 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4745 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4747 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4748 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4749 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4751 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4753 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4755 /* Speculation Barriers. */
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
4760 /* V7 instructions. */
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4769 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4771 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4773 /* Virtualization Extension instructions. */
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4775 /* We skip ERET as that is SUBS pc, lr, #0. */
4777 /* MP Extension instructions. */
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4780 /* Security extension instructions. */
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4783 /* ARMv8.5-A instructions. */
4784 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
4786 /* Instructions defined in the basic V6T2 set. */
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4793 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4796 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4797 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4799 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4801 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4803 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4805 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4807 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4809 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4811 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4813 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4815 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4817 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4819 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4821 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4823 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4824 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4825 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4826 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4827 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4829 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4831 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4833 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4835 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4837 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4839 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4841 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4843 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4844 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4845 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4847 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4849 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4851 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4853 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4855 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4857 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4859 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4861 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4863 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4865 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4867 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4869 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4871 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4873 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4875 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4877 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4879 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4881 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4883 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4885 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4887 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4889 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4891 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4893 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4895 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4897 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4899 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4901 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4903 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4905 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4907 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4909 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4911 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4913 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4915 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4917 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4919 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4921 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4923 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4925 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4927 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4929 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4931 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4933 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4935 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4937 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4939 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4941 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4943 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4945 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4947 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4949 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4951 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4952 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4953 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4955 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4957 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4959 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4961 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4963 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4965 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4967 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4969 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4971 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4973 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4975 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4977 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4979 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4981 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4983 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4985 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4987 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4989 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4991 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4993 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4995 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4997 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4999 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5001 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5003 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5005 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5007 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5009 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5011 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5013 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5015 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5017 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5019 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5021 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5023 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5025 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5027 0xf810f000, 0xff70f000, "pld%c\t%a"},
5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5029 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5031 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5033 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5035 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5037 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5039 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5041 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5043 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5045 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5047 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5049 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5051 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5053 0xfb100000, 0xfff000c0,
5054 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5056 0xfbc00080, 0xfff000c0,
5057 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5059 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5061 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5063 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
5064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5065 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5067 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
5068 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5069 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5071 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
5072 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5073 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5075 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5077 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5079 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5081 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5083 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5085 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5087 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5089 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5091 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5093 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
5094 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5095 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5097 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5099 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5101 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5103 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5105 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5107 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5109 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5111 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5113 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5115 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5117 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5119 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5121 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5123 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5125 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5127 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5129 0xe9400000, 0xff500000,
5130 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5132 0xe9500000, 0xff500000,
5133 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5135 0xe8600000, 0xff700000,
5136 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5138 0xe8700000, 0xff700000,
5139 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5141 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5143 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5145 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
5146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5147 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5149 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5151 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5153 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5155 /* These have been 32-bit since the invention of Thumb. */
5156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5157 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5159 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
5163 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
5164 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5167 static const char *const arm_conditional
[] =
5168 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5169 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5171 static const char *const arm_fp_const
[] =
5172 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5174 static const char *const arm_shift
[] =
5175 {"lsl", "lsr", "asr", "ror"};
5180 const char *description
;
5181 const char *reg_names
[16];
5185 static const arm_regname regnames
[] =
5187 { "reg-names-raw", N_("Select raw register names"),
5188 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5189 { "reg-names-gcc", N_("Select register names used by GCC"),
5190 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5191 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5192 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5193 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
5194 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
5195 { "reg-names-apcs", N_("Select register names used in the APCS"),
5196 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5197 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5198 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5199 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5200 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5201 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL
} }
5204 static const char *const iwmmxt_wwnames
[] =
5205 {"b", "h", "w", "d"};
5207 static const char *const iwmmxt_wwssnames
[] =
5208 {"b", "bus", "bc", "bss",
5209 "h", "hus", "hc", "hss",
5210 "w", "wus", "wc", "wss",
5211 "d", "dus", "dc", "dss"
5214 static const char *const iwmmxt_regnames
[] =
5215 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5216 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5219 static const char *const iwmmxt_cregnames
[] =
5220 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5221 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5224 static const char *const vec_condnames
[] =
5225 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5228 static const char *const mve_predicatenames
[] =
5229 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5230 "eee", "ee", "eet", "e", "ett", "et", "ete"
5233 /* Names for 2-bit size field for mve vector isntructions. */
5234 static const char *const mve_vec_sizename
[] =
5235 { "8", "16", "32", "64"};
5237 /* Indicates whether we are processing a then predicate,
5238 else predicate or none at all. */
5246 /* Information used to process a vpt block and subsequent instructions. */
5249 /* Are we in a vpt block. */
5252 /* Next predicate state if in vpt block. */
5253 enum vpt_pred_state next_pred_state
;
5255 /* Mask from vpt/vpst instruction. */
5256 long predicate_mask
;
5258 /* Instruction number in vpt block. */
5259 long current_insn_num
;
5261 /* Number of instructions in vpt block.. */
5265 static struct vpt_block vpt_block_state
=
5274 /* Default to GCC register name set. */
5275 static unsigned int regname_selected
= 1;
5277 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5278 #define arm_regnames regnames[regname_selected].reg_names
5280 static bool force_thumb
= false;
5281 static uint16_t cde_coprocs
= 0;
5283 /* Current IT instruction state. This contains the same state as the IT
5284 bits in the CPSR. */
5285 static unsigned int ifthen_state
;
5286 /* IT state for the next instruction. */
5287 static unsigned int ifthen_next_state
;
5288 /* The address of the insn for which the IT state is valid. */
5289 static bfd_vma ifthen_address
;
5290 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5291 /* Indicates that the current Conditional state is unconditional or outside
5293 #define COND_UNCOND 16
5297 /* Extract the predicate mask for a VPT or VPST instruction.
5298 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5301 mve_extract_pred_mask (long given
)
5303 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
5306 /* Return the number of instructions in a MVE predicate block. */
5308 num_instructions_vpt_block (long given
)
5310 long mask
= mve_extract_pred_mask (given
);
5317 if ((mask
& 7) == 4)
5320 if ((mask
& 3) == 2)
5323 if ((mask
& 1) == 1)
5330 mark_outside_vpt_block (void)
5332 vpt_block_state
.in_vpt_block
= false;
5333 vpt_block_state
.next_pred_state
= PRED_NONE
;
5334 vpt_block_state
.predicate_mask
= 0;
5335 vpt_block_state
.current_insn_num
= 0;
5336 vpt_block_state
.num_pred_insn
= 0;
5340 mark_inside_vpt_block (long given
)
5342 vpt_block_state
.in_vpt_block
= true;
5343 vpt_block_state
.next_pred_state
= PRED_THEN
;
5344 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
5345 vpt_block_state
.current_insn_num
= 0;
5346 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
5347 assert (vpt_block_state
.num_pred_insn
>= 1);
5350 static enum vpt_pred_state
5351 invert_next_predicate_state (enum vpt_pred_state astate
)
5353 if (astate
== PRED_THEN
)
5355 else if (astate
== PRED_ELSE
)
5361 static enum vpt_pred_state
5362 update_next_predicate_state (void)
5364 long pred_mask
= vpt_block_state
.predicate_mask
;
5365 long mask_for_insn
= 0;
5367 switch (vpt_block_state
.current_insn_num
)
5385 if (pred_mask
& mask_for_insn
)
5386 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
5388 return vpt_block_state
.next_pred_state
;
5392 update_vpt_block_state (void)
5394 vpt_block_state
.current_insn_num
++;
5395 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
5397 /* No more instructions to process in vpt block. */
5398 mark_outside_vpt_block ();
5402 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
5405 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5406 Returns pointer to following character of the format string and
5407 fills in *VALUEP and *WIDTHP with the extracted value and number of
5408 bits extracted. WIDTHP can be NULL. */
5411 arm_decode_bitfield (const char *ptr
,
5413 unsigned long *valuep
,
5416 unsigned long value
= 0;
5424 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5425 start
= start
* 10 + *ptr
- '0';
5427 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5428 end
= end
* 10 + *ptr
- '0';
5434 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
5437 while (*ptr
++ == ',');
5445 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
5448 func (stream
, "%s", arm_regnames
[given
& 0xf]);
5450 if ((given
& 0xff0) != 0)
5452 if ((given
& 0x10) == 0)
5454 int amount
= (given
& 0xf80) >> 7;
5455 int shift
= (given
& 0x60) >> 5;
5461 func (stream
, ", rrx");
5469 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
5471 func (stream
, ", #%d", amount
);
5473 else if ((given
& 0x80) == 0x80)
5474 func (stream
, "\t; <illegal shifter operand>");
5475 else if (print_shift
)
5476 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
5477 arm_regnames
[(given
& 0xf00) >> 8]);
5479 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
5483 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5486 is_mve_okay_in_it (enum mve_instructions matched_insn
)
5488 switch (matched_insn
)
5490 case MVE_VMOV_GP_TO_VEC_LANE
:
5491 case MVE_VMOV2_VEC_LANE_TO_GP
:
5492 case MVE_VMOV2_GP_TO_VEC_LANE
:
5493 case MVE_VMOV_VEC_LANE_TO_GP
:
5518 is_mve_architecture (struct disassemble_info
*info
)
5520 struct arm_private_data
*private_data
= info
->private_data
;
5521 arm_feature_set allowed_arches
= private_data
->features
;
5523 arm_feature_set arm_ext_v8_1m_main
5524 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
5526 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
5527 && !ARM_CPU_IS_ANY (allowed_arches
))
5534 is_vpt_instruction (long given
)
5537 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5538 if ((given
& 0x0040e000) == 0)
5541 /* VPT floating point T1 variant. */
5542 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
5543 /* VPT floating point T2 variant. */
5544 || ((given
& 0xefb10f50) == 0xee310f40)
5545 /* VPT vector T1 variant. */
5546 || ((given
& 0xff811f51) == 0xfe010f00)
5547 /* VPT vector T2 variant. */
5548 || ((given
& 0xff811f51) == 0xfe010f01
5549 && ((given
& 0x300000) != 0x300000))
5550 /* VPT vector T3 variant. */
5551 || ((given
& 0xff811f50) == 0xfe011f00)
5552 /* VPT vector T4 variant. */
5553 || ((given
& 0xff811f70) == 0xfe010f40)
5554 /* VPT vector T5 variant. */
5555 || ((given
& 0xff811f70) == 0xfe010f60)
5556 /* VPT vector T6 variant. */
5557 || ((given
& 0xff811f50) == 0xfe011f40)
5558 /* VPST vector T variant. */
5559 || ((given
& 0xffbf1fff) == 0xfe310f4d))
5565 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5566 and ending bitfield = END. END must be greater than START. */
5568 static unsigned long
5569 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
5571 int bits
= end
- start
;
5576 return ((given
>> start
) & ((2ul << bits
) - 1));
5579 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5580 START:END and START2:END2. END/END2 must be greater than
5583 static unsigned long
5584 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
5585 unsigned int end
, unsigned int start2
,
5588 int bits
= end
- start
;
5589 int bits2
= end2
- start2
;
5590 unsigned long value
= 0;
5596 value
= arm_decode_field (given
, start
, end
);
5599 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
5603 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5604 This helps us decode instructions that change mnemonic depending on specific
5605 operand values/encodings. */
5608 is_mve_encoding_conflict (unsigned long given
,
5609 enum mve_instructions matched_insn
)
5611 switch (matched_insn
)
5614 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5620 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5622 if ((arm_decode_field (given
, 12, 12) == 0)
5623 && (arm_decode_field (given
, 0, 0) == 1))
5628 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5630 if (arm_decode_field (given
, 0, 3) == 0xd)
5634 case MVE_VPT_VEC_T1
:
5635 case MVE_VPT_VEC_T2
:
5636 case MVE_VPT_VEC_T3
:
5637 case MVE_VPT_VEC_T4
:
5638 case MVE_VPT_VEC_T5
:
5639 case MVE_VPT_VEC_T6
:
5640 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5642 if (arm_decode_field (given
, 20, 21) == 3)
5646 case MVE_VCMP_FP_T1
:
5647 if ((arm_decode_field (given
, 12, 12) == 0)
5648 && (arm_decode_field (given
, 0, 0) == 1))
5653 case MVE_VCMP_FP_T2
:
5654 if (arm_decode_field (given
, 0, 3) == 0xd)
5661 case MVE_VMUL_VEC_T2
:
5668 case MVE_VADD_VEC_T2
:
5669 case MVE_VSUB_VEC_T2
:
5686 case MVE_VQDMULH_T3
:
5687 case MVE_VQRDMULH_T4
:
5693 case MVE_VCMP_VEC_T1
:
5694 case MVE_VCMP_VEC_T2
:
5695 case MVE_VCMP_VEC_T3
:
5696 case MVE_VCMP_VEC_T4
:
5697 case MVE_VCMP_VEC_T5
:
5698 case MVE_VCMP_VEC_T6
:
5699 if (arm_decode_field (given
, 20, 21) == 3)
5708 if (arm_decode_field (given
, 7, 8) == 3)
5715 if ((arm_decode_field (given
, 24, 24) == 0)
5716 && (arm_decode_field (given
, 21, 21) == 0))
5720 else if ((arm_decode_field (given
, 7, 8) == 3))
5731 if ((arm_decode_field (given
, 24, 24) == 0)
5732 && (arm_decode_field (given
, 21, 21) == 0))
5739 case MVE_VCVT_FP_FIX_VEC
:
5740 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
5745 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5747 if ((cmode
& 1) == 0)
5749 else if ((cmode
& 0xc) == 0xc)
5757 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5761 else if ((cmode
& 0x9) == 1)
5763 else if ((cmode
& 0xd) == 9)
5769 case MVE_VMOV_IMM_TO_VEC
:
5770 if ((arm_decode_field (given
, 5, 5) == 1)
5771 && (arm_decode_field (given
, 8, 11) != 0xe))
5778 unsigned long size
= arm_decode_field (given
, 19, 20);
5779 if ((size
== 0) || (size
== 3))
5800 if (arm_decode_field (given
, 18, 19) == 3)
5806 case MVE_VRMLSLDAVH
:
5809 if (arm_decode_field (given
, 20, 22) == 7)
5814 case MVE_VRMLALDAVH
:
5815 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
5822 if ((arm_decode_field (given
, 20, 21) == 3)
5823 || (arm_decode_field (given
, 1, 3) == 7))
5830 if (arm_decode_field (given
, 16, 18) == 0)
5832 unsigned long sz
= arm_decode_field (given
, 19, 20);
5834 if ((sz
== 1) || (sz
== 2))
5849 if (arm_decode_field (given
, 19, 21) == 0)
5855 if (arm_decode_field (given
, 16, 19) == 0xf)
5871 if (arm_decode_field (given
, 9, 11) == 0x7)
5879 unsigned long rm
, rn
;
5880 rm
= arm_decode_field (given
, 0, 3);
5881 rn
= arm_decode_field (given
, 16, 19);
5883 if (rm
== 0xf && rn
== 0xf)
5886 else if (rn
== rm
&& rn
!= 0xf)
5892 if (arm_decode_field (given
, 0, 3) == 0xd)
5895 else if (matched_insn
== MVE_CSNEG
)
5896 if (arm_decode_field (given
, 0, 3) == arm_decode_field (given
, 16, 19))
5901 case MVE_VADD_FP_T1
:
5902 case MVE_VADD_FP_T2
:
5903 case MVE_VADD_VEC_T1
:
5910 print_mve_vld_str_addr (struct disassemble_info
*info
,
5911 unsigned long given
,
5912 enum mve_instructions matched_insn
)
5914 void *stream
= info
->stream
;
5915 fprintf_ftype func
= info
->fprintf_func
;
5917 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
5919 imm
= arm_decode_field (given
, 0, 6);
5922 switch (matched_insn
)
5926 gpr
= arm_decode_field (given
, 16, 18);
5931 gpr
= arm_decode_field (given
, 16, 18);
5937 gpr
= arm_decode_field (given
, 16, 19);
5943 gpr
= arm_decode_field (given
, 16, 19);
5949 gpr
= arm_decode_field (given
, 16, 19);
5956 p
= arm_decode_field (given
, 24, 24);
5957 w
= arm_decode_field (given
, 21, 21);
5959 add
= arm_decode_field (given
, 23, 23);
5963 /* Don't print anything for '+' as it is implied. */
5973 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
5974 /* Pre-indexed mode. */
5976 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
5978 else if ((p
== 0) && (w
== 1))
5979 /* Post-index mode. */
5980 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
5983 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5984 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5985 this encoding is undefined. */
5988 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
5989 enum mve_undefined
*undefined_code
)
5991 *undefined_code
= UNDEF_NONE
;
5993 switch (matched_insn
)
5996 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
5998 *undefined_code
= UNDEF_SIZE_3
;
6006 case MVE_VMUL_VEC_T1
:
6008 case MVE_VADD_VEC_T1
:
6009 case MVE_VSUB_VEC_T1
:
6010 case MVE_VQDMULH_T1
:
6011 case MVE_VQRDMULH_T2
:
6015 if (arm_decode_field (given
, 20, 21) == 3)
6017 *undefined_code
= UNDEF_SIZE_3
;
6024 if (arm_decode_field (given
, 7, 8) == 3)
6026 *undefined_code
= UNDEF_SIZE_3
;
6033 if (arm_decode_field (given
, 7, 8) <= 1)
6035 *undefined_code
= UNDEF_SIZE_LE_1
;
6042 if ((arm_decode_field (given
, 7, 8) == 0))
6044 *undefined_code
= UNDEF_SIZE_0
;
6051 if ((arm_decode_field (given
, 7, 8) <= 1))
6053 *undefined_code
= UNDEF_SIZE_LE_1
;
6059 case MVE_VLDRB_GATHER_T1
:
6060 if (arm_decode_field (given
, 7, 8) == 3)
6062 *undefined_code
= UNDEF_SIZE_3
;
6065 else if ((arm_decode_field (given
, 28, 28) == 0)
6066 && (arm_decode_field (given
, 7, 8) == 0))
6068 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
6074 case MVE_VLDRH_GATHER_T2
:
6075 if (arm_decode_field (given
, 7, 8) == 3)
6077 *undefined_code
= UNDEF_SIZE_3
;
6080 else if ((arm_decode_field (given
, 28, 28) == 0)
6081 && (arm_decode_field (given
, 7, 8) == 1))
6083 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
6086 else if (arm_decode_field (given
, 7, 8) == 0)
6088 *undefined_code
= UNDEF_SIZE_0
;
6094 case MVE_VLDRW_GATHER_T3
:
6095 if (arm_decode_field (given
, 7, 8) != 2)
6097 *undefined_code
= UNDEF_SIZE_NOT_2
;
6100 else if (arm_decode_field (given
, 28, 28) == 0)
6102 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6108 case MVE_VLDRD_GATHER_T4
:
6109 if (arm_decode_field (given
, 7, 8) != 3)
6111 *undefined_code
= UNDEF_SIZE_NOT_3
;
6114 else if (arm_decode_field (given
, 28, 28) == 0)
6116 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6122 case MVE_VSTRB_SCATTER_T1
:
6123 if (arm_decode_field (given
, 7, 8) == 3)
6125 *undefined_code
= UNDEF_SIZE_3
;
6131 case MVE_VSTRH_SCATTER_T2
:
6133 unsigned long size
= arm_decode_field (given
, 7, 8);
6136 *undefined_code
= UNDEF_SIZE_3
;
6141 *undefined_code
= UNDEF_SIZE_0
;
6148 case MVE_VSTRW_SCATTER_T3
:
6149 if (arm_decode_field (given
, 7, 8) != 2)
6151 *undefined_code
= UNDEF_SIZE_NOT_2
;
6157 case MVE_VSTRD_SCATTER_T4
:
6158 if (arm_decode_field (given
, 7, 8) != 3)
6160 *undefined_code
= UNDEF_SIZE_NOT_3
;
6166 case MVE_VCVT_FP_FIX_VEC
:
6168 unsigned long imm6
= arm_decode_field (given
, 16, 21);
6169 if ((imm6
& 0x20) == 0)
6171 *undefined_code
= UNDEF_VCVT_IMM6
;
6175 if ((arm_decode_field (given
, 9, 9) == 0)
6176 && ((imm6
& 0x30) == 0x20))
6178 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
6187 case MVE_VCVT_BETWEEN_FP_INT
:
6188 case MVE_VCVT_FROM_FP_TO_INT
:
6190 unsigned long size
= arm_decode_field (given
, 18, 19);
6193 *undefined_code
= UNDEF_SIZE_0
;
6198 *undefined_code
= UNDEF_SIZE_3
;
6205 case MVE_VMOV_VEC_LANE_TO_GP
:
6207 unsigned long op1
= arm_decode_field (given
, 21, 22);
6208 unsigned long op2
= arm_decode_field (given
, 5, 6);
6209 unsigned long u
= arm_decode_field (given
, 23, 23);
6211 if ((op2
== 0) && (u
== 1))
6213 if ((op1
== 0) || (op1
== 1))
6215 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
6223 if ((op1
== 0) || (op1
== 1))
6225 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6235 case MVE_VMOV_GP_TO_VEC_LANE
:
6236 if (arm_decode_field (given
, 5, 6) == 2)
6238 unsigned long op1
= arm_decode_field (given
, 21, 22);
6239 if ((op1
== 0) || (op1
== 1))
6241 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6250 case MVE_VMOV_VEC_TO_VEC
:
6251 if ((arm_decode_field (given
, 5, 5) == 1)
6252 || (arm_decode_field (given
, 22, 22) == 1))
6256 case MVE_VMOV_IMM_TO_VEC
:
6257 if (arm_decode_field (given
, 5, 5) == 0)
6259 unsigned long cmode
= arm_decode_field (given
, 8, 11);
6261 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
6263 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
6274 if (arm_decode_field (given
, 18, 19) == 2)
6276 *undefined_code
= UNDEF_SIZE_2
;
6282 case MVE_VRMLALDAVH
:
6283 case MVE_VMLADAV_T1
:
6284 case MVE_VMLADAV_T2
:
6286 if ((arm_decode_field (given
, 28, 28) == 1)
6287 && (arm_decode_field (given
, 12, 12) == 1))
6289 *undefined_code
= UNDEF_XCHG_UNS
;
6300 unsigned long sz
= arm_decode_field (given
, 19, 20);
6303 else if ((sz
& 2) == 2)
6307 *undefined_code
= UNDEF_SIZE
;
6321 unsigned long sz
= arm_decode_field (given
, 19, 21);
6324 else if ((sz
& 6) == 2)
6326 else if ((sz
& 4) == 4)
6330 *undefined_code
= UNDEF_SIZE
;
6337 if (arm_decode_field (given
, 19, 20) == 0)
6339 *undefined_code
= UNDEF_SIZE_0
;
6346 if (arm_decode_field (given
, 18, 19) == 3)
6348 *undefined_code
= UNDEF_SIZE_3
;
6359 if (arm_decode_field (given
, 18, 19) == 3)
6361 *undefined_code
= UNDEF_SIZE_3
;
6368 if (arm_decode_field (given
, 18, 19) == 0)
6372 *undefined_code
= UNDEF_SIZE_NOT_0
;
6378 unsigned long size
= arm_decode_field (given
, 18, 19);
6379 if ((size
& 2) == 2)
6381 *undefined_code
= UNDEF_SIZE_2
;
6389 if (arm_decode_field (given
, 18, 19) != 3)
6393 *undefined_code
= UNDEF_SIZE_3
;
6402 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6403 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6404 why this encoding is unpredictable. */
6407 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
6408 enum mve_unpredictable
*unpredictable_code
)
6410 *unpredictable_code
= UNPRED_NONE
;
6412 switch (matched_insn
)
6414 case MVE_VCMP_FP_T2
:
6416 if ((arm_decode_field (given
, 12, 12) == 0)
6417 && (arm_decode_field (given
, 5, 5) == 1))
6419 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
6425 case MVE_VPT_VEC_T4
:
6426 case MVE_VPT_VEC_T5
:
6427 case MVE_VPT_VEC_T6
:
6428 case MVE_VCMP_VEC_T4
:
6429 case MVE_VCMP_VEC_T5
:
6430 case MVE_VCMP_VEC_T6
:
6431 if (arm_decode_field (given
, 0, 3) == 0xd)
6433 *unpredictable_code
= UNPRED_R13
;
6441 unsigned long gpr
= arm_decode_field (given
, 12, 15);
6444 *unpredictable_code
= UNPRED_R13
;
6447 else if (gpr
== 0xf)
6449 *unpredictable_code
= UNPRED_R15
;
6458 case MVE_VMUL_FP_T2
:
6459 case MVE_VMUL_VEC_T2
:
6462 case MVE_VADD_FP_T2
:
6463 case MVE_VSUB_FP_T2
:
6464 case MVE_VADD_VEC_T2
:
6465 case MVE_VSUB_VEC_T2
:
6475 case MVE_VQDMULH_T3
:
6476 case MVE_VQRDMULH_T4
:
6478 case MVE_VFMA_FP_SCALAR
:
6479 case MVE_VFMAS_FP_SCALAR
:
6483 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6486 *unpredictable_code
= UNPRED_R13
;
6489 else if (gpr
== 0xf)
6491 *unpredictable_code
= UNPRED_R15
;
6501 unsigned long rn
= arm_decode_field (given
, 16, 19);
6503 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6505 *unpredictable_code
= UNPRED_R13_AND_WB
;
6511 *unpredictable_code
= UNPRED_R15
;
6515 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
6517 *unpredictable_code
= UNPRED_Q_GT_6
;
6527 unsigned long rn
= arm_decode_field (given
, 16, 19);
6529 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6531 *unpredictable_code
= UNPRED_R13_AND_WB
;
6537 *unpredictable_code
= UNPRED_R15
;
6541 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
6543 *unpredictable_code
= UNPRED_Q_GT_4
;
6557 unsigned long rn
= arm_decode_field (given
, 16, 19);
6559 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6561 *unpredictable_code
= UNPRED_R13_AND_WB
;
6566 *unpredictable_code
= UNPRED_R15
;
6573 case MVE_VLDRB_GATHER_T1
:
6574 if (arm_decode_field (given
, 0, 0) == 1)
6576 *unpredictable_code
= UNPRED_OS
;
6581 /* To handle common code with T2-T4 variants. */
6582 case MVE_VLDRH_GATHER_T2
:
6583 case MVE_VLDRW_GATHER_T3
:
6584 case MVE_VLDRD_GATHER_T4
:
6586 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6587 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6591 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6595 if (arm_decode_field (given
, 16, 19) == 0xf)
6597 *unpredictable_code
= UNPRED_R15
;
6604 case MVE_VLDRW_GATHER_T5
:
6605 case MVE_VLDRD_GATHER_T6
:
6607 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6608 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6612 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6619 case MVE_VSTRB_SCATTER_T1
:
6620 if (arm_decode_field (given
, 16, 19) == 0xf)
6622 *unpredictable_code
= UNPRED_R15
;
6625 else if (arm_decode_field (given
, 0, 0) == 1)
6627 *unpredictable_code
= UNPRED_OS
;
6633 case MVE_VSTRH_SCATTER_T2
:
6634 case MVE_VSTRW_SCATTER_T3
:
6635 case MVE_VSTRD_SCATTER_T4
:
6636 if (arm_decode_field (given
, 16, 19) == 0xf)
6638 *unpredictable_code
= UNPRED_R15
;
6644 case MVE_VMOV2_VEC_LANE_TO_GP
:
6645 case MVE_VMOV2_GP_TO_VEC_LANE
:
6646 case MVE_VCVT_BETWEEN_FP_INT
:
6647 case MVE_VCVT_FROM_FP_TO_INT
:
6649 unsigned long rt
= arm_decode_field (given
, 0, 3);
6650 unsigned long rt2
= arm_decode_field (given
, 16, 19);
6652 if ((rt
== 0xd) || (rt2
== 0xd))
6654 *unpredictable_code
= UNPRED_R13
;
6657 else if ((rt
== 0xf) || (rt2
== 0xf))
6659 *unpredictable_code
= UNPRED_R15
;
6662 else if (rt
== rt2
&& matched_insn
!= MVE_VMOV2_GP_TO_VEC_LANE
)
6664 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
6673 case MVE_VMAXNMV_FP
:
6674 case MVE_VMAXNMAV_FP
:
6675 case MVE_VMINNMV_FP
:
6676 case MVE_VMINNMAV_FP
:
6680 case MVE_VMOV_HFP_TO_GP
:
6681 case MVE_VMOV_GP_TO_VEC_LANE
:
6682 case MVE_VMOV_VEC_LANE_TO_GP
:
6684 unsigned long rda
= arm_decode_field (given
, 12, 15);
6687 *unpredictable_code
= UNPRED_R13
;
6690 else if (rda
== 0xf)
6692 *unpredictable_code
= UNPRED_R15
;
6705 if (arm_decode_field (given
, 20, 21) == 2)
6707 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6708 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6709 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6711 if ((Qd
== Qn
) || (Qd
== Qm
))
6713 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6724 case MVE_VQDMULL_T1
:
6730 if (arm_decode_field (given
, 28, 28) == 1)
6732 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6733 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6734 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6736 if ((Qd
== Qn
) || (Qd
== Qm
))
6738 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6748 case MVE_VQDMULL_T2
:
6750 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6753 *unpredictable_code
= UNPRED_R13
;
6756 else if (gpr
== 0xf)
6758 *unpredictable_code
= UNPRED_R15
;
6762 if (arm_decode_field (given
, 28, 28) == 1)
6765 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6766 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6770 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6781 case MVE_VRMLSLDAVH
:
6784 if (arm_decode_field (given
, 20, 22) == 6)
6786 *unpredictable_code
= UNPRED_R13
;
6794 if (arm_decode_field (given
, 1, 3) == 6)
6796 *unpredictable_code
= UNPRED_R13
;
6805 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6806 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6807 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
6809 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6818 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6819 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6820 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
6822 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6835 if (arm_decode_field (given
, 20, 20) == 1)
6837 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6838 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6839 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6841 if ((Qda
== Qn
) || (Qda
== Qm
))
6843 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6855 if (arm_decode_field (given
, 16, 19) == 0xd)
6857 *unpredictable_code
= UNPRED_R13
;
6865 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6866 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 6, 6);
6870 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6889 unsigned long gpr
= arm_decode_field (given
, 9, 11);
6890 gpr
= ((gpr
<< 1) | 1);
6893 *unpredictable_code
= UNPRED_R13
;
6896 else if (gpr
== 0xf)
6898 *unpredictable_code
= UNPRED_R15
;
6911 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
6913 unsigned long op1
= arm_decode_field (given
, 21, 22);
6914 unsigned long op2
= arm_decode_field (given
, 5, 6);
6915 unsigned long h
= arm_decode_field (given
, 16, 16);
6916 unsigned long index_operand
, esize
, targetBeat
, idx
;
6917 void *stream
= info
->stream
;
6918 fprintf_ftype func
= info
->fprintf_func
;
6920 if ((op1
& 0x2) == 0x2)
6922 index_operand
= op2
;
6925 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
6927 index_operand
= op2
>> 1;
6930 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
6937 func (stream
, "<undefined index>");
6941 targetBeat
= (op1
& 0x1) | (h
<< 1);
6942 idx
= index_operand
+ targetBeat
* (32/esize
);
6944 func (stream
, "%lu", idx
);
6947 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6948 in length and integer of floating-point type. */
6950 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
6951 unsigned int ibit_loc
, const struct mopcode32
*insn
)
6954 int cmode
= (given
>> 8) & 0xf;
6955 int op
= (given
>> 5) & 0x1;
6956 unsigned long value
= 0, hival
= 0;
6960 void *stream
= info
->stream
;
6961 fprintf_ftype func
= info
->fprintf_func
;
6963 /* On Neon the 'i' bit is at bit 24, on mve it is
6965 bits
|= ((given
>> ibit_loc
) & 1) << 7;
6966 bits
|= ((given
>> 16) & 7) << 4;
6967 bits
|= ((given
>> 0) & 15) << 0;
6971 shift
= (cmode
>> 1) & 3;
6972 value
= (unsigned long) bits
<< (8 * shift
);
6975 else if (cmode
< 12)
6977 shift
= (cmode
>> 1) & 1;
6978 value
= (unsigned long) bits
<< (8 * shift
);
6981 else if (cmode
< 14)
6983 shift
= (cmode
& 1) + 1;
6984 value
= (unsigned long) bits
<< (8 * shift
);
6985 value
|= (1ul << (8 * shift
)) - 1;
6988 else if (cmode
== 14)
6992 /* Bit replication into bytes. */
6998 for (ix
= 7; ix
>= 0; ix
--)
7000 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
7002 value
= (value
<< 8) | mask
;
7004 hival
= (hival
<< 8) | mask
;
7010 /* Byte replication. */
7011 value
= (unsigned long) bits
;
7017 /* Floating point encoding. */
7020 value
= (unsigned long) (bits
& 0x7f) << 19;
7021 value
|= (unsigned long) (bits
& 0x80) << 24;
7022 tmp
= bits
& 0x40 ? 0x3c : 0x40;
7023 value
|= (unsigned long) tmp
<< 24;
7029 func (stream
, "<illegal constant %.8x:%x:%x>",
7035 /* printU determines whether the immediate value should be printed as
7037 unsigned printU
= 0;
7038 switch (insn
->mve_op
)
7042 /* We want this for instructions that don't have a 'signed' type. */
7046 case MVE_VMOV_IMM_TO_VEC
:
7053 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
7060 : "#%ld\t; 0x%.4lx", value
, value
);
7066 unsigned char valbytes
[4];
7069 /* Do this a byte at a time so we don't have to
7070 worry about the host's endianness. */
7071 valbytes
[0] = value
& 0xff;
7072 valbytes
[1] = (value
>> 8) & 0xff;
7073 valbytes
[2] = (value
>> 16) & 0xff;
7074 valbytes
[3] = (value
>> 24) & 0xff;
7076 floatformat_to_double
7077 (& floatformat_ieee_single_little
, valbytes
,
7080 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
7087 : "#%ld\t; 0x%.8lx",
7088 (long) (((value
& 0x80000000L
) != 0)
7090 ? value
| ~0xffffffffL
: value
),
7095 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
7105 print_mve_undefined (struct disassemble_info
*info
,
7106 enum mve_undefined undefined_code
)
7108 void *stream
= info
->stream
;
7109 fprintf_ftype func
= info
->fprintf_func
;
7111 func (stream
, "\t\tundefined instruction: ");
7113 switch (undefined_code
)
7116 func (stream
, "illegal size");
7120 func (stream
, "size equals zero");
7124 func (stream
, "size equals two");
7128 func (stream
, "size equals three");
7131 case UNDEF_SIZE_LE_1
:
7132 func (stream
, "size <= 1");
7135 case UNDEF_SIZE_NOT_0
:
7136 func (stream
, "size not equal to 0");
7139 case UNDEF_SIZE_NOT_2
:
7140 func (stream
, "size not equal to 2");
7143 case UNDEF_SIZE_NOT_3
:
7144 func (stream
, "size not equal to 3");
7147 case UNDEF_NOT_UNS_SIZE_0
:
7148 func (stream
, "not unsigned and size = zero");
7151 case UNDEF_NOT_UNS_SIZE_1
:
7152 func (stream
, "not unsigned and size = one");
7155 case UNDEF_NOT_UNSIGNED
:
7156 func (stream
, "not unsigned");
7159 case UNDEF_VCVT_IMM6
:
7160 func (stream
, "invalid imm6");
7163 case UNDEF_VCVT_FSI_IMM6
:
7164 func (stream
, "fsi = 0 and invalid imm6");
7167 case UNDEF_BAD_OP1_OP2
:
7168 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
7171 case UNDEF_BAD_U_OP1_OP2
:
7172 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
7175 case UNDEF_OP_0_BAD_CMODE
:
7176 func (stream
, "op field equal 0 and bad cmode");
7179 case UNDEF_XCHG_UNS
:
7180 func (stream
, "exchange and unsigned together");
7190 print_mve_unpredictable (struct disassemble_info
*info
,
7191 enum mve_unpredictable unpredict_code
)
7193 void *stream
= info
->stream
;
7194 fprintf_ftype func
= info
->fprintf_func
;
7196 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
7198 switch (unpredict_code
)
7200 case UNPRED_IT_BLOCK
:
7201 func (stream
, "mve instruction in it block");
7204 case UNPRED_FCA_0_FCB_1
:
7205 func (stream
, "condition bits, fca = 0 and fcb = 1");
7209 func (stream
, "use of r13 (sp)");
7213 func (stream
, "use of r15 (pc)");
7217 func (stream
, "start register block > r4");
7221 func (stream
, "start register block > r6");
7224 case UNPRED_R13_AND_WB
:
7225 func (stream
, "use of r13 and write back");
7228 case UNPRED_Q_REGS_EQUAL
:
7230 "same vector register used for destination and other operand");
7234 func (stream
, "use of offset scaled");
7237 case UNPRED_GP_REGS_EQUAL
:
7238 func (stream
, "same general-purpose register used for both operands");
7241 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
7242 func (stream
, "use of identical q registers and size = 1");
7245 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
7246 func (stream
, "use of identical q registers and size = 1");
7254 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7257 print_mve_register_blocks (struct disassemble_info
*info
,
7258 unsigned long given
,
7259 enum mve_instructions matched_insn
)
7261 void *stream
= info
->stream
;
7262 fprintf_ftype func
= info
->fprintf_func
;
7264 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
7267 switch (matched_insn
)
7271 if (q_reg_start
<= 6)
7272 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
7274 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7279 if (q_reg_start
<= 4)
7280 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
7281 q_reg_start
+ 1, q_reg_start
+ 2,
7284 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7293 print_mve_rounding_mode (struct disassemble_info
*info
,
7294 unsigned long given
,
7295 enum mve_instructions matched_insn
)
7297 void *stream
= info
->stream
;
7298 fprintf_ftype func
= info
->fprintf_func
;
7300 switch (matched_insn
)
7302 case MVE_VCVT_FROM_FP_TO_INT
:
7304 switch (arm_decode_field (given
, 8, 9))
7330 switch (arm_decode_field (given
, 7, 9))
7369 print_mve_vcvt_size (struct disassemble_info
*info
,
7370 unsigned long given
,
7371 enum mve_instructions matched_insn
)
7373 unsigned long mode
= 0;
7374 void *stream
= info
->stream
;
7375 fprintf_ftype func
= info
->fprintf_func
;
7377 switch (matched_insn
)
7379 case MVE_VCVT_FP_FIX_VEC
:
7381 mode
= (((given
& 0x200) >> 7)
7382 | ((given
& 0x10000000) >> 27)
7383 | ((given
& 0x100) >> 8));
7388 func (stream
, "f16.s16");
7392 func (stream
, "s16.f16");
7396 func (stream
, "f16.u16");
7400 func (stream
, "u16.f16");
7404 func (stream
, "f32.s32");
7408 func (stream
, "s32.f32");
7412 func (stream
, "f32.u32");
7416 func (stream
, "u32.f32");
7424 case MVE_VCVT_BETWEEN_FP_INT
:
7426 unsigned long size
= arm_decode_field (given
, 18, 19);
7427 unsigned long op
= arm_decode_field (given
, 7, 8);
7434 func (stream
, "f16.s16");
7438 func (stream
, "f16.u16");
7442 func (stream
, "s16.f16");
7446 func (stream
, "u16.f16");
7458 func (stream
, "f32.s32");
7462 func (stream
, "f32.u32");
7466 func (stream
, "s32.f32");
7470 func (stream
, "u32.f32");
7477 case MVE_VCVT_FP_HALF_FP
:
7479 unsigned long op
= arm_decode_field (given
, 28, 28);
7481 func (stream
, "f16.f32");
7483 func (stream
, "f32.f16");
7487 case MVE_VCVT_FROM_FP_TO_INT
:
7489 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
7494 func (stream
, "s16.f16");
7498 func (stream
, "u16.f16");
7502 func (stream
, "s32.f32");
7506 func (stream
, "u32.f32");
7521 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
7522 unsigned long rot_width
)
7524 void *stream
= info
->stream
;
7525 fprintf_ftype func
= info
->fprintf_func
;
7532 func (stream
, "90");
7535 func (stream
, "270");
7541 else if (rot_width
== 2)
7549 func (stream
, "90");
7552 func (stream
, "180");
7555 func (stream
, "270");
7564 print_instruction_predicate (struct disassemble_info
*info
)
7566 void *stream
= info
->stream
;
7567 fprintf_ftype func
= info
->fprintf_func
;
7569 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
7571 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
7576 print_mve_size (struct disassemble_info
*info
,
7578 enum mve_instructions matched_insn
)
7580 void *stream
= info
->stream
;
7581 fprintf_ftype func
= info
->fprintf_func
;
7583 switch (matched_insn
)
7589 case MVE_VADD_VEC_T1
:
7590 case MVE_VADD_VEC_T2
:
7596 case MVE_VCMP_VEC_T1
:
7597 case MVE_VCMP_VEC_T2
:
7598 case MVE_VCMP_VEC_T3
:
7599 case MVE_VCMP_VEC_T4
:
7600 case MVE_VCMP_VEC_T5
:
7601 case MVE_VCMP_VEC_T6
:
7614 case MVE_VLDRB_GATHER_T1
:
7615 case MVE_VLDRH_GATHER_T2
:
7616 case MVE_VLDRW_GATHER_T3
:
7617 case MVE_VLDRD_GATHER_T4
:
7630 case MVE_VMUL_VEC_T1
:
7631 case MVE_VMUL_VEC_T2
:
7637 case MVE_VPT_VEC_T1
:
7638 case MVE_VPT_VEC_T2
:
7639 case MVE_VPT_VEC_T3
:
7640 case MVE_VPT_VEC_T4
:
7641 case MVE_VPT_VEC_T5
:
7642 case MVE_VPT_VEC_T6
:
7654 case MVE_VQDMULH_T1
:
7655 case MVE_VQRDMULH_T2
:
7656 case MVE_VQDMULH_T3
:
7657 case MVE_VQRDMULH_T4
:
7676 case MVE_VSTRB_SCATTER_T1
:
7677 case MVE_VSTRH_SCATTER_T2
:
7678 case MVE_VSTRW_SCATTER_T3
:
7681 case MVE_VSUB_VEC_T1
:
7682 case MVE_VSUB_VEC_T2
:
7684 func (stream
, "%s", mve_vec_sizename
[size
]);
7686 func (stream
, "<undef size>");
7690 case MVE_VADD_FP_T1
:
7691 case MVE_VADD_FP_T2
:
7692 case MVE_VSUB_FP_T1
:
7693 case MVE_VSUB_FP_T2
:
7694 case MVE_VCMP_FP_T1
:
7695 case MVE_VCMP_FP_T2
:
7696 case MVE_VFMA_FP_SCALAR
:
7699 case MVE_VFMAS_FP_SCALAR
:
7701 case MVE_VMAXNMA_FP
:
7702 case MVE_VMAXNMV_FP
:
7703 case MVE_VMAXNMAV_FP
:
7705 case MVE_VMINNMA_FP
:
7706 case MVE_VMINNMV_FP
:
7707 case MVE_VMINNMAV_FP
:
7708 case MVE_VMUL_FP_T1
:
7709 case MVE_VMUL_FP_T2
:
7713 func (stream
, "32");
7715 func (stream
, "16");
7721 case MVE_VMLADAV_T1
:
7723 case MVE_VMLSDAV_T1
:
7726 case MVE_VQDMULL_T1
:
7727 case MVE_VQDMULL_T2
:
7731 func (stream
, "16");
7733 func (stream
, "32");
7740 func (stream
, "16");
7747 func (stream
, "32");
7750 func (stream
, "16");
7760 case MVE_VMOV_GP_TO_VEC_LANE
:
7761 case MVE_VMOV_VEC_LANE_TO_GP
:
7765 func (stream
, "32");
7770 func (stream
, "16");
7773 case 8: case 9: case 10: case 11:
7774 case 12: case 13: case 14: case 15:
7783 case MVE_VMOV_IMM_TO_VEC
:
7786 case 0: case 4: case 8:
7787 case 12: case 24: case 26:
7788 func (stream
, "i32");
7791 func (stream
, "i16");
7794 func (stream
, "i8");
7797 func (stream
, "i64");
7800 func (stream
, "f32");
7807 case MVE_VMULL_POLY
:
7809 func (stream
, "p8");
7811 func (stream
, "p16");
7817 case 0: case 2: case 4:
7818 case 6: case 12: case 13:
7819 func (stream
, "32");
7823 func (stream
, "16");
7837 func (stream
, "32");
7841 func (stream
, "16");
7859 func (stream
, "16");
7863 func (stream
, "32");
7888 func (stream
, "16");
7891 case 4: case 5: case 6: case 7:
7892 func (stream
, "32");
7907 print_mve_shift_n (struct disassemble_info
*info
, long given
,
7908 enum mve_instructions matched_insn
)
7910 void *stream
= info
->stream
;
7911 fprintf_ftype func
= info
->fprintf_func
;
7914 = matched_insn
== MVE_VQSHL_T2
7915 || matched_insn
== MVE_VQSHLU_T3
7916 || matched_insn
== MVE_VSHL_T1
7917 || matched_insn
== MVE_VSHLL_T1
7918 || matched_insn
== MVE_VSLI
;
7920 unsigned imm6
= (given
& 0x3f0000) >> 16;
7922 if (matched_insn
== MVE_VSHLL_T1
)
7925 unsigned shiftAmount
= 0;
7926 if ((imm6
& 0x20) != 0)
7927 shiftAmount
= startAt0
? imm6
- 32 : 64 - imm6
;
7928 else if ((imm6
& 0x10) != 0)
7929 shiftAmount
= startAt0
? imm6
- 16 : 32 - imm6
;
7930 else if ((imm6
& 0x08) != 0)
7931 shiftAmount
= startAt0
? imm6
- 8 : 16 - imm6
;
7933 print_mve_undefined (info
, UNDEF_SIZE_0
);
7935 func (stream
, "%u", shiftAmount
);
7939 print_vec_condition (struct disassemble_info
*info
, long given
,
7940 enum mve_instructions matched_insn
)
7942 void *stream
= info
->stream
;
7943 fprintf_ftype func
= info
->fprintf_func
;
7946 switch (matched_insn
)
7949 case MVE_VCMP_FP_T1
:
7950 vec_cond
= (((given
& 0x1000) >> 10)
7951 | ((given
& 1) << 1)
7952 | ((given
& 0x0080) >> 7));
7953 func (stream
, "%s",vec_condnames
[vec_cond
]);
7957 case MVE_VCMP_FP_T2
:
7958 vec_cond
= (((given
& 0x1000) >> 10)
7959 | ((given
& 0x0020) >> 4)
7960 | ((given
& 0x0080) >> 7));
7961 func (stream
, "%s",vec_condnames
[vec_cond
]);
7964 case MVE_VPT_VEC_T1
:
7965 case MVE_VCMP_VEC_T1
:
7966 vec_cond
= (given
& 0x0080) >> 7;
7967 func (stream
, "%s",vec_condnames
[vec_cond
]);
7970 case MVE_VPT_VEC_T2
:
7971 case MVE_VCMP_VEC_T2
:
7972 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7973 func (stream
, "%s",vec_condnames
[vec_cond
]);
7976 case MVE_VPT_VEC_T3
:
7977 case MVE_VCMP_VEC_T3
:
7978 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
7979 func (stream
, "%s",vec_condnames
[vec_cond
]);
7982 case MVE_VPT_VEC_T4
:
7983 case MVE_VCMP_VEC_T4
:
7984 vec_cond
= (given
& 0x0080) >> 7;
7985 func (stream
, "%s",vec_condnames
[vec_cond
]);
7988 case MVE_VPT_VEC_T5
:
7989 case MVE_VCMP_VEC_T5
:
7990 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7991 func (stream
, "%s",vec_condnames
[vec_cond
]);
7994 case MVE_VPT_VEC_T6
:
7995 case MVE_VCMP_VEC_T6
:
7996 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
7997 func (stream
, "%s",vec_condnames
[vec_cond
]);
8012 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8013 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8014 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
8015 #define PRE_BIT_SET (given & (1 << P_BIT))
8018 /* Print one coprocessor instruction on INFO->STREAM.
8019 Return TRUE if the instuction matched, FALSE if this is not a
8020 recognised coprocessor instruction. */
8023 print_insn_coprocessor_1 (const struct sopcode32
*opcodes
,
8025 struct disassemble_info
*info
,
8029 const struct sopcode32
*insn
;
8030 void *stream
= info
->stream
;
8031 fprintf_ftype func
= info
->fprintf_func
;
8033 unsigned long value
= 0;
8036 struct arm_private_data
*private_data
= info
->private_data
;
8037 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
8038 arm_feature_set arm_ext_v8_1m_main
=
8039 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
8041 allowed_arches
= private_data
->features
;
8043 for (insn
= opcodes
; insn
->assembler
; insn
++)
8045 unsigned long u_reg
= 16;
8046 bool is_unpredictable
= false;
8047 signed long value_in_comment
= 0;
8050 if (ARM_FEATURE_ZERO (insn
->arch
))
8051 switch (insn
->value
)
8053 case SENTINEL_IWMMXT_START
:
8054 if (info
->mach
!= bfd_mach_arm_XScale
8055 && info
->mach
!= bfd_mach_arm_iWMMXt
8056 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
8059 while ((! ARM_FEATURE_ZERO (insn
->arch
))
8060 && insn
->value
!= SENTINEL_IWMMXT_END
);
8063 case SENTINEL_IWMMXT_END
:
8066 case SENTINEL_GENERIC_START
:
8067 allowed_arches
= private_data
->features
;
8075 value
= insn
->value
;
8076 cp_num
= (given
>> 8) & 0xf;
8080 /* The high 4 bits are 0xe for Arm conditional instructions, and
8081 0xe for arm unconditional instructions. The rest of the
8082 encoding is the same. */
8084 value
|= 0xe0000000;
8092 /* Only match unconditional instuctions against unconditional
8094 if ((given
& 0xf0000000) == 0xf0000000)
8101 cond
= (given
>> 28) & 0xf;
8107 if ((insn
->isa
== T32
&& !thumb
)
8108 || (insn
->isa
== ARM
&& thumb
))
8111 if ((given
& mask
) != value
)
8114 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
8117 if (insn
->value
== 0xfe000010 /* mcr2 */
8118 || insn
->value
== 0xfe100010 /* mrc2 */
8119 || insn
->value
== 0xfc100000 /* ldc2 */
8120 || insn
->value
== 0xfc000000) /* stc2 */
8122 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8123 is_unpredictable
= true;
8125 /* Armv8.1-M Mainline FP & MVE instructions. */
8126 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8127 && !ARM_CPU_IS_ANY (allowed_arches
)
8128 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8132 else if (insn
->value
== 0x0e000000 /* cdp */
8133 || insn
->value
== 0xfe000000 /* cdp2 */
8134 || insn
->value
== 0x0e000010 /* mcr */
8135 || insn
->value
== 0x0e100010 /* mrc */
8136 || insn
->value
== 0x0c100000 /* ldc */
8137 || insn
->value
== 0x0c000000) /* stc */
8139 /* Floating-point instructions. */
8140 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8143 /* Armv8.1-M Mainline FP & MVE instructions. */
8144 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8145 && !ARM_CPU_IS_ANY (allowed_arches
)
8146 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8149 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
8150 || insn
->value
== 0xec000f80) /* vstr (system register) */
8151 && arm_decode_field (given
, 24, 24) == 0
8152 && arm_decode_field (given
, 21, 21) == 0)
8153 /* If the P and W bits are both 0 then these encodings match the MVE
8154 VLDR and VSTR instructions, these are in a different table, so we
8155 don't let it match here. */
8158 for (c
= insn
->assembler
; *c
; c
++)
8162 const char mod
= *++c
;
8166 func (stream
, "%%");
8172 int rn
= (given
>> 16) & 0xf;
8173 bfd_vma offset
= given
& 0xff;
8176 offset
= given
& 0x7f;
8178 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8180 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
8182 /* Not unindexed. The offset is scaled. */
8184 /* vldr.16/vstr.16 will shift the address
8185 left by 1 bit only. */
8186 offset
= offset
* 2;
8188 offset
= offset
* 4;
8190 if (NEGATIVE_BIT_SET
)
8193 value_in_comment
= offset
;
8199 func (stream
, ", #%d]%s",
8201 WRITEBACK_BIT_SET
? "!" : "");
8202 else if (NEGATIVE_BIT_SET
)
8203 func (stream
, ", #-0]");
8211 if (WRITEBACK_BIT_SET
)
8214 func (stream
, ", #%d", (int) offset
);
8215 else if (NEGATIVE_BIT_SET
)
8216 func (stream
, ", #-0");
8220 func (stream
, ", {%s%d}",
8221 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
8223 value_in_comment
= offset
;
8226 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
8228 func (stream
, "\t; ");
8229 /* For unaligned PCs, apply off-by-alignment
8231 info
->print_address_func (offset
+ pc
8232 + info
->bytes_per_chunk
* 2
8241 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
8242 int offset
= (given
>> 1) & 0x3f;
8245 func (stream
, "{d%d}", regno
);
8246 else if (regno
+ offset
> 32)
8247 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
8249 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
8255 bool single
= ((given
>> 8) & 1) == 0;
8256 char reg_prefix
= single
? 's' : 'd';
8257 int Dreg
= (given
>> 22) & 0x1;
8258 int Vdreg
= (given
>> 12) & 0xf;
8259 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
8260 : ((Dreg
<< 4) | Vdreg
);
8261 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
8262 int maxreg
= single
? 31 : 15;
8263 int topreg
= reg
+ num
- 1;
8266 func (stream
, "{VPR}");
8268 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
8269 else if (topreg
> maxreg
)
8270 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
8271 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
8273 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
8274 reg_prefix
, topreg
);
8279 if (cond
!= COND_UNCOND
)
8280 is_unpredictable
= true;
8284 if (cond
!= COND_UNCOND
&& cp_num
== 9)
8285 is_unpredictable
= true;
8289 func (stream
, "%s", arm_conditional
[cond
]);
8293 /* Print a Cirrus/DSP shift immediate. */
8294 /* Immediates are 7bit signed ints with bits 0..3 in
8295 bits 0..3 of opcode and bits 4..6 in bits 5..7
8300 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
8302 /* Is ``imm'' a negative number? */
8306 func (stream
, "%d", imm
);
8314 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
8319 func (stream
, "FPSCR");
8322 func (stream
, "FPSCR_nzcvqc");
8325 func (stream
, "VPR");
8328 func (stream
, "P0");
8331 func (stream
, "FPCXTNS");
8334 func (stream
, "FPCXTS");
8337 func (stream
, "<invalid reg %lu>", regno
);
8344 switch (given
& 0x00408000)
8361 switch (given
& 0x00080080)
8373 func (stream
, _("<illegal precision>"));
8379 switch (given
& 0x00408000)
8397 switch (given
& 0x60)
8413 case '0': case '1': case '2': case '3': case '4':
8414 case '5': case '6': case '7': case '8': case '9':
8418 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8424 is_unpredictable
= true;
8429 /* Eat the 'u' character. */
8433 is_unpredictable
= true;
8436 func (stream
, "%s", arm_regnames
[value
]);
8439 if (given
& (1 << 6))
8443 func (stream
, "d%ld", value
);
8448 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
8450 func (stream
, "q%ld", value
>> 1);
8453 func (stream
, "%ld", value
);
8454 value_in_comment
= value
;
8458 /* Converts immediate 8 bit back to float value. */
8459 unsigned floatVal
= (value
& 0x80) << 24
8460 | (value
& 0x3F) << 19
8461 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
8463 /* Quarter float have a maximum value of 31.0.
8464 Get floating point value multiplied by 1e7.
8465 The maximum value stays in limit of a 32-bit int. */
8467 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
8468 (16 + (value
& 0xF));
8470 if (!(decVal
% 1000000))
8471 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
8472 floatVal
, value
& 0x80 ? '-' : ' ',
8474 decVal
% 10000000 / 1000000);
8475 else if (!(decVal
% 10000))
8476 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
8477 floatVal
, value
& 0x80 ? '-' : ' ',
8479 decVal
% 10000000 / 10000);
8481 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
8482 floatVal
, value
& 0x80 ? '-' : ' ',
8483 decVal
/ 10000000, decVal
% 10000000);
8488 int from
= (given
& (1 << 7)) ? 32 : 16;
8489 func (stream
, "%ld", from
- value
);
8495 func (stream
, "#%s", arm_fp_const
[value
& 7]);
8497 func (stream
, "f%ld", value
);
8502 func (stream
, "%s", iwmmxt_wwnames
[value
]);
8504 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
8508 func (stream
, "%s", iwmmxt_regnames
[value
]);
8511 func (stream
, "%s", iwmmxt_cregnames
[value
]);
8515 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
8522 func (stream
, "eq");
8526 func (stream
, "vs");
8530 func (stream
, "ge");
8534 func (stream
, "gt");
8538 func (stream
, "??");
8546 func (stream
, "%c", *c
);
8550 if (value
== ((1ul << width
) - 1))
8551 func (stream
, "%c", *c
);
8554 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8566 int single
= *c
++ == 'y';
8571 case '4': /* Sm pair */
8572 case '0': /* Sm, Dm */
8573 regno
= given
& 0x0000000f;
8577 regno
+= (given
>> 5) & 1;
8580 regno
+= ((given
>> 5) & 1) << 4;
8583 case '1': /* Sd, Dd */
8584 regno
= (given
>> 12) & 0x0000000f;
8588 regno
+= (given
>> 22) & 1;
8591 regno
+= ((given
>> 22) & 1) << 4;
8594 case '2': /* Sn, Dn */
8595 regno
= (given
>> 16) & 0x0000000f;
8599 regno
+= (given
>> 7) & 1;
8602 regno
+= ((given
>> 7) & 1) << 4;
8605 case '3': /* List */
8607 regno
= (given
>> 12) & 0x0000000f;
8611 regno
+= (given
>> 22) & 1;
8614 regno
+= ((given
>> 22) & 1) << 4;
8621 func (stream
, "%c%d", single
? 's' : 'd', regno
);
8625 int count
= given
& 0xff;
8632 func (stream
, "-%c%d",
8640 func (stream
, ", %c%d", single
? 's' : 'd',
8646 switch (given
& 0x00400100)
8648 case 0x00000000: func (stream
, "b"); break;
8649 case 0x00400000: func (stream
, "h"); break;
8650 case 0x00000100: func (stream
, "w"); break;
8651 case 0x00400100: func (stream
, "d"); break;
8659 /* given (20, 23) | given (0, 3) */
8660 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
8661 func (stream
, "%d", (int) value
);
8666 /* This is like the 'A' operator, except that if
8667 the width field "M" is zero, then the offset is
8668 *not* multiplied by four. */
8670 int offset
= given
& 0xff;
8671 int multiplier
= (given
& 0x00000100) ? 4 : 1;
8673 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8677 value_in_comment
= offset
* multiplier
;
8678 if (NEGATIVE_BIT_SET
)
8679 value_in_comment
= - value_in_comment
;
8685 func (stream
, ", #%s%d]%s",
8686 NEGATIVE_BIT_SET
? "-" : "",
8687 offset
* multiplier
,
8688 WRITEBACK_BIT_SET
? "!" : "");
8690 func (stream
, "], #%s%d",
8691 NEGATIVE_BIT_SET
? "-" : "",
8692 offset
* multiplier
);
8701 int imm4
= (given
>> 4) & 0xf;
8702 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
8703 int ubit
= ! NEGATIVE_BIT_SET
;
8704 const char *rm
= arm_regnames
[given
& 0xf];
8705 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
8711 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
8713 func (stream
, ", lsl #%d", imm4
);
8720 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
8722 func (stream
, ", lsl #%d", imm4
);
8724 if (puw_bits
== 5 || puw_bits
== 7)
8729 func (stream
, "INVALID");
8737 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
8738 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
8747 func (stream
, "%c", *c
);
8750 if (value_in_comment
> 32 || value_in_comment
< -16)
8751 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8753 if (is_unpredictable
)
8754 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8762 print_insn_coprocessor (bfd_vma pc
,
8763 struct disassemble_info
*info
,
8767 return print_insn_coprocessor_1 (coprocessor_opcodes
,
8768 pc
, info
, given
, thumb
);
8772 print_insn_generic_coprocessor (bfd_vma pc
,
8773 struct disassemble_info
*info
,
8777 return print_insn_coprocessor_1 (generic_coprocessor_opcodes
,
8778 pc
, info
, given
, thumb
);
8781 /* Decodes and prints ARM addressing modes. Returns the offset
8782 used in the address, if any, if it is worthwhile printing the
8783 offset as a hexadecimal value in a comment at the end of the
8784 line of disassembly. */
8787 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8789 void *stream
= info
->stream
;
8790 fprintf_ftype func
= info
->fprintf_func
;
8793 if (((given
& 0x000f0000) == 0x000f0000)
8794 && ((given
& 0x02000000) == 0))
8796 offset
= given
& 0xfff;
8798 func (stream
, "[pc");
8802 /* Pre-indexed. Elide offset of positive zero when
8804 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8805 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8807 if (NEGATIVE_BIT_SET
)
8812 /* Cope with the possibility of write-back
8813 being used. Probably a very dangerous thing
8814 for the programmer to do, but who are we to
8816 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
8818 else /* Post indexed. */
8820 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8822 /* Ie ignore the offset. */
8826 func (stream
, "\t; ");
8827 info
->print_address_func (offset
, info
);
8832 func (stream
, "[%s",
8833 arm_regnames
[(given
>> 16) & 0xf]);
8837 if ((given
& 0x02000000) == 0)
8839 /* Elide offset of positive zero when non-writeback. */
8840 offset
= given
& 0xfff;
8841 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8842 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8846 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
8847 arm_decode_shift (given
, func
, stream
, true);
8850 func (stream
, "]%s",
8851 WRITEBACK_BIT_SET
? "!" : "");
8855 if ((given
& 0x02000000) == 0)
8857 /* Always show offset. */
8858 offset
= given
& 0xfff;
8859 func (stream
, "], #%s%d",
8860 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8864 func (stream
, "], %s",
8865 NEGATIVE_BIT_SET
? "-" : "");
8866 arm_decode_shift (given
, func
, stream
, true);
8869 if (NEGATIVE_BIT_SET
)
8873 return (signed long) offset
;
8877 /* Print one cde instruction on INFO->STREAM.
8878 Return TRUE if the instuction matched, FALSE if this is not a
8879 recognised cde instruction. */
8881 print_insn_cde (struct disassemble_info
*info
, long given
, bool thumb
)
8883 const struct cdeopcode32
*insn
;
8884 void *stream
= info
->stream
;
8885 fprintf_ftype func
= info
->fprintf_func
;
8889 /* Manually extract the coprocessor code from a known point.
8890 This position is the same across all CDE instructions. */
8891 for (insn
= cde_opcodes
; insn
->assembler
; insn
++)
8893 uint16_t coproc
= (given
>> insn
->coproc_shift
) & insn
->coproc_mask
;
8894 uint16_t coproc_mask
= 1 << coproc
;
8895 if (! (coproc_mask
& cde_coprocs
))
8898 if ((given
& insn
->mask
) == insn
->value
)
8900 bool is_unpredictable
= false;
8903 for (c
= insn
->assembler
; *c
; c
++)
8910 func (stream
, "%%");
8913 case '0': case '1': case '2': case '3': case '4':
8914 case '5': case '6': case '7': case '8': case '9':
8917 unsigned long value
;
8919 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8925 is_unpredictable
= true;
8929 is_unpredictable
= true;
8932 func (stream
, "%s", arm_regnames
[value
]);
8937 func (stream
, "%s", "APSR_nzcv");
8939 func (stream
, "%s", arm_regnames
[value
]);
8943 func (stream
, "%s", arm_regnames
[value
+ 1]);
8947 func (stream
, "%ld", value
);
8951 if (given
& (1 << 6))
8952 func (stream
, "q%ld", value
>> 1);
8953 else if (given
& (1 << 24))
8954 func (stream
, "d%ld", value
);
8957 /* Encoding for S register is different than for D and
8958 Q registers. S registers are encoded using the top
8959 single bit in position 22 as the lowest bit of the
8960 register number, while for Q and D it represents the
8961 highest bit of the register number. */
8962 uint8_t top_bit
= (value
>> 4) & 1;
8963 uint8_t tmp
= (value
<< 1) & 0x1e;
8964 uint8_t res
= tmp
| top_bit
;
8965 func (stream
, "s%u", res
);
8977 uint8_t proc_number
= (given
>> 8) & 0x7;
8978 func (stream
, "p%u", proc_number
);
8984 uint8_t a_offset
= 28;
8985 if (given
& (1 << a_offset
))
8994 func (stream
, "%c", *c
);
8997 if (is_unpredictable
)
8998 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9010 /* Print one neon instruction on INFO->STREAM.
9011 Return TRUE if the instuction matched, FALSE if this is not a
9012 recognised neon instruction. */
9015 print_insn_neon (struct disassemble_info
*info
, long given
, bool thumb
)
9017 const struct opcode32
*insn
;
9018 void *stream
= info
->stream
;
9019 fprintf_ftype func
= info
->fprintf_func
;
9023 if ((given
& 0xef000000) == 0xef000000)
9025 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
9026 unsigned long bit28
= given
& (1 << 28);
9028 given
&= 0x00ffffff;
9030 given
|= 0xf3000000;
9032 given
|= 0xf2000000;
9034 else if ((given
& 0xff000000) == 0xf9000000)
9035 given
^= 0xf9000000 ^ 0xf4000000;
9036 /* BFloat16 neon instructions without special top byte handling. */
9037 else if ((given
& 0xff000000) == 0xfe000000
9038 || (given
& 0xff000000) == 0xfc000000)
9040 /* vdup is also a valid neon instruction. */
9041 else if ((given
& 0xff900f5f) != 0xee800b10)
9045 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
9047 unsigned long cond_mask
= insn
->mask
;
9048 unsigned long cond_value
= insn
->value
;
9053 if ((cond_mask
& 0xf0000000) == 0) {
9054 /* For the entries in neon_opcodes, an opcode mask/value with
9055 the high 4 bits equal to 0 indicates a conditional
9056 instruction. For thumb however, we need to include those
9057 bits in the instruction matching. */
9058 cond_mask
|= 0xf0000000;
9059 /* Furthermore, the thumb encoding of a conditional instruction
9060 will have the high 4 bits equal to 0xe. */
9061 cond_value
|= 0xe0000000;
9070 if ((given
& 0xf0000000) == 0xf0000000)
9072 /* If the instruction is unconditional, update the mask to only
9073 match against unconditional opcode values. */
9074 cond_mask
|= 0xf0000000;
9079 cond
= (given
>> 28) & 0xf;
9085 if ((given
& cond_mask
) == cond_value
)
9087 signed long value_in_comment
= 0;
9088 bool is_unpredictable
= false;
9091 for (c
= insn
->assembler
; *c
; c
++)
9098 func (stream
, "%%");
9102 if (thumb
&& ifthen_state
)
9103 is_unpredictable
= true;
9107 func (stream
, "%s", arm_conditional
[cond
]);
9112 static const unsigned char enc
[16] =
9114 0x4, 0x14, /* st4 0,1 */
9126 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9127 int rn
= ((given
>> 16) & 0xf);
9128 int rm
= ((given
>> 0) & 0xf);
9129 int align
= ((given
>> 4) & 0x3);
9130 int type
= ((given
>> 8) & 0xf);
9131 int n
= enc
[type
] & 0xf;
9132 int stride
= (enc
[type
] >> 4) + 1;
9137 for (ix
= 0; ix
!= n
; ix
++)
9138 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
9140 func (stream
, "d%d", rd
);
9142 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
9143 func (stream
, "}, [%s", arm_regnames
[rn
]);
9145 func (stream
, " :%d", 32 << align
);
9150 func (stream
, ", %s", arm_regnames
[rm
]);
9156 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9157 int rn
= ((given
>> 16) & 0xf);
9158 int rm
= ((given
>> 0) & 0xf);
9159 int idx_align
= ((given
>> 4) & 0xf);
9161 int size
= ((given
>> 10) & 0x3);
9162 int idx
= idx_align
>> (size
+ 1);
9163 int length
= ((given
>> 8) & 3) + 1;
9167 if (length
> 1 && size
> 0)
9168 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
9174 int amask
= (1 << size
) - 1;
9175 if ((idx_align
& (1 << size
)) != 0)
9179 if ((idx_align
& amask
) == amask
)
9181 else if ((idx_align
& amask
) != 0)
9188 if (size
== 2 && (idx_align
& 2) != 0)
9190 align
= (idx_align
& 1) ? 16 << size
: 0;
9194 if ((size
== 2 && (idx_align
& 3) != 0)
9195 || (idx_align
& 1) != 0)
9202 if ((idx_align
& 3) == 3)
9204 align
= (idx_align
& 3) * 64;
9207 align
= (idx_align
& 1) ? 32 << size
: 0;
9215 for (i
= 0; i
< length
; i
++)
9216 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
9217 rd
+ i
* stride
, idx
);
9218 func (stream
, "}, [%s", arm_regnames
[rn
]);
9220 func (stream
, " :%d", align
);
9225 func (stream
, ", %s", arm_regnames
[rm
]);
9231 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9232 int rn
= ((given
>> 16) & 0xf);
9233 int rm
= ((given
>> 0) & 0xf);
9234 int align
= ((given
>> 4) & 0x1);
9235 int size
= ((given
>> 6) & 0x3);
9236 int type
= ((given
>> 8) & 0x3);
9238 int stride
= ((given
>> 5) & 0x1);
9241 if (stride
&& (n
== 1))
9248 for (ix
= 0; ix
!= n
; ix
++)
9249 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
9251 func (stream
, "d%d[]", rd
);
9253 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
9254 func (stream
, "}, [%s", arm_regnames
[rn
]);
9257 align
= (8 * (type
+ 1)) << size
;
9259 align
= (size
> 1) ? align
>> 1 : align
;
9260 if (type
== 2 || (type
== 0 && !size
))
9261 func (stream
, " :<bad align %d>", align
);
9263 func (stream
, " :%d", align
);
9269 func (stream
, ", %s", arm_regnames
[rm
]);
9275 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
9276 int size
= (given
>> 20) & 3;
9277 int reg
= raw_reg
& ((4 << size
) - 1);
9278 int ix
= raw_reg
>> size
>> 2;
9280 func (stream
, "d%d[%d]", reg
, ix
);
9285 /* Neon encoded constant for mov, mvn, vorr, vbic. */
9288 int cmode
= (given
>> 8) & 0xf;
9289 int op
= (given
>> 5) & 0x1;
9290 unsigned long value
= 0, hival
= 0;
9295 bits
|= ((given
>> 24) & 1) << 7;
9296 bits
|= ((given
>> 16) & 7) << 4;
9297 bits
|= ((given
>> 0) & 15) << 0;
9301 shift
= (cmode
>> 1) & 3;
9302 value
= (unsigned long) bits
<< (8 * shift
);
9305 else if (cmode
< 12)
9307 shift
= (cmode
>> 1) & 1;
9308 value
= (unsigned long) bits
<< (8 * shift
);
9311 else if (cmode
< 14)
9313 shift
= (cmode
& 1) + 1;
9314 value
= (unsigned long) bits
<< (8 * shift
);
9315 value
|= (1ul << (8 * shift
)) - 1;
9318 else if (cmode
== 14)
9322 /* Bit replication into bytes. */
9328 for (ix
= 7; ix
>= 0; ix
--)
9330 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
9332 value
= (value
<< 8) | mask
;
9334 hival
= (hival
<< 8) | mask
;
9340 /* Byte replication. */
9341 value
= (unsigned long) bits
;
9347 /* Floating point encoding. */
9350 value
= (unsigned long) (bits
& 0x7f) << 19;
9351 value
|= (unsigned long) (bits
& 0x80) << 24;
9352 tmp
= bits
& 0x40 ? 0x3c : 0x40;
9353 value
|= (unsigned long) tmp
<< 24;
9359 func (stream
, "<illegal constant %.8x:%x:%x>",
9367 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
9371 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
9377 unsigned char valbytes
[4];
9380 /* Do this a byte at a time so we don't have to
9381 worry about the host's endianness. */
9382 valbytes
[0] = value
& 0xff;
9383 valbytes
[1] = (value
>> 8) & 0xff;
9384 valbytes
[2] = (value
>> 16) & 0xff;
9385 valbytes
[3] = (value
>> 24) & 0xff;
9387 floatformat_to_double
9388 (& floatformat_ieee_single_little
, valbytes
,
9391 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
9395 func (stream
, "#%ld\t; 0x%.8lx",
9396 (long) (((value
& 0x80000000L
) != 0)
9397 ? value
| ~0xffffffffL
: value
),
9402 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
9413 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
9414 int num
= (given
>> 8) & 0x3;
9417 func (stream
, "{d%d}", regno
);
9418 else if (num
+ regno
>= 32)
9419 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
9421 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
9426 case '0': case '1': case '2': case '3': case '4':
9427 case '5': case '6': case '7': case '8': case '9':
9430 unsigned long value
;
9432 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9437 func (stream
, "%s", arm_regnames
[value
]);
9440 func (stream
, "%ld", value
);
9441 value_in_comment
= value
;
9444 func (stream
, "%ld", (1ul << width
) - value
);
9450 /* Various width encodings. */
9452 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
9457 if (*c
>= '0' && *c
<= '9')
9459 else if (*c
>= 'a' && *c
<= 'f')
9460 limit
= *c
- 'a' + 10;
9466 if (value
< low
|| value
> high
)
9467 func (stream
, "<illegal width %d>", base
<< value
);
9469 func (stream
, "%d", base
<< value
);
9473 if (given
& (1 << 6))
9477 func (stream
, "d%ld", value
);
9482 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
9484 func (stream
, "q%ld", value
>> 1);
9490 func (stream
, "%c", *c
);
9494 if (value
== ((1ul << width
) - 1))
9495 func (stream
, "%c", *c
);
9498 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
9512 func (stream
, "%c", *c
);
9515 if (value_in_comment
> 32 || value_in_comment
< -16)
9516 func (stream
, "\t; 0x%lx", value_in_comment
);
9518 if (is_unpredictable
)
9519 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9527 /* Print one mve instruction on INFO->STREAM.
9528 Return TRUE if the instuction matched, FALSE if this is not a
9529 recognised mve instruction. */
9532 print_insn_mve (struct disassemble_info
*info
, long given
)
9534 const struct mopcode32
*insn
;
9535 void *stream
= info
->stream
;
9536 fprintf_ftype func
= info
->fprintf_func
;
9538 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
9540 if (((given
& insn
->mask
) == insn
->value
)
9541 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
9543 signed long value_in_comment
= 0;
9544 bool is_unpredictable
= false;
9545 bool is_undefined
= false;
9547 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
9548 enum mve_undefined undefined_cond
= UNDEF_NONE
;
9550 /* Most vector mve instruction are illegal in a it block.
9551 There are a few exceptions; check for them. */
9552 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
9554 is_unpredictable
= true;
9555 unpredictable_cond
= UNPRED_IT_BLOCK
;
9557 else if (is_mve_unpredictable (given
, insn
->mve_op
,
9558 &unpredictable_cond
))
9559 is_unpredictable
= true;
9561 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
9562 is_undefined
= true;
9564 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9565 i.e "VMOV Qd, Qm". */
9566 if ((insn
->mve_op
== MVE_VORR_REG
)
9567 && (arm_decode_field (given
, 1, 3)
9568 == arm_decode_field (given
, 17, 19)))
9571 for (c
= insn
->assembler
; *c
; c
++)
9578 func (stream
, "%%");
9582 /* Don't print anything for '+' as it is implied. */
9583 if (arm_decode_field (given
, 23, 23) == 0)
9589 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9593 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
9598 long mve_mask
= mve_extract_pred_mask (given
);
9599 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
9605 unsigned int imm5
= 0;
9606 imm5
|= arm_decode_field (given
, 6, 7);
9607 imm5
|= (arm_decode_field (given
, 12, 14) << 2);
9608 func (stream
, "#%u", (imm5
== 0) ? 32 : imm5
);
9613 func (stream
, "#%u",
9614 (arm_decode_field (given
, 7, 7) == 0) ? 64 : 48);
9618 print_vec_condition (info
, given
, insn
->mve_op
);
9622 if (arm_decode_field (given
, 0, 0) == 1)
9625 = arm_decode_field (given
, 4, 4)
9626 | (arm_decode_field (given
, 6, 6) << 1);
9628 func (stream
, ", uxtw #%lu", size
);
9633 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
9637 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
9642 unsigned long op1
= arm_decode_field (given
, 21, 22);
9644 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
9646 /* Check for signed. */
9647 if (arm_decode_field (given
, 23, 23) == 0)
9649 /* We don't print 's' for S32. */
9650 if ((arm_decode_field (given
, 5, 6) == 0)
9651 && ((op1
== 0) || (op1
== 1)))
9661 if (arm_decode_field (given
, 28, 28) == 0)
9670 print_instruction_predicate (info
);
9674 if (arm_decode_field (given
, 21, 21) == 1)
9679 print_mve_register_blocks (info
, given
, insn
->mve_op
);
9683 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9685 print_simd_imm8 (info
, given
, 28, insn
);
9689 print_mve_vmov_index (info
, given
);
9693 if (arm_decode_field (given
, 12, 12) == 0)
9700 if (arm_decode_field (given
, 12, 12) == 1)
9704 case '0': case '1': case '2': case '3': case '4':
9705 case '5': case '6': case '7': case '8': case '9':
9708 unsigned long value
;
9710 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9716 is_unpredictable
= true;
9717 else if (value
== 15)
9718 func (stream
, "zr");
9720 func (stream
, "%s", arm_regnames
[value
]);
9724 func (stream
, "%s", arm_conditional
[value
]);
9729 func (stream
, "%s", arm_conditional
[value
]);
9733 if (value
== 13 || value
== 15)
9734 is_unpredictable
= true;
9736 func (stream
, "%s", arm_regnames
[value
]);
9740 print_mve_size (info
,
9754 unsigned int odd_reg
= (value
<< 1) | 1;
9755 func (stream
, "%s", arm_regnames
[odd_reg
]);
9761 = arm_decode_field (given
, 0, 6);
9762 unsigned long mod_imm
= imm
;
9764 switch (insn
->mve_op
)
9766 case MVE_VLDRW_GATHER_T5
:
9767 case MVE_VSTRW_SCATTER_T5
:
9768 mod_imm
= mod_imm
<< 2;
9770 case MVE_VSTRD_SCATTER_T6
:
9771 case MVE_VLDRD_GATHER_T6
:
9772 mod_imm
= mod_imm
<< 3;
9779 func (stream
, "%lu", mod_imm
);
9783 func (stream
, "%lu", 64 - value
);
9787 unsigned int even_reg
= value
<< 1;
9788 func (stream
, "%s", arm_regnames
[even_reg
]);
9811 print_mve_rotate (info
, value
, width
);
9814 func (stream
, "%s", arm_regnames
[value
]);
9817 if (insn
->mve_op
== MVE_VQSHL_T2
9818 || insn
->mve_op
== MVE_VQSHLU_T3
9819 || insn
->mve_op
== MVE_VRSHR
9820 || insn
->mve_op
== MVE_VRSHRN
9821 || insn
->mve_op
== MVE_VSHL_T1
9822 || insn
->mve_op
== MVE_VSHLL_T1
9823 || insn
->mve_op
== MVE_VSHR
9824 || insn
->mve_op
== MVE_VSHRN
9825 || insn
->mve_op
== MVE_VSLI
9826 || insn
->mve_op
== MVE_VSRI
)
9827 print_mve_shift_n (info
, given
, insn
->mve_op
);
9828 else if (insn
->mve_op
== MVE_VSHLL_T2
)
9836 func (stream
, "16");
9839 print_mve_undefined (info
, UNDEF_SIZE_0
);
9848 if (insn
->mve_op
== MVE_VSHLC
&& value
== 0)
9850 func (stream
, "%ld", value
);
9851 value_in_comment
= value
;
9855 func (stream
, "s%ld", value
);
9859 func (stream
, "<illegal reg q%ld.5>", value
);
9861 func (stream
, "q%ld", value
);
9864 func (stream
, "0x%08lx", value
);
9876 func (stream
, "%c", *c
);
9879 if (value_in_comment
> 32 || value_in_comment
< -16)
9880 func (stream
, "\t; 0x%lx", value_in_comment
);
9882 if (is_unpredictable
)
9883 print_mve_unpredictable (info
, unpredictable_cond
);
9886 print_mve_undefined (info
, undefined_cond
);
9888 if (!vpt_block_state
.in_vpt_block
9890 && is_vpt_instruction (given
))
9891 mark_inside_vpt_block (given
);
9892 else if (vpt_block_state
.in_vpt_block
)
9893 update_vpt_block_state ();
9902 /* Return the name of a v7A special register. */
9905 banked_regname (unsigned reg
)
9909 case 15: return "CPSR";
9910 case 32: return "R8_usr";
9911 case 33: return "R9_usr";
9912 case 34: return "R10_usr";
9913 case 35: return "R11_usr";
9914 case 36: return "R12_usr";
9915 case 37: return "SP_usr";
9916 case 38: return "LR_usr";
9917 case 40: return "R8_fiq";
9918 case 41: return "R9_fiq";
9919 case 42: return "R10_fiq";
9920 case 43: return "R11_fiq";
9921 case 44: return "R12_fiq";
9922 case 45: return "SP_fiq";
9923 case 46: return "LR_fiq";
9924 case 48: return "LR_irq";
9925 case 49: return "SP_irq";
9926 case 50: return "LR_svc";
9927 case 51: return "SP_svc";
9928 case 52: return "LR_abt";
9929 case 53: return "SP_abt";
9930 case 54: return "LR_und";
9931 case 55: return "SP_und";
9932 case 60: return "LR_mon";
9933 case 61: return "SP_mon";
9934 case 62: return "ELR_hyp";
9935 case 63: return "SP_hyp";
9936 case 79: return "SPSR";
9937 case 110: return "SPSR_fiq";
9938 case 112: return "SPSR_irq";
9939 case 114: return "SPSR_svc";
9940 case 116: return "SPSR_abt";
9941 case 118: return "SPSR_und";
9942 case 124: return "SPSR_mon";
9943 case 126: return "SPSR_hyp";
9944 default: return NULL
;
9948 /* Return the name of the DMB/DSB option. */
9950 data_barrier_option (unsigned option
)
9952 switch (option
& 0xf)
9954 case 0xf: return "sy";
9955 case 0xe: return "st";
9956 case 0xd: return "ld";
9957 case 0xb: return "ish";
9958 case 0xa: return "ishst";
9959 case 0x9: return "ishld";
9960 case 0x7: return "un";
9961 case 0x6: return "unst";
9962 case 0x5: return "nshld";
9963 case 0x3: return "osh";
9964 case 0x2: return "oshst";
9965 case 0x1: return "oshld";
9966 default: return NULL
;
9970 /* Print one ARM instruction from PC on INFO->STREAM. */
9973 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9975 const struct opcode32
*insn
;
9976 void *stream
= info
->stream
;
9977 fprintf_ftype func
= info
->fprintf_func
;
9978 struct arm_private_data
*private_data
= info
->private_data
;
9980 if (print_insn_coprocessor (pc
, info
, given
, false))
9983 if (print_insn_neon (info
, given
, false))
9986 if (print_insn_generic_coprocessor (pc
, info
, given
, false))
9989 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
9991 if ((given
& insn
->mask
) != insn
->value
)
9994 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
9997 /* Special case: an instruction with all bits set in the condition field
9998 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9999 or by the catchall at the end of the table. */
10000 if ((given
& 0xF0000000) != 0xF0000000
10001 || (insn
->mask
& 0xF0000000) == 0xF0000000
10002 || (insn
->mask
== 0 && insn
->value
== 0))
10004 unsigned long u_reg
= 16;
10005 unsigned long U_reg
= 16;
10006 bool is_unpredictable
= false;
10007 signed long value_in_comment
= 0;
10010 for (c
= insn
->assembler
; *c
; c
++)
10014 bool allow_unpredictable
= false;
10019 func (stream
, "%%");
10023 value_in_comment
= print_arm_address (pc
, info
, given
);
10027 /* Set P address bit and use normal address
10028 printing routine. */
10029 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
10033 allow_unpredictable
= true;
10034 /* Fall through. */
10036 if ((given
& 0x004f0000) == 0x004f0000)
10038 /* PC relative with immediate offset. */
10039 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
10043 /* Elide positive zero offset. */
10044 if (offset
|| NEGATIVE_BIT_SET
)
10045 func (stream
, "[pc, #%s%d]\t; ",
10046 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
10048 func (stream
, "[pc]\t; ");
10049 if (NEGATIVE_BIT_SET
)
10051 info
->print_address_func (offset
+ pc
+ 8, info
);
10055 /* Always show the offset. */
10056 func (stream
, "[pc], #%s%d",
10057 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
10058 if (! allow_unpredictable
)
10059 is_unpredictable
= true;
10064 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
10066 func (stream
, "[%s",
10067 arm_regnames
[(given
>> 16) & 0xf]);
10071 if (IMMEDIATE_BIT_SET
)
10073 /* Elide offset for non-writeback
10075 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
10077 func (stream
, ", #%s%d",
10078 NEGATIVE_BIT_SET
? "-" : "", offset
);
10080 if (NEGATIVE_BIT_SET
)
10083 value_in_comment
= offset
;
10087 /* Register Offset or Register Pre-Indexed. */
10088 func (stream
, ", %s%s",
10089 NEGATIVE_BIT_SET
? "-" : "",
10090 arm_regnames
[given
& 0xf]);
10092 /* Writing back to the register that is the source/
10093 destination of the load/store is unpredictable. */
10094 if (! allow_unpredictable
10095 && WRITEBACK_BIT_SET
10096 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
10097 is_unpredictable
= true;
10100 func (stream
, "]%s",
10101 WRITEBACK_BIT_SET
? "!" : "");
10105 if (IMMEDIATE_BIT_SET
)
10107 /* Immediate Post-indexed. */
10108 /* PR 10924: Offset must be printed, even if it is zero. */
10109 func (stream
, "], #%s%d",
10110 NEGATIVE_BIT_SET
? "-" : "", offset
);
10111 if (NEGATIVE_BIT_SET
)
10113 value_in_comment
= offset
;
10117 /* Register Post-indexed. */
10118 func (stream
, "], %s%s",
10119 NEGATIVE_BIT_SET
? "-" : "",
10120 arm_regnames
[given
& 0xf]);
10122 /* Writing back to the register that is the source/
10123 destination of the load/store is unpredictable. */
10124 if (! allow_unpredictable
10125 && (given
& 0xf) == ((given
>> 12) & 0xf))
10126 is_unpredictable
= true;
10129 if (! allow_unpredictable
)
10131 /* Writeback is automatically implied by post- addressing.
10132 Setting the W bit is unnecessary and ARM specify it as
10133 being unpredictable. */
10134 if (WRITEBACK_BIT_SET
10135 /* Specifying the PC register as the post-indexed
10136 registers is also unpredictable. */
10137 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
10138 is_unpredictable
= true;
10146 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
10147 bfd_vma target
= disp
* 4 + pc
+ 8;
10148 info
->print_address_func (target
, info
);
10150 /* Fill in instruction information. */
10151 info
->insn_info_valid
= 1;
10152 info
->insn_type
= dis_branch
;
10153 info
->target
= target
;
10158 if (((given
>> 28) & 0xf) != 0xe)
10159 func (stream
, "%s",
10160 arm_conditional
[(given
>> 28) & 0xf]);
10168 func (stream
, "{");
10169 for (reg
= 0; reg
< 16; reg
++)
10170 if ((given
& (1 << reg
)) != 0)
10173 func (stream
, ", ");
10175 func (stream
, "%s", arm_regnames
[reg
]);
10177 func (stream
, "}");
10179 is_unpredictable
= true;
10184 arm_decode_shift (given
, func
, stream
, false);
10188 if ((given
& 0x02000000) != 0)
10190 unsigned int rotate
= (given
& 0xf00) >> 7;
10191 unsigned int immed
= (given
& 0xff);
10194 a
= (immed
<< ((32 - rotate
) & 31)
10195 | immed
>> rotate
) & 0xffffffff;
10196 /* If there is another encoding with smaller rotate,
10197 the rotate should be specified directly. */
10198 for (i
= 0; i
< 32; i
+= 2)
10199 if ((a
<< i
| a
>> ((32 - i
) & 31)) <= 0xff)
10203 func (stream
, "#%d, %d", immed
, rotate
);
10205 func (stream
, "#%d", a
);
10206 value_in_comment
= a
;
10209 arm_decode_shift (given
, func
, stream
, true);
10213 if ((given
& 0x0000f000) == 0x0000f000)
10215 arm_feature_set arm_ext_v6
=
10216 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
10218 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10219 mechanism for setting PSR flag bits. They are
10220 obsolete in V6 onwards. */
10221 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
10223 func (stream
, "p");
10225 is_unpredictable
= true;
10230 if ((given
& 0x01200000) == 0x00200000)
10231 func (stream
, "t");
10236 int offset
= given
& 0xff;
10238 value_in_comment
= offset
* 4;
10239 if (NEGATIVE_BIT_SET
)
10240 value_in_comment
= - value_in_comment
;
10242 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
10247 func (stream
, ", #%d]%s",
10248 (int) value_in_comment
,
10249 WRITEBACK_BIT_SET
? "!" : "");
10251 func (stream
, "]");
10255 func (stream
, "]");
10257 if (WRITEBACK_BIT_SET
)
10260 func (stream
, ", #%d", (int) value_in_comment
);
10264 func (stream
, ", {%d}", (int) offset
);
10265 value_in_comment
= offset
;
10272 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10275 bfd_vma offset
= 0;
10277 if (! NEGATIVE_BIT_SET
)
10278 /* Is signed, hi bits should be ones. */
10279 offset
= (-1) ^ 0x00ffffff;
10281 /* Offset is (SignExtend(offset field)<<2). */
10282 offset
+= given
& 0x00ffffff;
10284 address
= offset
+ pc
+ 8;
10286 if (given
& 0x01000000)
10287 /* H bit allows addressing to 2-byte boundaries. */
10290 info
->print_address_func (address
, info
);
10292 /* Fill in instruction information. */
10293 info
->insn_info_valid
= 1;
10294 info
->insn_type
= dis_branch
;
10295 info
->target
= address
;
10300 if ((given
& 0x02000200) == 0x200)
10303 unsigned sysm
= (given
& 0x004f0000) >> 16;
10305 sysm
|= (given
& 0x300) >> 4;
10306 name
= banked_regname (sysm
);
10309 func (stream
, "%s", name
);
10311 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10315 func (stream
, "%cPSR_",
10316 (given
& 0x00400000) ? 'S' : 'C');
10317 if (given
& 0x80000)
10318 func (stream
, "f");
10319 if (given
& 0x40000)
10320 func (stream
, "s");
10321 if (given
& 0x20000)
10322 func (stream
, "x");
10323 if (given
& 0x10000)
10324 func (stream
, "c");
10329 if ((given
& 0xf0) == 0x60)
10331 switch (given
& 0xf)
10333 case 0xf: func (stream
, "sy"); break;
10335 func (stream
, "#%d", (int) given
& 0xf);
10341 const char * opt
= data_barrier_option (given
& 0xf);
10343 func (stream
, "%s", opt
);
10345 func (stream
, "#%d", (int) given
& 0xf);
10349 case '0': case '1': case '2': case '3': case '4':
10350 case '5': case '6': case '7': case '8': case '9':
10353 unsigned long value
;
10355 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
10361 is_unpredictable
= true;
10362 /* Fall through. */
10365 /* We want register + 1 when decoding T. */
10367 value
= (value
+ 1) & 0xf;
10371 /* Eat the 'u' character. */
10374 if (u_reg
== value
)
10375 is_unpredictable
= true;
10380 /* Eat the 'U' character. */
10383 if (U_reg
== value
)
10384 is_unpredictable
= true;
10387 func (stream
, "%s", arm_regnames
[value
]);
10390 func (stream
, "%ld", value
);
10391 value_in_comment
= value
;
10394 func (stream
, "%ld", value
* 8);
10395 value_in_comment
= value
* 8;
10398 func (stream
, "%ld", value
+ 1);
10399 value_in_comment
= value
+ 1;
10402 func (stream
, "0x%08lx", value
);
10404 /* Some SWI instructions have special
10406 if ((given
& 0x0fffffff) == 0x0FF00000)
10407 func (stream
, "\t; IMB");
10408 else if ((given
& 0x0fffffff) == 0x0FF00001)
10409 func (stream
, "\t; IMBRange");
10412 func (stream
, "%01lx", value
& 0xf);
10413 value_in_comment
= value
;
10418 func (stream
, "%c", *c
);
10422 if (value
== ((1ul << width
) - 1))
10423 func (stream
, "%c", *c
);
10426 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
10439 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
10440 func (stream
, "%d", imm
);
10441 value_in_comment
= imm
;
10446 /* LSB and WIDTH fields of BFI or BFC. The machine-
10447 language instruction encodes LSB and MSB. */
10449 long msb
= (given
& 0x001f0000) >> 16;
10450 long lsb
= (given
& 0x00000f80) >> 7;
10451 long w
= msb
- lsb
+ 1;
10454 func (stream
, "#%lu, #%lu", lsb
, w
);
10456 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
10461 /* Get the PSR/banked register name. */
10464 unsigned sysm
= (given
& 0x004f0000) >> 16;
10466 sysm
|= (given
& 0x300) >> 4;
10467 name
= banked_regname (sysm
);
10470 func (stream
, "%s", name
);
10472 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10477 /* 16-bit unsigned immediate from a MOVT or MOVW
10478 instruction, encoded in bits 0:11 and 15:19. */
10480 long hi
= (given
& 0x000f0000) >> 4;
10481 long lo
= (given
& 0x00000fff);
10482 long imm16
= hi
| lo
;
10484 func (stream
, "#%lu", imm16
);
10485 value_in_comment
= imm16
;
10494 func (stream
, "%c", *c
);
10497 if (value_in_comment
> 32 || value_in_comment
< -16)
10498 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
10500 if (is_unpredictable
)
10501 func (stream
, UNPREDICTABLE_INSTRUCTION
);
10506 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
10510 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10513 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10515 const struct opcode16
*insn
;
10516 void *stream
= info
->stream
;
10517 fprintf_ftype func
= info
->fprintf_func
;
10519 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
10520 if ((given
& insn
->mask
) == insn
->value
)
10522 signed long value_in_comment
= 0;
10523 const char *c
= insn
->assembler
;
10532 func (stream
, "%c", *c
);
10539 func (stream
, "%%");
10544 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10549 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10551 func (stream
, "s");
10558 ifthen_next_state
= given
& 0xff;
10559 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
10560 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
10561 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
10566 if (ifthen_next_state
)
10567 func (stream
, "\t; unpredictable branch in IT block\n");
10572 func (stream
, "\t; unpredictable <IT:%s>",
10573 arm_conditional
[IFTHEN_COND
]);
10580 reg
= (given
>> 3) & 0x7;
10581 if (given
& (1 << 6))
10584 func (stream
, "%s", arm_regnames
[reg
]);
10593 if (given
& (1 << 7))
10596 func (stream
, "%s", arm_regnames
[reg
]);
10601 if (given
& (1 << 8))
10603 /* Fall through. */
10605 if (*c
== 'O' && (given
& (1 << 8)))
10607 /* Fall through. */
10613 func (stream
, "{");
10615 /* It would be nice if we could spot
10616 ranges, and generate the rS-rE format: */
10617 for (reg
= 0; (reg
< 8); reg
++)
10618 if ((given
& (1 << reg
)) != 0)
10621 func (stream
, ", ");
10623 func (stream
, "%s", arm_regnames
[reg
]);
10629 func (stream
, ", ");
10631 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
10637 func (stream
, ", ");
10638 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
10641 func (stream
, "}");
10646 /* Print writeback indicator for a LDMIA. We are doing a
10647 writeback if the base register is not in the register
10649 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
10650 func (stream
, "!");
10654 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10656 bfd_vma address
= (pc
+ 4
10657 + ((given
& 0x00f8) >> 2)
10658 + ((given
& 0x0200) >> 3));
10659 info
->print_address_func (address
, info
);
10661 /* Fill in instruction information. */
10662 info
->insn_info_valid
= 1;
10663 info
->insn_type
= dis_branch
;
10664 info
->target
= address
;
10669 /* Right shift immediate -- bits 6..10; 1-31 print
10670 as themselves, 0 prints as 32. */
10672 long imm
= (given
& 0x07c0) >> 6;
10675 func (stream
, "#%ld", imm
);
10679 case '0': case '1': case '2': case '3': case '4':
10680 case '5': case '6': case '7': case '8': case '9':
10682 int bitstart
= *c
++ - '0';
10685 while (*c
>= '0' && *c
<= '9')
10686 bitstart
= (bitstart
* 10) + *c
++ - '0';
10695 while (*c
>= '0' && *c
<= '9')
10696 bitend
= (bitend
* 10) + *c
++ - '0';
10699 reg
= given
>> bitstart
;
10700 reg
&= (2 << (bitend
- bitstart
)) - 1;
10705 func (stream
, "%s", arm_regnames
[reg
]);
10709 func (stream
, "%ld", (long) reg
);
10710 value_in_comment
= reg
;
10714 func (stream
, "%ld", (long) (reg
<< 1));
10715 value_in_comment
= reg
<< 1;
10719 func (stream
, "%ld", (long) (reg
<< 2));
10720 value_in_comment
= reg
<< 2;
10724 /* PC-relative address -- the bottom two
10725 bits of the address are dropped
10726 before the calculation. */
10727 info
->print_address_func
10728 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
10729 value_in_comment
= 0;
10733 func (stream
, "0x%04lx", (long) reg
);
10737 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
10738 bfd_vma target
= reg
* 2 + pc
+ 4;
10739 info
->print_address_func (target
, info
);
10740 value_in_comment
= 0;
10742 /* Fill in instruction information. */
10743 info
->insn_info_valid
= 1;
10744 info
->insn_type
= dis_branch
;
10745 info
->target
= target
;
10749 func (stream
, "%s", arm_conditional
[reg
]);
10760 if ((given
& (1 << bitstart
)) != 0)
10761 func (stream
, "%c", *c
);
10766 if ((given
& (1 << bitstart
)) != 0)
10767 func (stream
, "%c", *c
++);
10769 func (stream
, "%c", *++c
);
10783 if (value_in_comment
> 32 || value_in_comment
< -16)
10784 func (stream
, "\t; 0x%lx", value_in_comment
);
10789 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
10793 /* Return the name of an V7M special register. */
10795 static const char *
10796 psr_name (int regno
)
10800 case 0x0: return "APSR";
10801 case 0x1: return "IAPSR";
10802 case 0x2: return "EAPSR";
10803 case 0x3: return "PSR";
10804 case 0x5: return "IPSR";
10805 case 0x6: return "EPSR";
10806 case 0x7: return "IEPSR";
10807 case 0x8: return "MSP";
10808 case 0x9: return "PSP";
10809 case 0xa: return "MSPLIM";
10810 case 0xb: return "PSPLIM";
10811 case 0x10: return "PRIMASK";
10812 case 0x11: return "BASEPRI";
10813 case 0x12: return "BASEPRI_MAX";
10814 case 0x13: return "FAULTMASK";
10815 case 0x14: return "CONTROL";
10816 case 0x88: return "MSP_NS";
10817 case 0x89: return "PSP_NS";
10818 case 0x8a: return "MSPLIM_NS";
10819 case 0x8b: return "PSPLIM_NS";
10820 case 0x90: return "PRIMASK_NS";
10821 case 0x91: return "BASEPRI_NS";
10822 case 0x93: return "FAULTMASK_NS";
10823 case 0x94: return "CONTROL_NS";
10824 case 0x98: return "SP_NS";
10825 default: return "<unknown>";
10829 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10832 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10834 const struct opcode32
*insn
;
10835 void *stream
= info
->stream
;
10836 fprintf_ftype func
= info
->fprintf_func
;
10837 bool is_mve
= is_mve_architecture (info
);
10839 if (print_insn_coprocessor (pc
, info
, given
, true))
10842 if (!is_mve
&& print_insn_neon (info
, given
, true))
10845 if (is_mve
&& print_insn_mve (info
, given
))
10848 if (print_insn_cde (info
, given
, true))
10851 if (print_insn_generic_coprocessor (pc
, info
, given
, true))
10854 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
10855 if ((given
& insn
->mask
) == insn
->value
)
10857 bool is_clrm
= false;
10858 bool is_unpredictable
= false;
10859 signed long value_in_comment
= 0;
10860 const char *c
= insn
->assembler
;
10866 func (stream
, "%c", *c
);
10873 func (stream
, "%%");
10878 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10882 if (ifthen_next_state
)
10883 func (stream
, "\t; unpredictable branch in IT block\n");
10888 func (stream
, "\t; unpredictable <IT:%s>",
10889 arm_conditional
[IFTHEN_COND
]);
10894 unsigned int imm12
= 0;
10896 imm12
|= (given
& 0x000000ffu
);
10897 imm12
|= (given
& 0x00007000u
) >> 4;
10898 imm12
|= (given
& 0x04000000u
) >> 15;
10899 func (stream
, "#%u", imm12
);
10900 value_in_comment
= imm12
;
10906 unsigned int bits
= 0, imm
, imm8
, mod
;
10908 bits
|= (given
& 0x000000ffu
);
10909 bits
|= (given
& 0x00007000u
) >> 4;
10910 bits
|= (given
& 0x04000000u
) >> 15;
10911 imm8
= (bits
& 0x0ff);
10912 mod
= (bits
& 0xf00) >> 8;
10915 case 0: imm
= imm8
; break;
10916 case 1: imm
= ((imm8
<< 16) | imm8
); break;
10917 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
10918 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
10920 mod
= (bits
& 0xf80) >> 7;
10921 imm8
= (bits
& 0x07f) | 0x80;
10922 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
10924 func (stream
, "#%u", imm
);
10925 value_in_comment
= imm
;
10931 unsigned int imm
= 0;
10933 imm
|= (given
& 0x000000ffu
);
10934 imm
|= (given
& 0x00007000u
) >> 4;
10935 imm
|= (given
& 0x04000000u
) >> 15;
10936 imm
|= (given
& 0x000f0000u
) >> 4;
10937 func (stream
, "#%u", imm
);
10938 value_in_comment
= imm
;
10944 unsigned int imm
= 0;
10946 imm
|= (given
& 0x000f0000u
) >> 16;
10947 imm
|= (given
& 0x00000ff0u
) >> 0;
10948 imm
|= (given
& 0x0000000fu
) << 12;
10949 func (stream
, "#%u", imm
);
10950 value_in_comment
= imm
;
10956 unsigned int imm
= 0;
10958 imm
|= (given
& 0x000f0000u
) >> 4;
10959 imm
|= (given
& 0x00000fffu
) >> 0;
10960 func (stream
, "#%u", imm
);
10961 value_in_comment
= imm
;
10967 unsigned int imm
= 0;
10969 imm
|= (given
& 0x00000fffu
);
10970 imm
|= (given
& 0x000f0000u
) >> 4;
10971 func (stream
, "#%u", imm
);
10972 value_in_comment
= imm
;
10978 unsigned int reg
= (given
& 0x0000000fu
);
10979 unsigned int stp
= (given
& 0x00000030u
) >> 4;
10980 unsigned int imm
= 0;
10981 imm
|= (given
& 0x000000c0u
) >> 6;
10982 imm
|= (given
& 0x00007000u
) >> 10;
10984 func (stream
, "%s", arm_regnames
[reg
]);
10989 func (stream
, ", lsl #%u", imm
);
10995 func (stream
, ", lsr #%u", imm
);
11001 func (stream
, ", asr #%u", imm
);
11006 func (stream
, ", rrx");
11008 func (stream
, ", ror #%u", imm
);
11015 unsigned int Rn
= (given
& 0x000f0000) >> 16;
11016 unsigned int U
= ! NEGATIVE_BIT_SET
;
11017 unsigned int op
= (given
& 0x00000f00) >> 8;
11018 unsigned int i12
= (given
& 0x00000fff);
11019 unsigned int i8
= (given
& 0x000000ff);
11020 bool writeback
= false, postind
= false;
11021 bfd_vma offset
= 0;
11023 func (stream
, "[%s", arm_regnames
[Rn
]);
11024 if (U
) /* 12-bit positive immediate offset. */
11028 value_in_comment
= offset
;
11030 else if (Rn
== 15) /* 12-bit negative immediate offset. */
11031 offset
= - (int) i12
;
11032 else if (op
== 0x0) /* Shifted register offset. */
11034 unsigned int Rm
= (i8
& 0x0f);
11035 unsigned int sh
= (i8
& 0x30) >> 4;
11037 func (stream
, ", %s", arm_regnames
[Rm
]);
11039 func (stream
, ", lsl #%u", sh
);
11040 func (stream
, "]");
11045 case 0xE: /* 8-bit positive immediate offset. */
11049 case 0xC: /* 8-bit negative immediate offset. */
11053 case 0xF: /* 8-bit + preindex with wb. */
11058 case 0xD: /* 8-bit - preindex with wb. */
11063 case 0xB: /* 8-bit + postindex. */
11068 case 0x9: /* 8-bit - postindex. */
11074 func (stream
, ", <undefined>]");
11079 func (stream
, "], #%d", (int) offset
);
11083 func (stream
, ", #%d", (int) offset
);
11084 func (stream
, writeback
? "]!" : "]");
11089 func (stream
, "\t; ");
11090 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
11098 unsigned int U
= ! NEGATIVE_BIT_SET
;
11099 unsigned int W
= WRITEBACK_BIT_SET
;
11100 unsigned int Rn
= (given
& 0x000f0000) >> 16;
11101 unsigned int off
= (given
& 0x000000ff);
11103 func (stream
, "[%s", arm_regnames
[Rn
]);
11109 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
11110 value_in_comment
= off
* 4 * (U
? 1 : -1);
11112 func (stream
, "]");
11114 func (stream
, "!");
11118 func (stream
, "], ");
11121 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
11122 value_in_comment
= off
* 4 * (U
? 1 : -1);
11126 func (stream
, "{%u}", off
);
11127 value_in_comment
= off
;
11135 unsigned int Sbit
= (given
& 0x01000000) >> 24;
11136 unsigned int type
= (given
& 0x00600000) >> 21;
11140 case 0: func (stream
, Sbit
? "sb" : "b"); break;
11141 case 1: func (stream
, Sbit
? "sh" : "h"); break;
11144 func (stream
, "??");
11147 func (stream
, "??");
11155 /* Fall through. */
11161 func (stream
, "{");
11162 for (reg
= 0; reg
< 16; reg
++)
11163 if ((given
& (1 << reg
)) != 0)
11166 func (stream
, ", ");
11168 if (is_clrm
&& reg
== 13)
11169 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
11170 else if (is_clrm
&& reg
== 15)
11171 func (stream
, "%s", "APSR");
11173 func (stream
, "%s", arm_regnames
[reg
]);
11175 func (stream
, "}");
11181 unsigned int msb
= (given
& 0x0000001f);
11182 unsigned int lsb
= 0;
11184 lsb
|= (given
& 0x000000c0u
) >> 6;
11185 lsb
|= (given
& 0x00007000u
) >> 10;
11186 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
11192 unsigned int width
= (given
& 0x0000001f) + 1;
11193 unsigned int lsb
= 0;
11195 lsb
|= (given
& 0x000000c0u
) >> 6;
11196 lsb
|= (given
& 0x00007000u
) >> 10;
11197 func (stream
, "#%u, #%u", lsb
, width
);
11203 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
11204 func (stream
, "%x", boff
);
11210 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
11211 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11212 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11213 bfd_vma offset
= 0;
11215 offset
|= immA
<< 12;
11216 offset
|= immB
<< 2;
11217 offset
|= immC
<< 1;
11219 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
11221 info
->print_address_func (pc
+ 4 + offset
, info
);
11227 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
11228 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11229 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11230 bfd_vma offset
= 0;
11232 offset
|= immA
<< 12;
11233 offset
|= immB
<< 2;
11234 offset
|= immC
<< 1;
11236 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
11238 info
->print_address_func (pc
+ 4 + offset
, info
);
11244 unsigned int immA
= (given
& 0x00010000u
) >> 16;
11245 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11246 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11247 bfd_vma offset
= 0;
11249 offset
|= immA
<< 12;
11250 offset
|= immB
<< 2;
11251 offset
|= immC
<< 1;
11253 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
11255 info
->print_address_func (pc
+ 4 + offset
, info
);
11257 unsigned int T
= (given
& 0x00020000u
) >> 17;
11258 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
11259 unsigned int boffset
= (T
== 1) ? 4 : 2;
11260 func (stream
, ", ");
11261 func (stream
, "%x", endoffset
+ boffset
);
11267 unsigned int immh
= (given
& 0x000007feu
) >> 1;
11268 unsigned int imml
= (given
& 0x00000800u
) >> 11;
11271 imm32
|= immh
<< 2;
11272 imm32
|= imml
<< 1;
11274 info
->print_address_func (pc
+ 4 + imm32
, info
);
11280 unsigned int immh
= (given
& 0x000007feu
) >> 1;
11281 unsigned int imml
= (given
& 0x00000800u
) >> 11;
11284 imm32
|= immh
<< 2;
11285 imm32
|= imml
<< 1;
11287 info
->print_address_func (pc
+ 4 - imm32
, info
);
11293 unsigned int S
= (given
& 0x04000000u
) >> 26;
11294 unsigned int J1
= (given
& 0x00002000u
) >> 13;
11295 unsigned int J2
= (given
& 0x00000800u
) >> 11;
11296 bfd_vma offset
= 0;
11298 offset
|= !S
<< 20;
11299 offset
|= J2
<< 19;
11300 offset
|= J1
<< 18;
11301 offset
|= (given
& 0x003f0000) >> 4;
11302 offset
|= (given
& 0x000007ff) << 1;
11303 offset
-= (1 << 20);
11305 bfd_vma target
= pc
+ 4 + offset
;
11306 info
->print_address_func (target
, info
);
11308 /* Fill in instruction information. */
11309 info
->insn_info_valid
= 1;
11310 info
->insn_type
= dis_branch
;
11311 info
->target
= target
;
11317 unsigned int S
= (given
& 0x04000000u
) >> 26;
11318 unsigned int I1
= (given
& 0x00002000u
) >> 13;
11319 unsigned int I2
= (given
& 0x00000800u
) >> 11;
11320 bfd_vma offset
= 0;
11322 offset
|= !S
<< 24;
11323 offset
|= !(I1
^ S
) << 23;
11324 offset
|= !(I2
^ S
) << 22;
11325 offset
|= (given
& 0x03ff0000u
) >> 4;
11326 offset
|= (given
& 0x000007ffu
) << 1;
11327 offset
-= (1 << 24);
11330 /* BLX target addresses are always word aligned. */
11331 if ((given
& 0x00001000u
) == 0)
11334 info
->print_address_func (offset
, info
);
11336 /* Fill in instruction information. */
11337 info
->insn_info_valid
= 1;
11338 info
->insn_type
= dis_branch
;
11339 info
->target
= offset
;
11345 unsigned int shift
= 0;
11347 shift
|= (given
& 0x000000c0u
) >> 6;
11348 shift
|= (given
& 0x00007000u
) >> 10;
11349 if (WRITEBACK_BIT_SET
)
11350 func (stream
, ", asr #%u", shift
);
11352 func (stream
, ", lsl #%u", shift
);
11353 /* else print nothing - lsl #0 */
11359 unsigned int rot
= (given
& 0x00000030) >> 4;
11362 func (stream
, ", ror #%u", rot
* 8);
11367 if ((given
& 0xf0) == 0x60)
11369 switch (given
& 0xf)
11371 case 0xf: func (stream
, "sy"); break;
11373 func (stream
, "#%d", (int) given
& 0xf);
11379 const char * opt
= data_barrier_option (given
& 0xf);
11381 func (stream
, "%s", opt
);
11383 func (stream
, "#%d", (int) given
& 0xf);
11388 if ((given
& 0xff) == 0)
11390 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
11392 func (stream
, "f");
11394 func (stream
, "s");
11396 func (stream
, "x");
11398 func (stream
, "c");
11400 else if ((given
& 0x20) == 0x20)
11403 unsigned sysm
= (given
& 0xf00) >> 8;
11405 sysm
|= (given
& 0x30);
11406 sysm
|= (given
& 0x00100000) >> 14;
11407 name
= banked_regname (sysm
);
11410 func (stream
, "%s", name
);
11412 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
11416 func (stream
, "%s", psr_name (given
& 0xff));
11421 if (((given
& 0xff) == 0)
11422 || ((given
& 0x20) == 0x20))
11425 unsigned sm
= (given
& 0xf0000) >> 16;
11427 sm
|= (given
& 0x30);
11428 sm
|= (given
& 0x00100000) >> 14;
11429 name
= banked_regname (sm
);
11432 func (stream
, "%s", name
);
11434 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
11437 func (stream
, "%s", psr_name (given
& 0xff));
11440 case '0': case '1': case '2': case '3': case '4':
11441 case '5': case '6': case '7': case '8': case '9':
11446 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
11452 func (stream
, "%s", mve_vec_sizename
[val
]);
11454 func (stream
, "<undef size>");
11458 func (stream
, "%lu", val
);
11459 value_in_comment
= val
;
11463 func (stream
, "%lu", val
+ 1);
11464 value_in_comment
= val
+ 1;
11468 func (stream
, "%lu", val
* 4);
11469 value_in_comment
= val
* 4;
11474 is_unpredictable
= true;
11475 /* Fall through. */
11478 is_unpredictable
= true;
11479 /* Fall through. */
11481 func (stream
, "%s", arm_regnames
[val
]);
11485 func (stream
, "%s", arm_conditional
[val
]);
11490 if (val
== ((1ul << width
) - 1))
11491 func (stream
, "%c", *c
);
11497 func (stream
, "%c", *c
);
11501 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
11506 func (stream
, "0x%lx", val
& 0xffffffffUL
);
11516 /* PR binutils/12534
11517 If we have a PC relative offset in an LDRD or STRD
11518 instructions then display the decoded address. */
11519 if (((given
>> 16) & 0xf) == 0xf)
11521 bfd_vma offset
= (given
& 0xff) * 4;
11523 if ((given
& (1 << 23)) == 0)
11525 func (stream
, "\t; ");
11526 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
11535 if (value_in_comment
> 32 || value_in_comment
< -16)
11536 func (stream
, "\t; 0x%lx", value_in_comment
);
11538 if (is_unpredictable
)
11539 func (stream
, UNPREDICTABLE_INSTRUCTION
);
11545 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
11549 /* Print data bytes on INFO->STREAM. */
11552 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
11553 struct disassemble_info
*info
,
11556 switch (info
->bytes_per_chunk
)
11559 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
11562 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
11565 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
11572 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11573 being displayed in symbol relative addresses.
11575 Also disallow private symbol, with __tagsym$$ prefix,
11576 from ARM RVCT toolchain being displayed. */
11579 arm_symbol_is_valid (asymbol
* sym
,
11580 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
11587 name
= bfd_asymbol_name (sym
);
11589 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
11592 /* Parse the string of disassembler options. */
11595 parse_arm_disassembler_options (const char *options
)
11599 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
11601 if (startswith (opt
, "reg-names-"))
11604 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11605 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
11607 regname_selected
= i
;
11611 if (i
>= NUM_ARM_OPTIONS
)
11612 /* xgettext: c-format */
11613 opcodes_error_handler (_("unrecognised register name set: %s"),
11616 else if (startswith (opt
, "force-thumb"))
11618 else if (startswith (opt
, "no-force-thumb"))
11620 else if (startswith (opt
, "coproc"))
11622 const char *procptr
= opt
+ sizeof ("coproc") - 1;
11624 uint8_t coproc_number
= strtol (procptr
, &endptr
, 10);
11625 if (endptr
!= procptr
+ 1 || coproc_number
> 7)
11627 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11631 if (*endptr
!= '=')
11633 opcodes_error_handler (_("coproc must have an argument: %s"),
11638 if (startswith (endptr
, "generic"))
11639 cde_coprocs
&= ~(1 << coproc_number
);
11640 else if (startswith (endptr
, "cde")
11641 || startswith (endptr
, "CDE"))
11642 cde_coprocs
|= (1 << coproc_number
);
11645 opcodes_error_handler (
11646 _("coprocN argument takes options \"generic\","
11647 " \"cde\", or \"CDE\": %s"), opt
);
11651 /* xgettext: c-format */
11652 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
11659 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11660 enum map_type
*map_symbol
);
11662 /* Search back through the insn stream to determine if this instruction is
11663 conditionally executed. */
11666 find_ifthen_state (bfd_vma pc
,
11667 struct disassemble_info
*info
,
11670 unsigned char b
[2];
11673 /* COUNT is twice the number of instructions seen. It will be odd if we
11674 just crossed an instruction boundary. */
11677 unsigned int seen_it
;
11680 ifthen_address
= pc
;
11687 /* Scan backwards looking for IT instructions, keeping track of where
11688 instruction boundaries are. We don't know if something is actually an
11689 IT instruction until we find a definite instruction boundary. */
11692 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
11694 /* A symbol must be on an instruction boundary, and will not
11695 be within an IT block. */
11696 if (seen_it
&& (count
& 1))
11702 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
11707 insn
= (b
[0]) | (b
[1] << 8);
11709 insn
= (b
[1]) | (b
[0] << 8);
11712 if ((insn
& 0xf800) < 0xe800)
11714 /* Addr + 2 is an instruction boundary. See if this matches
11715 the expected boundary based on the position of the last
11722 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
11724 enum map_type type
= MAP_ARM
;
11725 bool found
= mapping_symbol_for_insn (addr
, info
, &type
);
11727 if (!found
|| (found
&& type
== MAP_THUMB
))
11729 /* This could be an IT instruction. */
11731 it_count
= count
>> 1;
11734 if ((insn
& 0xf800) >= 0xe800)
11737 count
= (count
+ 2) | 1;
11738 /* IT blocks contain at most 4 instructions. */
11739 if (count
>= 8 && !seen_it
)
11742 /* We found an IT instruction. */
11743 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
11744 if ((ifthen_state
& 0xf) == 0)
11748 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11752 is_mapping_symbol (struct disassemble_info
*info
, int n
,
11753 enum map_type
*map_type
)
11757 name
= bfd_asymbol_name (info
->symtab
[n
]);
11758 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
11759 && (name
[2] == 0 || name
[2] == '.'))
11761 *map_type
= ((name
[1] == 'a') ? MAP_ARM
11762 : (name
[1] == 't') ? MAP_THUMB
11770 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11771 Returns nonzero if *MAP_TYPE was set. */
11774 get_map_sym_type (struct disassemble_info
*info
,
11776 enum map_type
*map_type
)
11778 /* If the symbol is in a different section, ignore it. */
11779 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11782 return is_mapping_symbol (info
, n
, map_type
);
11785 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11786 Returns nonzero if *MAP_TYPE was set. */
11789 get_sym_code_type (struct disassemble_info
*info
,
11791 enum map_type
*map_type
)
11793 elf_symbol_type
*es
;
11796 /* If the symbol is in a different section, ignore it. */
11797 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11800 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
11801 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11803 /* If the symbol has function type then use that. */
11804 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
11806 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11807 == ST_BRANCH_TO_THUMB
)
11808 *map_type
= MAP_THUMB
;
11810 *map_type
= MAP_ARM
;
11817 /* Search the mapping symbol state for instruction at pc. This is only
11818 applicable for elf target.
11820 There is an assumption Here, info->private_data contains the correct AND
11821 up-to-date information about current scan process. The information will be
11822 used to speed this search process.
11824 Return TRUE if the mapping state can be determined, and map_symbol
11825 will be updated accordingly. Otherwise, return FALSE. */
11828 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11829 enum map_type
*map_symbol
)
11831 bfd_vma addr
, section_vma
= 0;
11832 int n
, last_sym
= -1;
11833 bool found
= false;
11834 bool can_use_search_opt_p
= false;
11836 /* Default to DATA. A text section is required by the ABI to contain an
11837 INSN mapping symbol at the start. A data section has no such
11838 requirement, hence if no mapping symbol is found the section must
11839 contain only data. This however isn't very useful if the user has
11840 fully stripped the binaries. If this is the case use the section
11841 attributes to determine the default. If we have no section default to
11842 INSN as well, as we may be disassembling some raw bytes on a baremetal
11843 HEX file or similar. */
11844 enum map_type type
= MAP_DATA
;
11845 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
11847 struct arm_private_data
*private_data
;
11849 if (info
->private_data
== NULL
11850 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
11853 private_data
= info
->private_data
;
11855 /* First, look for mapping symbols. */
11856 if (info
->symtab_size
!= 0)
11858 if (pc
<= private_data
->last_mapping_addr
)
11859 private_data
->last_mapping_sym
= -1;
11861 /* Start scanning at the start of the function, or wherever
11862 we finished last time. */
11863 n
= info
->symtab_pos
+ 1;
11865 /* If the last stop offset is different from the current one it means we
11866 are disassembling a different glob of bytes. As such the optimization
11867 would not be safe and we should start over. */
11868 can_use_search_opt_p
11869 = private_data
->last_mapping_sym
>= 0
11870 && info
->stop_offset
== private_data
->last_stop_offset
;
11872 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11873 n
= private_data
->last_mapping_sym
;
11875 /* Look down while we haven't passed the location being disassembled.
11876 The reason for this is that there's no defined order between a symbol
11877 and an mapping symbol that may be at the same address. We may have to
11878 look at least one position ahead. */
11879 for (; n
< info
->symtab_size
; n
++)
11881 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11884 if (get_map_sym_type (info
, n
, &type
))
11893 n
= info
->symtab_pos
;
11894 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11895 n
= private_data
->last_mapping_sym
;
11897 /* No mapping symbol found at this address. Look backwards
11898 for a preceeding one, but don't go pass the section start
11899 otherwise a data section with no mapping symbol can pick up
11900 a text mapping symbol of a preceeding section. The documentation
11901 says section can be NULL, in which case we will seek up all the
11904 section_vma
= info
->section
->vma
;
11906 for (; n
>= 0; n
--)
11908 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11909 if (addr
< section_vma
)
11912 if (get_map_sym_type (info
, n
, &type
))
11922 /* If no mapping symbol was found, try looking up without a mapping
11923 symbol. This is done by walking up from the current PC to the nearest
11924 symbol. We don't actually have to loop here since symtab_pos will
11925 contain the nearest symbol already. */
11928 n
= info
->symtab_pos
;
11929 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
11936 private_data
->last_mapping_sym
= last_sym
;
11937 private_data
->last_type
= type
;
11938 private_data
->last_stop_offset
= info
->stop_offset
;
11940 *map_symbol
= type
;
11944 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11945 of the supplied arm_feature_set structure with bitmasks indicating
11946 the supported base architectures and coprocessor extensions.
11948 FIXME: This could more efficiently implemented as a constant array,
11949 although it would also be less robust. */
11952 select_arm_features (unsigned long mach
,
11953 arm_feature_set
* features
)
11955 arm_feature_set arch_fset
;
11956 const arm_feature_set fpu_any
= FPU_ANY
;
11958 #undef ARM_SET_FEATURES
11959 #define ARM_SET_FEATURES(FSET) \
11961 const arm_feature_set fset = FSET; \
11962 arch_fset = fset; \
11965 /* When several architecture versions share the same bfd_mach_arm_XXX value
11966 the most featureful is chosen. */
11969 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
11970 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
11971 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
11972 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
11973 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
11974 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
11975 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
11976 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
11977 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
11978 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
11979 case bfd_mach_arm_ep9312
:
11980 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
11981 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
11983 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
11984 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
11985 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
11986 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
11987 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
11988 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
11989 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
11990 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
11991 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
11992 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
11993 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
11994 case bfd_mach_arm_8
:
11996 /* Add bits for extensions that Armv8.6-A recognizes. */
11997 arm_feature_set armv8_6_ext_fset
11998 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
11999 ARM_SET_FEATURES (ARM_ARCH_V8_6A
);
12000 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_6_ext_fset
);
12003 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
12004 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
12005 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
12006 case bfd_mach_arm_8_1M_MAIN
:
12007 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
12008 arm_feature_set mve_all
12009 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
);
12010 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, mve_all
);
12013 /* If the machine type is unknown allow all architecture types and all
12014 extensions, with the exception of MVE as that clashes with NEON. */
12015 case bfd_mach_arm_unknown
:
12016 ARM_SET_FEATURES (ARM_FEATURE (-1,
12017 -1 & ~(ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
),
12023 #undef ARM_SET_FEATURES
12025 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12026 and thus on bfd_mach_arm_XXX value. Therefore for a given
12027 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12028 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
12032 /* NOTE: There are no checks in these routines that
12033 the relevant number of data bytes exist. */
12036 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bool little
)
12038 unsigned char b
[4];
12039 unsigned long given
;
12041 int is_thumb
= false;
12042 int is_data
= false;
12044 unsigned int size
= 4;
12045 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
12046 bool found
= false;
12047 struct arm_private_data
*private_data
;
12049 /* Clear instruction information field. */
12050 info
->insn_info_valid
= 0;
12051 info
->branch_delay_insns
= 0;
12052 info
->data_size
= 0;
12053 info
->insn_type
= dis_noninsn
;
12057 if (info
->disassembler_options
)
12059 parse_arm_disassembler_options (info
->disassembler_options
);
12061 /* To avoid repeated parsing of these options, we remove them here. */
12062 info
->disassembler_options
= NULL
;
12065 /* PR 10288: Control which instructions will be disassembled. */
12066 if (info
->private_data
== NULL
)
12068 static struct arm_private_data
private;
12070 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
12071 /* If the user did not use the -m command line switch then default to
12072 disassembling all types of ARM instruction.
12074 The info->mach value has to be ignored as this will be based on
12075 the default archictecture for the target and/or hints in the notes
12076 section, but it will never be greater than the current largest arm
12077 machine value (iWMMXt2), which is only equivalent to the V5TE
12078 architecture. ARM architectures have advanced beyond the machine
12079 value encoding, and these newer architectures would be ignored if
12080 the machine value was used.
12082 Ie the -m switch is used to restrict which instructions will be
12083 disassembled. If it is necessary to use the -m switch to tell
12084 objdump that an ARM binary is being disassembled, eg because the
12085 input is a raw binary file, but it is also desired to disassemble
12086 all ARM instructions then use "-marm". This will select the
12087 "unknown" arm architecture which is compatible with any ARM
12089 info
->mach
= bfd_mach_arm_unknown
;
12091 /* Compute the architecture bitmask from the machine number.
12092 Note: This assumes that the machine number will not change
12093 during disassembly.... */
12094 select_arm_features (info
->mach
, & private.features
);
12096 private.last_mapping_sym
= -1;
12097 private.last_mapping_addr
= 0;
12098 private.last_stop_offset
= 0;
12100 info
->private_data
= & private;
12103 private_data
= info
->private_data
;
12105 /* Decide if our code is going to be little-endian, despite what the
12106 function argument might say. */
12107 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
12109 /* For ELF, consult the symbol table to determine what kind of code
12110 or data we have. */
12111 if (info
->symtab_size
!= 0
12112 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
12117 enum map_type type
= MAP_ARM
;
12119 found
= mapping_symbol_for_insn (pc
, info
, &type
);
12120 last_sym
= private_data
->last_mapping_sym
;
12122 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
12123 is_data
= (private_data
->last_type
== MAP_DATA
);
12125 /* Look a little bit ahead to see if we should print out
12126 two or four bytes of data. If there's a symbol,
12127 mapping or otherwise, after two bytes then don't
12131 size
= 4 - (pc
& 3);
12132 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
12134 addr
= bfd_asymbol_value (info
->symtab
[n
]);
12136 && (info
->section
== NULL
12137 || info
->section
== info
->symtab
[n
]->section
))
12139 if (addr
- pc
< size
)
12144 /* If the next symbol is after three bytes, we need to
12145 print only part of the data, so that we can use either
12146 .byte or .short. */
12148 size
= (pc
& 1) ? 1 : 2;
12152 if (info
->symbols
!= NULL
)
12154 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
12156 coff_symbol_type
* cs
;
12158 cs
= coffsymbol (*info
->symbols
);
12159 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
12160 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
12161 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
12162 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
12163 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
12165 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
12168 /* If no mapping symbol has been found then fall back to the type
12169 of the function symbol. */
12170 elf_symbol_type
* es
;
12173 es
= *(elf_symbol_type
**)(info
->symbols
);
12174 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
12177 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
12178 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
12180 else if (bfd_asymbol_flavour (*info
->symbols
)
12181 == bfd_target_mach_o_flavour
)
12183 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
12185 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
12193 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
12195 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
12197 info
->bytes_per_line
= 4;
12199 /* PR 10263: Disassemble data if requested to do so by the user. */
12200 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
12204 /* Size was already set above. */
12205 info
->bytes_per_chunk
= size
;
12206 printer
= print_insn_data
;
12208 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
12211 for (i
= size
- 1; i
>= 0; i
--)
12212 given
= b
[i
] | (given
<< 8);
12214 for (i
= 0; i
< (int) size
; i
++)
12215 given
= b
[i
] | (given
<< 8);
12217 else if (!is_thumb
)
12219 /* In ARM mode endianness is a straightforward issue: the instruction
12220 is four bytes long and is either ordered 0123 or 3210. */
12221 printer
= print_insn_arm
;
12222 info
->bytes_per_chunk
= 4;
12225 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
12227 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | ((unsigned) b
[3] << 24);
12229 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | ((unsigned) b
[0] << 24);
12233 /* In Thumb mode we have the additional wrinkle of two
12234 instruction lengths. Fortunately, the bits that determine
12235 the length of the current instruction are always to be found
12236 in the first two bytes. */
12237 printer
= print_insn_thumb16
;
12238 info
->bytes_per_chunk
= 2;
12241 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
12243 given
= (b
[0]) | (b
[1] << 8);
12245 given
= (b
[1]) | (b
[0] << 8);
12249 /* These bit patterns signal a four-byte Thumb
12251 if ((given
& 0xF800) == 0xF800
12252 || (given
& 0xF800) == 0xF000
12253 || (given
& 0xF800) == 0xE800)
12255 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
12257 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
12259 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
12261 printer
= print_insn_thumb32
;
12266 if (ifthen_address
!= pc
)
12267 find_ifthen_state (pc
, info
, little_code
);
12271 if ((ifthen_state
& 0xf) == 0x8)
12272 ifthen_next_state
= 0;
12274 ifthen_next_state
= (ifthen_state
& 0xe0)
12275 | ((ifthen_state
& 0xf) << 1);
12281 info
->memory_error_func (status
, pc
, info
);
12284 if (info
->flags
& INSN_HAS_RELOC
)
12285 /* If the instruction has a reloc associated with it, then
12286 the offset field in the instruction will actually be the
12287 addend for the reloc. (We are using REL type relocs).
12288 In such cases, we can ignore the pc when computing
12289 addresses, since the addend is not currently pc-relative. */
12292 printer (pc
, info
, given
);
12296 ifthen_state
= ifthen_next_state
;
12297 ifthen_address
+= size
;
12303 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
12305 /* Detect BE8-ness and record it in the disassembler info. */
12306 if (info
->flavour
== bfd_target_elf_flavour
12307 && info
->section
!= NULL
12308 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
12309 info
->endian_code
= BFD_ENDIAN_LITTLE
;
12311 return print_insn (pc
, info
, false);
12315 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
12317 return print_insn (pc
, info
, true);
12320 const disasm_options_and_args_t
*
12321 disassembler_options_arm (void)
12323 static disasm_options_and_args_t
*opts_and_args
;
12325 if (opts_and_args
== NULL
)
12327 disasm_options_t
*opts
;
12330 opts_and_args
= XNEW (disasm_options_and_args_t
);
12331 opts_and_args
->args
= NULL
;
12333 opts
= &opts_and_args
->options
;
12334 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
12335 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
12337 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
12339 opts
->name
[i
] = regnames
[i
].name
;
12340 if (regnames
[i
].description
!= NULL
)
12341 opts
->description
[i
] = _(regnames
[i
].description
);
12343 opts
->description
[i
] = NULL
;
12345 /* The array we return must be NULL terminated. */
12346 opts
->name
[i
] = NULL
;
12347 opts
->description
[i
] = NULL
;
12350 return opts_and_args
;
12354 print_arm_disassembler_options (FILE *stream
)
12356 unsigned int i
, max_len
= 0;
12357 fprintf (stream
, _("\n\
12358 The following ARM specific disassembler options are supported for use with\n\
12359 the -M switch:\n"));
12361 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
12363 unsigned int len
= strlen (regnames
[i
].name
);
12368 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
12369 fprintf (stream
, " %s%*c %s\n",
12371 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
12372 _(regnames
[i
].description
));