1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
93 enum mve_unpredictable
95 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
97 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
99 UNPRED_R13
, /* Unpredictable because r13 (sp) or
101 UNPRED_NONE
/* No unpredictable behavior. */
106 UNDEF_NONE
/* no undefined behavior. */
111 arm_feature_set arch
; /* Architecture defining this insn. */
112 unsigned long value
; /* If arch is 0 then value is a sentinel. */
113 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
114 const char * assembler
; /* How to disassemble this insn. */
121 arm_feature_set arch
; /* Architecture defining this insn. */
122 enum mve_instructions mve_op
; /* Specific mve instruction for faster
124 unsigned long value
; /* If arch is 0 then value is a sentinel. */
125 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
126 const char * assembler
; /* How to disassemble this insn. */
136 /* Shared (between Arm and Thumb mode) opcode. */
139 enum isa isa
; /* Execution mode instruction availability. */
140 arm_feature_set arch
; /* Architecture defining this insn. */
141 unsigned long value
; /* If arch is 0 then value is a sentinel. */
142 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
143 const char * assembler
; /* How to disassemble this insn. */
148 arm_feature_set arch
; /* Architecture defining this insn. */
149 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
150 const char *assembler
; /* How to disassemble this insn. */
153 /* print_insn_coprocessor recognizes the following format control codes:
157 %c print condition code (always bits 28-31 in ARM mode)
158 %q print shifter argument
159 %u print condition code (unconditional in ARM mode,
160 UNPREDICTABLE if not AL in Thumb)
161 %A print address for ldc/stc/ldf/stf instruction
162 %B print vstm/vldm register list
163 %C print vscclrm register list
164 %I print cirrus signed shift immediate: bits 0..3|4..6
165 %J print register for VLDR instruction
166 %K print address for VLDR instruction
167 %F print the COUNT field of a LFM/SFM instruction.
168 %P print floating point precision in arithmetic insn
169 %Q print floating point precision in ldf/stf insn
170 %R print floating point rounding mode
172 %<bitfield>c print as a condition code (for vsel)
173 %<bitfield>r print as an ARM register
174 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
175 %<bitfield>ru as %<>r but each u register must be unique.
176 %<bitfield>d print the bitfield in decimal
177 %<bitfield>k print immediate for VFPv3 conversion instruction
178 %<bitfield>x print the bitfield in hex
179 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
180 %<bitfield>f print a floating point constant if >7 else a
181 floating point register
182 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
183 %<bitfield>g print as an iWMMXt 64-bit register
184 %<bitfield>G print as an iWMMXt general purpose or control register
185 %<bitfield>D print as a NEON D register
186 %<bitfield>Q print as a NEON Q register
187 %<bitfield>V print as a NEON D or Q register
188 %<bitfield>E print a quarter-float immediate value
190 %y<code> print a single precision VFP reg.
191 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
192 %z<code> print a double precision VFP reg
193 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
195 %<bitfield>'c print specified char iff bitfield is all ones
196 %<bitfield>`c print specified char iff bitfield is all zeroes
197 %<bitfield>?ab... select from array of values in big endian order
199 %L print as an iWMMXt N/M width field.
200 %Z print the Immediate of a WSHUFH instruction.
201 %l like 'A' except use byte offsets for 'B' & 'H'
203 %i print 5-bit immediate in bits 8,3..0
205 %r print register offset address for wldt/wstr instruction. */
207 enum opcode_sentinel_enum
209 SENTINEL_IWMMXT_START
= 1,
211 SENTINEL_GENERIC_START
214 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
215 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
216 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
217 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
219 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
221 static const struct sopcode32 coprocessor_opcodes
[] =
223 /* XScale instructions. */
224 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
225 0x0e200010, 0x0fff0ff0,
226 "mia%c\tacc0, %0-3r, %12-15r"},
227 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
228 0x0e280010, 0x0fff0ff0,
229 "miaph%c\tacc0, %0-3r, %12-15r"},
230 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
231 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
232 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
233 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
234 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
235 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
237 /* Intel Wireless MMX technology instructions. */
238 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
239 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
240 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
241 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
242 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
243 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
244 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
245 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
246 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
247 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
248 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
249 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
250 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
251 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
252 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
253 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
254 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
255 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
256 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
257 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
258 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
259 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
260 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
261 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
262 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
263 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
264 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
265 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
266 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
267 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
268 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
269 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
270 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
271 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
272 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
273 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
274 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
275 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
276 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
277 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
278 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
279 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
280 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
281 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
282 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
283 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
284 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
285 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
286 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
287 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
288 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
289 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
290 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
291 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
292 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
293 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
294 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
295 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
296 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
297 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
298 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
299 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
300 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
301 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
302 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
303 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
304 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
305 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
306 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
307 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
308 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
309 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
310 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
311 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
312 0x0e800120, 0x0f800ff0,
313 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
314 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
315 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
317 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
318 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
319 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
320 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
321 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
322 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
323 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
324 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
325 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
326 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
327 0x0e8000a0, 0x0f800ff0,
328 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
329 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
330 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
331 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
332 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
333 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
334 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
335 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
336 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
337 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
338 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
339 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
340 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
341 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
342 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
343 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
344 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
345 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
346 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
347 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
348 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
349 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
350 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
351 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
352 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
353 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
354 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
355 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
356 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
357 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
358 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
359 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
360 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
361 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
362 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
363 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
364 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
365 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
366 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
367 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
368 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
369 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
370 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
371 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
372 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
373 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
374 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
375 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
376 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
377 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
378 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
379 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
380 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
381 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
382 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
383 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
384 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
385 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
386 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
387 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
388 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
389 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
390 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
391 {ANY
, ARM_FEATURE_CORE_LOW (0),
392 SENTINEL_IWMMXT_END
, 0, "" },
394 /* Floating point coprocessor (FPA) instructions. */
395 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
396 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
397 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
398 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
399 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
400 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
401 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
402 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
403 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
404 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
405 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
406 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
407 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
408 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
409 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
410 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
411 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
412 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
413 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
414 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
415 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
416 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
417 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
418 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
419 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
420 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
421 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
422 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
423 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
424 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
425 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
426 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
427 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
428 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
429 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
430 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
431 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
432 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
433 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
434 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
435 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
436 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
437 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
438 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
439 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
440 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
441 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
442 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
443 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
444 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
445 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
446 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
447 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
448 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
449 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
450 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
451 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
452 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
453 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
454 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
455 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
456 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
457 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
458 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
459 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
460 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
461 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
462 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
463 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
464 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
465 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
466 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
467 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
468 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
469 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
470 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
471 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
472 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
473 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
474 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
475 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
476 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
477 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
478 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
479 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
480 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
482 /* Armv8.1-M Mainline instructions. */
483 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
484 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
485 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
486 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
488 /* ARMv8-M Mainline Security Extensions instructions. */
489 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
490 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
491 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
492 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
494 /* Register load/store. */
495 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
496 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
497 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
498 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
499 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
500 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
501 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
502 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
503 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
504 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
505 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
506 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
507 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
508 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
509 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
510 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
511 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
512 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
513 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
514 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
515 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
516 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
517 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
518 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
519 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
520 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
521 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
522 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
523 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
524 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
525 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
526 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
527 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
528 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
529 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
530 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
532 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
533 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
534 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
535 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
536 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
537 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
538 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
539 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
541 /* Data transfer between ARM and NEON registers. */
542 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
543 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
544 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
545 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
546 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
547 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
548 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
549 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
550 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
551 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
552 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
553 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
554 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
555 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
556 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
557 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
558 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
559 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
560 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
561 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
562 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
563 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
564 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
565 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
566 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
567 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
568 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
569 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
570 /* Half-precision conversion instructions. */
571 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
572 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
573 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
574 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
575 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
576 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
577 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
578 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
580 /* Floating point coprocessor (VFP) instructions. */
581 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
582 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
583 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
584 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
585 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
586 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
587 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
588 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
589 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
590 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
591 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
592 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
593 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
594 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
595 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
596 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
597 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
598 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
599 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
600 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
601 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
602 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
603 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
604 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
605 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
606 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
607 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
608 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
609 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
610 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
611 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
612 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
613 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
614 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
615 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
616 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
617 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
618 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
619 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
620 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
621 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
622 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
623 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
624 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
625 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
626 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
627 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
628 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
629 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
630 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
631 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
632 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
633 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
634 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
635 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
636 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
637 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
638 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
639 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
640 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
641 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
642 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
643 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
644 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
645 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
646 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
647 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
648 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
649 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
650 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
651 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
652 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
653 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
654 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
655 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
656 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
657 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
658 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
659 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
660 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
661 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
662 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
663 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
664 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
665 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
666 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
667 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
668 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
669 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
670 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
671 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
672 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
673 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
674 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
675 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
676 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
677 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
678 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
679 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
680 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
681 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
682 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
683 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
684 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
685 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
686 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
687 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
688 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
689 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
690 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
691 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
692 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
693 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
694 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
695 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
696 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
697 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
698 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
699 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
700 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
701 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
702 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
703 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
704 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
705 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
706 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
707 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
708 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
709 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
710 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
711 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
712 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
713 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
714 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
715 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
716 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
717 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
718 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
720 /* Cirrus coprocessor instructions. */
721 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
722 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
723 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
724 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
725 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
726 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
727 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
728 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
729 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
730 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
731 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
732 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
733 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
734 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
735 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
736 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
737 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
738 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
739 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
740 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
741 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
742 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
743 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
744 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
745 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
746 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
747 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
748 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
749 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
750 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
751 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
752 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
753 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
754 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
755 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
756 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
757 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
758 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
759 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
760 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
761 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
762 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
763 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
764 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
765 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
766 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
767 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
768 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
769 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
770 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
771 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
772 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
773 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
774 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
775 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
776 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
777 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
778 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
779 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
780 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
781 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
782 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
783 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
784 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
785 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
786 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
787 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
788 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
789 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
790 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
791 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
792 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
793 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
794 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
795 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
796 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
797 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
798 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
799 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
800 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
801 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
802 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
803 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
804 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
805 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
806 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
807 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
808 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
809 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
810 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
811 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
812 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
813 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
814 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
815 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
816 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
817 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
818 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
819 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
820 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
821 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
822 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
823 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
824 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
825 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
826 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
827 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
828 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
829 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
830 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
831 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
832 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
833 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
834 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
835 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
836 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
837 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
838 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
839 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
840 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
841 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
842 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
843 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
844 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
845 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
846 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
847 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
848 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
849 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
850 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
851 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
852 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
853 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
854 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
855 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
856 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
857 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
858 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
859 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
860 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
861 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
862 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
863 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
864 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
865 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
866 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
867 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
868 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
869 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
870 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
871 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
872 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
873 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
874 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
875 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
876 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
877 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
878 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
879 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
880 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
881 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
882 0x0e000600, 0x0ff00f10,
883 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
884 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
885 0x0e100600, 0x0ff00f10,
886 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
887 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
888 0x0e200600, 0x0ff00f10,
889 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
890 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
891 0x0e300600, 0x0ff00f10,
892 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
894 /* VFP Fused multiply add instructions. */
895 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
896 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
897 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
898 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
899 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
900 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
901 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
902 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
903 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
904 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
905 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
906 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
907 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
908 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
909 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
910 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
913 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
914 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
915 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
916 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
917 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
918 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
919 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
920 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
921 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
922 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
923 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
924 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
925 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
926 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
927 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
928 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
929 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
930 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
931 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
932 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
933 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
934 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
935 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
936 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
938 /* Generic coprocessor instructions. */
939 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
940 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
941 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
942 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
943 0x0c500000, 0x0ff00000,
944 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
945 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
946 0x0e000000, 0x0f000010,
947 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
948 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
949 0x0e10f010, 0x0f10f010,
950 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
951 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
952 0x0e100010, 0x0f100010,
953 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
954 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
955 0x0e000010, 0x0f100010,
956 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
957 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
958 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
959 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
960 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
962 /* V6 coprocessor instructions. */
963 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
964 0xfc500000, 0xfff00000,
965 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
966 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
967 0xfc400000, 0xfff00000,
968 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
970 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
971 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
972 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
973 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
974 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
975 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
976 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
977 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
978 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
979 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
980 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
981 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
982 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
983 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
984 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
985 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
986 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
987 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
988 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
989 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
990 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
992 /* Dot Product instructions in the space of coprocessor 13. */
993 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
994 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
995 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
996 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
998 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
999 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1000 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1001 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1002 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1003 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1004 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1005 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1006 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1007 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1008 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1009 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1010 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1011 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1012 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1013 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1014 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1016 /* V5 coprocessor instructions. */
1017 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1018 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1019 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1020 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1021 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1022 0xfe000000, 0xff000010,
1023 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1024 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1025 0xfe000010, 0xff100010,
1026 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1027 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1028 0xfe100010, 0xff100010,
1029 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1031 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1032 cp_num: bit <11:8> == 0b1001.
1033 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1034 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1035 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1036 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1037 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1038 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1039 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1040 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1041 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1042 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1043 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1044 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1045 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1046 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1047 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1048 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1049 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1050 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1051 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1052 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1053 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1054 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1055 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1056 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1057 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1058 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1059 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1060 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1061 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1062 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1063 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1064 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1065 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1066 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1067 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1068 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1069 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1070 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1071 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1072 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1073 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1074 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1075 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1076 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1077 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1078 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1079 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1080 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1081 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1082 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1083 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1084 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1085 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1086 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1087 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1088 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1089 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1090 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1091 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1092 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1093 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1094 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1095 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1096 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1097 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1098 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1099 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1100 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1101 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1102 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1103 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1105 /* ARMv8.3 javascript conversion instruction. */
1106 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1107 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1109 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1112 /* Neon opcode table: This does not encode the top byte -- that is
1113 checked by the print_insn_neon routine, as it depends on whether we are
1114 doing thumb32 or arm32 disassembly. */
1116 /* print_insn_neon recognizes the following format control codes:
1120 %c print condition code
1121 %u print condition code (unconditional in ARM mode,
1122 UNPREDICTABLE if not AL in Thumb)
1123 %A print v{st,ld}[1234] operands
1124 %B print v{st,ld}[1234] any one operands
1125 %C print v{st,ld}[1234] single->all operands
1127 %E print vmov, vmvn, vorr, vbic encoded constant
1128 %F print vtbl,vtbx register list
1130 %<bitfield>r print as an ARM register
1131 %<bitfield>d print the bitfield in decimal
1132 %<bitfield>e print the 2^N - bitfield in decimal
1133 %<bitfield>D print as a NEON D register
1134 %<bitfield>Q print as a NEON Q register
1135 %<bitfield>R print as a NEON D or Q register
1136 %<bitfield>Sn print byte scaled width limited by n
1137 %<bitfield>Tn print short scaled width limited by n
1138 %<bitfield>Un print long scaled width limited by n
1140 %<bitfield>'c print specified char iff bitfield is all ones
1141 %<bitfield>`c print specified char iff bitfield is all zeroes
1142 %<bitfield>?ab... select from array of values in big endian order. */
1144 static const struct opcode32 neon_opcodes
[] =
1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1148 0xf2b00840, 0xffb00850,
1149 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1151 0xf2b00000, 0xffb00810,
1152 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1154 /* Move data element to all lanes. */
1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1156 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1158 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1160 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1164 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1166 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1168 /* Half-precision conversions. */
1169 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1170 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1171 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1172 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1174 /* NEON fused multiply add instructions. */
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1176 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1177 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1178 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1180 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1182 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1184 /* Two registers, miscellaneous. */
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1186 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1188 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1190 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1191 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1192 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1194 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1195 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1196 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1197 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1198 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1199 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1200 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1201 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1202 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1203 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1204 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1205 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1206 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1208 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1210 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1212 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1214 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1216 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1218 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1220 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1222 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1224 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1226 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1228 0xf3b20300, 0xffb30fd0,
1229 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1231 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1232 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1233 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1235 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1237 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1239 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1241 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1243 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1245 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1247 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1249 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1251 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1253 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1255 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1257 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1259 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1261 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1263 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1264 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1265 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1267 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1269 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1271 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1272 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1273 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1275 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1276 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1277 0xf3bb0600, 0xffbf0e10,
1278 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1280 0xf3b70600, 0xffbf0e10,
1281 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1283 /* Three registers of the same length. */
1284 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1285 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1286 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1287 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1288 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1289 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1290 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1291 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1292 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1293 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1294 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1295 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1296 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1297 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1299 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1301 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1303 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1305 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1306 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1307 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1309 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1311 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1312 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1313 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1315 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1317 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1319 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1321 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1323 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1325 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1327 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1328 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1329 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1331 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1332 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1333 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1335 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1337 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1339 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1340 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1341 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1343 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1345 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1347 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1349 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1351 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1353 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1355 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1356 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1357 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1359 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1361 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1363 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1364 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1365 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1367 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1368 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1369 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1371 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1373 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1375 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1377 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1379 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1380 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1381 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1383 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1385 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1387 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1388 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1389 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1391 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1393 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1395 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1397 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1399 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1401 0xf2000b00, 0xff800f10,
1402 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1404 0xf2000b10, 0xff800f10,
1405 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1407 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1409 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1411 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1413 0xf3000b00, 0xff800f10,
1414 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1416 0xf2000000, 0xfe800f10,
1417 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1419 0xf2000010, 0xfe800f10,
1420 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1422 0xf2000100, 0xfe800f10,
1423 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1425 0xf2000200, 0xfe800f10,
1426 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1428 0xf2000210, 0xfe800f10,
1429 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1431 0xf2000300, 0xfe800f10,
1432 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1434 0xf2000310, 0xfe800f10,
1435 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1437 0xf2000400, 0xfe800f10,
1438 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1440 0xf2000410, 0xfe800f10,
1441 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1443 0xf2000500, 0xfe800f10,
1444 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1446 0xf2000510, 0xfe800f10,
1447 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1449 0xf2000600, 0xfe800f10,
1450 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1452 0xf2000610, 0xfe800f10,
1453 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1455 0xf2000700, 0xfe800f10,
1456 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1458 0xf2000710, 0xfe800f10,
1459 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1461 0xf2000910, 0xfe800f10,
1462 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1464 0xf2000a00, 0xfe800f10,
1465 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1467 0xf2000a10, 0xfe800f10,
1468 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1470 0xf3000b10, 0xff800f10,
1471 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1473 0xf3000c10, 0xff800f10,
1474 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1476 /* One register and an immediate value. */
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1478 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1480 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1482 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1484 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1486 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1488 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1490 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1492 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1494 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1496 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1498 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1500 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1502 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1504 /* Two registers and a shift amount. */
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1506 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1508 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1510 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1512 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1514 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1516 0xf2880950, 0xfeb80fd0,
1517 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1519 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1521 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1523 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1525 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1527 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1529 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1531 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1533 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1535 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1537 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1539 0xf2900950, 0xfeb00fd0,
1540 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1542 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1544 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1546 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1548 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1550 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1552 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1554 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1556 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1558 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1560 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1562 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1564 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1566 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1568 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1570 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1572 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1574 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1576 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1578 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1580 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1584 0xf2a00950, 0xfea00fd0,
1585 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1587 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1589 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1591 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1593 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1595 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1597 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1599 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1601 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1603 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1605 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1607 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1609 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1611 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1615 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1617 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1623 0xf2a00e10, 0xfea00e90,
1624 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1626 0xf2a00c10, 0xfea00e90,
1627 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1629 /* Three registers of different lengths. */
1630 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1631 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1633 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1635 0xf2800400, 0xff800f50,
1636 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1638 0xf2800600, 0xff800f50,
1639 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1641 0xf2800900, 0xff800f50,
1642 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1644 0xf2800b00, 0xff800f50,
1645 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1647 0xf2800d00, 0xff800f50,
1648 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1650 0xf3800400, 0xff800f50,
1651 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1653 0xf3800600, 0xff800f50,
1654 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1656 0xf2800000, 0xfe800f50,
1657 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1659 0xf2800100, 0xfe800f50,
1660 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1662 0xf2800200, 0xfe800f50,
1663 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1665 0xf2800300, 0xfe800f50,
1666 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1668 0xf2800500, 0xfe800f50,
1669 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1671 0xf2800700, 0xfe800f50,
1672 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1674 0xf2800800, 0xfe800f50,
1675 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1677 0xf2800a00, 0xfe800f50,
1678 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1680 0xf2800c00, 0xfe800f50,
1681 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1683 /* Two registers and a scalar. */
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1688 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1689 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1695 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1696 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1697 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1701 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1703 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1704 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1705 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1707 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1711 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1715 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1716 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1717 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1719 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1721 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1722 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1723 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1725 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1727 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1728 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1729 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1731 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1733 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1735 0xf2800240, 0xfe800f50,
1736 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1738 0xf2800640, 0xfe800f50,
1739 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf2800a40, 0xfe800f50,
1742 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1744 0xf2800e40, 0xff800f50,
1745 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1747 0xf2800f40, 0xff800f50,
1748 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1750 0xf3800e40, 0xff800f50,
1751 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1753 0xf3800f40, 0xff800f50,
1754 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1757 /* Element and structure load/store. */
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1761 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1763 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1767 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1769 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1771 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1775 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1777 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1779 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1781 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1783 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1785 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1787 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1789 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1791 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1793 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1795 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1797 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1800 /* mve opcode table. */
1802 /* print_insn_mve recognizes the following format control codes:
1806 %i print MVE predicate(s) for vpt and vpst
1807 %n print vector comparison code for predicated instruction
1808 %v print vector predicate for instruction in predicated
1810 %<bitfield>Q print as a MVE Q register
1811 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1813 %<bitfield>s print size for vector predicate & non VMOV instructions
1816 static const struct mopcode32 mve_opcodes
[] =
1820 {ARM_FEATURE_COPROC (FPU_MVE
),
1822 0xfe310f4d, 0xffbf1fff,
1826 /* Floating point VPT T1. */
1827 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1829 0xee310f00, 0xefb10f50,
1830 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1831 /* Floating point VPT T2. */
1832 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1834 0xee310f40, 0xefb10f50,
1835 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1837 /* Vector VPT T1. */
1838 {ARM_FEATURE_COPROC (FPU_MVE
),
1840 0xfe010f00, 0xff811f51,
1841 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1842 /* Vector VPT T2. */
1843 {ARM_FEATURE_COPROC (FPU_MVE
),
1845 0xfe010f01, 0xff811f51,
1846 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1847 /* Vector VPT T3. */
1848 {ARM_FEATURE_COPROC (FPU_MVE
),
1850 0xfe011f00, 0xff811f50,
1851 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1852 /* Vector VPT T4. */
1853 {ARM_FEATURE_COPROC (FPU_MVE
),
1855 0xfe010f40, 0xff811f70,
1856 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1857 /* Vector VPT T5. */
1858 {ARM_FEATURE_COPROC (FPU_MVE
),
1860 0xfe010f60, 0xff811f70,
1861 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
1862 /* Vector VPT T6. */
1863 {ARM_FEATURE_COPROC (FPU_MVE
),
1865 0xfe011f40, 0xff811f50,
1866 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
1868 /* Vector VCMP floating point T1. */
1869 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1871 0xee310f00, 0xeff1ef50,
1872 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
1874 /* Vector VCMP floating point T2. */
1875 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1877 0xee310f40, 0xeff1ef50,
1878 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
1880 /* Vector VCMP T1. */
1881 {ARM_FEATURE_COPROC (FPU_MVE
),
1883 0xfe010f00, 0xffc1ff51,
1884 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1885 /* Vector VCMP T2. */
1886 {ARM_FEATURE_COPROC (FPU_MVE
),
1888 0xfe010f01, 0xffc1ff51,
1889 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1890 /* Vector VCMP T3. */
1891 {ARM_FEATURE_COPROC (FPU_MVE
),
1893 0xfe011f00, 0xffc1ff50,
1894 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1895 /* Vector VCMP T4. */
1896 {ARM_FEATURE_COPROC (FPU_MVE
),
1898 0xfe010f40, 0xffc1ff70,
1899 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
1900 /* Vector VCMP T5. */
1901 {ARM_FEATURE_COPROC (FPU_MVE
),
1903 0xfe010f60, 0xffc1ff70,
1904 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
1905 /* Vector VCMP T6. */
1906 {ARM_FEATURE_COPROC (FPU_MVE
),
1908 0xfe011f40, 0xffc1ff50,
1909 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
1911 {ARM_FEATURE_CORE_LOW (0),
1913 0x00000000, 0x00000000, 0}
1916 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1917 ordered: they must be searched linearly from the top to obtain a correct
1920 /* print_insn_arm recognizes the following format control codes:
1924 %a print address for ldr/str instruction
1925 %s print address for ldr/str halfword/signextend instruction
1926 %S like %s but allow UNPREDICTABLE addressing
1927 %b print branch destination
1928 %c print condition code (always bits 28-31)
1929 %m print register mask for ldm/stm instruction
1930 %o print operand2 (immediate or register + shift)
1931 %p print 'p' iff bits 12-15 are 15
1932 %t print 't' iff bit 21 set and bit 24 clear
1933 %B print arm BLX(1) destination
1934 %C print the PSR sub type.
1935 %U print barrier type.
1936 %P print address for pli instruction.
1938 %<bitfield>r print as an ARM register
1939 %<bitfield>T print as an ARM register + 1
1940 %<bitfield>R as %r but r15 is UNPREDICTABLE
1941 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1942 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1943 %<bitfield>d print the bitfield in decimal
1944 %<bitfield>W print the bitfield plus one in decimal
1945 %<bitfield>x print the bitfield in hex
1946 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1948 %<bitfield>'c print specified char iff bitfield is all ones
1949 %<bitfield>`c print specified char iff bitfield is all zeroes
1950 %<bitfield>?ab... select from array of values in big endian order
1952 %e print arm SMI operand (bits 0..7,8..19).
1953 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1954 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1955 %R print the SPSR/CPSR or banked register of an MRS. */
1957 static const struct opcode32 arm_opcodes
[] =
1959 /* ARM instructions. */
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
1961 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
1963 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
1966 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1968 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1970 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
1972 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
1974 0x00800090, 0x0fa000f0,
1975 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
1977 0x00a00090, 0x0fa000f0,
1978 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1980 /* V8.2 RAS extension instructions. */
1981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
1982 0xe320f010, 0xffffffff, "esb"},
1984 /* V8 instructions. */
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1986 0x0320f005, 0x0fffffff, "sevl"},
1987 /* Defined in V8 but is in NOP space so available to all arch. */
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
1989 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
1991 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1993 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1995 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1997 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1999 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2000 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2001 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2002 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2003 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
2004 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2005 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2006 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2007 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
2008 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2009 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
2010 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2011 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2013 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2015 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2017 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2018 /* CRC32 instructions. */
2019 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2020 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2021 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2022 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2023 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2024 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2025 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2026 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2027 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2028 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2029 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2030 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
2032 /* Privileged Access Never extension instructions. */
2033 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
2034 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2036 /* Virtualization Extension instructions. */
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
2040 /* Integer Divide Extension instructions. */
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2042 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2044 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
2046 /* MP Extension instructions. */
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
2049 /* Speculation Barriers. */
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
2054 /* V7 instructions. */
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
2063 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
2065 /* ARM V6T2 instructions. */
2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2067 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2069 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2071 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2073 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2076 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2078 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2081 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
2082 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2083 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2085 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2087 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
2089 /* ARM Security extension instructions. */
2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
2091 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2093 /* ARM V6K instructions. */
2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2095 0xf57ff01f, 0xffffffff, "clrex"},
2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2097 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2099 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2101 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2103 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2105 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2107 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
2109 /* ARMv8.5-A instructions. */
2110 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
2112 /* ARM V6K NOP hints. */
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2114 0x0320f001, 0x0fffffff, "yield%c"},
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2116 0x0320f002, 0x0fffffff, "wfe%c"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2118 0x0320f003, 0x0fffffff, "wfi%c"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2120 0x0320f004, 0x0fffffff, "sev%c"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2122 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
2124 /* ARM V6 instructions. */
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2126 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2128 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2130 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2132 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2134 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2136 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2138 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2140 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2142 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2144 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2146 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2148 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2150 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2152 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2154 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2156 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2158 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2160 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2162 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2164 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2166 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2168 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2170 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2172 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2174 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2176 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2178 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2180 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2182 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2184 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2186 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2188 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2190 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2192 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2194 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2196 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2198 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2200 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2202 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2204 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2206 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2208 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2210 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2212 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2214 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2216 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2218 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2220 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2222 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2224 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2226 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2228 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2230 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2232 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2234 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2236 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2238 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2240 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2242 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2244 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2246 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2248 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2250 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2252 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2254 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2256 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2258 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2260 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2262 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2264 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2266 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2268 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2270 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2272 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2274 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2276 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2278 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2280 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2282 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2284 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2286 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2288 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2290 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2292 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2294 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2296 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2298 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2300 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2302 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2304 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2306 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2308 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2310 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2312 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2314 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2316 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2318 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2320 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2322 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2324 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2326 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2328 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2330 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2332 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2334 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2336 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2338 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2340 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2342 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2344 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2346 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2348 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2350 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2352 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2354 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2356 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2358 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2360 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2362 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2364 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2366 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2368 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2370 /* V5J instruction. */
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
2372 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2374 /* V5 Instructions. */
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2376 0xe1200070, 0xfff000f0,
2377 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2379 0xfa000000, 0xfe000000, "blx\t%B"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2381 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2383 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2385 /* V5E "El Segundo" Instructions. */
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2387 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2389 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2391 0xf450f000, 0xfc70f000, "pld\t%a"},
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2393 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2395 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2397 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2399 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2402 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2404 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2407 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2409 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2411 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2413 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2416 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2418 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2420 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2422 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2425 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2427 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2430 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2432 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2434 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2436 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2438 /* ARM Instructions. */
2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2440 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2443 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2445 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2447 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2449 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2451 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2453 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2456 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2458 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2460 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2462 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2465 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2467 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2469 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2471 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2474 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2476 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2478 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2481 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2483 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2485 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2488 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2490 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2492 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2495 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2497 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2499 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2502 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2504 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2506 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2509 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2511 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2513 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2516 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2518 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2520 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2523 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2525 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2527 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2529 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
2530 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
2532 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
2534 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2537 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2539 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2541 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2544 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2546 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2548 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2551 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2553 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2555 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2558 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2560 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2562 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2565 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2567 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2569 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2572 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2574 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2576 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2578 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2580 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2582 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2584 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2587 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2589 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2591 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2594 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2596 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2598 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2601 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2603 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2606 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2609 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2611 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2614 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2616 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2618 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2620 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2622 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2624 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2626 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2628 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2630 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2632 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2634 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2636 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2638 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2640 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2642 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2644 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2646 0x092d0000, 0x0fff0000, "push%c\t%m"},
2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2648 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2650 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2653 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2655 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2657 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2659 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2661 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2663 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2665 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2667 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2669 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2671 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2673 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2675 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2677 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2679 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2681 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2683 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2685 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2687 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2689 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2692 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2694 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
2698 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
2699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2700 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
2701 {ARM_FEATURE_CORE_LOW (0),
2702 0x00000000, 0x00000000, 0}
2705 /* print_insn_thumb16 recognizes the following format control codes:
2707 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2708 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2709 %<bitfield>I print bitfield as a signed decimal
2710 (top bit of range being the sign bit)
2711 %N print Thumb register mask (with LR)
2712 %O print Thumb register mask (with PC)
2713 %M print Thumb register mask
2714 %b print CZB's 6-bit unsigned branch destination
2715 %s print Thumb right-shift immediate (6..10; 0 == 32).
2716 %c print the condition code
2717 %C print the condition code, or "s" if not conditional
2718 %x print warning if conditional an not at end of IT block"
2719 %X print "\t; unpredictable <IT:code>" if conditional
2720 %I print IT instruction suffix and operands
2721 %W print Thumb Writeback indicator for LDMIA
2722 %<bitfield>r print bitfield as an ARM register
2723 %<bitfield>d print bitfield as a decimal
2724 %<bitfield>H print (bitfield * 2) as a decimal
2725 %<bitfield>W print (bitfield * 4) as a decimal
2726 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2727 %<bitfield>B print Thumb branch destination (signed displacement)
2728 %<bitfield>c print bitfield as a condition code
2729 %<bitnum>'c print specified char iff bit is one
2730 %<bitnum>?ab print a if bit is one else print b. */
2732 static const struct opcode16 thumb_opcodes
[] =
2734 /* Thumb instructions. */
2736 /* ARMv8-M Security Extensions instructions. */
2737 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
2738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
2740 /* ARM V8 instructions. */
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
2743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
2745 /* ARM V6K no-argument instructions. */
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2753 /* ARM V6T2 instructions. */
2754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2755 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2757 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2773 /* ARM V5 ISA extends Thumb. */
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
2775 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
2776 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
2778 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
2779 /* ARM V4T ISA (Thumb v1). */
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2781 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2812 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2814 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2816 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2818 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2821 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2823 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2825 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2828 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2830 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2834 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2843 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2846 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2849 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2851 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2853 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2855 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2858 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2860 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2863 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2865 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2868 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2870 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2883 /* The E800 .. FFFF range is unconditionally redirected to the
2884 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2885 are processed via that table. Thus, we can never encounter a
2886 bare "second half of BL/BLX(1)" instruction here. */
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
2888 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2891 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2892 We adopt the convention that hw1 is the high 16 bits of .value and
2893 .mask, hw2 the low 16 bits.
2895 print_insn_thumb32 recognizes the following format control codes:
2899 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2900 %M print a modified 12-bit immediate (same location)
2901 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2902 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2903 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
2904 %S print a possibly-shifted Rm
2906 %L print address for a ldrd/strd instruction
2907 %a print the address of a plain load/store
2908 %w print the width and signedness of a core load/store
2909 %m print register mask for ldm/stm
2910 %n print register mask for clrm
2912 %E print the lsb and width fields of a bfc/bfi instruction
2913 %F print the lsb and width fields of a sbfx/ubfx instruction
2914 %G print a fallback offset for Branch Future instructions
2915 %W print an offset for BF instruction
2916 %Y print an offset for BFL instruction
2917 %Z print an offset for BFCSEL instruction
2918 %Q print an offset for Low Overhead Loop instructions
2919 %P print an offset for Low Overhead Loop end instructions
2920 %b print a conditional branch offset
2921 %B print an unconditional branch offset
2922 %s print the shift field of an SSAT instruction
2923 %R print the rotation field of an SXT instruction
2924 %U print barrier type.
2925 %P print address for pli instruction.
2926 %c print the condition code
2927 %x print warning if conditional an not at end of IT block"
2928 %X print "\t; unpredictable <IT:code>" if conditional
2930 %<bitfield>d print bitfield in decimal
2931 %<bitfield>D print bitfield plus one in decimal
2932 %<bitfield>W print bitfield*4 in decimal
2933 %<bitfield>r print bitfield as an ARM register
2934 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2935 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
2936 %<bitfield>c print bitfield as a condition code
2938 %<bitfield>'c print specified char iff bitfield is all ones
2939 %<bitfield>`c print specified char iff bitfield is all zeroes
2940 %<bitfield>?ab... select from array of values in big endian order
2942 With one exception at the bottom (done because BL and BLX(1) need
2943 to come dead last), this table was machine-sorted first in
2944 decreasing order of number of bits set in the mask, then in
2945 increasing numeric order of mask, then in increasing numeric order
2946 of opcode. This order is not the clearest for a human reader, but
2947 is guaranteed never to catch a special-case bit pattern with a more
2948 general mask, which is important, because this instruction encoding
2949 makes heavy use of special-case bit patterns. */
2950 static const struct opcode32 thumb32_opcodes
[] =
2952 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2955 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
2956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2957 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
2958 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2959 0xf02fc001, 0xfffff001, "le\t%P"},
2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2961 0xf00fc001, 0xfffff001, "le\tlr, %P"},
2963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2964 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
2965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2966 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
2967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2968 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
2969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2970 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
2971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2972 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
2974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
2975 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
2977 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
2979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2980 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2982 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2984 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2986 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2988 /* ARM V8.2 RAS extension instructions. */
2989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
2990 0xf3af8010, 0xffffffff, "esb"},
2992 /* V8 instructions. */
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2994 0xf3af8005, 0xffffffff, "sevl%c.w"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2996 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2998 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3000 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3002 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3004 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3006 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3008 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3010 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3012 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3014 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3016 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3018 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3020 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3022 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3024 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
3026 /* CRC32 instructions. */
3027 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3028 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
3029 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3030 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
3031 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3032 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
3033 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3034 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
3035 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3036 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
3037 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3038 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
3040 /* Speculation Barriers. */
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
3045 /* V7 instructions. */
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3054 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3056 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3058 /* Virtualization Extension instructions. */
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3060 /* We skip ERET as that is SUBS pc, lr, #0. */
3062 /* MP Extension instructions. */
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
3065 /* Security extension instructions. */
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3068 /* ARMv8.5-A instructions. */
3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
3071 /* Instructions defined in the basic V6T2 set. */
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3078 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3082 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3084 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3086 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3088 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3090 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3092 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3094 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3096 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3098 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3100 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3102 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3104 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3106 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3108 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3110 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3112 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3114 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3116 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3118 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3120 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3122 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3124 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3126 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3128 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3129 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3130 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3132 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3134 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3136 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3138 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3140 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3142 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3144 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3146 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3148 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3150 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3152 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3154 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3156 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3158 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3160 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3162 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3164 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3166 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3168 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3170 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3172 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3174 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3176 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3178 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3180 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3182 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3184 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3186 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3188 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3190 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3192 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3194 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3196 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3198 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3200 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3202 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3204 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3206 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3208 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3210 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3212 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3214 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3216 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3218 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3220 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3222 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3224 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3226 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3228 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3230 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3232 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3234 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3236 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3237 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3238 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3240 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3242 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3244 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3246 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3248 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3250 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3252 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3254 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3256 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3258 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3260 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3262 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3264 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3266 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3268 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3270 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3272 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3274 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3276 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3278 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3280 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3282 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3284 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3286 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3288 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3290 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3292 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3294 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3296 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3298 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3300 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3302 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3304 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3305 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3306 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3308 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3310 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3312 0xf810f000, 0xff70f000, "pld%c\t%a"},
3313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3314 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3316 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3318 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3320 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3322 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3324 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3326 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3328 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3330 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3332 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3334 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3336 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3338 0xfb100000, 0xfff000c0,
3339 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3341 0xfbc00080, 0xfff000c0,
3342 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3344 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3346 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3348 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3350 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3352 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3353 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3354 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3356 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3357 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3358 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3360 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3362 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3364 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3366 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3368 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3370 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3372 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3374 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3376 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3378 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3380 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3382 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3384 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3386 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3388 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3390 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3392 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3394 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3396 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3398 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3400 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3402 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3404 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3406 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3408 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3410 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3412 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3414 0xe9400000, 0xff500000,
3415 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3417 0xe9500000, 0xff500000,
3418 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3420 0xe8600000, 0xff700000,
3421 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3423 0xe8700000, 0xff700000,
3424 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3426 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3428 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3430 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3432 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3434 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3436 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3438 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3440 /* These have been 32-bit since the invention of Thumb. */
3441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3442 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3444 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3448 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3449 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3452 static const char *const arm_conditional
[] =
3453 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3454 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3456 static const char *const arm_fp_const
[] =
3457 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3459 static const char *const arm_shift
[] =
3460 {"lsl", "lsr", "asr", "ror"};
3465 const char *description
;
3466 const char *reg_names
[16];
3470 static const arm_regname regnames
[] =
3472 { "reg-names-raw", N_("Select raw register names"),
3473 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3474 { "reg-names-gcc", N_("Select register names used by GCC"),
3475 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3476 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3477 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3478 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
3479 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
3480 { "reg-names-apcs", N_("Select register names used in the APCS"),
3481 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3482 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3483 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3484 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3485 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
3488 static const char *const iwmmxt_wwnames
[] =
3489 {"b", "h", "w", "d"};
3491 static const char *const iwmmxt_wwssnames
[] =
3492 {"b", "bus", "bc", "bss",
3493 "h", "hus", "hc", "hss",
3494 "w", "wus", "wc", "wss",
3495 "d", "dus", "dc", "dss"
3498 static const char *const iwmmxt_regnames
[] =
3499 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3500 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3503 static const char *const iwmmxt_cregnames
[] =
3504 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3505 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3508 static const char *const vec_condnames
[] =
3509 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
3512 static const char *const mve_predicatenames
[] =
3513 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
3514 "eee", "ee", "eet", "e", "ett", "et", "ete"
3517 /* Names for 2-bit size field for mve vector isntructions. */
3518 static const char *const mve_vec_sizename
[] =
3519 { "8", "16", "32", "64"};
3521 /* Indicates whether we are processing a then predicate,
3522 else predicate or none at all. */
3530 /* Information used to process a vpt block and subsequent instructions. */
3533 /* Are we in a vpt block. */
3534 bfd_boolean in_vpt_block
;
3536 /* Next predicate state if in vpt block. */
3537 enum vpt_pred_state next_pred_state
;
3539 /* Mask from vpt/vpst instruction. */
3540 long predicate_mask
;
3542 /* Instruction number in vpt block. */
3543 long current_insn_num
;
3545 /* Number of instructions in vpt block.. */
3549 static struct vpt_block vpt_block_state
=
3558 /* Default to GCC register name set. */
3559 static unsigned int regname_selected
= 1;
3561 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
3562 #define arm_regnames regnames[regname_selected].reg_names
3564 static bfd_boolean force_thumb
= FALSE
;
3566 /* Current IT instruction state. This contains the same state as the IT
3567 bits in the CPSR. */
3568 static unsigned int ifthen_state
;
3569 /* IT state for the next instruction. */
3570 static unsigned int ifthen_next_state
;
3571 /* The address of the insn for which the IT state is valid. */
3572 static bfd_vma ifthen_address
;
3573 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3574 /* Indicates that the current Conditional state is unconditional or outside
3576 #define COND_UNCOND 16
3580 /* Extract the predicate mask for a VPT or VPST instruction.
3581 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
3584 mve_extract_pred_mask (long given
)
3586 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
3589 /* Return the number of instructions in a MVE predicate block. */
3591 num_instructions_vpt_block (long given
)
3593 long mask
= mve_extract_pred_mask (given
);
3600 if ((mask
& 7) == 4)
3603 if ((mask
& 3) == 2)
3606 if ((mask
& 1) == 1)
3613 mark_outside_vpt_block (void)
3615 vpt_block_state
.in_vpt_block
= FALSE
;
3616 vpt_block_state
.next_pred_state
= PRED_NONE
;
3617 vpt_block_state
.predicate_mask
= 0;
3618 vpt_block_state
.current_insn_num
= 0;
3619 vpt_block_state
.num_pred_insn
= 0;
3623 mark_inside_vpt_block (long given
)
3625 vpt_block_state
.in_vpt_block
= TRUE
;
3626 vpt_block_state
.next_pred_state
= PRED_THEN
;
3627 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
3628 vpt_block_state
.current_insn_num
= 0;
3629 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
3630 assert (vpt_block_state
.num_pred_insn
>= 1);
3633 static enum vpt_pred_state
3634 invert_next_predicate_state (enum vpt_pred_state astate
)
3636 if (astate
== PRED_THEN
)
3638 else if (astate
== PRED_ELSE
)
3644 static enum vpt_pred_state
3645 update_next_predicate_state (void)
3647 long pred_mask
= vpt_block_state
.predicate_mask
;
3648 long mask_for_insn
= 0;
3650 switch (vpt_block_state
.current_insn_num
)
3668 if (pred_mask
& mask_for_insn
)
3669 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
3671 return vpt_block_state
.next_pred_state
;
3675 update_vpt_block_state (void)
3677 vpt_block_state
.current_insn_num
++;
3678 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
3680 /* No more instructions to process in vpt block. */
3681 mark_outside_vpt_block ();
3685 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
3688 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3689 Returns pointer to following character of the format string and
3690 fills in *VALUEP and *WIDTHP with the extracted value and number of
3691 bits extracted. WIDTHP can be NULL. */
3694 arm_decode_bitfield (const char *ptr
,
3696 unsigned long *valuep
,
3699 unsigned long value
= 0;
3707 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
3708 start
= start
* 10 + *ptr
- '0';
3710 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
3711 end
= end
* 10 + *ptr
- '0';
3717 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
3720 while (*ptr
++ == ',');
3728 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
3729 bfd_boolean print_shift
)
3731 func (stream
, "%s", arm_regnames
[given
& 0xf]);
3733 if ((given
& 0xff0) != 0)
3735 if ((given
& 0x10) == 0)
3737 int amount
= (given
& 0xf80) >> 7;
3738 int shift
= (given
& 0x60) >> 5;
3744 func (stream
, ", rrx");
3752 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
3754 func (stream
, ", #%d", amount
);
3756 else if ((given
& 0x80) == 0x80)
3757 func (stream
, "\t; <illegal shifter operand>");
3758 else if (print_shift
)
3759 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
3760 arm_regnames
[(given
& 0xf00) >> 8]);
3762 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
3766 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
3769 is_mve_okay_in_it (enum mve_instructions matched_insn
)
3775 is_mve_architecture (struct disassemble_info
*info
)
3777 struct arm_private_data
*private_data
= info
->private_data
;
3778 arm_feature_set allowed_arches
= private_data
->features
;
3780 arm_feature_set arm_ext_v8_1m_main
3781 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
3783 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
3784 && !ARM_CPU_IS_ANY (allowed_arches
))
3791 is_vpt_instruction (long given
)
3794 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
3795 if ((given
& 0x0040e000) == 0)
3798 /* VPT floating point T1 variant. */
3799 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
3800 /* VPT floating point T2 variant. */
3801 || ((given
& 0xefb10f50) == 0xee310f40)
3802 /* VPT vector T1 variant. */
3803 || ((given
& 0xff811f51) == 0xfe010f00)
3804 /* VPT vector T2 variant. */
3805 || ((given
& 0xff811f51) == 0xfe010f01
3806 && ((given
& 0x300000) != 0x300000))
3807 /* VPT vector T3 variant. */
3808 || ((given
& 0xff811f50) == 0xfe011f00)
3809 /* VPT vector T4 variant. */
3810 || ((given
& 0xff811f70) == 0xfe010f40)
3811 /* VPT vector T5 variant. */
3812 || ((given
& 0xff811f70) == 0xfe010f60)
3813 /* VPT vector T6 variant. */
3814 || ((given
& 0xff811f50) == 0xfe011f40)
3815 /* VPST vector T variant. */
3816 || ((given
& 0xffbf1fff) == 0xfe310f4d))
3822 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
3823 and ending bitfield = END. END must be greater than START. */
3825 static unsigned long
3826 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
3828 int bits
= end
- start
;
3833 return ((given
>> start
) & ((2ul << bits
) - 1));
3836 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
3837 START:END and START2:END2. END/END2 must be greater than
3840 static unsigned long
3841 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
3842 unsigned int end
, unsigned int start2
,
3845 int bits
= end
- start
;
3846 int bits2
= end2
- start2
;
3847 unsigned long value
= 0;
3853 value
= arm_decode_field (given
, start
, end
);
3856 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
3860 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
3861 This helps us decode instructions that change mnemonic depending on specific
3862 operand values/encodings. */
3865 is_mve_encoding_conflict (unsigned long given
,
3866 enum mve_instructions matched_insn
)
3868 switch (matched_insn
)
3871 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
3877 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
3879 if ((arm_decode_field (given
, 12, 12) == 0)
3880 && (arm_decode_field (given
, 0, 0) == 1))
3885 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
3887 if (arm_decode_field (given
, 0, 3) == 0xd)
3891 case MVE_VPT_VEC_T1
:
3892 case MVE_VPT_VEC_T2
:
3893 case MVE_VPT_VEC_T3
:
3894 case MVE_VPT_VEC_T4
:
3895 case MVE_VPT_VEC_T5
:
3896 case MVE_VPT_VEC_T6
:
3897 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
3899 if (arm_decode_field (given
, 20, 21) == 3)
3903 case MVE_VCMP_FP_T1
:
3904 if ((arm_decode_field (given
, 12, 12) == 0)
3905 && (arm_decode_field (given
, 0, 0) == 1))
3910 case MVE_VCMP_FP_T2
:
3911 if (arm_decode_field (given
, 0, 3) == 0xd)
3916 case MVE_VCMP_VEC_T1
:
3917 case MVE_VCMP_VEC_T2
:
3918 case MVE_VCMP_VEC_T3
:
3919 case MVE_VCMP_VEC_T4
:
3920 case MVE_VCMP_VEC_T5
:
3921 case MVE_VCMP_VEC_T6
:
3922 if (arm_decode_field (given
, 20, 21) == 3)
3933 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
3934 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
3935 this encoding is undefined. */
3938 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
3939 enum mve_undefined
*undefined_code
)
3941 *undefined_code
= UNDEF_NONE
;
3946 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
3947 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
3948 why this encoding is unpredictable. */
3951 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
3952 enum mve_unpredictable
*unpredictable_code
)
3954 *unpredictable_code
= UNPRED_NONE
;
3956 switch (matched_insn
)
3958 case MVE_VCMP_FP_T2
:
3960 if ((arm_decode_field (given
, 12, 12) == 0)
3961 && (arm_decode_field (given
, 5, 5) == 1))
3963 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
3969 case MVE_VPT_VEC_T4
:
3970 case MVE_VPT_VEC_T5
:
3971 case MVE_VPT_VEC_T6
:
3972 case MVE_VCMP_VEC_T4
:
3973 case MVE_VCMP_VEC_T5
:
3974 case MVE_VCMP_VEC_T6
:
3975 if (arm_decode_field (given
, 0, 3) == 0xd)
3977 *unpredictable_code
= UNPRED_R13
;
3989 print_mve_undefined (struct disassemble_info
*info
,
3990 enum mve_undefined undefined_code
)
3992 void *stream
= info
->stream
;
3993 fprintf_ftype func
= info
->fprintf_func
;
3995 func (stream
, "\t\tundefined instruction: ");
3997 switch (undefined_code
)
4006 print_mve_unpredictable (struct disassemble_info
*info
,
4007 enum mve_unpredictable unpredict_code
)
4009 void *stream
= info
->stream
;
4010 fprintf_ftype func
= info
->fprintf_func
;
4012 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
4014 switch (unpredict_code
)
4016 case UNPRED_IT_BLOCK
:
4017 func (stream
, "mve instruction in it block");
4020 case UNPRED_FCA_0_FCB_1
:
4021 func (stream
, "condition bits, fca = 0 and fcb = 1");
4025 func (stream
, "use of r13 (sp)");
4034 print_instruction_predicate (struct disassemble_info
*info
)
4036 void *stream
= info
->stream
;
4037 fprintf_ftype func
= info
->fprintf_func
;
4039 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
4041 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
4046 print_mve_size (struct disassemble_info
*info
,
4048 enum mve_instructions matched_insn
)
4050 void *stream
= info
->stream
;
4051 fprintf_ftype func
= info
->fprintf_func
;
4053 switch (matched_insn
)
4055 case MVE_VCMP_VEC_T1
:
4056 case MVE_VCMP_VEC_T2
:
4057 case MVE_VCMP_VEC_T3
:
4058 case MVE_VCMP_VEC_T4
:
4059 case MVE_VCMP_VEC_T5
:
4060 case MVE_VCMP_VEC_T6
:
4061 case MVE_VPT_VEC_T1
:
4062 case MVE_VPT_VEC_T2
:
4063 case MVE_VPT_VEC_T3
:
4064 case MVE_VPT_VEC_T4
:
4065 case MVE_VPT_VEC_T5
:
4066 case MVE_VPT_VEC_T6
:
4068 func (stream
, "%s", mve_vec_sizename
[size
]);
4070 func (stream
, "<undef size>");
4073 case MVE_VCMP_FP_T1
:
4074 case MVE_VCMP_FP_T2
:
4078 func (stream
, "32");
4080 func (stream
, "16");
4089 print_vec_condition (struct disassemble_info
*info
, long given
,
4090 enum mve_instructions matched_insn
)
4092 void *stream
= info
->stream
;
4093 fprintf_ftype func
= info
->fprintf_func
;
4096 switch (matched_insn
)
4099 case MVE_VCMP_FP_T1
:
4100 vec_cond
= (((given
& 0x1000) >> 10)
4101 | ((given
& 1) << 1)
4102 | ((given
& 0x0080) >> 7));
4103 func (stream
, "%s",vec_condnames
[vec_cond
]);
4107 case MVE_VCMP_FP_T2
:
4108 vec_cond
= (((given
& 0x1000) >> 10)
4109 | ((given
& 0x0020) >> 4)
4110 | ((given
& 0x0080) >> 7));
4111 func (stream
, "%s",vec_condnames
[vec_cond
]);
4114 case MVE_VPT_VEC_T1
:
4115 case MVE_VCMP_VEC_T1
:
4116 vec_cond
= (given
& 0x0080) >> 7;
4117 func (stream
, "%s",vec_condnames
[vec_cond
]);
4120 case MVE_VPT_VEC_T2
:
4121 case MVE_VCMP_VEC_T2
:
4122 vec_cond
= 2 | ((given
& 0x0080) >> 7);
4123 func (stream
, "%s",vec_condnames
[vec_cond
]);
4126 case MVE_VPT_VEC_T3
:
4127 case MVE_VCMP_VEC_T3
:
4128 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
4129 func (stream
, "%s",vec_condnames
[vec_cond
]);
4132 case MVE_VPT_VEC_T4
:
4133 case MVE_VCMP_VEC_T4
:
4134 vec_cond
= (given
& 0x0080) >> 7;
4135 func (stream
, "%s",vec_condnames
[vec_cond
]);
4138 case MVE_VPT_VEC_T5
:
4139 case MVE_VCMP_VEC_T5
:
4140 vec_cond
= 2 | ((given
& 0x0080) >> 7);
4141 func (stream
, "%s",vec_condnames
[vec_cond
]);
4144 case MVE_VPT_VEC_T6
:
4145 case MVE_VCMP_VEC_T6
:
4146 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
4147 func (stream
, "%s",vec_condnames
[vec_cond
]);
4162 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
4163 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
4164 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
4165 #define PRE_BIT_SET (given & (1 << P_BIT))
4168 /* Print one coprocessor instruction on INFO->STREAM.
4169 Return TRUE if the instuction matched, FALSE if this is not a
4170 recognised coprocessor instruction. */
4173 print_insn_coprocessor (bfd_vma pc
,
4174 struct disassemble_info
*info
,
4178 const struct sopcode32
*insn
;
4179 void *stream
= info
->stream
;
4180 fprintf_ftype func
= info
->fprintf_func
;
4182 unsigned long value
= 0;
4185 struct arm_private_data
*private_data
= info
->private_data
;
4186 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
4187 arm_feature_set arm_ext_v8_1m_main
=
4188 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
4190 allowed_arches
= private_data
->features
;
4192 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
4194 unsigned long u_reg
= 16;
4195 bfd_boolean is_unpredictable
= FALSE
;
4196 signed long value_in_comment
= 0;
4199 if (ARM_FEATURE_ZERO (insn
->arch
))
4200 switch (insn
->value
)
4202 case SENTINEL_IWMMXT_START
:
4203 if (info
->mach
!= bfd_mach_arm_XScale
4204 && info
->mach
!= bfd_mach_arm_iWMMXt
4205 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
4208 while ((! ARM_FEATURE_ZERO (insn
->arch
))
4209 && insn
->value
!= SENTINEL_IWMMXT_END
);
4212 case SENTINEL_IWMMXT_END
:
4215 case SENTINEL_GENERIC_START
:
4216 allowed_arches
= private_data
->features
;
4224 value
= insn
->value
;
4225 cp_num
= (given
>> 8) & 0xf;
4229 /* The high 4 bits are 0xe for Arm conditional instructions, and
4230 0xe for arm unconditional instructions. The rest of the
4231 encoding is the same. */
4233 value
|= 0xe0000000;
4241 /* Only match unconditional instuctions against unconditional
4243 if ((given
& 0xf0000000) == 0xf0000000)
4250 cond
= (given
>> 28) & 0xf;
4256 if ((insn
->isa
== T32
&& !thumb
)
4257 || (insn
->isa
== ARM
&& thumb
))
4260 if ((given
& mask
) != value
)
4263 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
4266 if (insn
->value
== 0xfe000010 /* mcr2 */
4267 || insn
->value
== 0xfe100010 /* mrc2 */
4268 || insn
->value
== 0xfc100000 /* ldc2 */
4269 || insn
->value
== 0xfc000000) /* stc2 */
4271 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
4272 is_unpredictable
= TRUE
;
4274 /* Armv8.1-M Mainline FP & MVE instructions. */
4275 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
4276 && !ARM_CPU_IS_ANY (allowed_arches
)
4277 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
4281 else if (insn
->value
== 0x0e000000 /* cdp */
4282 || insn
->value
== 0xfe000000 /* cdp2 */
4283 || insn
->value
== 0x0e000010 /* mcr */
4284 || insn
->value
== 0x0e100010 /* mrc */
4285 || insn
->value
== 0x0c100000 /* ldc */
4286 || insn
->value
== 0x0c000000) /* stc */
4288 /* Floating-point instructions. */
4289 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
4292 /* Armv8.1-M Mainline FP & MVE instructions. */
4293 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
4294 && !ARM_CPU_IS_ANY (allowed_arches
)
4295 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
4299 for (c
= insn
->assembler
; *c
; c
++)
4303 const char mod
= *++c
;
4307 func (stream
, "%%");
4313 int rn
= (given
>> 16) & 0xf;
4314 bfd_vma offset
= given
& 0xff;
4317 offset
= given
& 0x7f;
4319 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
4321 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
4323 /* Not unindexed. The offset is scaled. */
4325 /* vldr.16/vstr.16 will shift the address
4326 left by 1 bit only. */
4327 offset
= offset
* 2;
4329 offset
= offset
* 4;
4331 if (NEGATIVE_BIT_SET
)
4334 value_in_comment
= offset
;
4340 func (stream
, ", #%d]%s",
4342 WRITEBACK_BIT_SET
? "!" : "");
4343 else if (NEGATIVE_BIT_SET
)
4344 func (stream
, ", #-0]");
4352 if (WRITEBACK_BIT_SET
)
4355 func (stream
, ", #%d", (int) offset
);
4356 else if (NEGATIVE_BIT_SET
)
4357 func (stream
, ", #-0");
4361 func (stream
, ", {%s%d}",
4362 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
4364 value_in_comment
= offset
;
4367 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
4369 func (stream
, "\t; ");
4370 /* For unaligned PCs, apply off-by-alignment
4372 info
->print_address_func (offset
+ pc
4373 + info
->bytes_per_chunk
* 2
4382 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
4383 int offset
= (given
>> 1) & 0x3f;
4386 func (stream
, "{d%d}", regno
);
4387 else if (regno
+ offset
> 32)
4388 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
4390 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
4396 bfd_boolean single
= ((given
>> 8) & 1) == 0;
4397 char reg_prefix
= single
? 's' : 'd';
4398 int Dreg
= (given
>> 22) & 0x1;
4399 int Vdreg
= (given
>> 12) & 0xf;
4400 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
4401 : ((Dreg
<< 4) | Vdreg
);
4402 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
4403 int maxreg
= single
? 31 : 15;
4404 int topreg
= reg
+ num
- 1;
4407 func (stream
, "{VPR}");
4409 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
4410 else if (topreg
> maxreg
)
4411 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
4412 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
4414 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
4415 reg_prefix
, topreg
);
4420 if (cond
!= COND_UNCOND
)
4421 is_unpredictable
= TRUE
;
4425 if (cond
!= COND_UNCOND
&& cp_num
== 9)
4426 is_unpredictable
= TRUE
;
4428 func (stream
, "%s", arm_conditional
[cond
]);
4432 /* Print a Cirrus/DSP shift immediate. */
4433 /* Immediates are 7bit signed ints with bits 0..3 in
4434 bits 0..3 of opcode and bits 4..6 in bits 5..7
4439 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
4441 /* Is ``imm'' a negative number? */
4445 func (stream
, "%d", imm
);
4453 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
4458 func (stream
, "FPSCR");
4461 func (stream
, "FPSCR_nzcvqc");
4464 func (stream
, "VPR");
4467 func (stream
, "P0");
4470 func (stream
, "FPCXTNS");
4473 func (stream
, "FPCXTS");
4476 func (stream
, "<invalid reg %lu>", regno
);
4483 switch (given
& 0x00408000)
4500 switch (given
& 0x00080080)
4512 func (stream
, _("<illegal precision>"));
4518 switch (given
& 0x00408000)
4536 switch (given
& 0x60)
4552 case '0': case '1': case '2': case '3': case '4':
4553 case '5': case '6': case '7': case '8': case '9':
4557 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
4563 is_unpredictable
= TRUE
;
4568 /* Eat the 'u' character. */
4572 is_unpredictable
= TRUE
;
4575 func (stream
, "%s", arm_regnames
[value
]);
4578 if (given
& (1 << 6))
4582 func (stream
, "d%ld", value
);
4587 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
4589 func (stream
, "q%ld", value
>> 1);
4592 func (stream
, "%ld", value
);
4593 value_in_comment
= value
;
4597 /* Converts immediate 8 bit back to float value. */
4598 unsigned floatVal
= (value
& 0x80) << 24
4599 | (value
& 0x3F) << 19
4600 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
4602 /* Quarter float have a maximum value of 31.0.
4603 Get floating point value multiplied by 1e7.
4604 The maximum value stays in limit of a 32-bit int. */
4606 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
4607 (16 + (value
& 0xF));
4609 if (!(decVal
% 1000000))
4610 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
4611 floatVal
, value
& 0x80 ? '-' : ' ',
4613 decVal
% 10000000 / 1000000);
4614 else if (!(decVal
% 10000))
4615 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
4616 floatVal
, value
& 0x80 ? '-' : ' ',
4618 decVal
% 10000000 / 10000);
4620 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
4621 floatVal
, value
& 0x80 ? '-' : ' ',
4622 decVal
/ 10000000, decVal
% 10000000);
4627 int from
= (given
& (1 << 7)) ? 32 : 16;
4628 func (stream
, "%ld", from
- value
);
4634 func (stream
, "#%s", arm_fp_const
[value
& 7]);
4636 func (stream
, "f%ld", value
);
4641 func (stream
, "%s", iwmmxt_wwnames
[value
]);
4643 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
4647 func (stream
, "%s", iwmmxt_regnames
[value
]);
4650 func (stream
, "%s", iwmmxt_cregnames
[value
]);
4654 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
4661 func (stream
, "eq");
4665 func (stream
, "vs");
4669 func (stream
, "ge");
4673 func (stream
, "gt");
4677 func (stream
, "??");
4685 func (stream
, "%c", *c
);
4689 if (value
== ((1ul << width
) - 1))
4690 func (stream
, "%c", *c
);
4693 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
4705 int single
= *c
++ == 'y';
4710 case '4': /* Sm pair */
4711 case '0': /* Sm, Dm */
4712 regno
= given
& 0x0000000f;
4716 regno
+= (given
>> 5) & 1;
4719 regno
+= ((given
>> 5) & 1) << 4;
4722 case '1': /* Sd, Dd */
4723 regno
= (given
>> 12) & 0x0000000f;
4727 regno
+= (given
>> 22) & 1;
4730 regno
+= ((given
>> 22) & 1) << 4;
4733 case '2': /* Sn, Dn */
4734 regno
= (given
>> 16) & 0x0000000f;
4738 regno
+= (given
>> 7) & 1;
4741 regno
+= ((given
>> 7) & 1) << 4;
4744 case '3': /* List */
4746 regno
= (given
>> 12) & 0x0000000f;
4750 regno
+= (given
>> 22) & 1;
4753 regno
+= ((given
>> 22) & 1) << 4;
4760 func (stream
, "%c%d", single
? 's' : 'd', regno
);
4764 int count
= given
& 0xff;
4771 func (stream
, "-%c%d",
4779 func (stream
, ", %c%d", single
? 's' : 'd',
4785 switch (given
& 0x00400100)
4787 case 0x00000000: func (stream
, "b"); break;
4788 case 0x00400000: func (stream
, "h"); break;
4789 case 0x00000100: func (stream
, "w"); break;
4790 case 0x00400100: func (stream
, "d"); break;
4798 /* given (20, 23) | given (0, 3) */
4799 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
4800 func (stream
, "%d", (int) value
);
4805 /* This is like the 'A' operator, except that if
4806 the width field "M" is zero, then the offset is
4807 *not* multiplied by four. */
4809 int offset
= given
& 0xff;
4810 int multiplier
= (given
& 0x00000100) ? 4 : 1;
4812 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
4816 value_in_comment
= offset
* multiplier
;
4817 if (NEGATIVE_BIT_SET
)
4818 value_in_comment
= - value_in_comment
;
4824 func (stream
, ", #%s%d]%s",
4825 NEGATIVE_BIT_SET
? "-" : "",
4826 offset
* multiplier
,
4827 WRITEBACK_BIT_SET
? "!" : "");
4829 func (stream
, "], #%s%d",
4830 NEGATIVE_BIT_SET
? "-" : "",
4831 offset
* multiplier
);
4840 int imm4
= (given
>> 4) & 0xf;
4841 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
4842 int ubit
= ! NEGATIVE_BIT_SET
;
4843 const char *rm
= arm_regnames
[given
& 0xf];
4844 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
4850 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
4852 func (stream
, ", lsl #%d", imm4
);
4859 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
4861 func (stream
, ", lsl #%d", imm4
);
4863 if (puw_bits
== 5 || puw_bits
== 7)
4868 func (stream
, "INVALID");
4876 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
4877 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
4886 func (stream
, "%c", *c
);
4889 if (value_in_comment
> 32 || value_in_comment
< -16)
4890 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
4892 if (is_unpredictable
)
4893 func (stream
, UNPREDICTABLE_INSTRUCTION
);
4900 /* Decodes and prints ARM addressing modes. Returns the offset
4901 used in the address, if any, if it is worthwhile printing the
4902 offset as a hexadecimal value in a comment at the end of the
4903 line of disassembly. */
4906 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
4908 void *stream
= info
->stream
;
4909 fprintf_ftype func
= info
->fprintf_func
;
4912 if (((given
& 0x000f0000) == 0x000f0000)
4913 && ((given
& 0x02000000) == 0))
4915 offset
= given
& 0xfff;
4917 func (stream
, "[pc");
4921 /* Pre-indexed. Elide offset of positive zero when
4923 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
4924 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4926 if (NEGATIVE_BIT_SET
)
4931 /* Cope with the possibility of write-back
4932 being used. Probably a very dangerous thing
4933 for the programmer to do, but who are we to
4935 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
4937 else /* Post indexed. */
4939 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4941 /* Ie ignore the offset. */
4945 func (stream
, "\t; ");
4946 info
->print_address_func (offset
, info
);
4951 func (stream
, "[%s",
4952 arm_regnames
[(given
>> 16) & 0xf]);
4956 if ((given
& 0x02000000) == 0)
4958 /* Elide offset of positive zero when non-writeback. */
4959 offset
= given
& 0xfff;
4960 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
4961 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4965 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
4966 arm_decode_shift (given
, func
, stream
, TRUE
);
4969 func (stream
, "]%s",
4970 WRITEBACK_BIT_SET
? "!" : "");
4974 if ((given
& 0x02000000) == 0)
4976 /* Always show offset. */
4977 offset
= given
& 0xfff;
4978 func (stream
, "], #%s%d",
4979 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4983 func (stream
, "], %s",
4984 NEGATIVE_BIT_SET
? "-" : "");
4985 arm_decode_shift (given
, func
, stream
, TRUE
);
4988 if (NEGATIVE_BIT_SET
)
4992 return (signed long) offset
;
4995 /* Print one neon instruction on INFO->STREAM.
4996 Return TRUE if the instuction matched, FALSE if this is not a
4997 recognised neon instruction. */
5000 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
5002 const struct opcode32
*insn
;
5003 void *stream
= info
->stream
;
5004 fprintf_ftype func
= info
->fprintf_func
;
5008 if ((given
& 0xef000000) == 0xef000000)
5010 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
5011 unsigned long bit28
= given
& (1 << 28);
5013 given
&= 0x00ffffff;
5015 given
|= 0xf3000000;
5017 given
|= 0xf2000000;
5019 else if ((given
& 0xff000000) == 0xf9000000)
5020 given
^= 0xf9000000 ^ 0xf4000000;
5025 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
5027 if ((given
& insn
->mask
) == insn
->value
)
5029 signed long value_in_comment
= 0;
5030 bfd_boolean is_unpredictable
= FALSE
;
5033 for (c
= insn
->assembler
; *c
; c
++)
5040 func (stream
, "%%");
5044 if (thumb
&& ifthen_state
)
5045 is_unpredictable
= TRUE
;
5049 if (thumb
&& ifthen_state
)
5050 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
5055 static const unsigned char enc
[16] =
5057 0x4, 0x14, /* st4 0,1 */
5069 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
5070 int rn
= ((given
>> 16) & 0xf);
5071 int rm
= ((given
>> 0) & 0xf);
5072 int align
= ((given
>> 4) & 0x3);
5073 int type
= ((given
>> 8) & 0xf);
5074 int n
= enc
[type
] & 0xf;
5075 int stride
= (enc
[type
] >> 4) + 1;
5080 for (ix
= 0; ix
!= n
; ix
++)
5081 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
5083 func (stream
, "d%d", rd
);
5085 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
5086 func (stream
, "}, [%s", arm_regnames
[rn
]);
5088 func (stream
, " :%d", 32 << align
);
5093 func (stream
, ", %s", arm_regnames
[rm
]);
5099 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
5100 int rn
= ((given
>> 16) & 0xf);
5101 int rm
= ((given
>> 0) & 0xf);
5102 int idx_align
= ((given
>> 4) & 0xf);
5104 int size
= ((given
>> 10) & 0x3);
5105 int idx
= idx_align
>> (size
+ 1);
5106 int length
= ((given
>> 8) & 3) + 1;
5110 if (length
> 1 && size
> 0)
5111 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
5117 int amask
= (1 << size
) - 1;
5118 if ((idx_align
& (1 << size
)) != 0)
5122 if ((idx_align
& amask
) == amask
)
5124 else if ((idx_align
& amask
) != 0)
5131 if (size
== 2 && (idx_align
& 2) != 0)
5133 align
= (idx_align
& 1) ? 16 << size
: 0;
5137 if ((size
== 2 && (idx_align
& 3) != 0)
5138 || (idx_align
& 1) != 0)
5145 if ((idx_align
& 3) == 3)
5147 align
= (idx_align
& 3) * 64;
5150 align
= (idx_align
& 1) ? 32 << size
: 0;
5158 for (i
= 0; i
< length
; i
++)
5159 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
5160 rd
+ i
* stride
, idx
);
5161 func (stream
, "}, [%s", arm_regnames
[rn
]);
5163 func (stream
, " :%d", align
);
5168 func (stream
, ", %s", arm_regnames
[rm
]);
5174 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
5175 int rn
= ((given
>> 16) & 0xf);
5176 int rm
= ((given
>> 0) & 0xf);
5177 int align
= ((given
>> 4) & 0x1);
5178 int size
= ((given
>> 6) & 0x3);
5179 int type
= ((given
>> 8) & 0x3);
5181 int stride
= ((given
>> 5) & 0x1);
5184 if (stride
&& (n
== 1))
5191 for (ix
= 0; ix
!= n
; ix
++)
5192 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
5194 func (stream
, "d%d[]", rd
);
5196 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
5197 func (stream
, "}, [%s", arm_regnames
[rn
]);
5200 align
= (8 * (type
+ 1)) << size
;
5202 align
= (size
> 1) ? align
>> 1 : align
;
5203 if (type
== 2 || (type
== 0 && !size
))
5204 func (stream
, " :<bad align %d>", align
);
5206 func (stream
, " :%d", align
);
5212 func (stream
, ", %s", arm_regnames
[rm
]);
5218 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
5219 int size
= (given
>> 20) & 3;
5220 int reg
= raw_reg
& ((4 << size
) - 1);
5221 int ix
= raw_reg
>> size
>> 2;
5223 func (stream
, "d%d[%d]", reg
, ix
);
5228 /* Neon encoded constant for mov, mvn, vorr, vbic. */
5231 int cmode
= (given
>> 8) & 0xf;
5232 int op
= (given
>> 5) & 0x1;
5233 unsigned long value
= 0, hival
= 0;
5238 bits
|= ((given
>> 24) & 1) << 7;
5239 bits
|= ((given
>> 16) & 7) << 4;
5240 bits
|= ((given
>> 0) & 15) << 0;
5244 shift
= (cmode
>> 1) & 3;
5245 value
= (unsigned long) bits
<< (8 * shift
);
5248 else if (cmode
< 12)
5250 shift
= (cmode
>> 1) & 1;
5251 value
= (unsigned long) bits
<< (8 * shift
);
5254 else if (cmode
< 14)
5256 shift
= (cmode
& 1) + 1;
5257 value
= (unsigned long) bits
<< (8 * shift
);
5258 value
|= (1ul << (8 * shift
)) - 1;
5261 else if (cmode
== 14)
5265 /* Bit replication into bytes. */
5271 for (ix
= 7; ix
>= 0; ix
--)
5273 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
5275 value
= (value
<< 8) | mask
;
5277 hival
= (hival
<< 8) | mask
;
5283 /* Byte replication. */
5284 value
= (unsigned long) bits
;
5290 /* Floating point encoding. */
5293 value
= (unsigned long) (bits
& 0x7f) << 19;
5294 value
|= (unsigned long) (bits
& 0x80) << 24;
5295 tmp
= bits
& 0x40 ? 0x3c : 0x40;
5296 value
|= (unsigned long) tmp
<< 24;
5302 func (stream
, "<illegal constant %.8x:%x:%x>",
5310 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
5314 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
5320 unsigned char valbytes
[4];
5323 /* Do this a byte at a time so we don't have to
5324 worry about the host's endianness. */
5325 valbytes
[0] = value
& 0xff;
5326 valbytes
[1] = (value
>> 8) & 0xff;
5327 valbytes
[2] = (value
>> 16) & 0xff;
5328 valbytes
[3] = (value
>> 24) & 0xff;
5330 floatformat_to_double
5331 (& floatformat_ieee_single_little
, valbytes
,
5334 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
5338 func (stream
, "#%ld\t; 0x%.8lx",
5339 (long) (((value
& 0x80000000L
) != 0)
5340 ? value
| ~0xffffffffL
: value
),
5345 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
5356 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
5357 int num
= (given
>> 8) & 0x3;
5360 func (stream
, "{d%d}", regno
);
5361 else if (num
+ regno
>= 32)
5362 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
5364 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
5369 case '0': case '1': case '2': case '3': case '4':
5370 case '5': case '6': case '7': case '8': case '9':
5373 unsigned long value
;
5375 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
5380 func (stream
, "%s", arm_regnames
[value
]);
5383 func (stream
, "%ld", value
);
5384 value_in_comment
= value
;
5387 func (stream
, "%ld", (1ul << width
) - value
);
5393 /* Various width encodings. */
5395 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
5400 if (*c
>= '0' && *c
<= '9')
5402 else if (*c
>= 'a' && *c
<= 'f')
5403 limit
= *c
- 'a' + 10;
5409 if (value
< low
|| value
> high
)
5410 func (stream
, "<illegal width %d>", base
<< value
);
5412 func (stream
, "%d", base
<< value
);
5416 if (given
& (1 << 6))
5420 func (stream
, "d%ld", value
);
5425 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
5427 func (stream
, "q%ld", value
>> 1);
5433 func (stream
, "%c", *c
);
5437 if (value
== ((1ul << width
) - 1))
5438 func (stream
, "%c", *c
);
5441 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
5455 func (stream
, "%c", *c
);
5458 if (value_in_comment
> 32 || value_in_comment
< -16)
5459 func (stream
, "\t; 0x%lx", value_in_comment
);
5461 if (is_unpredictable
)
5462 func (stream
, UNPREDICTABLE_INSTRUCTION
);
5470 /* Print one mve instruction on INFO->STREAM.
5471 Return TRUE if the instuction matched, FALSE if this is not a
5472 recognised mve instruction. */
5475 print_insn_mve (struct disassemble_info
*info
, long given
)
5477 const struct mopcode32
*insn
;
5478 void *stream
= info
->stream
;
5479 fprintf_ftype func
= info
->fprintf_func
;
5481 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
5483 if (((given
& insn
->mask
) == insn
->value
)
5484 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
5486 signed long value_in_comment
= 0;
5487 bfd_boolean is_unpredictable
= FALSE
;
5488 bfd_boolean is_undefined
= FALSE
;
5490 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
5491 enum mve_undefined undefined_cond
= UNDEF_NONE
;
5493 /* Most vector mve instruction are illegal in a it block.
5494 There are a few exceptions; check for them. */
5495 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
5497 is_unpredictable
= TRUE
;
5498 unpredictable_cond
= UNPRED_IT_BLOCK
;
5500 else if (is_mve_unpredictable (given
, insn
->mve_op
,
5501 &unpredictable_cond
))
5502 is_unpredictable
= TRUE
;
5504 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
5505 is_undefined
= TRUE
;
5507 for (c
= insn
->assembler
; *c
; c
++)
5514 func (stream
, "%%");
5519 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
5524 long mve_mask
= mve_extract_pred_mask (given
);
5525 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
5530 print_vec_condition (info
, given
, insn
->mve_op
);
5534 print_instruction_predicate (info
);
5537 case '0': case '1': case '2': case '3': case '4':
5538 case '5': case '6': case '7': case '8': case '9':
5541 unsigned long value
;
5543 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
5549 is_unpredictable
= TRUE
;
5550 else if (value
== 15)
5551 func (stream
, "zr");
5553 func (stream
, "%s", arm_regnames
[value
]);
5556 print_mve_size (info
,
5562 func (stream
, "<illegal reg q%ld.5>", value
);
5564 func (stream
, "q%ld", value
);
5576 func (stream
, "%c", *c
);
5579 if (value_in_comment
> 32 || value_in_comment
< -16)
5580 func (stream
, "\t; 0x%lx", value_in_comment
);
5582 if (is_unpredictable
)
5583 print_mve_unpredictable (info
, unpredictable_cond
);
5586 print_mve_undefined (info
, undefined_cond
);
5588 if ((vpt_block_state
.in_vpt_block
== FALSE
)
5590 && (is_vpt_instruction (given
) == TRUE
))
5591 mark_inside_vpt_block (given
);
5592 else if (vpt_block_state
.in_vpt_block
== TRUE
)
5593 update_vpt_block_state ();
5602 /* Return the name of a v7A special register. */
5605 banked_regname (unsigned reg
)
5609 case 15: return "CPSR";
5610 case 32: return "R8_usr";
5611 case 33: return "R9_usr";
5612 case 34: return "R10_usr";
5613 case 35: return "R11_usr";
5614 case 36: return "R12_usr";
5615 case 37: return "SP_usr";
5616 case 38: return "LR_usr";
5617 case 40: return "R8_fiq";
5618 case 41: return "R9_fiq";
5619 case 42: return "R10_fiq";
5620 case 43: return "R11_fiq";
5621 case 44: return "R12_fiq";
5622 case 45: return "SP_fiq";
5623 case 46: return "LR_fiq";
5624 case 48: return "LR_irq";
5625 case 49: return "SP_irq";
5626 case 50: return "LR_svc";
5627 case 51: return "SP_svc";
5628 case 52: return "LR_abt";
5629 case 53: return "SP_abt";
5630 case 54: return "LR_und";
5631 case 55: return "SP_und";
5632 case 60: return "LR_mon";
5633 case 61: return "SP_mon";
5634 case 62: return "ELR_hyp";
5635 case 63: return "SP_hyp";
5636 case 79: return "SPSR";
5637 case 110: return "SPSR_fiq";
5638 case 112: return "SPSR_irq";
5639 case 114: return "SPSR_svc";
5640 case 116: return "SPSR_abt";
5641 case 118: return "SPSR_und";
5642 case 124: return "SPSR_mon";
5643 case 126: return "SPSR_hyp";
5644 default: return NULL
;
5648 /* Return the name of the DMB/DSB option. */
5650 data_barrier_option (unsigned option
)
5652 switch (option
& 0xf)
5654 case 0xf: return "sy";
5655 case 0xe: return "st";
5656 case 0xd: return "ld";
5657 case 0xb: return "ish";
5658 case 0xa: return "ishst";
5659 case 0x9: return "ishld";
5660 case 0x7: return "un";
5661 case 0x6: return "unst";
5662 case 0x5: return "nshld";
5663 case 0x3: return "osh";
5664 case 0x2: return "oshst";
5665 case 0x1: return "oshld";
5666 default: return NULL
;
5670 /* Print one ARM instruction from PC on INFO->STREAM. */
5673 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
5675 const struct opcode32
*insn
;
5676 void *stream
= info
->stream
;
5677 fprintf_ftype func
= info
->fprintf_func
;
5678 struct arm_private_data
*private_data
= info
->private_data
;
5680 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
5683 if (print_insn_neon (info
, given
, FALSE
))
5686 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
5688 if ((given
& insn
->mask
) != insn
->value
)
5691 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
5694 /* Special case: an instruction with all bits set in the condition field
5695 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
5696 or by the catchall at the end of the table. */
5697 if ((given
& 0xF0000000) != 0xF0000000
5698 || (insn
->mask
& 0xF0000000) == 0xF0000000
5699 || (insn
->mask
== 0 && insn
->value
== 0))
5701 unsigned long u_reg
= 16;
5702 unsigned long U_reg
= 16;
5703 bfd_boolean is_unpredictable
= FALSE
;
5704 signed long value_in_comment
= 0;
5707 for (c
= insn
->assembler
; *c
; c
++)
5711 bfd_boolean allow_unpredictable
= FALSE
;
5716 func (stream
, "%%");
5720 value_in_comment
= print_arm_address (pc
, info
, given
);
5724 /* Set P address bit and use normal address
5725 printing routine. */
5726 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
5730 allow_unpredictable
= TRUE
;
5733 if ((given
& 0x004f0000) == 0x004f0000)
5735 /* PC relative with immediate offset. */
5736 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
5740 /* Elide positive zero offset. */
5741 if (offset
|| NEGATIVE_BIT_SET
)
5742 func (stream
, "[pc, #%s%d]\t; ",
5743 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
5745 func (stream
, "[pc]\t; ");
5746 if (NEGATIVE_BIT_SET
)
5748 info
->print_address_func (offset
+ pc
+ 8, info
);
5752 /* Always show the offset. */
5753 func (stream
, "[pc], #%s%d",
5754 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
5755 if (! allow_unpredictable
)
5756 is_unpredictable
= TRUE
;
5761 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
5763 func (stream
, "[%s",
5764 arm_regnames
[(given
>> 16) & 0xf]);
5768 if (IMMEDIATE_BIT_SET
)
5770 /* Elide offset for non-writeback
5772 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
5774 func (stream
, ", #%s%d",
5775 NEGATIVE_BIT_SET
? "-" : "", offset
);
5777 if (NEGATIVE_BIT_SET
)
5780 value_in_comment
= offset
;
5784 /* Register Offset or Register Pre-Indexed. */
5785 func (stream
, ", %s%s",
5786 NEGATIVE_BIT_SET
? "-" : "",
5787 arm_regnames
[given
& 0xf]);
5789 /* Writing back to the register that is the source/
5790 destination of the load/store is unpredictable. */
5791 if (! allow_unpredictable
5792 && WRITEBACK_BIT_SET
5793 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
5794 is_unpredictable
= TRUE
;
5797 func (stream
, "]%s",
5798 WRITEBACK_BIT_SET
? "!" : "");
5802 if (IMMEDIATE_BIT_SET
)
5804 /* Immediate Post-indexed. */
5805 /* PR 10924: Offset must be printed, even if it is zero. */
5806 func (stream
, "], #%s%d",
5807 NEGATIVE_BIT_SET
? "-" : "", offset
);
5808 if (NEGATIVE_BIT_SET
)
5810 value_in_comment
= offset
;
5814 /* Register Post-indexed. */
5815 func (stream
, "], %s%s",
5816 NEGATIVE_BIT_SET
? "-" : "",
5817 arm_regnames
[given
& 0xf]);
5819 /* Writing back to the register that is the source/
5820 destination of the load/store is unpredictable. */
5821 if (! allow_unpredictable
5822 && (given
& 0xf) == ((given
>> 12) & 0xf))
5823 is_unpredictable
= TRUE
;
5826 if (! allow_unpredictable
)
5828 /* Writeback is automatically implied by post- addressing.
5829 Setting the W bit is unnecessary and ARM specify it as
5830 being unpredictable. */
5831 if (WRITEBACK_BIT_SET
5832 /* Specifying the PC register as the post-indexed
5833 registers is also unpredictable. */
5834 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
5835 is_unpredictable
= TRUE
;
5843 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
5844 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
5849 if (((given
>> 28) & 0xf) != 0xe)
5851 arm_conditional
[(given
>> 28) & 0xf]);
5860 for (reg
= 0; reg
< 16; reg
++)
5861 if ((given
& (1 << reg
)) != 0)
5864 func (stream
, ", ");
5866 func (stream
, "%s", arm_regnames
[reg
]);
5870 is_unpredictable
= TRUE
;
5875 arm_decode_shift (given
, func
, stream
, FALSE
);
5879 if ((given
& 0x02000000) != 0)
5881 unsigned int rotate
= (given
& 0xf00) >> 7;
5882 unsigned int immed
= (given
& 0xff);
5885 a
= (((immed
<< (32 - rotate
))
5886 | (immed
>> rotate
)) & 0xffffffff);
5887 /* If there is another encoding with smaller rotate,
5888 the rotate should be specified directly. */
5889 for (i
= 0; i
< 32; i
+= 2)
5890 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
5894 func (stream
, "#%d, %d", immed
, rotate
);
5896 func (stream
, "#%d", a
);
5897 value_in_comment
= a
;
5900 arm_decode_shift (given
, func
, stream
, TRUE
);
5904 if ((given
& 0x0000f000) == 0x0000f000)
5906 arm_feature_set arm_ext_v6
=
5907 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
5909 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
5910 mechanism for setting PSR flag bits. They are
5911 obsolete in V6 onwards. */
5912 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
5916 is_unpredictable
= TRUE
;
5921 if ((given
& 0x01200000) == 0x00200000)
5927 int offset
= given
& 0xff;
5929 value_in_comment
= offset
* 4;
5930 if (NEGATIVE_BIT_SET
)
5931 value_in_comment
= - value_in_comment
;
5933 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
5938 func (stream
, ", #%d]%s",
5939 (int) value_in_comment
,
5940 WRITEBACK_BIT_SET
? "!" : "");
5948 if (WRITEBACK_BIT_SET
)
5951 func (stream
, ", #%d", (int) value_in_comment
);
5955 func (stream
, ", {%d}", (int) offset
);
5956 value_in_comment
= offset
;
5963 /* Print ARM V5 BLX(1) address: pc+25 bits. */
5968 if (! NEGATIVE_BIT_SET
)
5969 /* Is signed, hi bits should be ones. */
5970 offset
= (-1) ^ 0x00ffffff;
5972 /* Offset is (SignExtend(offset field)<<2). */
5973 offset
+= given
& 0x00ffffff;
5975 address
= offset
+ pc
+ 8;
5977 if (given
& 0x01000000)
5978 /* H bit allows addressing to 2-byte boundaries. */
5981 info
->print_address_func (address
, info
);
5986 if ((given
& 0x02000200) == 0x200)
5989 unsigned sysm
= (given
& 0x004f0000) >> 16;
5991 sysm
|= (given
& 0x300) >> 4;
5992 name
= banked_regname (sysm
);
5995 func (stream
, "%s", name
);
5997 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
6001 func (stream
, "%cPSR_",
6002 (given
& 0x00400000) ? 'S' : 'C');
6003 if (given
& 0x80000)
6005 if (given
& 0x40000)
6007 if (given
& 0x20000)
6009 if (given
& 0x10000)
6015 if ((given
& 0xf0) == 0x60)
6017 switch (given
& 0xf)
6019 case 0xf: func (stream
, "sy"); break;
6021 func (stream
, "#%d", (int) given
& 0xf);
6027 const char * opt
= data_barrier_option (given
& 0xf);
6029 func (stream
, "%s", opt
);
6031 func (stream
, "#%d", (int) given
& 0xf);
6035 case '0': case '1': case '2': case '3': case '4':
6036 case '5': case '6': case '7': case '8': case '9':
6039 unsigned long value
;
6041 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
6047 is_unpredictable
= TRUE
;
6051 /* We want register + 1 when decoding T. */
6057 /* Eat the 'u' character. */
6061 is_unpredictable
= TRUE
;
6066 /* Eat the 'U' character. */
6070 is_unpredictable
= TRUE
;
6073 func (stream
, "%s", arm_regnames
[value
]);
6076 func (stream
, "%ld", value
);
6077 value_in_comment
= value
;
6080 func (stream
, "%ld", value
* 8);
6081 value_in_comment
= value
* 8;
6084 func (stream
, "%ld", value
+ 1);
6085 value_in_comment
= value
+ 1;
6088 func (stream
, "0x%08lx", value
);
6090 /* Some SWI instructions have special
6092 if ((given
& 0x0fffffff) == 0x0FF00000)
6093 func (stream
, "\t; IMB");
6094 else if ((given
& 0x0fffffff) == 0x0FF00001)
6095 func (stream
, "\t; IMBRange");
6098 func (stream
, "%01lx", value
& 0xf);
6099 value_in_comment
= value
;
6104 func (stream
, "%c", *c
);
6108 if (value
== ((1ul << width
) - 1))
6109 func (stream
, "%c", *c
);
6112 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
6125 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
6126 func (stream
, "%d", imm
);
6127 value_in_comment
= imm
;
6132 /* LSB and WIDTH fields of BFI or BFC. The machine-
6133 language instruction encodes LSB and MSB. */
6135 long msb
= (given
& 0x001f0000) >> 16;
6136 long lsb
= (given
& 0x00000f80) >> 7;
6137 long w
= msb
- lsb
+ 1;
6140 func (stream
, "#%lu, #%lu", lsb
, w
);
6142 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
6147 /* Get the PSR/banked register name. */
6150 unsigned sysm
= (given
& 0x004f0000) >> 16;
6152 sysm
|= (given
& 0x300) >> 4;
6153 name
= banked_regname (sysm
);
6156 func (stream
, "%s", name
);
6158 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
6163 /* 16-bit unsigned immediate from a MOVT or MOVW
6164 instruction, encoded in bits 0:11 and 15:19. */
6166 long hi
= (given
& 0x000f0000) >> 4;
6167 long lo
= (given
& 0x00000fff);
6168 long imm16
= hi
| lo
;
6170 func (stream
, "#%lu", imm16
);
6171 value_in_comment
= imm16
;
6180 func (stream
, "%c", *c
);
6183 if (value_in_comment
> 32 || value_in_comment
< -16)
6184 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
6186 if (is_unpredictable
)
6187 func (stream
, UNPREDICTABLE_INSTRUCTION
);
6192 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
6196 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
6199 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
6201 const struct opcode16
*insn
;
6202 void *stream
= info
->stream
;
6203 fprintf_ftype func
= info
->fprintf_func
;
6205 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
6206 if ((given
& insn
->mask
) == insn
->value
)
6208 signed long value_in_comment
= 0;
6209 const char *c
= insn
->assembler
;
6218 func (stream
, "%c", *c
);
6225 func (stream
, "%%");
6230 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
6235 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
6244 ifthen_next_state
= given
& 0xff;
6245 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
6246 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
6247 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
6252 if (ifthen_next_state
)
6253 func (stream
, "\t; unpredictable branch in IT block\n");
6258 func (stream
, "\t; unpredictable <IT:%s>",
6259 arm_conditional
[IFTHEN_COND
]);
6266 reg
= (given
>> 3) & 0x7;
6267 if (given
& (1 << 6))
6270 func (stream
, "%s", arm_regnames
[reg
]);
6279 if (given
& (1 << 7))
6282 func (stream
, "%s", arm_regnames
[reg
]);
6287 if (given
& (1 << 8))
6291 if (*c
== 'O' && (given
& (1 << 8)))
6301 /* It would be nice if we could spot
6302 ranges, and generate the rS-rE format: */
6303 for (reg
= 0; (reg
< 8); reg
++)
6304 if ((given
& (1 << reg
)) != 0)
6307 func (stream
, ", ");
6309 func (stream
, "%s", arm_regnames
[reg
]);
6315 func (stream
, ", ");
6317 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
6323 func (stream
, ", ");
6324 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
6332 /* Print writeback indicator for a LDMIA. We are doing a
6333 writeback if the base register is not in the register
6335 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
6340 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
6342 bfd_vma address
= (pc
+ 4
6343 + ((given
& 0x00f8) >> 2)
6344 + ((given
& 0x0200) >> 3));
6345 info
->print_address_func (address
, info
);
6350 /* Right shift immediate -- bits 6..10; 1-31 print
6351 as themselves, 0 prints as 32. */
6353 long imm
= (given
& 0x07c0) >> 6;
6356 func (stream
, "#%ld", imm
);
6360 case '0': case '1': case '2': case '3': case '4':
6361 case '5': case '6': case '7': case '8': case '9':
6363 int bitstart
= *c
++ - '0';
6366 while (*c
>= '0' && *c
<= '9')
6367 bitstart
= (bitstart
* 10) + *c
++ - '0';
6376 while (*c
>= '0' && *c
<= '9')
6377 bitend
= (bitend
* 10) + *c
++ - '0';
6380 reg
= given
>> bitstart
;
6381 reg
&= (2 << (bitend
- bitstart
)) - 1;
6386 func (stream
, "%s", arm_regnames
[reg
]);
6390 func (stream
, "%ld", (long) reg
);
6391 value_in_comment
= reg
;
6395 func (stream
, "%ld", (long) (reg
<< 1));
6396 value_in_comment
= reg
<< 1;
6400 func (stream
, "%ld", (long) (reg
<< 2));
6401 value_in_comment
= reg
<< 2;
6405 /* PC-relative address -- the bottom two
6406 bits of the address are dropped
6407 before the calculation. */
6408 info
->print_address_func
6409 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
6410 value_in_comment
= 0;
6414 func (stream
, "0x%04lx", (long) reg
);
6418 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
6419 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
6420 value_in_comment
= 0;
6424 func (stream
, "%s", arm_conditional
[reg
]);
6435 if ((given
& (1 << bitstart
)) != 0)
6436 func (stream
, "%c", *c
);
6441 if ((given
& (1 << bitstart
)) != 0)
6442 func (stream
, "%c", *c
++);
6444 func (stream
, "%c", *++c
);
6458 if (value_in_comment
> 32 || value_in_comment
< -16)
6459 func (stream
, "\t; 0x%lx", value_in_comment
);
6464 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
6468 /* Return the name of an V7M special register. */
6471 psr_name (int regno
)
6475 case 0x0: return "APSR";
6476 case 0x1: return "IAPSR";
6477 case 0x2: return "EAPSR";
6478 case 0x3: return "PSR";
6479 case 0x5: return "IPSR";
6480 case 0x6: return "EPSR";
6481 case 0x7: return "IEPSR";
6482 case 0x8: return "MSP";
6483 case 0x9: return "PSP";
6484 case 0xa: return "MSPLIM";
6485 case 0xb: return "PSPLIM";
6486 case 0x10: return "PRIMASK";
6487 case 0x11: return "BASEPRI";
6488 case 0x12: return "BASEPRI_MAX";
6489 case 0x13: return "FAULTMASK";
6490 case 0x14: return "CONTROL";
6491 case 0x88: return "MSP_NS";
6492 case 0x89: return "PSP_NS";
6493 case 0x8a: return "MSPLIM_NS";
6494 case 0x8b: return "PSPLIM_NS";
6495 case 0x90: return "PRIMASK_NS";
6496 case 0x91: return "BASEPRI_NS";
6497 case 0x93: return "FAULTMASK_NS";
6498 case 0x94: return "CONTROL_NS";
6499 case 0x98: return "SP_NS";
6500 default: return "<unknown>";
6504 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
6507 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
6509 const struct opcode32
*insn
;
6510 void *stream
= info
->stream
;
6511 fprintf_ftype func
= info
->fprintf_func
;
6512 bfd_boolean is_mve
= is_mve_architecture (info
);
6514 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
6517 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
6520 if (is_mve
&& print_insn_mve (info
, given
))
6523 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
6524 if ((given
& insn
->mask
) == insn
->value
)
6526 bfd_boolean is_clrm
= FALSE
;
6527 bfd_boolean is_unpredictable
= FALSE
;
6528 signed long value_in_comment
= 0;
6529 const char *c
= insn
->assembler
;
6535 func (stream
, "%c", *c
);
6542 func (stream
, "%%");
6547 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
6551 if (ifthen_next_state
)
6552 func (stream
, "\t; unpredictable branch in IT block\n");
6557 func (stream
, "\t; unpredictable <IT:%s>",
6558 arm_conditional
[IFTHEN_COND
]);
6563 unsigned int imm12
= 0;
6565 imm12
|= (given
& 0x000000ffu
);
6566 imm12
|= (given
& 0x00007000u
) >> 4;
6567 imm12
|= (given
& 0x04000000u
) >> 15;
6568 func (stream
, "#%u", imm12
);
6569 value_in_comment
= imm12
;
6575 unsigned int bits
= 0, imm
, imm8
, mod
;
6577 bits
|= (given
& 0x000000ffu
);
6578 bits
|= (given
& 0x00007000u
) >> 4;
6579 bits
|= (given
& 0x04000000u
) >> 15;
6580 imm8
= (bits
& 0x0ff);
6581 mod
= (bits
& 0xf00) >> 8;
6584 case 0: imm
= imm8
; break;
6585 case 1: imm
= ((imm8
<< 16) | imm8
); break;
6586 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
6587 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
6589 mod
= (bits
& 0xf80) >> 7;
6590 imm8
= (bits
& 0x07f) | 0x80;
6591 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
6593 func (stream
, "#%u", imm
);
6594 value_in_comment
= imm
;
6600 unsigned int imm
= 0;
6602 imm
|= (given
& 0x000000ffu
);
6603 imm
|= (given
& 0x00007000u
) >> 4;
6604 imm
|= (given
& 0x04000000u
) >> 15;
6605 imm
|= (given
& 0x000f0000u
) >> 4;
6606 func (stream
, "#%u", imm
);
6607 value_in_comment
= imm
;
6613 unsigned int imm
= 0;
6615 imm
|= (given
& 0x000f0000u
) >> 16;
6616 imm
|= (given
& 0x00000ff0u
) >> 0;
6617 imm
|= (given
& 0x0000000fu
) << 12;
6618 func (stream
, "#%u", imm
);
6619 value_in_comment
= imm
;
6625 unsigned int imm
= 0;
6627 imm
|= (given
& 0x000f0000u
) >> 4;
6628 imm
|= (given
& 0x00000fffu
) >> 0;
6629 func (stream
, "#%u", imm
);
6630 value_in_comment
= imm
;
6636 unsigned int imm
= 0;
6638 imm
|= (given
& 0x00000fffu
);
6639 imm
|= (given
& 0x000f0000u
) >> 4;
6640 func (stream
, "#%u", imm
);
6641 value_in_comment
= imm
;
6647 unsigned int reg
= (given
& 0x0000000fu
);
6648 unsigned int stp
= (given
& 0x00000030u
) >> 4;
6649 unsigned int imm
= 0;
6650 imm
|= (given
& 0x000000c0u
) >> 6;
6651 imm
|= (given
& 0x00007000u
) >> 10;
6653 func (stream
, "%s", arm_regnames
[reg
]);
6658 func (stream
, ", lsl #%u", imm
);
6664 func (stream
, ", lsr #%u", imm
);
6670 func (stream
, ", asr #%u", imm
);
6675 func (stream
, ", rrx");
6677 func (stream
, ", ror #%u", imm
);
6684 unsigned int Rn
= (given
& 0x000f0000) >> 16;
6685 unsigned int U
= ! NEGATIVE_BIT_SET
;
6686 unsigned int op
= (given
& 0x00000f00) >> 8;
6687 unsigned int i12
= (given
& 0x00000fff);
6688 unsigned int i8
= (given
& 0x000000ff);
6689 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
6692 func (stream
, "[%s", arm_regnames
[Rn
]);
6693 if (U
) /* 12-bit positive immediate offset. */
6697 value_in_comment
= offset
;
6699 else if (Rn
== 15) /* 12-bit negative immediate offset. */
6700 offset
= - (int) i12
;
6701 else if (op
== 0x0) /* Shifted register offset. */
6703 unsigned int Rm
= (i8
& 0x0f);
6704 unsigned int sh
= (i8
& 0x30) >> 4;
6706 func (stream
, ", %s", arm_regnames
[Rm
]);
6708 func (stream
, ", lsl #%u", sh
);
6714 case 0xE: /* 8-bit positive immediate offset. */
6718 case 0xC: /* 8-bit negative immediate offset. */
6722 case 0xF: /* 8-bit + preindex with wb. */
6727 case 0xD: /* 8-bit - preindex with wb. */
6732 case 0xB: /* 8-bit + postindex. */
6737 case 0x9: /* 8-bit - postindex. */
6743 func (stream
, ", <undefined>]");
6748 func (stream
, "], #%d", (int) offset
);
6752 func (stream
, ", #%d", (int) offset
);
6753 func (stream
, writeback
? "]!" : "]");
6758 func (stream
, "\t; ");
6759 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
6767 unsigned int U
= ! NEGATIVE_BIT_SET
;
6768 unsigned int W
= WRITEBACK_BIT_SET
;
6769 unsigned int Rn
= (given
& 0x000f0000) >> 16;
6770 unsigned int off
= (given
& 0x000000ff);
6772 func (stream
, "[%s", arm_regnames
[Rn
]);
6778 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
6779 value_in_comment
= off
* 4 * (U
? 1 : -1);
6787 func (stream
, "], ");
6790 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
6791 value_in_comment
= off
* 4 * (U
? 1 : -1);
6795 func (stream
, "{%u}", off
);
6796 value_in_comment
= off
;
6804 unsigned int Sbit
= (given
& 0x01000000) >> 24;
6805 unsigned int type
= (given
& 0x00600000) >> 21;
6809 case 0: func (stream
, Sbit
? "sb" : "b"); break;
6810 case 1: func (stream
, Sbit
? "sh" : "h"); break;
6813 func (stream
, "??");
6816 func (stream
, "??");
6831 for (reg
= 0; reg
< 16; reg
++)
6832 if ((given
& (1 << reg
)) != 0)
6835 func (stream
, ", ");
6837 if (is_clrm
&& reg
== 13)
6838 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
6839 else if (is_clrm
&& reg
== 15)
6840 func (stream
, "%s", "APSR");
6842 func (stream
, "%s", arm_regnames
[reg
]);
6850 unsigned int msb
= (given
& 0x0000001f);
6851 unsigned int lsb
= 0;
6853 lsb
|= (given
& 0x000000c0u
) >> 6;
6854 lsb
|= (given
& 0x00007000u
) >> 10;
6855 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
6861 unsigned int width
= (given
& 0x0000001f) + 1;
6862 unsigned int lsb
= 0;
6864 lsb
|= (given
& 0x000000c0u
) >> 6;
6865 lsb
|= (given
& 0x00007000u
) >> 10;
6866 func (stream
, "#%u, #%u", lsb
, width
);
6872 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
6873 func (stream
, "%x", boff
);
6879 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
6880 unsigned int immB
= (given
& 0x000007feu
) >> 1;
6881 unsigned int immC
= (given
& 0x00000800u
) >> 11;
6884 offset
|= immA
<< 12;
6885 offset
|= immB
<< 2;
6886 offset
|= immC
<< 1;
6888 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
6890 info
->print_address_func (pc
+ 4 + offset
, info
);
6896 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
6897 unsigned int immB
= (given
& 0x000007feu
) >> 1;
6898 unsigned int immC
= (given
& 0x00000800u
) >> 11;
6901 offset
|= immA
<< 12;
6902 offset
|= immB
<< 2;
6903 offset
|= immC
<< 1;
6905 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
6907 info
->print_address_func (pc
+ 4 + offset
, info
);
6913 unsigned int immA
= (given
& 0x00010000u
) >> 16;
6914 unsigned int immB
= (given
& 0x000007feu
) >> 1;
6915 unsigned int immC
= (given
& 0x00000800u
) >> 11;
6918 offset
|= immA
<< 12;
6919 offset
|= immB
<< 2;
6920 offset
|= immC
<< 1;
6922 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
6924 info
->print_address_func (pc
+ 4 + offset
, info
);
6926 unsigned int T
= (given
& 0x00020000u
) >> 17;
6927 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
6928 unsigned int boffset
= (T
== 1) ? 4 : 2;
6929 func (stream
, ", ");
6930 func (stream
, "%x", endoffset
+ boffset
);
6936 unsigned int immh
= (given
& 0x000007feu
) >> 1;
6937 unsigned int imml
= (given
& 0x00000800u
) >> 11;
6943 info
->print_address_func (pc
+ 4 + imm32
, info
);
6949 unsigned int immh
= (given
& 0x000007feu
) >> 1;
6950 unsigned int imml
= (given
& 0x00000800u
) >> 11;
6956 info
->print_address_func (pc
+ 4 - imm32
, info
);
6962 unsigned int S
= (given
& 0x04000000u
) >> 26;
6963 unsigned int J1
= (given
& 0x00002000u
) >> 13;
6964 unsigned int J2
= (given
& 0x00000800u
) >> 11;
6970 offset
|= (given
& 0x003f0000) >> 4;
6971 offset
|= (given
& 0x000007ff) << 1;
6972 offset
-= (1 << 20);
6974 info
->print_address_func (pc
+ 4 + offset
, info
);
6980 unsigned int S
= (given
& 0x04000000u
) >> 26;
6981 unsigned int I1
= (given
& 0x00002000u
) >> 13;
6982 unsigned int I2
= (given
& 0x00000800u
) >> 11;
6986 offset
|= !(I1
^ S
) << 23;
6987 offset
|= !(I2
^ S
) << 22;
6988 offset
|= (given
& 0x03ff0000u
) >> 4;
6989 offset
|= (given
& 0x000007ffu
) << 1;
6990 offset
-= (1 << 24);
6993 /* BLX target addresses are always word aligned. */
6994 if ((given
& 0x00001000u
) == 0)
6997 info
->print_address_func (offset
, info
);
7003 unsigned int shift
= 0;
7005 shift
|= (given
& 0x000000c0u
) >> 6;
7006 shift
|= (given
& 0x00007000u
) >> 10;
7007 if (WRITEBACK_BIT_SET
)
7008 func (stream
, ", asr #%u", shift
);
7010 func (stream
, ", lsl #%u", shift
);
7011 /* else print nothing - lsl #0 */
7017 unsigned int rot
= (given
& 0x00000030) >> 4;
7020 func (stream
, ", ror #%u", rot
* 8);
7025 if ((given
& 0xf0) == 0x60)
7027 switch (given
& 0xf)
7029 case 0xf: func (stream
, "sy"); break;
7031 func (stream
, "#%d", (int) given
& 0xf);
7037 const char * opt
= data_barrier_option (given
& 0xf);
7039 func (stream
, "%s", opt
);
7041 func (stream
, "#%d", (int) given
& 0xf);
7046 if ((given
& 0xff) == 0)
7048 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
7058 else if ((given
& 0x20) == 0x20)
7061 unsigned sysm
= (given
& 0xf00) >> 8;
7063 sysm
|= (given
& 0x30);
7064 sysm
|= (given
& 0x00100000) >> 14;
7065 name
= banked_regname (sysm
);
7068 func (stream
, "%s", name
);
7070 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
7074 func (stream
, "%s", psr_name (given
& 0xff));
7079 if (((given
& 0xff) == 0)
7080 || ((given
& 0x20) == 0x20))
7083 unsigned sm
= (given
& 0xf0000) >> 16;
7085 sm
|= (given
& 0x30);
7086 sm
|= (given
& 0x00100000) >> 14;
7087 name
= banked_regname (sm
);
7090 func (stream
, "%s", name
);
7092 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
7095 func (stream
, "%s", psr_name (given
& 0xff));
7098 case '0': case '1': case '2': case '3': case '4':
7099 case '5': case '6': case '7': case '8': case '9':
7104 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
7109 func (stream
, "%lu", val
);
7110 value_in_comment
= val
;
7114 func (stream
, "%lu", val
+ 1);
7115 value_in_comment
= val
+ 1;
7119 func (stream
, "%lu", val
* 4);
7120 value_in_comment
= val
* 4;
7125 is_unpredictable
= TRUE
;
7129 is_unpredictable
= TRUE
;
7132 func (stream
, "%s", arm_regnames
[val
]);
7136 func (stream
, "%s", arm_conditional
[val
]);
7141 if (val
== ((1ul << width
) - 1))
7142 func (stream
, "%c", *c
);
7148 func (stream
, "%c", *c
);
7152 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
7157 func (stream
, "0x%lx", val
& 0xffffffffUL
);
7167 /* PR binutils/12534
7168 If we have a PC relative offset in an LDRD or STRD
7169 instructions then display the decoded address. */
7170 if (((given
>> 16) & 0xf) == 0xf)
7172 bfd_vma offset
= (given
& 0xff) * 4;
7174 if ((given
& (1 << 23)) == 0)
7176 func (stream
, "\t; ");
7177 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
7186 if (value_in_comment
> 32 || value_in_comment
< -16)
7187 func (stream
, "\t; 0x%lx", value_in_comment
);
7189 if (is_unpredictable
)
7190 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7196 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
7200 /* Print data bytes on INFO->STREAM. */
7203 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
7204 struct disassemble_info
*info
,
7207 switch (info
->bytes_per_chunk
)
7210 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
7213 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
7216 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
7223 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
7224 being displayed in symbol relative addresses.
7226 Also disallow private symbol, with __tagsym$$ prefix,
7227 from ARM RVCT toolchain being displayed. */
7230 arm_symbol_is_valid (asymbol
* sym
,
7231 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
7238 name
= bfd_asymbol_name (sym
);
7240 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
7243 /* Parse the string of disassembler options. */
7246 parse_arm_disassembler_options (const char *options
)
7250 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
7252 if (CONST_STRNEQ (opt
, "reg-names-"))
7255 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
7256 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
7258 regname_selected
= i
;
7262 if (i
>= NUM_ARM_OPTIONS
)
7263 /* xgettext: c-format */
7264 opcodes_error_handler (_("unrecognised register name set: %s"),
7267 else if (CONST_STRNEQ (opt
, "force-thumb"))
7269 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
7272 /* xgettext: c-format */
7273 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
7280 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
7281 enum map_type
*map_symbol
);
7283 /* Search back through the insn stream to determine if this instruction is
7284 conditionally executed. */
7287 find_ifthen_state (bfd_vma pc
,
7288 struct disassemble_info
*info
,
7294 /* COUNT is twice the number of instructions seen. It will be odd if we
7295 just crossed an instruction boundary. */
7298 unsigned int seen_it
;
7301 ifthen_address
= pc
;
7308 /* Scan backwards looking for IT instructions, keeping track of where
7309 instruction boundaries are. We don't know if something is actually an
7310 IT instruction until we find a definite instruction boundary. */
7313 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
7315 /* A symbol must be on an instruction boundary, and will not
7316 be within an IT block. */
7317 if (seen_it
&& (count
& 1))
7323 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
7328 insn
= (b
[0]) | (b
[1] << 8);
7330 insn
= (b
[1]) | (b
[0] << 8);
7333 if ((insn
& 0xf800) < 0xe800)
7335 /* Addr + 2 is an instruction boundary. See if this matches
7336 the expected boundary based on the position of the last
7343 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
7345 enum map_type type
= MAP_ARM
;
7346 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
7348 if (!found
|| (found
&& type
== MAP_THUMB
))
7350 /* This could be an IT instruction. */
7352 it_count
= count
>> 1;
7355 if ((insn
& 0xf800) >= 0xe800)
7358 count
= (count
+ 2) | 1;
7359 /* IT blocks contain at most 4 instructions. */
7360 if (count
>= 8 && !seen_it
)
7363 /* We found an IT instruction. */
7364 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
7365 if ((ifthen_state
& 0xf) == 0)
7369 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
7373 is_mapping_symbol (struct disassemble_info
*info
, int n
,
7374 enum map_type
*map_type
)
7378 name
= bfd_asymbol_name (info
->symtab
[n
]);
7379 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
7380 && (name
[2] == 0 || name
[2] == '.'))
7382 *map_type
= ((name
[1] == 'a') ? MAP_ARM
7383 : (name
[1] == 't') ? MAP_THUMB
7391 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
7392 Returns nonzero if *MAP_TYPE was set. */
7395 get_map_sym_type (struct disassemble_info
*info
,
7397 enum map_type
*map_type
)
7399 /* If the symbol is in a different section, ignore it. */
7400 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
7403 return is_mapping_symbol (info
, n
, map_type
);
7406 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
7407 Returns nonzero if *MAP_TYPE was set. */
7410 get_sym_code_type (struct disassemble_info
*info
,
7412 enum map_type
*map_type
)
7414 elf_symbol_type
*es
;
7417 /* If the symbol is in a different section, ignore it. */
7418 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
7421 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
7422 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
7424 /* If the symbol has function type then use that. */
7425 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
7427 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
7428 == ST_BRANCH_TO_THUMB
)
7429 *map_type
= MAP_THUMB
;
7431 *map_type
= MAP_ARM
;
7438 /* Search the mapping symbol state for instruction at pc. This is only
7439 applicable for elf target.
7441 There is an assumption Here, info->private_data contains the correct AND
7442 up-to-date information about current scan process. The information will be
7443 used to speed this search process.
7445 Return TRUE if the mapping state can be determined, and map_symbol
7446 will be updated accordingly. Otherwise, return FALSE. */
7449 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
7450 enum map_type
*map_symbol
)
7452 bfd_vma addr
, section_vma
= 0;
7453 int n
, last_sym
= -1;
7454 bfd_boolean found
= FALSE
;
7455 bfd_boolean can_use_search_opt_p
= FALSE
;
7457 /* Default to DATA. A text section is required by the ABI to contain an
7458 INSN mapping symbol at the start. A data section has no such
7459 requirement, hence if no mapping symbol is found the section must
7460 contain only data. This however isn't very useful if the user has
7461 fully stripped the binaries. If this is the case use the section
7462 attributes to determine the default. If we have no section default to
7463 INSN as well, as we may be disassembling some raw bytes on a baremetal
7464 HEX file or similar. */
7465 enum map_type type
= MAP_DATA
;
7466 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
7468 struct arm_private_data
*private_data
;
7470 if (info
->private_data
== NULL
7471 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
7474 private_data
= info
->private_data
;
7476 /* First, look for mapping symbols. */
7477 if (info
->symtab_size
!= 0)
7479 if (pc
<= private_data
->last_mapping_addr
)
7480 private_data
->last_mapping_sym
= -1;
7482 /* Start scanning at the start of the function, or wherever
7483 we finished last time. */
7484 n
= info
->symtab_pos
+ 1;
7486 /* If the last stop offset is different from the current one it means we
7487 are disassembling a different glob of bytes. As such the optimization
7488 would not be safe and we should start over. */
7489 can_use_search_opt_p
7490 = private_data
->last_mapping_sym
>= 0
7491 && info
->stop_offset
== private_data
->last_stop_offset
;
7493 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
7494 n
= private_data
->last_mapping_sym
;
7496 /* Look down while we haven't passed the location being disassembled.
7497 The reason for this is that there's no defined order between a symbol
7498 and an mapping symbol that may be at the same address. We may have to
7499 look at least one position ahead. */
7500 for (; n
< info
->symtab_size
; n
++)
7502 addr
= bfd_asymbol_value (info
->symtab
[n
]);
7505 if (get_map_sym_type (info
, n
, &type
))
7514 n
= info
->symtab_pos
;
7515 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
7516 n
= private_data
->last_mapping_sym
;
7518 /* No mapping symbol found at this address. Look backwards
7519 for a preceeding one, but don't go pass the section start
7520 otherwise a data section with no mapping symbol can pick up
7521 a text mapping symbol of a preceeding section. The documentation
7522 says section can be NULL, in which case we will seek up all the
7525 section_vma
= info
->section
->vma
;
7529 addr
= bfd_asymbol_value (info
->symtab
[n
]);
7530 if (addr
< section_vma
)
7533 if (get_map_sym_type (info
, n
, &type
))
7543 /* If no mapping symbol was found, try looking up without a mapping
7544 symbol. This is done by walking up from the current PC to the nearest
7545 symbol. We don't actually have to loop here since symtab_pos will
7546 contain the nearest symbol already. */
7549 n
= info
->symtab_pos
;
7550 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
7557 private_data
->last_mapping_sym
= last_sym
;
7558 private_data
->last_type
= type
;
7559 private_data
->last_stop_offset
= info
->stop_offset
;
7565 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
7566 of the supplied arm_feature_set structure with bitmasks indicating
7567 the supported base architectures and coprocessor extensions.
7569 FIXME: This could more efficiently implemented as a constant array,
7570 although it would also be less robust. */
7573 select_arm_features (unsigned long mach
,
7574 arm_feature_set
* features
)
7576 arm_feature_set arch_fset
;
7577 const arm_feature_set fpu_any
= FPU_ANY
;
7579 #undef ARM_SET_FEATURES
7580 #define ARM_SET_FEATURES(FSET) \
7582 const arm_feature_set fset = FSET; \
7586 /* When several architecture versions share the same bfd_mach_arm_XXX value
7587 the most featureful is chosen. */
7590 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
7591 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
7592 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
7593 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
7594 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
7595 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
7596 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
7597 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
7598 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
7599 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
7600 case bfd_mach_arm_ep9312
:
7601 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
7602 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
7604 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
7605 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
7606 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
7607 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
7608 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
7609 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
7610 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
7611 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
7612 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
7613 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
7614 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
7615 case bfd_mach_arm_8
:
7617 /* Add bits for extensions that Armv8.5-A recognizes. */
7618 arm_feature_set armv8_5_ext_fset
7619 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
7620 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
7621 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
7624 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
7625 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
7626 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
7627 case bfd_mach_arm_8_1M_MAIN
:
7628 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
7631 /* If the machine type is unknown allow all architecture types and all
7633 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
7637 #undef ARM_SET_FEATURES
7639 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
7640 and thus on bfd_mach_arm_XXX value. Therefore for a given
7641 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
7642 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
7646 /* NOTE: There are no checks in these routines that
7647 the relevant number of data bytes exist. */
7650 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
7655 int is_thumb
= FALSE
;
7656 int is_data
= FALSE
;
7658 unsigned int size
= 4;
7659 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
7660 bfd_boolean found
= FALSE
;
7661 struct arm_private_data
*private_data
;
7663 if (info
->disassembler_options
)
7665 parse_arm_disassembler_options (info
->disassembler_options
);
7667 /* To avoid repeated parsing of these options, we remove them here. */
7668 info
->disassembler_options
= NULL
;
7671 /* PR 10288: Control which instructions will be disassembled. */
7672 if (info
->private_data
== NULL
)
7674 static struct arm_private_data
private;
7676 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
7677 /* If the user did not use the -m command line switch then default to
7678 disassembling all types of ARM instruction.
7680 The info->mach value has to be ignored as this will be based on
7681 the default archictecture for the target and/or hints in the notes
7682 section, but it will never be greater than the current largest arm
7683 machine value (iWMMXt2), which is only equivalent to the V5TE
7684 architecture. ARM architectures have advanced beyond the machine
7685 value encoding, and these newer architectures would be ignored if
7686 the machine value was used.
7688 Ie the -m switch is used to restrict which instructions will be
7689 disassembled. If it is necessary to use the -m switch to tell
7690 objdump that an ARM binary is being disassembled, eg because the
7691 input is a raw binary file, but it is also desired to disassemble
7692 all ARM instructions then use "-marm". This will select the
7693 "unknown" arm architecture which is compatible with any ARM
7695 info
->mach
= bfd_mach_arm_unknown
;
7697 /* Compute the architecture bitmask from the machine number.
7698 Note: This assumes that the machine number will not change
7699 during disassembly.... */
7700 select_arm_features (info
->mach
, & private.features
);
7702 private.last_mapping_sym
= -1;
7703 private.last_mapping_addr
= 0;
7704 private.last_stop_offset
= 0;
7706 info
->private_data
= & private;
7709 private_data
= info
->private_data
;
7711 /* Decide if our code is going to be little-endian, despite what the
7712 function argument might say. */
7713 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
7715 /* For ELF, consult the symbol table to determine what kind of code
7717 if (info
->symtab_size
!= 0
7718 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
7723 enum map_type type
= MAP_ARM
;
7725 found
= mapping_symbol_for_insn (pc
, info
, &type
);
7726 last_sym
= private_data
->last_mapping_sym
;
7728 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
7729 is_data
= (private_data
->last_type
== MAP_DATA
);
7731 /* Look a little bit ahead to see if we should print out
7732 two or four bytes of data. If there's a symbol,
7733 mapping or otherwise, after two bytes then don't
7737 size
= 4 - (pc
& 3);
7738 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
7740 addr
= bfd_asymbol_value (info
->symtab
[n
]);
7742 && (info
->section
== NULL
7743 || info
->section
== info
->symtab
[n
]->section
))
7745 if (addr
- pc
< size
)
7750 /* If the next symbol is after three bytes, we need to
7751 print only part of the data, so that we can use either
7754 size
= (pc
& 1) ? 1 : 2;
7758 if (info
->symbols
!= NULL
)
7760 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
7762 coff_symbol_type
* cs
;
7764 cs
= coffsymbol (*info
->symbols
);
7765 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
7766 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
7767 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
7768 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
7769 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
7771 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
7774 /* If no mapping symbol has been found then fall back to the type
7775 of the function symbol. */
7776 elf_symbol_type
* es
;
7779 es
= *(elf_symbol_type
**)(info
->symbols
);
7780 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
7783 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
7784 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
7786 else if (bfd_asymbol_flavour (*info
->symbols
)
7787 == bfd_target_mach_o_flavour
)
7789 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
7791 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
7799 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
7801 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
7803 info
->bytes_per_line
= 4;
7805 /* PR 10263: Disassemble data if requested to do so by the user. */
7806 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
7810 /* Size was already set above. */
7811 info
->bytes_per_chunk
= size
;
7812 printer
= print_insn_data
;
7814 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
7817 for (i
= size
- 1; i
>= 0; i
--)
7818 given
= b
[i
] | (given
<< 8);
7820 for (i
= 0; i
< (int) size
; i
++)
7821 given
= b
[i
] | (given
<< 8);
7825 /* In ARM mode endianness is a straightforward issue: the instruction
7826 is four bytes long and is either ordered 0123 or 3210. */
7827 printer
= print_insn_arm
;
7828 info
->bytes_per_chunk
= 4;
7831 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
7833 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
7835 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
7839 /* In Thumb mode we have the additional wrinkle of two
7840 instruction lengths. Fortunately, the bits that determine
7841 the length of the current instruction are always to be found
7842 in the first two bytes. */
7843 printer
= print_insn_thumb16
;
7844 info
->bytes_per_chunk
= 2;
7847 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
7849 given
= (b
[0]) | (b
[1] << 8);
7851 given
= (b
[1]) | (b
[0] << 8);
7855 /* These bit patterns signal a four-byte Thumb
7857 if ((given
& 0xF800) == 0xF800
7858 || (given
& 0xF800) == 0xF000
7859 || (given
& 0xF800) == 0xE800)
7861 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
7863 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
7865 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
7867 printer
= print_insn_thumb32
;
7872 if (ifthen_address
!= pc
)
7873 find_ifthen_state (pc
, info
, little_code
);
7877 if ((ifthen_state
& 0xf) == 0x8)
7878 ifthen_next_state
= 0;
7880 ifthen_next_state
= (ifthen_state
& 0xe0)
7881 | ((ifthen_state
& 0xf) << 1);
7887 info
->memory_error_func (status
, pc
, info
);
7890 if (info
->flags
& INSN_HAS_RELOC
)
7891 /* If the instruction has a reloc associated with it, then
7892 the offset field in the instruction will actually be the
7893 addend for the reloc. (We are using REL type relocs).
7894 In such cases, we can ignore the pc when computing
7895 addresses, since the addend is not currently pc-relative. */
7898 printer (pc
, info
, given
);
7902 ifthen_state
= ifthen_next_state
;
7903 ifthen_address
+= size
;
7909 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
7911 /* Detect BE8-ness and record it in the disassembler info. */
7912 if (info
->flavour
== bfd_target_elf_flavour
7913 && info
->section
!= NULL
7914 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
7915 info
->endian_code
= BFD_ENDIAN_LITTLE
;
7917 return print_insn (pc
, info
, FALSE
);
7921 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
7923 return print_insn (pc
, info
, TRUE
);
7926 const disasm_options_and_args_t
*
7927 disassembler_options_arm (void)
7929 static disasm_options_and_args_t
*opts_and_args
;
7931 if (opts_and_args
== NULL
)
7933 disasm_options_t
*opts
;
7936 opts_and_args
= XNEW (disasm_options_and_args_t
);
7937 opts_and_args
->args
= NULL
;
7939 opts
= &opts_and_args
->options
;
7940 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
7941 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
7943 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
7945 opts
->name
[i
] = regnames
[i
].name
;
7946 if (regnames
[i
].description
!= NULL
)
7947 opts
->description
[i
] = _(regnames
[i
].description
);
7949 opts
->description
[i
] = NULL
;
7951 /* The array we return must be NULL terminated. */
7952 opts
->name
[i
] = NULL
;
7953 opts
->description
[i
] = NULL
;
7956 return opts_and_args
;
7960 print_arm_disassembler_options (FILE *stream
)
7962 unsigned int i
, max_len
= 0;
7963 fprintf (stream
, _("\n\
7964 The following ARM specific disassembler options are supported for use with\n\
7965 the -M switch:\n"));
7967 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
7969 unsigned int len
= strlen (regnames
[i
].name
);
7974 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
7975 fprintf (stream
, " %s%*c %s\n",
7977 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
7978 _(regnames
[i
].description
));