projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[binutils][arm] BFloat16 enablement [4/X]
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <assert.h>
25
26 #include "disassemble.h"
27 #include "opcode/arm.h"
28 #include "opintl.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
32
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
35 #include "libcoff.h"
36 #include "bfd.h"
37 #include "elf-bfd.h"
38 #include "elf/internal.h"
39 #include "elf/arm.h"
40 #include "mach-o.h"
41
42 /* FIXME: Belongs in global header. */
43 #ifndef strneq
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45 #endif
46
47 /* Cached mapping symbol state. */
48 enum map_type
49 {
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53 };
54
55 struct arm_private_data
56 {
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
68 bfd_vma last_mapping_addr;
69 };
70
71 enum mve_instructions
72 {
73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
293 MVE_NONE
294 };
295
296 enum mve_unpredictable
297 {
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
320 UNPRED_NONE /* No unpredictable behavior. */
321 };
322
323 enum mve_undefined
324 {
325 UNDEF_SIZE, /* undefined size. */
326 UNDEF_SIZE_0, /* undefined because size == 0. */
327 UNDEF_SIZE_2, /* undefined because size == 2. */
328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
347 UNDEF_NONE /* no undefined behavior. */
348 };
349
350 struct opcode32
351 {
352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
355 const char * assembler; /* How to disassemble this insn. */
356 };
357
358 /* MVE opcodes. */
359
360 struct mopcode32
361 {
362 arm_feature_set arch; /* Architecture defining this insn. */
363 enum mve_instructions mve_op; /* Specific mve instruction for faster
364 decoding. */
365 unsigned long value; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask; /* Recognise insn if (op & mask) == value. */
367 const char * assembler; /* How to disassemble this insn. */
368 };
369
370 enum isa {
371 ANY,
372 T32,
373 ARM
374 };
375
376
377 /* Shared (between Arm and Thumb mode) opcode. */
378 struct sopcode32
379 {
380 enum isa isa; /* Execution mode instruction availability. */
381 arm_feature_set arch; /* Architecture defining this insn. */
382 unsigned long value; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask; /* Recognise insn if (op & mask) == value. */
384 const char * assembler; /* How to disassemble this insn. */
385 };
386
387 struct opcode16
388 {
389 arm_feature_set arch; /* Architecture defining this insn. */
390 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
391 const char *assembler; /* How to disassemble this insn. */
392 };
393
394 /* print_insn_coprocessor recognizes the following format control codes:
395
396 %% %
397
398 %c print condition code (always bits 28-31 in ARM mode)
399 %b print condition code allowing cp_num == 9
400 %q print shifter argument
401 %u print condition code (unconditional in ARM mode,
402 UNPREDICTABLE if not AL in Thumb)
403 %A print address for ldc/stc/ldf/stf instruction
404 %B print vstm/vldm register list
405 %C print vscclrm register list
406 %I print cirrus signed shift immediate: bits 0..3|4..6
407 %J print register for VLDR instruction
408 %K print address for VLDR instruction
409 %F print the COUNT field of a LFM/SFM instruction.
410 %P print floating point precision in arithmetic insn
411 %Q print floating point precision in ldf/stf insn
412 %R print floating point rounding mode
413
414 %<bitfield>c print as a condition code (for vsel)
415 %<bitfield>r print as an ARM register
416 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
417 %<bitfield>ru as %<>r but each u register must be unique.
418 %<bitfield>d print the bitfield in decimal
419 %<bitfield>k print immediate for VFPv3 conversion instruction
420 %<bitfield>x print the bitfield in hex
421 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
422 %<bitfield>f print a floating point constant if >7 else a
423 floating point register
424 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
425 %<bitfield>g print as an iWMMXt 64-bit register
426 %<bitfield>G print as an iWMMXt general purpose or control register
427 %<bitfield>D print as a NEON D register
428 %<bitfield>Q print as a NEON Q register
429 %<bitfield>V print as a NEON D or Q register
430 %<bitfield>E print a quarter-float immediate value
431
432 %y<code> print a single precision VFP reg.
433 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
434 %z<code> print a double precision VFP reg
435 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
436
437 %<bitfield>'c print specified char iff bitfield is all ones
438 %<bitfield>`c print specified char iff bitfield is all zeroes
439 %<bitfield>?ab... select from array of values in big endian order
440
441 %L print as an iWMMXt N/M width field.
442 %Z print the Immediate of a WSHUFH instruction.
443 %l like 'A' except use byte offsets for 'B' & 'H'
444 versions.
445 %i print 5-bit immediate in bits 8,3..0
446 (print "32" when 0)
447 %r print register offset address for wldt/wstr instruction. */
448
449 enum opcode_sentinel_enum
450 {
451 SENTINEL_IWMMXT_START = 1,
452 SENTINEL_IWMMXT_END,
453 SENTINEL_GENERIC_START
454 } opcode_sentinels;
455
456 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
457 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
458 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
459 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
460
461 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
462
463 static const struct sopcode32 coprocessor_opcodes[] =
464 {
465 /* XScale instructions. */
466 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
467 0x0e200010, 0x0fff0ff0,
468 "mia%c\tacc0, %0-3r, %12-15r"},
469 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
470 0x0e280010, 0x0fff0ff0,
471 "miaph%c\tacc0, %0-3r, %12-15r"},
472 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
473 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
474 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
475 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
476 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
477 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
478
479 /* Intel Wireless MMX technology instructions. */
480 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
481 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
482 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
483 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
484 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
485 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
486 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
488 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
490 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
491 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
492 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
493 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
494 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
495 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
496 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
497 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
498 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
499 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
500 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
501 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
502 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
503 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
504 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
505 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
506 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
507 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
508 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
510 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
512 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
514 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
515 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
516 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
517 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
518 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
519 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
520 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
521 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
522 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
523 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
524 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
525 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
526 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
527 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
528 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
529 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
530 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
531 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
532 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
534 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
535 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
536 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
537 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
538 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
540 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
542 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
544 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
546 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
547 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
548 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
549 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
550 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
551 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
552 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
553 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
554 0x0e800120, 0x0f800ff0,
555 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
556 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
557 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
558 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
559 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
561 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
563 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
565 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
567 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
569 0x0e8000a0, 0x0f800ff0,
570 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
572 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
574 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
576 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
578 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
580 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
582 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
584 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
586 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
588 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
590 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
592 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
594 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
596 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
598 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
600 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
602 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
604 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
606 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
608 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
610 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
612 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
614 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
616 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
618 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
620 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
622 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
624 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
626 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
628 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
629 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
630 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
631 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
632 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
633 {ANY, ARM_FEATURE_CORE_LOW (0),
634 SENTINEL_IWMMXT_END, 0, "" },
635
636 /* Floating point coprocessor (FPA) instructions. */
637 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
638 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
639 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
640 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
641 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
642 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
643 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
644 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
645 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
646 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
647 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
648 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
649 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
650 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
651 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
652 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
653 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
654 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
655 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
656 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
657 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
658 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
659 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
660 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
661 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
662 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
663 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
664 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
665 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
666 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
667 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
668 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
669 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
670 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
671 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
672 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
673 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
674 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
675 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
676 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
677 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
678 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
679 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
680 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
681 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
682 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
683 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
684 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
685 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
686 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
687 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
688 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
689 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
690 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
691 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
692 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
693 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
694 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
695 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
696 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
697 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
698 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
699 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
700 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
701 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
702 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
703 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
704 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
705 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
706 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
707 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
708 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
709 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
710 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
712 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
714 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
716 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
718 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
720 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
722 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
723
724 /* Armv8.1-M Mainline instructions. */
725 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
726 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
727 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
728 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
729
730 /* ARMv8-M Mainline Security Extensions instructions. */
731 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
732 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
733 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
734 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
735
736 /* Register load/store. */
737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
738 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
740 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
742 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
744 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
746 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
748 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
750 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
752 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
754 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
756 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
758 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
760 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
762 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
764 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
766 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
768 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
769 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
770 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
771 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
772 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
773
774 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
775 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
776 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
777 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
778 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
779 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
780 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
781 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
782
783 /* Data transfer between ARM and NEON registers. */
784 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
785 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
786 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
787 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
788 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
789 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
790 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
791 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
792 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
793 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
794 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
795 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
796 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
797 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
798 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
799 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
800 /* Half-precision conversion instructions. */
801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
802 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
804 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
806 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
808 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
809
810 /* Floating point coprocessor (VFP) instructions. */
811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
812 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
814 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
815 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
816 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
818 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
820 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
822 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
824 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
826 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
828 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
829 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
830 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
831 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
832 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
833 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
834 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
835 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
836 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
838 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
840 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
842 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
843 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
844 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
845 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
846 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
847 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
848 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
849 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
850 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
851 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
852 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
854 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
856 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
857 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
858 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
859 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
860 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
861 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
862 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
863 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
864 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
865 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
866 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
867 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
868 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
869 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
870 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
871 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
872 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
873 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
874 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
876 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
878 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
880 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
882 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
883 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
884 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
886 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
887 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
888 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
889 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
890 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
892 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
894 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
896 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
898 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
900 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
902 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
903 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
904 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
905 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
906 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
907 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
908 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
909 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
910 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
912 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
914 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
915 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
916 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
917 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
918 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
920 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
922 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
924 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
926 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
928 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
930 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
931 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
932 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
933 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
934 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
935 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
936 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
937 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
938 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
940 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
942 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
944 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
946 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
948 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
950 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
952 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
954 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
956 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
958 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
960 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
962 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
964 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
966 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
968 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
969
970 /* Cirrus coprocessor instructions. */
971 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
972 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
973 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
974 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
976 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
977 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
978 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
979 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
980 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
981 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
982 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
983 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
984 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
985 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
986 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
987 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
988 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
989 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
990 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
991 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
992 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
993 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
994 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
995 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
996 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
997 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
998 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
999 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1000 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1001 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1002 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1003 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1004 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1005 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1006 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1007 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1008 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1009 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1010 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1011 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1012 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1013 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1014 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1015 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1016 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1017 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1018 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1019 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1020 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1021 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1022 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1023 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1024 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1025 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1026 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1027 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1028 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1029 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1030 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1031 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1032 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1033 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1034 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1035 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1036 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1037 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1038 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1039 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1040 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1041 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1042 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1043 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1044 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1046 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1048 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1050 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1052 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1054 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1056 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1058 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1060 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1062 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1064 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1066 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1068 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1070 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1072 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1074 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1076 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1078 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1080 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1082 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1084 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1086 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1088 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1090 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1092 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1094 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1096 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1098 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1100 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1102 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1103 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1104 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1105 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1106 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1108 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1109 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1110 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1111 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1112 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1114 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1115 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1116 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1117 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1118 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1120 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1121 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1122 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1123 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1124 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1125 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1126 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1127 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1128 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1129 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1130 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1131 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1132 0x0e000600, 0x0ff00f10,
1133 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1134 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1135 0x0e100600, 0x0ff00f10,
1136 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1137 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1138 0x0e200600, 0x0ff00f10,
1139 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1140 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1141 0x0e300600, 0x0ff00f10,
1142 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1143
1144 /* VFP Fused multiply add instructions. */
1145 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1146 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1147 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1148 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1149 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1150 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1151 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1152 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1153 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1154 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1155 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1156 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1157 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1158 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1159 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1160 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1161
1162 /* FP v5. */
1163 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1164 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1165 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1166 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1167 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1168 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1169 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1170 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1171 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1172 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1173 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1174 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1175 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1176 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1177 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1178 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1179 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1180 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1181 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1182 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1183 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1184 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1185 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1186 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1187
1188 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1189 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1191 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1193 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1195 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1197 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1198 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1199 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1201 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1203 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1205 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1207 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1209 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1210
1211 /* BFloat16 instructions. */
1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1213 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1214
1215 /* Dot Product instructions in the space of coprocessor 13. */
1216 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1217 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1218 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1219 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1220
1221 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1223 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1224 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1225 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1226 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1227 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1229 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1231 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1233 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1235 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1237 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1238
1239 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1240 cp_num: bit <11:8> == 0b1001.
1241 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1242 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1243 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1244 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1245 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1246 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1247 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1249 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1250 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1251 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1253 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1254 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1255 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1256 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1257 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1258 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1259 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1260 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1261 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1262 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1263 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1265 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1267 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1269 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1271 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1273 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1274 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1275 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1276 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1277 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1278 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1279 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1281 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1283 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1284 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1285 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1287 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1288 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1289 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1290 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1291 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1292 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1293 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1294 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1295 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1296 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1297 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1298 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1299 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1301 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1303 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1305 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1307 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1309 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1311 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1312
1313 /* ARMv8.3 javascript conversion instruction. */
1314 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1315 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1316
1317 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1318 };
1319
1320 /* Generic coprocessor instructions. These are only matched if a more specific
1321 SIMD or co-processor instruction does not match first. */
1322
1323 static const struct sopcode32 generic_coprocessor_opcodes[] =
1324 {
1325 /* Generic coprocessor instructions. */
1326 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1327 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1328 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1329 0x0c500000, 0x0ff00000,
1330 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1331 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1332 0x0e000000, 0x0f000010,
1333 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1334 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1335 0x0e10f010, 0x0f10f010,
1336 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1337 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1338 0x0e100010, 0x0f100010,
1339 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1340 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1341 0x0e000010, 0x0f100010,
1342 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1343 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1344 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1345 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1346 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1347
1348 /* V6 coprocessor instructions. */
1349 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1350 0xfc500000, 0xfff00000,
1351 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1352 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1353 0xfc400000, 0xfff00000,
1354 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1355
1356 /* V5 coprocessor instructions. */
1357 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1358 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1359 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1360 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1361 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1362 0xfe000000, 0xff000010,
1363 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1364 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1365 0xfe000010, 0xff100010,
1366 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1367 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1368 0xfe100010, 0xff100010,
1369 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1370
1371 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1372 };
1373
1374 /* Neon opcode table: This does not encode the top byte -- that is
1375 checked by the print_insn_neon routine, as it depends on whether we are
1376 doing thumb32 or arm32 disassembly. */
1377
1378 /* print_insn_neon recognizes the following format control codes:
1379
1380 %% %
1381
1382 %c print condition code
1383 %u print condition code (unconditional in ARM mode,
1384 UNPREDICTABLE if not AL in Thumb)
1385 %A print v{st,ld}[1234] operands
1386 %B print v{st,ld}[1234] any one operands
1387 %C print v{st,ld}[1234] single->all operands
1388 %D print scalar
1389 %E print vmov, vmvn, vorr, vbic encoded constant
1390 %F print vtbl,vtbx register list
1391
1392 %<bitfield>r print as an ARM register
1393 %<bitfield>d print the bitfield in decimal
1394 %<bitfield>e print the 2^N - bitfield in decimal
1395 %<bitfield>D print as a NEON D register
1396 %<bitfield>Q print as a NEON Q register
1397 %<bitfield>R print as a NEON D or Q register
1398 %<bitfield>Sn print byte scaled width limited by n
1399 %<bitfield>Tn print short scaled width limited by n
1400 %<bitfield>Un print long scaled width limited by n
1401
1402 %<bitfield>'c print specified char iff bitfield is all ones
1403 %<bitfield>`c print specified char iff bitfield is all zeroes
1404 %<bitfield>?ab... select from array of values in big endian order. */
1405
1406 static const struct opcode32 neon_opcodes[] =
1407 {
1408 /* Extract. */
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410 0xf2b00840, 0xffb00850,
1411 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2b00000, 0xffb00810,
1414 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1415
1416 /* Data transfer between ARM and NEON registers. */
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1429
1430 /* Move data element to all lanes. */
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1437
1438 /* Table lookup. */
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1443
1444 /* Half-precision conversions. */
1445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1446 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1448 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1449
1450 /* NEON fused multiply add instructions. */
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1452 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1454 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1456 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1458 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1459
1460 /* BFloat16 instructions. */
1461 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1462 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1464 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1466 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1468 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1470 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1471 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1472 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1473
1474 /* Two registers, miscellaneous. */
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1476 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1478 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1480 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1482 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1483 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1484 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1485 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1486 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1487 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1488 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1489 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1490 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1491 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1492 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1493 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1494 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1495 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1496 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3b20300, 0xffb30fd0,
1519 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1523 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1526 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1527 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1529 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1541 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1547 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1553 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1559 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1564 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1565 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf3bb0600, 0xffbf0e10,
1568 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570 0xf3b70600, 0xffbf0e10,
1571 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1572
1573 /* Three registers of the same length. */
1574 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1575 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1576 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1577 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1578 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1579 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1580 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1581 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1582 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1583 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1584 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1585 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1586 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1587 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1589 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1591 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1593 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1595 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1618 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1619 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1622 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1623 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1627 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1630 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1631 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1634 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1635 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1638 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1639 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1642 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1643 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1646 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1647 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1650 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1651 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1655 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1658 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1659 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1663 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1667 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1670 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1671 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1673 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1675 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1679 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1683 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2000b00, 0xff800f10,
1692 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2000b10, 0xff800f10,
1695 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf3000b00, 0xff800f10,
1704 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2000000, 0xfe800f10,
1707 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf2000010, 0xfe800f10,
1710 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2000100, 0xfe800f10,
1713 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf2000200, 0xfe800f10,
1716 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf2000210, 0xfe800f10,
1719 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf2000300, 0xfe800f10,
1722 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf2000310, 0xfe800f10,
1725 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2000400, 0xfe800f10,
1728 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2000410, 0xfe800f10,
1731 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733 0xf2000500, 0xfe800f10,
1734 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2000510, 0xfe800f10,
1737 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1739 0xf2000600, 0xfe800f10,
1740 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742 0xf2000610, 0xfe800f10,
1743 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2000700, 0xfe800f10,
1746 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1748 0xf2000710, 0xfe800f10,
1749 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf2000910, 0xfe800f10,
1752 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1754 0xf2000a00, 0xfe800f10,
1755 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2000a10, 0xfe800f10,
1758 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1759 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1760 0xf3000b10, 0xff800f10,
1761 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1763 0xf3000c10, 0xff800f10,
1764 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1765
1766 /* One register and an immediate value. */
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1770 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1771 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1772 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1774 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1776 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1793
1794 /* Two registers and a shift amount. */
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2880950, 0xfeb80fd0,
1807 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2900950, 0xfeb00fd0,
1830 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1832 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1838 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1846 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1848 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2a00950, 0xfea00fd0,
1875 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1877 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1879 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1883 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1887 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf2a00e10, 0xfea00e90,
1914 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1915 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1916 0xf2a00c10, 0xfea00e90,
1917 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1918
1919 /* Three registers of different lengths. */
1920 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1921 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1923 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf2800400, 0xff800f50,
1926 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf2800600, 0xff800f50,
1929 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1931 0xf2800900, 0xff800f50,
1932 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934 0xf2800b00, 0xff800f50,
1935 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf2800d00, 0xff800f50,
1938 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940 0xf3800400, 0xff800f50,
1941 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf3800600, 0xff800f50,
1944 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946 0xf2800000, 0xfe800f50,
1947 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1949 0xf2800100, 0xfe800f50,
1950 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952 0xf2800200, 0xfe800f50,
1953 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1955 0xf2800300, 0xfe800f50,
1956 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958 0xf2800500, 0xfe800f50,
1959 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1961 0xf2800700, 0xfe800f50,
1962 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1964 0xf2800800, 0xfe800f50,
1965 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967 0xf2800a00, 0xfe800f50,
1968 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf2800c00, 0xfe800f50,
1971 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1972
1973 /* Two registers and a scalar. */
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1978 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1979 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1986 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1987 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1991 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1994 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1995 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2003 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2005 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2006 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2007 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2008 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2009 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2012 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2013 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2015 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2016 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2017 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2018 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2019 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2021 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2023 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025 0xf2800240, 0xfe800f50,
2026 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028 0xf2800640, 0xfe800f50,
2029 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2031 0xf2800a40, 0xfe800f50,
2032 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2034 0xf2800e40, 0xff800f50,
2035 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2037 0xf2800f40, 0xff800f50,
2038 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2040 0xf3800e40, 0xff800f50,
2041 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2043 0xf3800f40, 0xff800f50,
2044 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2045 },
2046
2047 /* Element and structure load/store. */
2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2049 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2051 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2052 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2053 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2057 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2058 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2059 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2060 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2061 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2065 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2067 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2073 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2075 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2081 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2083 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2086
2087 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2088 };
2089
2090 /* mve opcode table. */
2091
2092 /* print_insn_mve recognizes the following format control codes:
2093
2094 %% %
2095
2096 %a print '+' or '-' or imm offset in vldr[bhwd] and
2097 vstr[bhwd]
2098 %c print condition code
2099 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2100 %u print 'U' (unsigned) or 'S' for various mve instructions
2101 %i print MVE predicate(s) for vpt and vpst
2102 %j print a 5-bit immediate from hw2[14:12,7:6]
2103 %k print 48 if the 7th position bit is set else print 64.
2104 %m print rounding mode for vcvt and vrint
2105 %n print vector comparison code for predicated instruction
2106 %s print size for various vcvt instructions
2107 %v print vector predicate for instruction in predicated
2108 block
2109 %o print offset scaled for vldr[hwd] and vstr[hwd]
2110 %w print writeback mode for MVE v{st,ld}[24]
2111 %B print v{st,ld}[24] any one operands
2112 %E print vmov, vmvn, vorr, vbic encoded constant
2113 %N print generic index for vmov
2114 %T print bottom ('b') or top ('t') of source register
2115 %X print exchange field in vmla* instructions
2116
2117 %<bitfield>r print as an ARM register
2118 %<bitfield>d print the bitfield in decimal
2119 %<bitfield>A print accumulate or not
2120 %<bitfield>c print bitfield as a condition code
2121 %<bitfield>C print bitfield as an inverted condition code
2122 %<bitfield>Q print as a MVE Q register
2123 %<bitfield>F print as a MVE S register
2124 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2125 UNPREDICTABLE
2126
2127 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2128 %<bitfield>s print size for vector predicate & non VMOV instructions
2129 %<bitfield>I print carry flag or not
2130 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2131 %<bitfield>h print high half of 64-bit destination reg
2132 %<bitfield>k print immediate for vector conversion instruction
2133 %<bitfield>l print low half of 64-bit destination reg
2134 %<bitfield>o print rotate value for vcmul
2135 %<bitfield>u print immediate value for vddup/vdwdup
2136 %<bitfield>x print the bitfield in hex.
2137 */
2138
2139 static const struct mopcode32 mve_opcodes[] =
2140 {
2141 /* MVE. */
2142
2143 {ARM_FEATURE_COPROC (FPU_MVE),
2144 MVE_VPST,
2145 0xfe310f4d, 0xffbf1fff,
2146 "vpst%i"
2147 },
2148
2149 /* Floating point VPT T1. */
2150 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2151 MVE_VPT_FP_T1,
2152 0xee310f00, 0xefb10f50,
2153 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2154 /* Floating point VPT T2. */
2155 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2156 MVE_VPT_FP_T2,
2157 0xee310f40, 0xefb10f50,
2158 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2159
2160 /* Vector VPT T1. */
2161 {ARM_FEATURE_COPROC (FPU_MVE),
2162 MVE_VPT_VEC_T1,
2163 0xfe010f00, 0xff811f51,
2164 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2165 /* Vector VPT T2. */
2166 {ARM_FEATURE_COPROC (FPU_MVE),
2167 MVE_VPT_VEC_T2,
2168 0xfe010f01, 0xff811f51,
2169 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2170 /* Vector VPT T3. */
2171 {ARM_FEATURE_COPROC (FPU_MVE),
2172 MVE_VPT_VEC_T3,
2173 0xfe011f00, 0xff811f50,
2174 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2175 /* Vector VPT T4. */
2176 {ARM_FEATURE_COPROC (FPU_MVE),
2177 MVE_VPT_VEC_T4,
2178 0xfe010f40, 0xff811f70,
2179 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2180 /* Vector VPT T5. */
2181 {ARM_FEATURE_COPROC (FPU_MVE),
2182 MVE_VPT_VEC_T5,
2183 0xfe010f60, 0xff811f70,
2184 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2185 /* Vector VPT T6. */
2186 {ARM_FEATURE_COPROC (FPU_MVE),
2187 MVE_VPT_VEC_T6,
2188 0xfe011f40, 0xff811f50,
2189 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2190
2191 /* Vector VBIC immediate. */
2192 {ARM_FEATURE_COPROC (FPU_MVE),
2193 MVE_VBIC_IMM,
2194 0xef800070, 0xefb81070,
2195 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2196
2197 /* Vector VBIC register. */
2198 {ARM_FEATURE_COPROC (FPU_MVE),
2199 MVE_VBIC_REG,
2200 0xef100150, 0xffb11f51,
2201 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2202
2203 /* Vector VABAV. */
2204 {ARM_FEATURE_COPROC (FPU_MVE),
2205 MVE_VABAV,
2206 0xee800f01, 0xefc10f51,
2207 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2208
2209 /* Vector VABD floating point. */
2210 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2211 MVE_VABD_FP,
2212 0xff200d40, 0xffa11f51,
2213 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2214
2215 /* Vector VABD. */
2216 {ARM_FEATURE_COPROC (FPU_MVE),
2217 MVE_VABD_VEC,
2218 0xef000740, 0xef811f51,
2219 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2220
2221 /* Vector VABS floating point. */
2222 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2223 MVE_VABS_FP,
2224 0xFFB10740, 0xFFB31FD1,
2225 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2226 /* Vector VABS. */
2227 {ARM_FEATURE_COPROC (FPU_MVE),
2228 MVE_VABS_VEC,
2229 0xffb10340, 0xffb31fd1,
2230 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2231
2232 /* Vector VADD floating point T1. */
2233 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2234 MVE_VADD_FP_T1,
2235 0xef000d40, 0xffa11f51,
2236 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2237 /* Vector VADD floating point T2. */
2238 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2239 MVE_VADD_FP_T2,
2240 0xee300f40, 0xefb11f70,
2241 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2242 /* Vector VADD T1. */
2243 {ARM_FEATURE_COPROC (FPU_MVE),
2244 MVE_VADD_VEC_T1,
2245 0xef000840, 0xff811f51,
2246 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2247 /* Vector VADD T2. */
2248 {ARM_FEATURE_COPROC (FPU_MVE),
2249 MVE_VADD_VEC_T2,
2250 0xee010f40, 0xff811f70,
2251 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2252
2253 /* Vector VADDLV. */
2254 {ARM_FEATURE_COPROC (FPU_MVE),
2255 MVE_VADDLV,
2256 0xee890f00, 0xef8f1fd1,
2257 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2258
2259 /* Vector VADDV. */
2260 {ARM_FEATURE_COPROC (FPU_MVE),
2261 MVE_VADDV,
2262 0xeef10f00, 0xeff31fd1,
2263 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2264
2265 /* Vector VADC. */
2266 {ARM_FEATURE_COPROC (FPU_MVE),
2267 MVE_VADC,
2268 0xee300f00, 0xffb10f51,
2269 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2270
2271 /* Vector VAND. */
2272 {ARM_FEATURE_COPROC (FPU_MVE),
2273 MVE_VAND,
2274 0xef000150, 0xffb11f51,
2275 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2276
2277 /* Vector VBRSR register. */
2278 {ARM_FEATURE_COPROC (FPU_MVE),
2279 MVE_VBRSR,
2280 0xfe011e60, 0xff811f70,
2281 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2282
2283 /* Vector VCADD floating point. */
2284 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2285 MVE_VCADD_FP,
2286 0xfc800840, 0xfea11f51,
2287 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2288
2289 /* Vector VCADD. */
2290 {ARM_FEATURE_COPROC (FPU_MVE),
2291 MVE_VCADD_VEC,
2292 0xfe000f00, 0xff810f51,
2293 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2294
2295 /* Vector VCLS. */
2296 {ARM_FEATURE_COPROC (FPU_MVE),
2297 MVE_VCLS,
2298 0xffb00440, 0xffb31fd1,
2299 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2300
2301 /* Vector VCLZ. */
2302 {ARM_FEATURE_COPROC (FPU_MVE),
2303 MVE_VCLZ,
2304 0xffb004c0, 0xffb31fd1,
2305 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2306
2307 /* Vector VCMLA. */
2308 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2309 MVE_VCMLA_FP,
2310 0xfc200840, 0xfe211f51,
2311 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2312
2313 /* Vector VCMP floating point T1. */
2314 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2315 MVE_VCMP_FP_T1,
2316 0xee310f00, 0xeff1ef50,
2317 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2318
2319 /* Vector VCMP floating point T2. */
2320 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2321 MVE_VCMP_FP_T2,
2322 0xee310f40, 0xeff1ef50,
2323 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2324
2325 /* Vector VCMP T1. */
2326 {ARM_FEATURE_COPROC (FPU_MVE),
2327 MVE_VCMP_VEC_T1,
2328 0xfe010f00, 0xffc1ff51,
2329 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2330 /* Vector VCMP T2. */
2331 {ARM_FEATURE_COPROC (FPU_MVE),
2332 MVE_VCMP_VEC_T2,
2333 0xfe010f01, 0xffc1ff51,
2334 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2335 /* Vector VCMP T3. */
2336 {ARM_FEATURE_COPROC (FPU_MVE),
2337 MVE_VCMP_VEC_T3,
2338 0xfe011f00, 0xffc1ff50,
2339 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2340 /* Vector VCMP T4. */
2341 {ARM_FEATURE_COPROC (FPU_MVE),
2342 MVE_VCMP_VEC_T4,
2343 0xfe010f40, 0xffc1ff70,
2344 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2345 /* Vector VCMP T5. */
2346 {ARM_FEATURE_COPROC (FPU_MVE),
2347 MVE_VCMP_VEC_T5,
2348 0xfe010f60, 0xffc1ff70,
2349 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2350 /* Vector VCMP T6. */
2351 {ARM_FEATURE_COPROC (FPU_MVE),
2352 MVE_VCMP_VEC_T6,
2353 0xfe011f40, 0xffc1ff50,
2354 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2355
2356 /* Vector VDUP. */
2357 {ARM_FEATURE_COPROC (FPU_MVE),
2358 MVE_VDUP,
2359 0xeea00b10, 0xffb10f5f,
2360 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2361
2362 /* Vector VEOR. */
2363 {ARM_FEATURE_COPROC (FPU_MVE),
2364 MVE_VEOR,
2365 0xff000150, 0xffd11f51,
2366 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2367
2368 /* Vector VFMA, vector * scalar. */
2369 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2370 MVE_VFMA_FP_SCALAR,
2371 0xee310e40, 0xefb11f70,
2372 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2373
2374 /* Vector VFMA floating point. */
2375 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2376 MVE_VFMA_FP,
2377 0xef000c50, 0xffa11f51,
2378 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2379
2380 /* Vector VFMS floating point. */
2381 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2382 MVE_VFMS_FP,
2383 0xef200c50, 0xffa11f51,
2384 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2385
2386 /* Vector VFMAS, vector * scalar. */
2387 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2388 MVE_VFMAS_FP_SCALAR,
2389 0xee311e40, 0xefb11f70,
2390 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2391
2392 /* Vector VHADD T1. */
2393 {ARM_FEATURE_COPROC (FPU_MVE),
2394 MVE_VHADD_T1,
2395 0xef000040, 0xef811f51,
2396 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2397
2398 /* Vector VHADD T2. */
2399 {ARM_FEATURE_COPROC (FPU_MVE),
2400 MVE_VHADD_T2,
2401 0xee000f40, 0xef811f70,
2402 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2403
2404 /* Vector VHSUB T1. */
2405 {ARM_FEATURE_COPROC (FPU_MVE),
2406 MVE_VHSUB_T1,
2407 0xef000240, 0xef811f51,
2408 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2409
2410 /* Vector VHSUB T2. */
2411 {ARM_FEATURE_COPROC (FPU_MVE),
2412 MVE_VHSUB_T2,
2413 0xee001f40, 0xef811f70,
2414 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2415
2416 /* Vector VCMUL. */
2417 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2418 MVE_VCMUL_FP,
2419 0xee300e00, 0xefb10f50,
2420 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2421
2422 /* Vector VCTP. */
2423 {ARM_FEATURE_COPROC (FPU_MVE),
2424 MVE_VCTP,
2425 0xf000e801, 0xffc0ffff,
2426 "vctp%v.%20-21s\t%16-19r"},
2427
2428 /* Vector VDUP. */
2429 {ARM_FEATURE_COPROC (FPU_MVE),
2430 MVE_VDUP,
2431 0xeea00b10, 0xffb10f5f,
2432 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2433
2434 /* Vector VRHADD. */
2435 {ARM_FEATURE_COPROC (FPU_MVE),
2436 MVE_VRHADD,
2437 0xef000140, 0xef811f51,
2438 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2439
2440 /* Vector VCVT. */
2441 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2442 MVE_VCVT_FP_FIX_VEC,
2443 0xef800c50, 0xef801cd1,
2444 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2445
2446 /* Vector VCVT. */
2447 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2448 MVE_VCVT_BETWEEN_FP_INT,
2449 0xffb30640, 0xffb31e51,
2450 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2451
2452 /* Vector VCVT between single and half-precision float, bottom half. */
2453 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2454 MVE_VCVT_FP_HALF_FP,
2455 0xee3f0e01, 0xefbf1fd1,
2456 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2457
2458 /* Vector VCVT between single and half-precision float, top half. */
2459 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2460 MVE_VCVT_FP_HALF_FP,
2461 0xee3f1e01, 0xefbf1fd1,
2462 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2463
2464 /* Vector VCVT. */
2465 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2466 MVE_VCVT_FROM_FP_TO_INT,
2467 0xffb30040, 0xffb31c51,
2468 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2469
2470 /* Vector VDDUP. */
2471 {ARM_FEATURE_COPROC (FPU_MVE),
2472 MVE_VDDUP,
2473 0xee011f6e, 0xff811f7e,
2474 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2475
2476 /* Vector VDWDUP. */
2477 {ARM_FEATURE_COPROC (FPU_MVE),
2478 MVE_VDWDUP,
2479 0xee011f60, 0xff811f70,
2480 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2481
2482 /* Vector VHCADD. */
2483 {ARM_FEATURE_COPROC (FPU_MVE),
2484 MVE_VHCADD,
2485 0xee000f00, 0xff810f51,
2486 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2487
2488 /* Vector VIWDUP. */
2489 {ARM_FEATURE_COPROC (FPU_MVE),
2490 MVE_VIWDUP,
2491 0xee010f60, 0xff811f70,
2492 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2493
2494 /* Vector VIDUP. */
2495 {ARM_FEATURE_COPROC (FPU_MVE),
2496 MVE_VIDUP,
2497 0xee010f6e, 0xff811f7e,
2498 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2499
2500 /* Vector VLD2. */
2501 {ARM_FEATURE_COPROC (FPU_MVE),
2502 MVE_VLD2,
2503 0xfc901e00, 0xff901e5f,
2504 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2505
2506 /* Vector VLD4. */
2507 {ARM_FEATURE_COPROC (FPU_MVE),
2508 MVE_VLD4,
2509 0xfc901e01, 0xff901e1f,
2510 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2511
2512 /* Vector VLDRB gather load. */
2513 {ARM_FEATURE_COPROC (FPU_MVE),
2514 MVE_VLDRB_GATHER_T1,
2515 0xec900e00, 0xefb01e50,
2516 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2517
2518 /* Vector VLDRH gather load. */
2519 {ARM_FEATURE_COPROC (FPU_MVE),
2520 MVE_VLDRH_GATHER_T2,
2521 0xec900e10, 0xefb01e50,
2522 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2523
2524 /* Vector VLDRW gather load. */
2525 {ARM_FEATURE_COPROC (FPU_MVE),
2526 MVE_VLDRW_GATHER_T3,
2527 0xfc900f40, 0xffb01fd0,
2528 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2529
2530 /* Vector VLDRD gather load. */
2531 {ARM_FEATURE_COPROC (FPU_MVE),
2532 MVE_VLDRD_GATHER_T4,
2533 0xec900fd0, 0xefb01fd0,
2534 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2535
2536 /* Vector VLDRW gather load. */
2537 {ARM_FEATURE_COPROC (FPU_MVE),
2538 MVE_VLDRW_GATHER_T5,
2539 0xfd101e00, 0xff111f00,
2540 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2541
2542 /* Vector VLDRD gather load, variant T6. */
2543 {ARM_FEATURE_COPROC (FPU_MVE),
2544 MVE_VLDRD_GATHER_T6,
2545 0xfd101f00, 0xff111f00,
2546 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2547
2548 /* Vector VLDRB. */
2549 {ARM_FEATURE_COPROC (FPU_MVE),
2550 MVE_VLDRB_T1,
2551 0xec100e00, 0xee581e00,
2552 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2553
2554 /* Vector VLDRH. */
2555 {ARM_FEATURE_COPROC (FPU_MVE),
2556 MVE_VLDRH_T2,
2557 0xec180e00, 0xee581e00,
2558 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2559
2560 /* Vector VLDRB unsigned, variant T5. */
2561 {ARM_FEATURE_COPROC (FPU_MVE),
2562 MVE_VLDRB_T5,
2563 0xec101e00, 0xfe101f80,
2564 "vldrb%v.u8\t%13-15,22Q, %d"},
2565
2566 /* Vector VLDRH unsigned, variant T6. */
2567 {ARM_FEATURE_COPROC (FPU_MVE),
2568 MVE_VLDRH_T6,
2569 0xec101e80, 0xfe101f80,
2570 "vldrh%v.u16\t%13-15,22Q, %d"},
2571
2572 /* Vector VLDRW unsigned, variant T7. */
2573 {ARM_FEATURE_COPROC (FPU_MVE),
2574 MVE_VLDRW_T7,
2575 0xec101f00, 0xfe101f80,
2576 "vldrw%v.u32\t%13-15,22Q, %d"},
2577
2578 /* Vector VMAX. */
2579 {ARM_FEATURE_COPROC (FPU_MVE),
2580 MVE_VMAX,
2581 0xef000640, 0xef811f51,
2582 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2583
2584 /* Vector VMAXA. */
2585 {ARM_FEATURE_COPROC (FPU_MVE),
2586 MVE_VMAXA,
2587 0xee330e81, 0xffb31fd1,
2588 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2589
2590 /* Vector VMAXNM floating point. */
2591 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2592 MVE_VMAXNM_FP,
2593 0xff000f50, 0xffa11f51,
2594 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2595
2596 /* Vector VMAXNMA floating point. */
2597 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2598 MVE_VMAXNMA_FP,
2599 0xee3f0e81, 0xefbf1fd1,
2600 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2601
2602 /* Vector VMAXNMV floating point. */
2603 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2604 MVE_VMAXNMV_FP,
2605 0xeeee0f00, 0xefff0fd1,
2606 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2607
2608 /* Vector VMAXNMAV floating point. */
2609 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2610 MVE_VMAXNMAV_FP,
2611 0xeeec0f00, 0xefff0fd1,
2612 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2613
2614 /* Vector VMAXV. */
2615 {ARM_FEATURE_COPROC (FPU_MVE),
2616 MVE_VMAXV,
2617 0xeee20f00, 0xeff30fd1,
2618 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2619
2620 /* Vector VMAXAV. */
2621 {ARM_FEATURE_COPROC (FPU_MVE),
2622 MVE_VMAXAV,
2623 0xeee00f00, 0xfff30fd1,
2624 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2625
2626 /* Vector VMIN. */
2627 {ARM_FEATURE_COPROC (FPU_MVE),
2628 MVE_VMIN,
2629 0xef000650, 0xef811f51,
2630 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2631
2632 /* Vector VMINA. */
2633 {ARM_FEATURE_COPROC (FPU_MVE),
2634 MVE_VMINA,
2635 0xee331e81, 0xffb31fd1,
2636 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2637
2638 /* Vector VMINNM floating point. */
2639 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2640 MVE_VMINNM_FP,
2641 0xff200f50, 0xffa11f51,
2642 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2643
2644 /* Vector VMINNMA floating point. */
2645 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2646 MVE_VMINNMA_FP,
2647 0xee3f1e81, 0xefbf1fd1,
2648 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2649
2650 /* Vector VMINNMV floating point. */
2651 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2652 MVE_VMINNMV_FP,
2653 0xeeee0f80, 0xefff0fd1,
2654 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2655
2656 /* Vector VMINNMAV floating point. */
2657 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2658 MVE_VMINNMAV_FP,
2659 0xeeec0f80, 0xefff0fd1,
2660 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2661
2662 /* Vector VMINV. */
2663 {ARM_FEATURE_COPROC (FPU_MVE),
2664 MVE_VMINV,
2665 0xeee20f80, 0xeff30fd1,
2666 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2667
2668 /* Vector VMINAV. */
2669 {ARM_FEATURE_COPROC (FPU_MVE),
2670 MVE_VMINAV,
2671 0xeee00f80, 0xfff30fd1,
2672 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2673
2674 /* Vector VMLA. */
2675 {ARM_FEATURE_COPROC (FPU_MVE),
2676 MVE_VMLA,
2677 0xee010e40, 0xef811f70,
2678 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2679
2680 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2681 opcode aliasing. */
2682 {ARM_FEATURE_COPROC (FPU_MVE),
2683 MVE_VMLALDAV,
2684 0xee801e00, 0xef801f51,
2685 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2686
2687 {ARM_FEATURE_COPROC (FPU_MVE),
2688 MVE_VMLALDAV,
2689 0xee800e00, 0xef801f51,
2690 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2691
2692 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2693 {ARM_FEATURE_COPROC (FPU_MVE),
2694 MVE_VMLADAV_T1,
2695 0xeef00e00, 0xeff01f51,
2696 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2697
2698 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2699 {ARM_FEATURE_COPROC (FPU_MVE),
2700 MVE_VMLADAV_T2,
2701 0xeef00f00, 0xeff11f51,
2702 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2703
2704 /* Vector VMLADAV T1 variant. */
2705 {ARM_FEATURE_COPROC (FPU_MVE),
2706 MVE_VMLADAV_T1,
2707 0xeef01e00, 0xeff01f51,
2708 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2709
2710 /* Vector VMLADAV T2 variant. */
2711 {ARM_FEATURE_COPROC (FPU_MVE),
2712 MVE_VMLADAV_T2,
2713 0xeef01f00, 0xeff11f51,
2714 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2715
2716 /* Vector VMLAS. */
2717 {ARM_FEATURE_COPROC (FPU_MVE),
2718 MVE_VMLAS,
2719 0xee011e40, 0xef811f70,
2720 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2721
2722 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2723 opcode aliasing. */
2724 {ARM_FEATURE_COPROC (FPU_MVE),
2725 MVE_VRMLSLDAVH,
2726 0xfe800e01, 0xff810f51,
2727 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2728
2729 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2730 opcdoe aliasing. */
2731 {ARM_FEATURE_COPROC (FPU_MVE),
2732 MVE_VMLSLDAV,
2733 0xee800e01, 0xff800f51,
2734 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2735
2736 /* Vector VMLSDAV T1 Variant. */
2737 {ARM_FEATURE_COPROC (FPU_MVE),
2738 MVE_VMLSDAV_T1,
2739 0xeef00e01, 0xfff00f51,
2740 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2741
2742 /* Vector VMLSDAV T2 Variant. */
2743 {ARM_FEATURE_COPROC (FPU_MVE),
2744 MVE_VMLSDAV_T2,
2745 0xfef00e01, 0xfff10f51,
2746 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2747
2748 /* Vector VMOV between gpr and half precision register, op == 0. */
2749 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2750 MVE_VMOV_HFP_TO_GP,
2751 0xee000910, 0xfff00f7f,
2752 "vmov.f16\t%7,16-19F, %12-15r"},
2753
2754 /* Vector VMOV between gpr and half precision register, op == 1. */
2755 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2756 MVE_VMOV_HFP_TO_GP,
2757 0xee100910, 0xfff00f7f,
2758 "vmov.f16\t%12-15r, %7,16-19F"},
2759
2760 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2761 MVE_VMOV_GP_TO_VEC_LANE,
2762 0xee000b10, 0xff900f1f,
2763 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2764
2765 /* Vector VORR immediate to vector.
2766 NOTE: MVE_VORR_IMM must appear in the table
2767 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2768 {ARM_FEATURE_COPROC (FPU_MVE),
2769 MVE_VORR_IMM,
2770 0xef800050, 0xefb810f0,
2771 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2772
2773 /* Vector VQSHL T2 Variant.
2774 NOTE: MVE_VQSHL_T2 must appear in the table before
2775 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2776 {ARM_FEATURE_COPROC (FPU_MVE),
2777 MVE_VQSHL_T2,
2778 0xef800750, 0xef801fd1,
2779 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2780
2781 /* Vector VQSHLU T3 Variant
2782 NOTE: MVE_VQSHL_T2 must appear in the table before
2783 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2784
2785 {ARM_FEATURE_COPROC (FPU_MVE),
2786 MVE_VQSHLU_T3,
2787 0xff800650, 0xff801fd1,
2788 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2789
2790 /* Vector VRSHR
2791 NOTE: MVE_VRSHR must appear in the table before
2792 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2793 {ARM_FEATURE_COPROC (FPU_MVE),
2794 MVE_VRSHR,
2795 0xef800250, 0xef801fd1,
2796 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2797
2798 /* Vector VSHL.
2799 NOTE: MVE_VSHL must appear in the table before
2800 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2801 {ARM_FEATURE_COPROC (FPU_MVE),
2802 MVE_VSHL_T1,
2803 0xef800550, 0xff801fd1,
2804 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2805
2806 /* Vector VSHR
2807 NOTE: MVE_VSHR must appear in the table before
2808 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2809 {ARM_FEATURE_COPROC (FPU_MVE),
2810 MVE_VSHR,
2811 0xef800050, 0xef801fd1,
2812 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2813
2814 /* Vector VSLI
2815 NOTE: MVE_VSLI must appear in the table before
2816 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2817 {ARM_FEATURE_COPROC (FPU_MVE),
2818 MVE_VSLI,
2819 0xff800550, 0xff801fd1,
2820 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2821
2822 /* Vector VSRI
2823 NOTE: MVE_VSRI must appear in the table before
2824 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2825 {ARM_FEATURE_COPROC (FPU_MVE),
2826 MVE_VSRI,
2827 0xff800450, 0xff801fd1,
2828 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2829
2830 /* Vector VMOV immediate to vector,
2831 cmode == 11x1 -> VMVN which is UNDEFINED
2832 for such a cmode. */
2833 {ARM_FEATURE_COPROC (FPU_MVE),
2834 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2835
2836 /* Vector VMOV immediate to vector. */
2837 {ARM_FEATURE_COPROC (FPU_MVE),
2838 MVE_VMOV_IMM_TO_VEC,
2839 0xef800050, 0xefb810d0,
2840 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2841
2842 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2843 {ARM_FEATURE_COPROC (FPU_MVE),
2844 MVE_VMOV2_VEC_LANE_TO_GP,
2845 0xec000f00, 0xffb01ff0,
2846 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2847
2848 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2849 {ARM_FEATURE_COPROC (FPU_MVE),
2850 MVE_VMOV2_VEC_LANE_TO_GP,
2851 0xec000f10, 0xffb01ff0,
2852 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2853
2854 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2855 {ARM_FEATURE_COPROC (FPU_MVE),
2856 MVE_VMOV2_GP_TO_VEC_LANE,
2857 0xec100f00, 0xffb01ff0,
2858 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2859
2860 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2861 {ARM_FEATURE_COPROC (FPU_MVE),
2862 MVE_VMOV2_GP_TO_VEC_LANE,
2863 0xec100f10, 0xffb01ff0,
2864 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2865
2866 /* Vector VMOV Vector lane to gpr. */
2867 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2868 MVE_VMOV_VEC_LANE_TO_GP,
2869 0xee100b10, 0xff100f1f,
2870 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2871
2872 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2873 to instruction opcode aliasing. */
2874 {ARM_FEATURE_COPROC (FPU_MVE),
2875 MVE_VSHLL_T1,
2876 0xeea00f40, 0xefa00fd1,
2877 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2878
2879 /* Vector VMOVL long. */
2880 {ARM_FEATURE_COPROC (FPU_MVE),
2881 MVE_VMOVL,
2882 0xeea00f40, 0xefa70fd1,
2883 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2884
2885 /* Vector VMOV and narrow. */
2886 {ARM_FEATURE_COPROC (FPU_MVE),
2887 MVE_VMOVN,
2888 0xfe310e81, 0xffb30fd1,
2889 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2890
2891 /* Floating point move extract. */
2892 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2893 MVE_VMOVX,
2894 0xfeb00a40, 0xffbf0fd0,
2895 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2896
2897 /* Vector VMUL floating-point T1 variant. */
2898 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2899 MVE_VMUL_FP_T1,
2900 0xff000d50, 0xffa11f51,
2901 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2902
2903 /* Vector VMUL floating-point T2 variant. */
2904 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2905 MVE_VMUL_FP_T2,
2906 0xee310e60, 0xefb11f70,
2907 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2908
2909 /* Vector VMUL T1 variant. */
2910 {ARM_FEATURE_COPROC (FPU_MVE),
2911 MVE_VMUL_VEC_T1,
2912 0xef000950, 0xff811f51,
2913 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2914
2915 /* Vector VMUL T2 variant. */
2916 {ARM_FEATURE_COPROC (FPU_MVE),
2917 MVE_VMUL_VEC_T2,
2918 0xee011e60, 0xff811f70,
2919 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2920
2921 /* Vector VMULH. */
2922 {ARM_FEATURE_COPROC (FPU_MVE),
2923 MVE_VMULH,
2924 0xee010e01, 0xef811f51,
2925 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2926
2927 /* Vector VRMULH. */
2928 {ARM_FEATURE_COPROC (FPU_MVE),
2929 MVE_VRMULH,
2930 0xee011e01, 0xef811f51,
2931 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2932
2933 /* Vector VMULL integer. */
2934 {ARM_FEATURE_COPROC (FPU_MVE),
2935 MVE_VMULL_INT,
2936 0xee010e00, 0xef810f51,
2937 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2938
2939 /* Vector VMULL polynomial. */
2940 {ARM_FEATURE_COPROC (FPU_MVE),
2941 MVE_VMULL_POLY,
2942 0xee310e00, 0xefb10f51,
2943 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2944
2945 /* Vector VMVN immediate to vector. */
2946 {ARM_FEATURE_COPROC (FPU_MVE),
2947 MVE_VMVN_IMM,
2948 0xef800070, 0xefb810f0,
2949 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2950
2951 /* Vector VMVN register. */
2952 {ARM_FEATURE_COPROC (FPU_MVE),
2953 MVE_VMVN_REG,
2954 0xffb005c0, 0xffbf1fd1,
2955 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2956
2957 /* Vector VNEG floating point. */
2958 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2959 MVE_VNEG_FP,
2960 0xffb107c0, 0xffb31fd1,
2961 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2962
2963 /* Vector VNEG. */
2964 {ARM_FEATURE_COPROC (FPU_MVE),
2965 MVE_VNEG_VEC,
2966 0xffb103c0, 0xffb31fd1,
2967 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2968
2969 /* Vector VORN, vector bitwise or not. */
2970 {ARM_FEATURE_COPROC (FPU_MVE),
2971 MVE_VORN,
2972 0xef300150, 0xffb11f51,
2973 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2974
2975 /* Vector VORR register. */
2976 {ARM_FEATURE_COPROC (FPU_MVE),
2977 MVE_VORR_REG,
2978 0xef200150, 0xffb11f51,
2979 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2980
2981 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2982 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2983 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2984 array. */
2985
2986 {ARM_FEATURE_COPROC (FPU_MVE),
2987 MVE_VMOV_VEC_TO_VEC,
2988 0xef200150, 0xffb11f51,
2989 "vmov%v\t%13-15,22Q, %17-19,7Q"},
2990
2991 /* Vector VQDMULL T1 variant. */
2992 {ARM_FEATURE_COPROC (FPU_MVE),
2993 MVE_VQDMULL_T1,
2994 0xee300f01, 0xefb10f51,
2995 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2996
2997 /* Vector VPNOT. */
2998 {ARM_FEATURE_COPROC (FPU_MVE),
2999 MVE_VPNOT,
3000 0xfe310f4d, 0xffffffff,
3001 "vpnot%v"},
3002
3003 /* Vector VPSEL. */
3004 {ARM_FEATURE_COPROC (FPU_MVE),
3005 MVE_VPSEL,
3006 0xfe310f01, 0xffb11f51,
3007 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3008
3009 /* Vector VQABS. */
3010 {ARM_FEATURE_COPROC (FPU_MVE),
3011 MVE_VQABS,
3012 0xffb00740, 0xffb31fd1,
3013 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3014
3015 /* Vector VQADD T1 variant. */
3016 {ARM_FEATURE_COPROC (FPU_MVE),
3017 MVE_VQADD_T1,
3018 0xef000050, 0xef811f51,
3019 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3020
3021 /* Vector VQADD T2 variant. */
3022 {ARM_FEATURE_COPROC (FPU_MVE),
3023 MVE_VQADD_T2,
3024 0xee000f60, 0xef811f70,
3025 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3026
3027 /* Vector VQDMULL T2 variant. */
3028 {ARM_FEATURE_COPROC (FPU_MVE),
3029 MVE_VQDMULL_T2,
3030 0xee300f60, 0xefb10f70,
3031 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3032
3033 /* Vector VQMOVN. */
3034 {ARM_FEATURE_COPROC (FPU_MVE),
3035 MVE_VQMOVN,
3036 0xee330e01, 0xefb30fd1,
3037 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3038
3039 /* Vector VQMOVUN. */
3040 {ARM_FEATURE_COPROC (FPU_MVE),
3041 MVE_VQMOVUN,
3042 0xee310e81, 0xffb30fd1,
3043 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3044
3045 /* Vector VQDMLADH. */
3046 {ARM_FEATURE_COPROC (FPU_MVE),
3047 MVE_VQDMLADH,
3048 0xee000e00, 0xff810f51,
3049 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3050
3051 /* Vector VQRDMLADH. */
3052 {ARM_FEATURE_COPROC (FPU_MVE),
3053 MVE_VQRDMLADH,
3054 0xee000e01, 0xff810f51,
3055 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3056
3057 /* Vector VQDMLAH. */
3058 {ARM_FEATURE_COPROC (FPU_MVE),
3059 MVE_VQDMLAH,
3060 0xee000e60, 0xff811f70,
3061 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3062
3063 /* Vector VQRDMLAH. */
3064 {ARM_FEATURE_COPROC (FPU_MVE),
3065 MVE_VQRDMLAH,
3066 0xee000e40, 0xff811f70,
3067 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3068
3069 /* Vector VQDMLASH. */
3070 {ARM_FEATURE_COPROC (FPU_MVE),
3071 MVE_VQDMLASH,
3072 0xee001e60, 0xff811f70,
3073 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3074
3075 /* Vector VQRDMLASH. */
3076 {ARM_FEATURE_COPROC (FPU_MVE),
3077 MVE_VQRDMLASH,
3078 0xee001e40, 0xff811f70,
3079 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3080
3081 /* Vector VQDMLSDH. */
3082 {ARM_FEATURE_COPROC (FPU_MVE),
3083 MVE_VQDMLSDH,
3084 0xfe000e00, 0xff810f51,
3085 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3086
3087 /* Vector VQRDMLSDH. */
3088 {ARM_FEATURE_COPROC (FPU_MVE),
3089 MVE_VQRDMLSDH,
3090 0xfe000e01, 0xff810f51,
3091 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3092
3093 /* Vector VQDMULH T1 variant. */
3094 {ARM_FEATURE_COPROC (FPU_MVE),
3095 MVE_VQDMULH_T1,
3096 0xef000b40, 0xff811f51,
3097 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3098
3099 /* Vector VQRDMULH T2 variant. */
3100 {ARM_FEATURE_COPROC (FPU_MVE),
3101 MVE_VQRDMULH_T2,
3102 0xff000b40, 0xff811f51,
3103 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3104
3105 /* Vector VQDMULH T3 variant. */
3106 {ARM_FEATURE_COPROC (FPU_MVE),
3107 MVE_VQDMULH_T3,
3108 0xee010e60, 0xff811f70,
3109 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3110
3111 /* Vector VQRDMULH T4 variant. */
3112 {ARM_FEATURE_COPROC (FPU_MVE),
3113 MVE_VQRDMULH_T4,
3114 0xfe010e60, 0xff811f70,
3115 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3116
3117 /* Vector VQNEG. */
3118 {ARM_FEATURE_COPROC (FPU_MVE),
3119 MVE_VQNEG,
3120 0xffb007c0, 0xffb31fd1,
3121 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3122
3123 /* Vector VQRSHL T1 variant. */
3124 {ARM_FEATURE_COPROC (FPU_MVE),
3125 MVE_VQRSHL_T1,
3126 0xef000550, 0xef811f51,
3127 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3128
3129 /* Vector VQRSHL T2 variant. */
3130 {ARM_FEATURE_COPROC (FPU_MVE),
3131 MVE_VQRSHL_T2,
3132 0xee331ee0, 0xefb31ff0,
3133 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3134
3135 /* Vector VQRSHRN. */
3136 {ARM_FEATURE_COPROC (FPU_MVE),
3137 MVE_VQRSHRN,
3138 0xee800f41, 0xefa00fd1,
3139 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3140
3141 /* Vector VQRSHRUN. */
3142 {ARM_FEATURE_COPROC (FPU_MVE),
3143 MVE_VQRSHRUN,
3144 0xfe800fc0, 0xffa00fd1,
3145 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3146
3147 /* Vector VQSHL T1 Variant. */
3148 {ARM_FEATURE_COPROC (FPU_MVE),
3149 MVE_VQSHL_T1,
3150 0xee311ee0, 0xefb31ff0,
3151 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3152
3153 /* Vector VQSHL T4 Variant. */
3154 {ARM_FEATURE_COPROC (FPU_MVE),
3155 MVE_VQSHL_T4,
3156 0xef000450, 0xef811f51,
3157 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3158
3159 /* Vector VQSHRN. */
3160 {ARM_FEATURE_COPROC (FPU_MVE),
3161 MVE_VQSHRN,
3162 0xee800f40, 0xefa00fd1,
3163 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3164
3165 /* Vector VQSHRUN. */
3166 {ARM_FEATURE_COPROC (FPU_MVE),
3167 MVE_VQSHRUN,
3168 0xee800fc0, 0xffa00fd1,
3169 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3170
3171 /* Vector VQSUB T1 Variant. */
3172 {ARM_FEATURE_COPROC (FPU_MVE),
3173 MVE_VQSUB_T1,
3174 0xef000250, 0xef811f51,
3175 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3176
3177 /* Vector VQSUB T2 Variant. */
3178 {ARM_FEATURE_COPROC (FPU_MVE),
3179 MVE_VQSUB_T2,
3180 0xee001f60, 0xef811f70,
3181 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3182
3183 /* Vector VREV16. */
3184 {ARM_FEATURE_COPROC (FPU_MVE),
3185 MVE_VREV16,
3186 0xffb00140, 0xffb31fd1,
3187 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3188
3189 /* Vector VREV32. */
3190 {ARM_FEATURE_COPROC (FPU_MVE),
3191 MVE_VREV32,
3192 0xffb000c0, 0xffb31fd1,
3193 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3194
3195 /* Vector VREV64. */
3196 {ARM_FEATURE_COPROC (FPU_MVE),
3197 MVE_VREV64,
3198 0xffb00040, 0xffb31fd1,
3199 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3200
3201 /* Vector VRINT floating point. */
3202 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3203 MVE_VRINT_FP,
3204 0xffb20440, 0xffb31c51,
3205 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3206
3207 /* Vector VRMLALDAVH. */
3208 {ARM_FEATURE_COPROC (FPU_MVE),
3209 MVE_VRMLALDAVH,
3210 0xee800f00, 0xef811f51,
3211 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3212
3213 /* Vector VRMLALDAVH. */
3214 {ARM_FEATURE_COPROC (FPU_MVE),
3215 MVE_VRMLALDAVH,
3216 0xee801f00, 0xef811f51,
3217 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3218
3219 /* Vector VRSHL T1 Variant. */
3220 {ARM_FEATURE_COPROC (FPU_MVE),
3221 MVE_VRSHL_T1,
3222 0xef000540, 0xef811f51,
3223 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3224
3225 /* Vector VRSHL T2 Variant. */
3226 {ARM_FEATURE_COPROC (FPU_MVE),
3227 MVE_VRSHL_T2,
3228 0xee331e60, 0xefb31ff0,
3229 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3230
3231 /* Vector VRSHRN. */
3232 {ARM_FEATURE_COPROC (FPU_MVE),
3233 MVE_VRSHRN,
3234 0xfe800fc1, 0xffa00fd1,
3235 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3236
3237 /* Vector VSBC. */
3238 {ARM_FEATURE_COPROC (FPU_MVE),
3239 MVE_VSBC,
3240 0xfe300f00, 0xffb10f51,
3241 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3242
3243 /* Vector VSHL T2 Variant. */
3244 {ARM_FEATURE_COPROC (FPU_MVE),
3245 MVE_VSHL_T2,
3246 0xee311e60, 0xefb31ff0,
3247 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3248
3249 /* Vector VSHL T3 Variant. */
3250 {ARM_FEATURE_COPROC (FPU_MVE),
3251 MVE_VSHL_T3,
3252 0xef000440, 0xef811f51,
3253 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3254
3255 /* Vector VSHLC. */
3256 {ARM_FEATURE_COPROC (FPU_MVE),
3257 MVE_VSHLC,
3258 0xeea00fc0, 0xffa01ff0,
3259 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3260
3261 /* Vector VSHLL T2 Variant. */
3262 {ARM_FEATURE_COPROC (FPU_MVE),
3263 MVE_VSHLL_T2,
3264 0xee310e01, 0xefb30fd1,
3265 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3266
3267 /* Vector VSHRN. */
3268 {ARM_FEATURE_COPROC (FPU_MVE),
3269 MVE_VSHRN,
3270 0xee800fc1, 0xffa00fd1,
3271 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3272
3273 /* Vector VST2 no writeback. */
3274 {ARM_FEATURE_COPROC (FPU_MVE),
3275 MVE_VST2,
3276 0xfc801e00, 0xffb01e5f,
3277 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3278
3279 /* Vector VST2 writeback. */
3280 {ARM_FEATURE_COPROC (FPU_MVE),
3281 MVE_VST2,
3282 0xfca01e00, 0xffb01e5f,
3283 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3284
3285 /* Vector VST4 no writeback. */
3286 {ARM_FEATURE_COPROC (FPU_MVE),
3287 MVE_VST4,
3288 0xfc801e01, 0xffb01e1f,
3289 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3290
3291 /* Vector VST4 writeback. */
3292 {ARM_FEATURE_COPROC (FPU_MVE),
3293 MVE_VST4,
3294 0xfca01e01, 0xffb01e1f,
3295 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3296
3297 /* Vector VSTRB scatter store, T1 variant. */
3298 {ARM_FEATURE_COPROC (FPU_MVE),
3299 MVE_VSTRB_SCATTER_T1,
3300 0xec800e00, 0xffb01e50,
3301 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3302
3303 /* Vector VSTRH scatter store, T2 variant. */
3304 {ARM_FEATURE_COPROC (FPU_MVE),
3305 MVE_VSTRH_SCATTER_T2,
3306 0xec800e10, 0xffb01e50,
3307 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3308
3309 /* Vector VSTRW scatter store, T3 variant. */
3310 {ARM_FEATURE_COPROC (FPU_MVE),
3311 MVE_VSTRW_SCATTER_T3,
3312 0xec800e40, 0xffb01e50,
3313 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3314
3315 /* Vector VSTRD scatter store, T4 variant. */
3316 {ARM_FEATURE_COPROC (FPU_MVE),
3317 MVE_VSTRD_SCATTER_T4,
3318 0xec800fd0, 0xffb01fd0,
3319 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3320
3321 /* Vector VSTRW scatter store, T5 variant. */
3322 {ARM_FEATURE_COPROC (FPU_MVE),
3323 MVE_VSTRW_SCATTER_T5,
3324 0xfd001e00, 0xff111f00,
3325 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3326
3327 /* Vector VSTRD scatter store, T6 variant. */
3328 {ARM_FEATURE_COPROC (FPU_MVE),
3329 MVE_VSTRD_SCATTER_T6,
3330 0xfd001f00, 0xff111f00,
3331 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3332
3333 /* Vector VSTRB. */
3334 {ARM_FEATURE_COPROC (FPU_MVE),
3335 MVE_VSTRB_T1,
3336 0xec000e00, 0xfe581e00,
3337 "vstrb%v.%7-8s\t%13-15Q, %d"},
3338
3339 /* Vector VSTRH. */
3340 {ARM_FEATURE_COPROC (FPU_MVE),
3341 MVE_VSTRH_T2,
3342 0xec080e00, 0xfe581e00,
3343 "vstrh%v.%7-8s\t%13-15Q, %d"},
3344
3345 /* Vector VSTRB variant T5. */
3346 {ARM_FEATURE_COPROC (FPU_MVE),
3347 MVE_VSTRB_T5,
3348 0xec001e00, 0xfe101f80,
3349 "vstrb%v.8\t%13-15,22Q, %d"},
3350
3351 /* Vector VSTRH variant T6. */
3352 {ARM_FEATURE_COPROC (FPU_MVE),
3353 MVE_VSTRH_T6,
3354 0xec001e80, 0xfe101f80,
3355 "vstrh%v.16\t%13-15,22Q, %d"},
3356
3357 /* Vector VSTRW variant T7. */
3358 {ARM_FEATURE_COPROC (FPU_MVE),
3359 MVE_VSTRW_T7,
3360 0xec001f00, 0xfe101f80,
3361 "vstrw%v.32\t%13-15,22Q, %d"},
3362
3363 /* Vector VSUB floating point T1 variant. */
3364 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3365 MVE_VSUB_FP_T1,
3366 0xef200d40, 0xffa11f51,
3367 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3368
3369 /* Vector VSUB floating point T2 variant. */
3370 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3371 MVE_VSUB_FP_T2,
3372 0xee301f40, 0xefb11f70,
3373 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3374
3375 /* Vector VSUB T1 variant. */
3376 {ARM_FEATURE_COPROC (FPU_MVE),
3377 MVE_VSUB_VEC_T1,
3378 0xff000840, 0xff811f51,
3379 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3380
3381 /* Vector VSUB T2 variant. */
3382 {ARM_FEATURE_COPROC (FPU_MVE),
3383 MVE_VSUB_VEC_T2,
3384 0xee011f40, 0xff811f70,
3385 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3386
3387 {ARM_FEATURE_COPROC (FPU_MVE),
3388 MVE_ASRLI,
3389 0xea50012f, 0xfff1813f,
3390 "asrl%c\t%17-19l, %9-11h, %j"},
3391
3392 {ARM_FEATURE_COPROC (FPU_MVE),
3393 MVE_ASRL,
3394 0xea50012d, 0xfff101ff,
3395 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3396
3397 {ARM_FEATURE_COPROC (FPU_MVE),
3398 MVE_LSLLI,
3399 0xea50010f, 0xfff1813f,
3400 "lsll%c\t%17-19l, %9-11h, %j"},
3401
3402 {ARM_FEATURE_COPROC (FPU_MVE),
3403 MVE_LSLL,
3404 0xea50010d, 0xfff101ff,
3405 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3406
3407 {ARM_FEATURE_COPROC (FPU_MVE),
3408 MVE_LSRL,
3409 0xea50011f, 0xfff1813f,
3410 "lsrl%c\t%17-19l, %9-11h, %j"},
3411
3412 {ARM_FEATURE_COPROC (FPU_MVE),
3413 MVE_SQRSHRL,
3414 0xea51012d, 0xfff1017f,
3415 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3416
3417 {ARM_FEATURE_COPROC (FPU_MVE),
3418 MVE_SQRSHR,
3419 0xea500f2d, 0xfff00fff,
3420 "sqrshr%c\t%16-19S, %12-15S"},
3421
3422 {ARM_FEATURE_COPROC (FPU_MVE),
3423 MVE_SQSHLL,
3424 0xea51013f, 0xfff1813f,
3425 "sqshll%c\t%17-19l, %9-11h, %j"},
3426
3427 {ARM_FEATURE_COPROC (FPU_MVE),
3428 MVE_SQSHL,
3429 0xea500f3f, 0xfff08f3f,
3430 "sqshl%c\t%16-19S, %j"},
3431
3432 {ARM_FEATURE_COPROC (FPU_MVE),
3433 MVE_SRSHRL,
3434 0xea51012f, 0xfff1813f,
3435 "srshrl%c\t%17-19l, %9-11h, %j"},
3436
3437 {ARM_FEATURE_COPROC (FPU_MVE),
3438 MVE_SRSHR,
3439 0xea500f2f, 0xfff08f3f,
3440 "srshr%c\t%16-19S, %j"},
3441
3442 {ARM_FEATURE_COPROC (FPU_MVE),
3443 MVE_UQRSHLL,
3444 0xea51010d, 0xfff1017f,
3445 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3446
3447 {ARM_FEATURE_COPROC (FPU_MVE),
3448 MVE_UQRSHL,
3449 0xea500f0d, 0xfff00fff,
3450 "uqrshl%c\t%16-19S, %12-15S"},
3451
3452 {ARM_FEATURE_COPROC (FPU_MVE),
3453 MVE_UQSHLL,
3454 0xea51010f, 0xfff1813f,
3455 "uqshll%c\t%17-19l, %9-11h, %j"},
3456
3457 {ARM_FEATURE_COPROC (FPU_MVE),
3458 MVE_UQSHL,
3459 0xea500f0f, 0xfff08f3f,
3460 "uqshl%c\t%16-19S, %j"},
3461
3462 {ARM_FEATURE_COPROC (FPU_MVE),
3463 MVE_URSHRL,
3464 0xea51011f, 0xfff1813f,
3465 "urshrl%c\t%17-19l, %9-11h, %j"},
3466
3467 {ARM_FEATURE_COPROC (FPU_MVE),
3468 MVE_URSHR,
3469 0xea500f1f, 0xfff08f3f,
3470 "urshr%c\t%16-19S, %j"},
3471
3472 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3473 MVE_CSINC,
3474 0xea509000, 0xfff0f000,
3475 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3476
3477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3478 MVE_CSINV,
3479 0xea50a000, 0xfff0f000,
3480 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3481
3482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3483 MVE_CSET,
3484 0xea5f900f, 0xfffff00f,
3485 "cset\t%8-11S, %4-7C"},
3486
3487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3488 MVE_CSETM,
3489 0xea5fa00f, 0xfffff00f,
3490 "csetm\t%8-11S, %4-7C"},
3491
3492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3493 MVE_CSEL,
3494 0xea508000, 0xfff0f000,
3495 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3496
3497 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3498 MVE_CSNEG,
3499 0xea50b000, 0xfff0f000,
3500 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3501
3502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3503 MVE_CINC,
3504 0xea509000, 0xfff0f000,
3505 "cinc\t%8-11S, %16-19Z, %4-7C"},
3506
3507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3508 MVE_CINV,
3509 0xea50a000, 0xfff0f000,
3510 "cinv\t%8-11S, %16-19Z, %4-7C"},
3511
3512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3513 MVE_CNEG,
3514 0xea50b000, 0xfff0f000,
3515 "cneg\t%8-11S, %16-19Z, %4-7C"},
3516
3517 {ARM_FEATURE_CORE_LOW (0),
3518 MVE_NONE,
3519 0x00000000, 0x00000000, 0}
3520 };
3521
3522 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3523 ordered: they must be searched linearly from the top to obtain a correct
3524 match. */
3525
3526 /* print_insn_arm recognizes the following format control codes:
3527
3528 %% %
3529
3530 %a print address for ldr/str instruction
3531 %s print address for ldr/str halfword/signextend instruction
3532 %S like %s but allow UNPREDICTABLE addressing
3533 %b print branch destination
3534 %c print condition code (always bits 28-31)
3535 %m print register mask for ldm/stm instruction
3536 %o print operand2 (immediate or register + shift)
3537 %p print 'p' iff bits 12-15 are 15
3538 %t print 't' iff bit 21 set and bit 24 clear
3539 %B print arm BLX(1) destination
3540 %C print the PSR sub type.
3541 %U print barrier type.
3542 %P print address for pli instruction.
3543
3544 %<bitfield>r print as an ARM register
3545 %<bitfield>T print as an ARM register + 1
3546 %<bitfield>R as %r but r15 is UNPREDICTABLE
3547 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3548 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3549 %<bitfield>d print the bitfield in decimal
3550 %<bitfield>W print the bitfield plus one in decimal
3551 %<bitfield>x print the bitfield in hex
3552 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3553
3554 %<bitfield>'c print specified char iff bitfield is all ones
3555 %<bitfield>`c print specified char iff bitfield is all zeroes
3556 %<bitfield>?ab... select from array of values in big endian order
3557
3558 %e print arm SMI operand (bits 0..7,8..19).
3559 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3560 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3561 %R print the SPSR/CPSR or banked register of an MRS. */
3562
3563 static const struct opcode32 arm_opcodes[] =
3564 {
3565 /* ARM instructions. */
3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3567 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3569 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3570
3571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3572 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3574 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3576 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3578 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3580 0x00800090, 0x0fa000f0,
3581 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3583 0x00a00090, 0x0fa000f0,
3584 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3585
3586 /* V8.2 RAS extension instructions. */
3587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3588 0xe320f010, 0xffffffff, "esb"},
3589
3590 /* V8 instructions. */
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3592 0x0320f005, 0x0fffffff, "sevl"},
3593 /* Defined in V8 but is in NOP space so available to all arch. */
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3595 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3596 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3597 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3599 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3601 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3603 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3605 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3607 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3609 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3611 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3613 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3615 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3617 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3619 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3621 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3623 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3624 /* CRC32 instructions. */
3625 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3626 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3627 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3628 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3629 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3630 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3631 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3632 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3633 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3634 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3635 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3636 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3637
3638 /* Privileged Access Never extension instructions. */
3639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3640 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3641
3642 /* Virtualization Extension instructions. */
3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3645
3646 /* Integer Divide Extension instructions. */
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3648 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3650 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3651
3652 /* MP Extension instructions. */
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3654
3655 /* Speculation Barriers. */
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3659
3660 /* V7 instructions. */
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3669 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3670
3671 /* ARM V6T2 instructions. */
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3673 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3675 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3677 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3679 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3680
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3682 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3684 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3685
3686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3687 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3689 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3691 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3693 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3694
3695 /* ARM Security extension instructions. */
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3697 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3698
3699 /* ARM V6K instructions. */
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3701 0xf57ff01f, 0xffffffff, "clrex"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3703 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3705 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3707 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3709 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3711 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3713 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3714
3715 /* ARMv8.5-A instructions. */
3716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3717
3718 /* ARM V6K NOP hints. */
3719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3720 0x0320f001, 0x0fffffff, "yield%c"},
3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3722 0x0320f002, 0x0fffffff, "wfe%c"},
3723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3724 0x0320f003, 0x0fffffff, "wfi%c"},
3725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3726 0x0320f004, 0x0fffffff, "sev%c"},
3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3728 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3729
3730 /* ARM V6 instructions. */
3731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3732 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3734 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3736 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3738 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3740 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3742 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3744 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3746 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3748 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3750 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3752 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3754 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3756 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3758 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3760 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3762 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3764 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3766 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3768 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3770 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3772 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3774 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3776 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3778 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3780 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3782 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3784 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3786 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3788 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3790 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3792 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3794 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3796 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3798 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3800 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3802 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3804 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3806 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3808 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3810 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3812 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3814 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3816 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3818 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3820 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3822 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3824 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3826 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3828 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3830 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3832 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3834 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3836 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3838 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3840 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3842 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3844 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3846 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3848 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3850 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3852 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3854 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3856 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3858 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3860 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3862 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3864 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3866 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3868 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3870 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3872 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3874 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3876 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3878 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3880 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3882 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3884 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3886 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3888 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3890 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3892 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3894 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3896 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3898 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3900 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3902 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3904 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3906 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3908 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3910 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3912 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3914 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3916 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3918 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3920 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3922 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3924 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3926 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3928 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3930 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3932 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3934 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3936 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3938 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3940 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3942 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3944 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3946 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3948 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3950 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3952 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3954 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3956 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3958 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3960 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3962 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3964 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3966 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3968 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3970 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3972 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3974 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3975
3976 /* V5J instruction. */
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3978 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3979
3980 /* V5 Instructions. */
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3982 0xe1200070, 0xfff000f0,
3983 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3985 0xfa000000, 0xfe000000, "blx\t%B"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3987 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3989 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3990
3991 /* V5E "El Segundo" Instructions. */
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3993 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3995 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3997 0xf450f000, 0xfc70f000, "pld\t%a"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3999 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4001 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4003 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4005 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4006
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4008 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4010 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4011
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4013 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4015 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4017 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4019 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4020
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4022 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4024 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4026 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4028 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4029
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4031 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4033 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4034
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4036 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4038 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4040 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4042 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4043
4044 /* ARM Instructions. */
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4046 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4047
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4049 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4051 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4053 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4055 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4057 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4059 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4060
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4062 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4064 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4069
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4071 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4073 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4075 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4077 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4078
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4080 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4082 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4084 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4085
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4087 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4091 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4092
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4094 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4096 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4098 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4099
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4105 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4106
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4108 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4110 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4112 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4113
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4115 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4117 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4119 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4120
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4122 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4124 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4126 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4127
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4129 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4131 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4133 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4134
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4136 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4138 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4140 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4141
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4145 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4147 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4148
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4155
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4162
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4164 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4166 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4169
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4171 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4173 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4176
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4178 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4180 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4190 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4191
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4197 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4198
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4204 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4205
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4210
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4213
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4215 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4217 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4218
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4220 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4222 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4224 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4232 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4234 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4236 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4238 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4246 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4248 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4250 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4252 0x092d0000, 0x0fff0000, "push%c\t%m"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4257
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4259 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4267 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4269 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4271 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4273 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4289 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4291 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4293 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4295 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4296
4297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4298 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4300 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4301
4302 /* The rest. */
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4304 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4306 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4307 {ARM_FEATURE_CORE_LOW (0),
4308 0x00000000, 0x00000000, 0}
4309 };
4310
4311 /* print_insn_thumb16 recognizes the following format control codes:
4312
4313 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4314 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4315 %<bitfield>I print bitfield as a signed decimal
4316 (top bit of range being the sign bit)
4317 %N print Thumb register mask (with LR)
4318 %O print Thumb register mask (with PC)
4319 %M print Thumb register mask
4320 %b print CZB's 6-bit unsigned branch destination
4321 %s print Thumb right-shift immediate (6..10; 0 == 32).
4322 %c print the condition code
4323 %C print the condition code, or "s" if not conditional
4324 %x print warning if conditional an not at end of IT block"
4325 %X print "\t; unpredictable <IT:code>" if conditional
4326 %I print IT instruction suffix and operands
4327 %W print Thumb Writeback indicator for LDMIA
4328 %<bitfield>r print bitfield as an ARM register
4329 %<bitfield>d print bitfield as a decimal
4330 %<bitfield>H print (bitfield * 2) as a decimal
4331 %<bitfield>W print (bitfield * 4) as a decimal
4332 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4333 %<bitfield>B print Thumb branch destination (signed displacement)
4334 %<bitfield>c print bitfield as a condition code
4335 %<bitnum>'c print specified char iff bit is one
4336 %<bitnum>?ab print a if bit is one else print b. */
4337
4338 static const struct opcode16 thumb_opcodes[] =
4339 {
4340 /* Thumb instructions. */
4341
4342 /* ARMv8-M Security Extensions instructions. */
4343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4345
4346 /* ARM V8 instructions. */
4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
4349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4350
4351 /* ARM V6K no-argument instructions. */
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4358
4359 /* ARM V6T2 instructions. */
4360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4361 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4363 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4365
4366 /* ARM V6. */
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4378
4379 /* ARM V5 ISA extends Thumb. */
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4381 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4382 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4384 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4385 /* ARM V4T ISA (Thumb v1). */
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4387 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4388 /* Format 4. */
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4405 /* format 13 */
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4408 /* format 5 */
4409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4413 /* format 14 */
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4416 /* format 2 */
4417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4418 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4420 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4422 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4424 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4425 /* format 8 */
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4427 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4429 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4431 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4432 /* format 7 */
4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4434 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4436 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4437 /* format 1 */
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4440 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4443 /* format 3 */
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4448 /* format 6 */
4449 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4451 0x4800, 0xF800,
4452 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4453 /* format 9 */
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4455 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4457 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4459 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4461 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4462 /* format 10 */
4463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4464 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4466 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4467 /* format 11 */
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4469 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4471 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4472 /* format 12 */
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4474 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4476 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4477 /* format 15 */
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4480 /* format 17 */
4481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4482 /* format 16 */
4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4486 /* format 18 */
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4488
4489 /* The E800 .. FFFF range is unconditionally redirected to the
4490 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4491 are processed via that table. Thus, we can never encounter a
4492 bare "second half of BL/BLX(1)" instruction here. */
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4494 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4495 };
4496
4497 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4498 We adopt the convention that hw1 is the high 16 bits of .value and
4499 .mask, hw2 the low 16 bits.
4500
4501 print_insn_thumb32 recognizes the following format control codes:
4502
4503 %% %
4504
4505 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4506 %M print a modified 12-bit immediate (same location)
4507 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4508 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4509 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4510 %S print a possibly-shifted Rm
4511
4512 %L print address for a ldrd/strd instruction
4513 %a print the address of a plain load/store
4514 %w print the width and signedness of a core load/store
4515 %m print register mask for ldm/stm
4516 %n print register mask for clrm
4517
4518 %E print the lsb and width fields of a bfc/bfi instruction
4519 %F print the lsb and width fields of a sbfx/ubfx instruction
4520 %G print a fallback offset for Branch Future instructions
4521 %W print an offset for BF instruction
4522 %Y print an offset for BFL instruction
4523 %Z print an offset for BFCSEL instruction
4524 %Q print an offset for Low Overhead Loop instructions
4525 %P print an offset for Low Overhead Loop end instructions
4526 %b print a conditional branch offset
4527 %B print an unconditional branch offset
4528 %s print the shift field of an SSAT instruction
4529 %R print the rotation field of an SXT instruction
4530 %U print barrier type.
4531 %P print address for pli instruction.
4532 %c print the condition code
4533 %x print warning if conditional an not at end of IT block"
4534 %X print "\t; unpredictable <IT:code>" if conditional
4535
4536 %<bitfield>d print bitfield in decimal
4537 %<bitfield>D print bitfield plus one in decimal
4538 %<bitfield>W print bitfield*4 in decimal
4539 %<bitfield>r print bitfield as an ARM register
4540 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4541 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4542 %<bitfield>c print bitfield as a condition code
4543
4544 %<bitfield>'c print specified char iff bitfield is all ones
4545 %<bitfield>`c print specified char iff bitfield is all zeroes
4546 %<bitfield>?ab... select from array of values in big endian order
4547
4548 With one exception at the bottom (done because BL and BLX(1) need
4549 to come dead last), this table was machine-sorted first in
4550 decreasing order of number of bits set in the mask, then in
4551 increasing numeric order of mask, then in increasing numeric order
4552 of opcode. This order is not the clearest for a human reader, but
4553 is guaranteed never to catch a special-case bit pattern with a more
4554 general mask, which is important, because this instruction encoding
4555 makes heavy use of special-case bit patterns. */
4556 static const struct opcode32 thumb32_opcodes[] =
4557 {
4558 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4559 instructions. */
4560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4561 0xf00fe001, 0xffffffff, "lctp%c"},
4562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4563 0xf02fc001, 0xfffff001, "le\t%P"},
4564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4565 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4567 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4569 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4571 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4572 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4573 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4575 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4576
4577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4578 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4580 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4581 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4582 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4584 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4586 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4587
4588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4589 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4590
4591 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4592 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4593 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4594 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4596 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4597 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4598 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4600 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4601
4602 /* ARM V8.2 RAS extension instructions. */
4603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4604 0xf3af8010, 0xffffffff, "esb"},
4605
4606 /* V8 instructions. */
4607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4608 0xf3af8005, 0xffffffff, "sevl%c.w"},
4609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4610 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4612 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4614 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4616 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4618 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4620 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4622 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4624 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4626 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4628 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4630 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4632 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4634 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4636 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4638 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4639
4640 /* CRC32 instructions. */
4641 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4642 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4643 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4644 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4645 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4646 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4647 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4648 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4649 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4650 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4651 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4652 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4653
4654 /* Speculation Barriers. */
4655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4658
4659 /* V7 instructions. */
4660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4667 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4668 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4669 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4670 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4671
4672 /* Virtualization Extension instructions. */
4673 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4674 /* We skip ERET as that is SUBS pc, lr, #0. */
4675
4676 /* MP Extension instructions. */
4677 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4678
4679 /* Security extension instructions. */
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4681
4682 /* ARMv8.5-A instructions. */
4683 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4684
4685 /* Instructions defined in the basic V6T2 set. */
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4692 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4694
4695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4696 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4698 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4700 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4702 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4704 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4706 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4708 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4710 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4712 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4714 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4716 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4718 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4720 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4722 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4724 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4725 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4726 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4728 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4730 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4732 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4734 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4736 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4738 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4740 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4742 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4744 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4746 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4748 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4750 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4752 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4754 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4756 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4758 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4760 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4762 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4764 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4766 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4768 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4770 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4772 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4774 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4776 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4778 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4780 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4782 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4784 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4786 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4788 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4790 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4792 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4794 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4796 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4798 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4800 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4802 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4842 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4851 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4852 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4919 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4920 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xf810f000, 0xff70f000, "pld%c\t%a"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952 0xfb100000, 0xfff000c0,
4953 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4955 0xfbc00080, 0xfff000c0,
4956 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4968 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4970 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4972 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4994 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5026 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5028 0xe9400000, 0xff500000,
5029 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5031 0xe9500000, 0xff500000,
5032 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034 0xe8600000, 0xff700000,
5035 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5037 0xe8700000, 0xff700000,
5038 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5043
5044 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
5045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5046 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5052 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5053
5054 /* These have been 32-bit since the invention of Thumb. */
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5056 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5058 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5059
5060 /* Fallback. */
5061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5062 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5063 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5064 };
5065
5066 static const char *const arm_conditional[] =
5067 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5068 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5069
5070 static const char *const arm_fp_const[] =
5071 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5072
5073 static const char *const arm_shift[] =
5074 {"lsl", "lsr", "asr", "ror"};
5075
5076 typedef struct
5077 {
5078 const char *name;
5079 const char *description;
5080 const char *reg_names[16];
5081 }
5082 arm_regname;
5083
5084 static const arm_regname regnames[] =
5085 {
5086 { "reg-names-raw", N_("Select raw register names"),
5087 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5088 { "reg-names-gcc", N_("Select register names used by GCC"),
5089 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5090 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5091 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5092 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5093 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5094 { "reg-names-apcs", N_("Select register names used in the APCS"),
5095 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5096 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5097 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5098 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5099 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
5100 };
5101
5102 static const char *const iwmmxt_wwnames[] =
5103 {"b", "h", "w", "d"};
5104
5105 static const char *const iwmmxt_wwssnames[] =
5106 {"b", "bus", "bc", "bss",
5107 "h", "hus", "hc", "hss",
5108 "w", "wus", "wc", "wss",
5109 "d", "dus", "dc", "dss"
5110 };
5111
5112 static const char *const iwmmxt_regnames[] =
5113 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5114 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5115 };
5116
5117 static const char *const iwmmxt_cregnames[] =
5118 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5119 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5120 };
5121
5122 static const char *const vec_condnames[] =
5123 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5124 };
5125
5126 static const char *const mve_predicatenames[] =
5127 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5128 "eee", "ee", "eet", "e", "ett", "et", "ete"
5129 };
5130
5131 /* Names for 2-bit size field for mve vector isntructions. */
5132 static const char *const mve_vec_sizename[] =
5133 { "8", "16", "32", "64"};
5134
5135 /* Indicates whether we are processing a then predicate,
5136 else predicate or none at all. */
5137 enum vpt_pred_state
5138 {
5139 PRED_NONE,
5140 PRED_THEN,
5141 PRED_ELSE
5142 };
5143
5144 /* Information used to process a vpt block and subsequent instructions. */
5145 struct vpt_block
5146 {
5147 /* Are we in a vpt block. */
5148 bfd_boolean in_vpt_block;
5149
5150 /* Next predicate state if in vpt block. */
5151 enum vpt_pred_state next_pred_state;
5152
5153 /* Mask from vpt/vpst instruction. */
5154 long predicate_mask;
5155
5156 /* Instruction number in vpt block. */
5157 long current_insn_num;
5158
5159 /* Number of instructions in vpt block.. */
5160 long num_pred_insn;
5161 };
5162
5163 static struct vpt_block vpt_block_state =
5164 {
5165 FALSE,
5166 PRED_NONE,
5167 0,
5168 0,
5169 0
5170 };
5171
5172 /* Default to GCC register name set. */
5173 static unsigned int regname_selected = 1;
5174
5175 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5176 #define arm_regnames regnames[regname_selected].reg_names
5177
5178 static bfd_boolean force_thumb = FALSE;
5179
5180 /* Current IT instruction state. This contains the same state as the IT
5181 bits in the CPSR. */
5182 static unsigned int ifthen_state;
5183 /* IT state for the next instruction. */
5184 static unsigned int ifthen_next_state;
5185 /* The address of the insn for which the IT state is valid. */
5186 static bfd_vma ifthen_address;
5187 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5188 /* Indicates that the current Conditional state is unconditional or outside
5189 an IT block. */
5190 #define COND_UNCOND 16
5191
5192 \f
5193 /* Functions. */
5194 /* Extract the predicate mask for a VPT or VPST instruction.
5195 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5196
5197 static long
5198 mve_extract_pred_mask (long given)
5199 {
5200 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5201 }
5202
5203 /* Return the number of instructions in a MVE predicate block. */
5204 static long
5205 num_instructions_vpt_block (long given)
5206 {
5207 long mask = mve_extract_pred_mask (given);
5208 if (mask == 0)
5209 return 0;
5210
5211 if (mask == 8)
5212 return 1;
5213
5214 if ((mask & 7) == 4)
5215 return 2;
5216
5217 if ((mask & 3) == 2)
5218 return 3;
5219
5220 if ((mask & 1) == 1)
5221 return 4;
5222
5223 return 0;
5224 }
5225
5226 static void
5227 mark_outside_vpt_block (void)
5228 {
5229 vpt_block_state.in_vpt_block = FALSE;
5230 vpt_block_state.next_pred_state = PRED_NONE;
5231 vpt_block_state.predicate_mask = 0;
5232 vpt_block_state.current_insn_num = 0;
5233 vpt_block_state.num_pred_insn = 0;
5234 }
5235
5236 static void
5237 mark_inside_vpt_block (long given)
5238 {
5239 vpt_block_state.in_vpt_block = TRUE;
5240 vpt_block_state.next_pred_state = PRED_THEN;
5241 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5242 vpt_block_state.current_insn_num = 0;
5243 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5244 assert (vpt_block_state.num_pred_insn >= 1);
5245 }
5246
5247 static enum vpt_pred_state
5248 invert_next_predicate_state (enum vpt_pred_state astate)
5249 {
5250 if (astate == PRED_THEN)
5251 return PRED_ELSE;
5252 else if (astate == PRED_ELSE)
5253 return PRED_THEN;
5254 else
5255 return PRED_NONE;
5256 }
5257
5258 static enum vpt_pred_state
5259 update_next_predicate_state (void)
5260 {
5261 long pred_mask = vpt_block_state.predicate_mask;
5262 long mask_for_insn = 0;
5263
5264 switch (vpt_block_state.current_insn_num)
5265 {
5266 case 1:
5267 mask_for_insn = 8;
5268 break;
5269
5270 case 2:
5271 mask_for_insn = 4;
5272 break;
5273
5274 case 3:
5275 mask_for_insn = 2;
5276 break;
5277
5278 case 4:
5279 return PRED_NONE;
5280 }
5281
5282 if (pred_mask & mask_for_insn)
5283 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5284 else
5285 return vpt_block_state.next_pred_state;
5286 }
5287
5288 static void
5289 update_vpt_block_state (void)
5290 {
5291 vpt_block_state.current_insn_num++;
5292 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5293 {
5294 /* No more instructions to process in vpt block. */
5295 mark_outside_vpt_block ();
5296 return;
5297 }
5298
5299 vpt_block_state.next_pred_state = update_next_predicate_state ();
5300 }
5301
5302 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5303 Returns pointer to following character of the format string and
5304 fills in *VALUEP and *WIDTHP with the extracted value and number of
5305 bits extracted. WIDTHP can be NULL. */
5306
5307 static const char *
5308 arm_decode_bitfield (const char *ptr,
5309 unsigned long insn,
5310 unsigned long *valuep,
5311 int *widthp)
5312 {
5313 unsigned long value = 0;
5314 int width = 0;
5315
5316 do
5317 {
5318 int start, end;
5319 int bits;
5320
5321 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5322 start = start * 10 + *ptr - '0';
5323 if (*ptr == '-')
5324 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5325 end = end * 10 + *ptr - '0';
5326 else
5327 end = start;
5328 bits = end - start;
5329 if (bits < 0)
5330 abort ();
5331 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5332 width += bits + 1;
5333 }
5334 while (*ptr++ == ',');
5335 *valuep = value;
5336 if (widthp)
5337 *widthp = width;
5338 return ptr - 1;
5339 }
5340
5341 static void
5342 arm_decode_shift (long given, fprintf_ftype func, void *stream,
5343 bfd_boolean print_shift)
5344 {
5345 func (stream, "%s", arm_regnames[given & 0xf]);
5346
5347 if ((given & 0xff0) != 0)
5348 {
5349 if ((given & 0x10) == 0)
5350 {
5351 int amount = (given & 0xf80) >> 7;
5352 int shift = (given & 0x60) >> 5;
5353
5354 if (amount == 0)
5355 {
5356 if (shift == 3)
5357 {
5358 func (stream, ", rrx");
5359 return;
5360 }
5361
5362 amount = 32;
5363 }
5364
5365 if (print_shift)
5366 func (stream, ", %s #%d", arm_shift[shift], amount);
5367 else
5368 func (stream, ", #%d", amount);
5369 }
5370 else if ((given & 0x80) == 0x80)
5371 func (stream, "\t; <illegal shifter operand>");
5372 else if (print_shift)
5373 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5374 arm_regnames[(given & 0xf00) >> 8]);
5375 else
5376 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
5377 }
5378 }
5379
5380 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5381
5382 static bfd_boolean
5383 is_mve_okay_in_it (enum mve_instructions matched_insn)
5384 {
5385 switch (matched_insn)
5386 {
5387 case MVE_VMOV_GP_TO_VEC_LANE:
5388 case MVE_VMOV2_VEC_LANE_TO_GP:
5389 case MVE_VMOV2_GP_TO_VEC_LANE:
5390 case MVE_VMOV_VEC_LANE_TO_GP:
5391 case MVE_LSLL:
5392 case MVE_LSLLI:
5393 case MVE_LSRL:
5394 case MVE_ASRL:
5395 case MVE_ASRLI:
5396 case MVE_SQRSHRL:
5397 case MVE_SQRSHR:
5398 case MVE_UQRSHL:
5399 case MVE_UQRSHLL:
5400 case MVE_UQSHL:
5401 case MVE_UQSHLL:
5402 case MVE_URSHRL:
5403 case MVE_URSHR:
5404 case MVE_SRSHRL:
5405 case MVE_SRSHR:
5406 case MVE_SQSHLL:
5407 case MVE_SQSHL:
5408 return TRUE;
5409 default:
5410 return FALSE;
5411 }
5412 }
5413
5414 static bfd_boolean
5415 is_mve_architecture (struct disassemble_info *info)
5416 {
5417 struct arm_private_data *private_data = info->private_data;
5418 arm_feature_set allowed_arches = private_data->features;
5419
5420 arm_feature_set arm_ext_v8_1m_main
5421 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5422
5423 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5424 && !ARM_CPU_IS_ANY (allowed_arches))
5425 return TRUE;
5426 else
5427 return FALSE;
5428 }
5429
5430 static bfd_boolean
5431 is_vpt_instruction (long given)
5432 {
5433
5434 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5435 if ((given & 0x0040e000) == 0)
5436 return FALSE;
5437
5438 /* VPT floating point T1 variant. */
5439 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5440 /* VPT floating point T2 variant. */
5441 || ((given & 0xefb10f50) == 0xee310f40)
5442 /* VPT vector T1 variant. */
5443 || ((given & 0xff811f51) == 0xfe010f00)
5444 /* VPT vector T2 variant. */
5445 || ((given & 0xff811f51) == 0xfe010f01
5446 && ((given & 0x300000) != 0x300000))
5447 /* VPT vector T3 variant. */
5448 || ((given & 0xff811f50) == 0xfe011f00)
5449 /* VPT vector T4 variant. */
5450 || ((given & 0xff811f70) == 0xfe010f40)
5451 /* VPT vector T5 variant. */
5452 || ((given & 0xff811f70) == 0xfe010f60)
5453 /* VPT vector T6 variant. */
5454 || ((given & 0xff811f50) == 0xfe011f40)
5455 /* VPST vector T variant. */
5456 || ((given & 0xffbf1fff) == 0xfe310f4d))
5457 return TRUE;
5458 else
5459 return FALSE;
5460 }
5461
5462 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5463 and ending bitfield = END. END must be greater than START. */
5464
5465 static unsigned long
5466 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5467 {
5468 int bits = end - start;
5469
5470 if (bits < 0)
5471 abort ();
5472
5473 return ((given >> start) & ((2ul << bits) - 1));
5474 }
5475
5476 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5477 START:END and START2:END2. END/END2 must be greater than
5478 START/START2. */
5479
5480 static unsigned long
5481 arm_decode_field_multiple (unsigned long given, unsigned int start,
5482 unsigned int end, unsigned int start2,
5483 unsigned int end2)
5484 {
5485 int bits = end - start;
5486 int bits2 = end2 - start2;
5487 unsigned long value = 0;
5488 int width = 0;
5489
5490 if (bits2 < 0)
5491 abort ();
5492
5493 value = arm_decode_field (given, start, end);
5494 width += bits + 1;
5495
5496 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5497 return value;
5498 }
5499
5500 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5501 This helps us decode instructions that change mnemonic depending on specific
5502 operand values/encodings. */
5503
5504 static bfd_boolean
5505 is_mve_encoding_conflict (unsigned long given,
5506 enum mve_instructions matched_insn)
5507 {
5508 switch (matched_insn)
5509 {
5510 case MVE_VPST:
5511 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5512 return TRUE;
5513 else
5514 return FALSE;
5515
5516 case MVE_VPT_FP_T1:
5517 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5518 return TRUE;
5519 if ((arm_decode_field (given, 12, 12) == 0)
5520 && (arm_decode_field (given, 0, 0) == 1))
5521 return TRUE;
5522 return FALSE;
5523
5524 case MVE_VPT_FP_T2:
5525 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5526 return TRUE;
5527 if (arm_decode_field (given, 0, 3) == 0xd)
5528 return TRUE;
5529 return FALSE;
5530
5531 case MVE_VPT_VEC_T1:
5532 case MVE_VPT_VEC_T2:
5533 case MVE_VPT_VEC_T3:
5534 case MVE_VPT_VEC_T4:
5535 case MVE_VPT_VEC_T5:
5536 case MVE_VPT_VEC_T6:
5537 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5538 return TRUE;
5539 if (arm_decode_field (given, 20, 21) == 3)
5540 return TRUE;
5541 return FALSE;
5542
5543 case MVE_VCMP_FP_T1:
5544 if ((arm_decode_field (given, 12, 12) == 0)
5545 && (arm_decode_field (given, 0, 0) == 1))
5546 return TRUE;
5547 else
5548 return FALSE;
5549
5550 case MVE_VCMP_FP_T2:
5551 if (arm_decode_field (given, 0, 3) == 0xd)
5552 return TRUE;
5553 else
5554 return FALSE;
5555
5556 case MVE_VQADD_T2:
5557 case MVE_VQSUB_T2:
5558 case MVE_VMUL_VEC_T2:
5559 case MVE_VMULH:
5560 case MVE_VRMULH:
5561 case MVE_VMLA:
5562 case MVE_VMAX:
5563 case MVE_VMIN:
5564 case MVE_VBRSR:
5565 case MVE_VADD_VEC_T2:
5566 case MVE_VSUB_VEC_T2:
5567 case MVE_VABAV:
5568 case MVE_VQRSHL_T1:
5569 case MVE_VQSHL_T4:
5570 case MVE_VRSHL_T1:
5571 case MVE_VSHL_T3:
5572 case MVE_VCADD_VEC:
5573 case MVE_VHCADD:
5574 case MVE_VDDUP:
5575 case MVE_VIDUP:
5576 case MVE_VQRDMLADH:
5577 case MVE_VQDMLAH:
5578 case MVE_VQRDMLAH:
5579 case MVE_VQDMLASH:
5580 case MVE_VQRDMLASH:
5581 case MVE_VQDMLSDH:
5582 case MVE_VQRDMLSDH:
5583 case MVE_VQDMULH_T3:
5584 case MVE_VQRDMULH_T4:
5585 case MVE_VQDMLADH:
5586 case MVE_VMLAS:
5587 case MVE_VMULL_INT:
5588 case MVE_VHADD_T2:
5589 case MVE_VHSUB_T2:
5590 case MVE_VCMP_VEC_T1:
5591 case MVE_VCMP_VEC_T2:
5592 case MVE_VCMP_VEC_T3:
5593 case MVE_VCMP_VEC_T4:
5594 case MVE_VCMP_VEC_T5:
5595 case MVE_VCMP_VEC_T6:
5596 if (arm_decode_field (given, 20, 21) == 3)
5597 return TRUE;
5598 else
5599 return FALSE;
5600
5601 case MVE_VLD2:
5602 case MVE_VLD4:
5603 case MVE_VST2:
5604 case MVE_VST4:
5605 if (arm_decode_field (given, 7, 8) == 3)
5606 return TRUE;
5607 else
5608 return FALSE;
5609
5610 case MVE_VSTRB_T1:
5611 case MVE_VSTRH_T2:
5612 if ((arm_decode_field (given, 24, 24) == 0)
5613 && (arm_decode_field (given, 21, 21) == 0))
5614 {
5615 return TRUE;
5616 }
5617 else if ((arm_decode_field (given, 7, 8) == 3))
5618 return TRUE;
5619 else
5620 return FALSE;
5621
5622 case MVE_VSTRB_T5:
5623 case MVE_VSTRH_T6:
5624 case MVE_VSTRW_T7:
5625 if ((arm_decode_field (given, 24, 24) == 0)
5626 && (arm_decode_field (given, 21, 21) == 0))
5627 {
5628 return TRUE;
5629 }
5630 else
5631 return FALSE;
5632
5633 case MVE_VCVT_FP_FIX_VEC:
5634 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5635
5636 case MVE_VBIC_IMM:
5637 case MVE_VORR_IMM:
5638 {
5639 unsigned long cmode = arm_decode_field (given, 8, 11);
5640
5641 if ((cmode & 1) == 0)
5642 return TRUE;
5643 else if ((cmode & 0xc) == 0xc)
5644 return TRUE;
5645 else
5646 return FALSE;
5647 }
5648
5649 case MVE_VMVN_IMM:
5650 {
5651 unsigned long cmode = arm_decode_field (given, 8, 11);
5652
5653 if ((cmode & 9) == 1)
5654 return TRUE;
5655 else if ((cmode & 5) == 1)
5656 return TRUE;
5657 else if ((cmode & 0xe) == 0xe)
5658 return TRUE;
5659 else
5660 return FALSE;
5661 }
5662
5663 case MVE_VMOV_IMM_TO_VEC:
5664 if ((arm_decode_field (given, 5, 5) == 1)
5665 && (arm_decode_field (given, 8, 11) != 0xe))
5666 return TRUE;
5667 else
5668 return FALSE;
5669
5670 case MVE_VMOVL:
5671 {
5672 unsigned long size = arm_decode_field (given, 19, 20);
5673 if ((size == 0) || (size == 3))
5674 return TRUE;
5675 else
5676 return FALSE;
5677 }
5678
5679 case MVE_VMAXA:
5680 case MVE_VMINA:
5681 case MVE_VMAXV:
5682 case MVE_VMAXAV:
5683 case MVE_VMINV:
5684 case MVE_VMINAV:
5685 case MVE_VQRSHL_T2:
5686 case MVE_VQSHL_T1:
5687 case MVE_VRSHL_T2:
5688 case MVE_VSHL_T2:
5689 case MVE_VSHLL_T2:
5690 case MVE_VADDV:
5691 case MVE_VMOVN:
5692 case MVE_VQMOVUN:
5693 case MVE_VQMOVN:
5694 if (arm_decode_field (given, 18, 19) == 3)
5695 return TRUE;
5696 else
5697 return FALSE;
5698
5699 case MVE_VMLSLDAV:
5700 case MVE_VRMLSLDAVH:
5701 case MVE_VMLALDAV:
5702 case MVE_VADDLV:
5703 if (arm_decode_field (given, 20, 22) == 7)
5704 return TRUE;
5705 else
5706 return FALSE;
5707
5708 case MVE_VRMLALDAVH:
5709 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5710 return TRUE;
5711 else
5712 return FALSE;
5713
5714 case MVE_VDWDUP:
5715 case MVE_VIWDUP:
5716 if ((arm_decode_field (given, 20, 21) == 3)
5717 || (arm_decode_field (given, 1, 3) == 7))
5718 return TRUE;
5719 else
5720 return FALSE;
5721
5722
5723 case MVE_VSHLL_T1:
5724 if (arm_decode_field (given, 16, 18) == 0)
5725 {
5726 unsigned long sz = arm_decode_field (given, 19, 20);
5727
5728 if ((sz == 1) || (sz == 2))
5729 return TRUE;
5730 else
5731 return FALSE;
5732 }
5733 else
5734 return FALSE;
5735
5736 case MVE_VQSHL_T2:
5737 case MVE_VQSHLU_T3:
5738 case MVE_VRSHR:
5739 case MVE_VSHL_T1:
5740 case MVE_VSHR:
5741 case MVE_VSLI:
5742 case MVE_VSRI:
5743 if (arm_decode_field (given, 19, 21) == 0)
5744 return TRUE;
5745 else
5746 return FALSE;
5747
5748 case MVE_VCTP:
5749 if (arm_decode_field (given, 16, 19) == 0xf)
5750 return TRUE;
5751 else
5752 return FALSE;
5753
5754 case MVE_ASRLI:
5755 case MVE_ASRL:
5756 case MVE_LSLLI:
5757 case MVE_LSLL:
5758 case MVE_LSRL:
5759 case MVE_SQRSHRL:
5760 case MVE_SQSHLL:
5761 case MVE_SRSHRL:
5762 case MVE_UQRSHLL:
5763 case MVE_UQSHLL:
5764 case MVE_URSHRL:
5765 if (arm_decode_field (given, 9, 11) == 0x7)
5766 return TRUE;
5767 else
5768 return FALSE;
5769
5770 case MVE_CSINC:
5771 case MVE_CSINV:
5772 {
5773 unsigned long rm, rn;
5774 rm = arm_decode_field (given, 0, 3);
5775 rn = arm_decode_field (given, 16, 19);
5776 /* CSET/CSETM. */
5777 if (rm == 0xf && rn == 0xf)
5778 return TRUE;
5779 /* CINC/CINV. */
5780 else if (rn == rm && rn != 0xf)
5781 return TRUE;
5782 }
5783 /* Fall through. */
5784 case MVE_CSEL:
5785 case MVE_CSNEG:
5786 if (arm_decode_field (given, 0, 3) == 0xd)
5787 return TRUE;
5788 /* CNEG. */
5789 else if (matched_insn == MVE_CSNEG)
5790 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5791 return TRUE;
5792 return FALSE;
5793
5794 default:
5795 case MVE_VADD_FP_T1:
5796 case MVE_VADD_FP_T2:
5797 case MVE_VADD_VEC_T1:
5798 return FALSE;
5799
5800 }
5801 }
5802
5803 static void
5804 print_mve_vld_str_addr (struct disassemble_info *info,
5805 unsigned long given,
5806 enum mve_instructions matched_insn)
5807 {
5808 void *stream = info->stream;
5809 fprintf_ftype func = info->fprintf_func;
5810
5811 unsigned long p, w, gpr, imm, add, mod_imm;
5812
5813 imm = arm_decode_field (given, 0, 6);
5814 mod_imm = imm;
5815
5816 switch (matched_insn)
5817 {
5818 case MVE_VLDRB_T1:
5819 case MVE_VSTRB_T1:
5820 gpr = arm_decode_field (given, 16, 18);
5821 break;
5822
5823 case MVE_VLDRH_T2:
5824 case MVE_VSTRH_T2:
5825 gpr = arm_decode_field (given, 16, 18);
5826 mod_imm = imm << 1;
5827 break;
5828
5829 case MVE_VLDRH_T6:
5830 case MVE_VSTRH_T6:
5831 gpr = arm_decode_field (given, 16, 19);
5832 mod_imm = imm << 1;
5833 break;
5834
5835 case MVE_VLDRW_T7:
5836 case MVE_VSTRW_T7:
5837 gpr = arm_decode_field (given, 16, 19);
5838 mod_imm = imm << 2;
5839 break;
5840
5841 case MVE_VLDRB_T5:
5842 case MVE_VSTRB_T5:
5843 gpr = arm_decode_field (given, 16, 19);
5844 break;
5845
5846 default:
5847 return;
5848 }
5849
5850 p = arm_decode_field (given, 24, 24);
5851 w = arm_decode_field (given, 21, 21);
5852
5853 add = arm_decode_field (given, 23, 23);
5854
5855 char * add_sub;
5856
5857 /* Don't print anything for '+' as it is implied. */
5858 if (add == 1)
5859 add_sub = "";
5860 else
5861 add_sub = "-";
5862
5863 if (p == 1)
5864 {
5865 /* Offset mode. */
5866 if (w == 0)
5867 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5868 /* Pre-indexed mode. */
5869 else
5870 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5871 }
5872 else if ((p == 0) && (w == 1))
5873 /* Post-index mode. */
5874 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5875 }
5876
5877 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5878 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5879 this encoding is undefined. */
5880
5881 static bfd_boolean
5882 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5883 enum mve_undefined *undefined_code)
5884 {
5885 *undefined_code = UNDEF_NONE;
5886
5887 switch (matched_insn)
5888 {
5889 case MVE_VDUP:
5890 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5891 {
5892 *undefined_code = UNDEF_SIZE_3;
5893 return TRUE;
5894 }
5895 else
5896 return FALSE;
5897
5898 case MVE_VQADD_T1:
5899 case MVE_VQSUB_T1:
5900 case MVE_VMUL_VEC_T1:
5901 case MVE_VABD_VEC:
5902 case MVE_VADD_VEC_T1:
5903 case MVE_VSUB_VEC_T1:
5904 case MVE_VQDMULH_T1:
5905 case MVE_VQRDMULH_T2:
5906 case MVE_VRHADD:
5907 case MVE_VHADD_T1:
5908 case MVE_VHSUB_T1:
5909 if (arm_decode_field (given, 20, 21) == 3)
5910 {
5911 *undefined_code = UNDEF_SIZE_3;
5912 return TRUE;
5913 }
5914 else
5915 return FALSE;
5916
5917 case MVE_VLDRB_T1:
5918 if (arm_decode_field (given, 7, 8) == 3)
5919 {
5920 *undefined_code = UNDEF_SIZE_3;
5921 return TRUE;
5922 }
5923 else
5924 return FALSE;
5925
5926 case MVE_VLDRH_T2:
5927 if (arm_decode_field (given, 7, 8) <= 1)
5928 {
5929 *undefined_code = UNDEF_SIZE_LE_1;
5930 return TRUE;
5931 }
5932 else
5933 return FALSE;
5934
5935 case MVE_VSTRB_T1:
5936 if ((arm_decode_field (given, 7, 8) == 0))
5937 {
5938 *undefined_code = UNDEF_SIZE_0;
5939 return TRUE;
5940 }
5941 else
5942 return FALSE;
5943
5944 case MVE_VSTRH_T2:
5945 if ((arm_decode_field (given, 7, 8) <= 1))
5946 {
5947 *undefined_code = UNDEF_SIZE_LE_1;
5948 return TRUE;
5949 }
5950 else
5951 return FALSE;
5952
5953 case MVE_VLDRB_GATHER_T1:
5954 if (arm_decode_field (given, 7, 8) == 3)
5955 {
5956 *undefined_code = UNDEF_SIZE_3;
5957 return TRUE;
5958 }
5959 else if ((arm_decode_field (given, 28, 28) == 0)
5960 && (arm_decode_field (given, 7, 8) == 0))
5961 {
5962 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5963 return TRUE;
5964 }
5965 else
5966 return FALSE;
5967
5968 case MVE_VLDRH_GATHER_T2:
5969 if (arm_decode_field (given, 7, 8) == 3)
5970 {
5971 *undefined_code = UNDEF_SIZE_3;
5972 return TRUE;
5973 }
5974 else if ((arm_decode_field (given, 28, 28) == 0)
5975 && (arm_decode_field (given, 7, 8) == 1))
5976 {
5977 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5978 return TRUE;
5979 }
5980 else if (arm_decode_field (given, 7, 8) == 0)
5981 {
5982 *undefined_code = UNDEF_SIZE_0;
5983 return TRUE;
5984 }
5985 else
5986 return FALSE;
5987
5988 case MVE_VLDRW_GATHER_T3:
5989 if (arm_decode_field (given, 7, 8) != 2)
5990 {
5991 *undefined_code = UNDEF_SIZE_NOT_2;
5992 return TRUE;
5993 }
5994 else if (arm_decode_field (given, 28, 28) == 0)
5995 {
5996 *undefined_code = UNDEF_NOT_UNSIGNED;
5997 return TRUE;
5998 }
5999 else
6000 return FALSE;
6001
6002 case MVE_VLDRD_GATHER_T4:
6003 if (arm_decode_field (given, 7, 8) != 3)
6004 {
6005 *undefined_code = UNDEF_SIZE_NOT_3;
6006 return TRUE;
6007 }
6008 else if (arm_decode_field (given, 28, 28) == 0)
6009 {
6010 *undefined_code = UNDEF_NOT_UNSIGNED;
6011 return TRUE;
6012 }
6013 else
6014 return FALSE;
6015
6016 case MVE_VSTRB_SCATTER_T1:
6017 if (arm_decode_field (given, 7, 8) == 3)
6018 {
6019 *undefined_code = UNDEF_SIZE_3;
6020 return TRUE;
6021 }
6022 else
6023 return FALSE;
6024
6025 case MVE_VSTRH_SCATTER_T2:
6026 {
6027 unsigned long size = arm_decode_field (given, 7, 8);
6028 if (size == 3)
6029 {
6030 *undefined_code = UNDEF_SIZE_3;
6031 return TRUE;
6032 }
6033 else if (size == 0)
6034 {
6035 *undefined_code = UNDEF_SIZE_0;
6036 return TRUE;
6037 }
6038 else
6039 return FALSE;
6040 }
6041
6042 case MVE_VSTRW_SCATTER_T3:
6043 if (arm_decode_field (given, 7, 8) != 2)
6044 {
6045 *undefined_code = UNDEF_SIZE_NOT_2;
6046 return TRUE;
6047 }
6048 else
6049 return FALSE;
6050
6051 case MVE_VSTRD_SCATTER_T4:
6052 if (arm_decode_field (given, 7, 8) != 3)
6053 {
6054 *undefined_code = UNDEF_SIZE_NOT_3;
6055 return TRUE;
6056 }
6057 else
6058 return FALSE;
6059
6060 case MVE_VCVT_FP_FIX_VEC:
6061 {
6062 unsigned long imm6 = arm_decode_field (given, 16, 21);
6063 if ((imm6 & 0x20) == 0)
6064 {
6065 *undefined_code = UNDEF_VCVT_IMM6;
6066 return TRUE;
6067 }
6068
6069 if ((arm_decode_field (given, 9, 9) == 0)
6070 && ((imm6 & 0x30) == 0x20))
6071 {
6072 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6073 return TRUE;
6074 }
6075
6076 return FALSE;
6077 }
6078
6079 case MVE_VNEG_FP:
6080 case MVE_VABS_FP:
6081 case MVE_VCVT_BETWEEN_FP_INT:
6082 case MVE_VCVT_FROM_FP_TO_INT:
6083 {
6084 unsigned long size = arm_decode_field (given, 18, 19);
6085 if (size == 0)
6086 {
6087 *undefined_code = UNDEF_SIZE_0;
6088 return TRUE;
6089 }
6090 else if (size == 3)
6091 {
6092 *undefined_code = UNDEF_SIZE_3;
6093 return TRUE;
6094 }
6095 else
6096 return FALSE;
6097 }
6098
6099 case MVE_VMOV_VEC_LANE_TO_GP:
6100 {
6101 unsigned long op1 = arm_decode_field (given, 21, 22);
6102 unsigned long op2 = arm_decode_field (given, 5, 6);
6103 unsigned long u = arm_decode_field (given, 23, 23);
6104
6105 if ((op2 == 0) && (u == 1))
6106 {
6107 if ((op1 == 0) || (op1 == 1))
6108 {
6109 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6110 return TRUE;
6111 }
6112 else
6113 return FALSE;
6114 }
6115 else if (op2 == 2)
6116 {
6117 if ((op1 == 0) || (op1 == 1))
6118 {
6119 *undefined_code = UNDEF_BAD_OP1_OP2;
6120 return TRUE;
6121 }
6122 else
6123 return FALSE;
6124 }
6125
6126 return FALSE;
6127 }
6128
6129 case MVE_VMOV_GP_TO_VEC_LANE:
6130 if (arm_decode_field (given, 5, 6) == 2)
6131 {
6132 unsigned long op1 = arm_decode_field (given, 21, 22);
6133 if ((op1 == 0) || (op1 == 1))
6134 {
6135 *undefined_code = UNDEF_BAD_OP1_OP2;
6136 return TRUE;
6137 }
6138 else
6139 return FALSE;
6140 }
6141 else
6142 return FALSE;
6143
6144 case MVE_VMOV_VEC_TO_VEC:
6145 if ((arm_decode_field (given, 5, 5) == 1)
6146 || (arm_decode_field (given, 22, 22) == 1))
6147 return TRUE;
6148 return FALSE;
6149
6150 case MVE_VMOV_IMM_TO_VEC:
6151 if (arm_decode_field (given, 5, 5) == 0)
6152 {
6153 unsigned long cmode = arm_decode_field (given, 8, 11);
6154
6155 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6156 {
6157 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6158 return TRUE;
6159 }
6160 else
6161 return FALSE;
6162 }
6163 else
6164 return FALSE;
6165
6166 case MVE_VSHLL_T2:
6167 case MVE_VMOVN:
6168 if (arm_decode_field (given, 18, 19) == 2)
6169 {
6170 *undefined_code = UNDEF_SIZE_2;
6171 return TRUE;
6172 }
6173 else
6174 return FALSE;
6175
6176 case MVE_VRMLALDAVH:
6177 case MVE_VMLADAV_T1:
6178 case MVE_VMLADAV_T2:
6179 case MVE_VMLALDAV:
6180 if ((arm_decode_field (given, 28, 28) == 1)
6181 && (arm_decode_field (given, 12, 12) == 1))
6182 {
6183 *undefined_code = UNDEF_XCHG_UNS;
6184 return TRUE;
6185 }
6186 else
6187 return FALSE;
6188
6189 case MVE_VQSHRN:
6190 case MVE_VQSHRUN:
6191 case MVE_VSHLL_T1:
6192 case MVE_VSHRN:
6193 {
6194 unsigned long sz = arm_decode_field (given, 19, 20);
6195 if (sz == 1)
6196 return FALSE;
6197 else if ((sz & 2) == 2)
6198 return FALSE;
6199 else
6200 {
6201 *undefined_code = UNDEF_SIZE;
6202 return TRUE;
6203 }
6204 }
6205 break;
6206
6207 case MVE_VQSHL_T2:
6208 case MVE_VQSHLU_T3:
6209 case MVE_VRSHR:
6210 case MVE_VSHL_T1:
6211 case MVE_VSHR:
6212 case MVE_VSLI:
6213 case MVE_VSRI:
6214 {
6215 unsigned long sz = arm_decode_field (given, 19, 21);
6216 if ((sz & 7) == 1)
6217 return FALSE;
6218 else if ((sz & 6) == 2)
6219 return FALSE;
6220 else if ((sz & 4) == 4)
6221 return FALSE;
6222 else
6223 {
6224 *undefined_code = UNDEF_SIZE;
6225 return TRUE;
6226 }
6227 }
6228
6229 case MVE_VQRSHRN:
6230 case MVE_VQRSHRUN:
6231 if (arm_decode_field (given, 19, 20) == 0)
6232 {
6233 *undefined_code = UNDEF_SIZE_0;
6234 return TRUE;
6235 }
6236 else
6237 return FALSE;
6238
6239 case MVE_VABS_VEC:
6240 if (arm_decode_field (given, 18, 19) == 3)
6241 {
6242 *undefined_code = UNDEF_SIZE_3;
6243 return TRUE;
6244 }
6245 else
6246 return FALSE;
6247
6248 case MVE_VQNEG:
6249 case MVE_VQABS:
6250 case MVE_VNEG_VEC:
6251 case MVE_VCLS:
6252 case MVE_VCLZ:
6253 if (arm_decode_field (given, 18, 19) == 3)
6254 {
6255 *undefined_code = UNDEF_SIZE_3;
6256 return TRUE;
6257 }
6258 else
6259 return FALSE;
6260
6261 case MVE_VREV16:
6262 if (arm_decode_field (given, 18, 19) == 0)
6263 return FALSE;
6264 else
6265 {
6266 *undefined_code = UNDEF_SIZE_NOT_0;
6267 return TRUE;
6268 }
6269
6270 case MVE_VREV32:
6271 {
6272 unsigned long size = arm_decode_field (given, 18, 19);
6273 if ((size & 2) == 2)
6274 {
6275 *undefined_code = UNDEF_SIZE_2;
6276 return TRUE;
6277 }
6278 else
6279 return FALSE;
6280 }
6281
6282 case MVE_VREV64:
6283 if (arm_decode_field (given, 18, 19) != 3)
6284 return FALSE;
6285 else
6286 {
6287 *undefined_code = UNDEF_SIZE_3;
6288 return TRUE;
6289 }
6290
6291 default:
6292 return FALSE;
6293 }
6294 }
6295
6296 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6297 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6298 why this encoding is unpredictable. */
6299
6300 static bfd_boolean
6301 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6302 enum mve_unpredictable *unpredictable_code)
6303 {
6304 *unpredictable_code = UNPRED_NONE;
6305
6306 switch (matched_insn)
6307 {
6308 case MVE_VCMP_FP_T2:
6309 case MVE_VPT_FP_T2:
6310 if ((arm_decode_field (given, 12, 12) == 0)
6311 && (arm_decode_field (given, 5, 5) == 1))
6312 {
6313 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6314 return TRUE;
6315 }
6316 else
6317 return FALSE;
6318
6319 case MVE_VPT_VEC_T4:
6320 case MVE_VPT_VEC_T5:
6321 case MVE_VPT_VEC_T6:
6322 case MVE_VCMP_VEC_T4:
6323 case MVE_VCMP_VEC_T5:
6324 case MVE_VCMP_VEC_T6:
6325 if (arm_decode_field (given, 0, 3) == 0xd)
6326 {
6327 *unpredictable_code = UNPRED_R13;
6328 return TRUE;
6329 }
6330 else
6331 return FALSE;
6332
6333 case MVE_VDUP:
6334 {
6335 unsigned long gpr = arm_decode_field (given, 12, 15);
6336 if (gpr == 0xd)
6337 {
6338 *unpredictable_code = UNPRED_R13;
6339 return TRUE;
6340 }
6341 else if (gpr == 0xf)
6342 {
6343 *unpredictable_code = UNPRED_R15;
6344 return TRUE;
6345 }
6346
6347 return FALSE;
6348 }
6349
6350 case MVE_VQADD_T2:
6351 case MVE_VQSUB_T2:
6352 case MVE_VMUL_FP_T2:
6353 case MVE_VMUL_VEC_T2:
6354 case MVE_VMLA:
6355 case MVE_VBRSR:
6356 case MVE_VADD_FP_T2:
6357 case MVE_VSUB_FP_T2:
6358 case MVE_VADD_VEC_T2:
6359 case MVE_VSUB_VEC_T2:
6360 case MVE_VQRSHL_T2:
6361 case MVE_VQSHL_T1:
6362 case MVE_VRSHL_T2:
6363 case MVE_VSHL_T2:
6364 case MVE_VSHLC:
6365 case MVE_VQDMLAH:
6366 case MVE_VQRDMLAH:
6367 case MVE_VQDMLASH:
6368 case MVE_VQRDMLASH:
6369 case MVE_VQDMULH_T3:
6370 case MVE_VQRDMULH_T4:
6371 case MVE_VMLAS:
6372 case MVE_VFMA_FP_SCALAR:
6373 case MVE_VFMAS_FP_SCALAR:
6374 case MVE_VHADD_T2:
6375 case MVE_VHSUB_T2:
6376 {
6377 unsigned long gpr = arm_decode_field (given, 0, 3);
6378 if (gpr == 0xd)
6379 {
6380 *unpredictable_code = UNPRED_R13;
6381 return TRUE;
6382 }
6383 else if (gpr == 0xf)
6384 {
6385 *unpredictable_code = UNPRED_R15;
6386 return TRUE;
6387 }
6388
6389 return FALSE;
6390 }
6391
6392 case MVE_VLD2:
6393 case MVE_VST2:
6394 {
6395 unsigned long rn = arm_decode_field (given, 16, 19);
6396
6397 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6398 {
6399 *unpredictable_code = UNPRED_R13_AND_WB;
6400 return TRUE;
6401 }
6402
6403 if (rn == 0xf)
6404 {
6405 *unpredictable_code = UNPRED_R15;
6406 return TRUE;
6407 }
6408
6409 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6410 {
6411 *unpredictable_code = UNPRED_Q_GT_6;
6412 return TRUE;
6413 }
6414 else
6415 return FALSE;
6416 }
6417
6418 case MVE_VLD4:
6419 case MVE_VST4:
6420 {
6421 unsigned long rn = arm_decode_field (given, 16, 19);
6422
6423 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6424 {
6425 *unpredictable_code = UNPRED_R13_AND_WB;
6426 return TRUE;
6427 }
6428
6429 if (rn == 0xf)
6430 {
6431 *unpredictable_code = UNPRED_R15;
6432 return TRUE;
6433 }
6434
6435 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6436 {
6437 *unpredictable_code = UNPRED_Q_GT_4;
6438 return TRUE;
6439 }
6440 else
6441 return FALSE;
6442 }
6443
6444 case MVE_VLDRB_T5:
6445 case MVE_VLDRH_T6:
6446 case MVE_VLDRW_T7:
6447 case MVE_VSTRB_T5:
6448 case MVE_VSTRH_T6:
6449 case MVE_VSTRW_T7:
6450 {
6451 unsigned long rn = arm_decode_field (given, 16, 19);
6452
6453 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6454 {
6455 *unpredictable_code = UNPRED_R13_AND_WB;
6456 return TRUE;
6457 }
6458 else if (rn == 0xf)
6459 {
6460 *unpredictable_code = UNPRED_R15;
6461 return TRUE;
6462 }
6463 else
6464 return FALSE;
6465 }
6466
6467 case MVE_VLDRB_GATHER_T1:
6468 if (arm_decode_field (given, 0, 0) == 1)
6469 {
6470 *unpredictable_code = UNPRED_OS;
6471 return TRUE;
6472 }
6473
6474 /* fall through. */
6475 /* To handle common code with T2-T4 variants. */
6476 case MVE_VLDRH_GATHER_T2:
6477 case MVE_VLDRW_GATHER_T3:
6478 case MVE_VLDRD_GATHER_T4:
6479 {
6480 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6481 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6482
6483 if (qd == qm)
6484 {
6485 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6486 return TRUE;
6487 }
6488
6489 if (arm_decode_field (given, 16, 19) == 0xf)
6490 {
6491 *unpredictable_code = UNPRED_R15;
6492 return TRUE;
6493 }
6494
6495 return FALSE;
6496 }
6497
6498 case MVE_VLDRW_GATHER_T5:
6499 case MVE_VLDRD_GATHER_T6:
6500 {
6501 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6502 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6503
6504 if (qd == qm)
6505 {
6506 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6507 return TRUE;
6508 }
6509 else
6510 return FALSE;
6511 }
6512
6513 case MVE_VSTRB_SCATTER_T1:
6514 if (arm_decode_field (given, 16, 19) == 0xf)
6515 {
6516 *unpredictable_code = UNPRED_R15;
6517 return TRUE;
6518 }
6519 else if (arm_decode_field (given, 0, 0) == 1)
6520 {
6521 *unpredictable_code = UNPRED_OS;
6522 return TRUE;
6523 }
6524 else
6525 return FALSE;
6526
6527 case MVE_VSTRH_SCATTER_T2:
6528 case MVE_VSTRW_SCATTER_T3:
6529 case MVE_VSTRD_SCATTER_T4:
6530 if (arm_decode_field (given, 16, 19) == 0xf)
6531 {
6532 *unpredictable_code = UNPRED_R15;
6533 return TRUE;
6534 }
6535 else
6536 return FALSE;
6537
6538 case MVE_VMOV2_VEC_LANE_TO_GP:
6539 case MVE_VMOV2_GP_TO_VEC_LANE:
6540 case MVE_VCVT_BETWEEN_FP_INT:
6541 case MVE_VCVT_FROM_FP_TO_INT:
6542 {
6543 unsigned long rt = arm_decode_field (given, 0, 3);
6544 unsigned long rt2 = arm_decode_field (given, 16, 19);
6545
6546 if ((rt == 0xd) || (rt2 == 0xd))
6547 {
6548 *unpredictable_code = UNPRED_R13;
6549 return TRUE;
6550 }
6551 else if ((rt == 0xf) || (rt2 == 0xf))
6552 {
6553 *unpredictable_code = UNPRED_R15;
6554 return TRUE;
6555 }
6556 else if (rt == rt2)
6557 {
6558 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6559 return TRUE;
6560 }
6561
6562 return FALSE;
6563 }
6564
6565 case MVE_VMAXV:
6566 case MVE_VMAXAV:
6567 case MVE_VMAXNMV_FP:
6568 case MVE_VMAXNMAV_FP:
6569 case MVE_VMINNMV_FP:
6570 case MVE_VMINNMAV_FP:
6571 case MVE_VMINV:
6572 case MVE_VMINAV:
6573 case MVE_VABAV:
6574 case MVE_VMOV_HFP_TO_GP:
6575 case MVE_VMOV_GP_TO_VEC_LANE:
6576 case MVE_VMOV_VEC_LANE_TO_GP:
6577 {
6578 unsigned long rda = arm_decode_field (given, 12, 15);
6579 if (rda == 0xd)
6580 {
6581 *unpredictable_code = UNPRED_R13;
6582 return TRUE;
6583 }
6584 else if (rda == 0xf)
6585 {
6586 *unpredictable_code = UNPRED_R15;
6587 return TRUE;
6588 }
6589
6590 return FALSE;
6591 }
6592
6593 case MVE_VMULL_INT:
6594 {
6595 unsigned long Qd;
6596 unsigned long Qm;
6597 unsigned long Qn;
6598
6599 if (arm_decode_field (given, 20, 21) == 2)
6600 {
6601 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6602 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6603 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6604
6605 if ((Qd == Qn) || (Qd == Qm))
6606 {
6607 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6608 return TRUE;
6609 }
6610 else
6611 return FALSE;
6612 }
6613 else
6614 return FALSE;
6615 }
6616
6617 case MVE_VCMUL_FP:
6618 case MVE_VQDMULL_T1:
6619 {
6620 unsigned long Qd;
6621 unsigned long Qm;
6622 unsigned long Qn;
6623
6624 if (arm_decode_field (given, 28, 28) == 1)
6625 {
6626 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6627 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6628 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6629
6630 if ((Qd == Qn) || (Qd == Qm))
6631 {
6632 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6633 return TRUE;
6634 }
6635 else
6636 return FALSE;
6637 }
6638 else
6639 return FALSE;
6640 }
6641
6642 case MVE_VQDMULL_T2:
6643 {
6644 unsigned long gpr = arm_decode_field (given, 0, 3);
6645 if (gpr == 0xd)
6646 {
6647 *unpredictable_code = UNPRED_R13;
6648 return TRUE;
6649 }
6650 else if (gpr == 0xf)
6651 {
6652 *unpredictable_code = UNPRED_R15;
6653 return TRUE;
6654 }
6655
6656 if (arm_decode_field (given, 28, 28) == 1)
6657 {
6658 unsigned long Qd
6659 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6660 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6661
6662 if (Qd == Qn)
6663 {
6664 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6665 return TRUE;
6666 }
6667 else
6668 return FALSE;
6669 }
6670
6671 return FALSE;
6672 }
6673
6674 case MVE_VMLSLDAV:
6675 case MVE_VRMLSLDAVH:
6676 case MVE_VMLALDAV:
6677 case MVE_VADDLV:
6678 if (arm_decode_field (given, 20, 22) == 6)
6679 {
6680 *unpredictable_code = UNPRED_R13;
6681 return TRUE;
6682 }
6683 else
6684 return FALSE;
6685
6686 case MVE_VDWDUP:
6687 case MVE_VIWDUP:
6688 if (arm_decode_field (given, 1, 3) == 6)
6689 {
6690 *unpredictable_code = UNPRED_R13;
6691 return TRUE;
6692 }
6693 else
6694 return FALSE;
6695
6696 case MVE_VCADD_VEC:
6697 case MVE_VHCADD:
6698 {
6699 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6700 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6701 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6702 {
6703 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6704 return TRUE;
6705 }
6706 else
6707 return FALSE;
6708 }
6709
6710 case MVE_VCADD_FP:
6711 {
6712 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6713 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6714 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6715 {
6716 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6717 return TRUE;
6718 }
6719 else
6720 return FALSE;
6721 }
6722
6723 case MVE_VCMLA_FP:
6724 {
6725 unsigned long Qda;
6726 unsigned long Qm;
6727 unsigned long Qn;
6728
6729 if (arm_decode_field (given, 20, 20) == 1)
6730 {
6731 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6732 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6733 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6734
6735 if ((Qda == Qn) || (Qda == Qm))
6736 {
6737 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6738 return TRUE;
6739 }
6740 else
6741 return FALSE;
6742 }
6743 else
6744 return FALSE;
6745
6746 }
6747
6748 case MVE_VCTP:
6749 if (arm_decode_field (given, 16, 19) == 0xd)
6750 {
6751 *unpredictable_code = UNPRED_R13;
6752 return TRUE;
6753 }
6754 else
6755 return FALSE;
6756
6757 case MVE_VREV64:
6758 {
6759 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6760 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6761
6762 if (qd == qm)
6763 {
6764 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6765 return TRUE;
6766 }
6767 else
6768 return FALSE;
6769 }
6770
6771 case MVE_LSLL:
6772 case MVE_LSLLI:
6773 case MVE_LSRL:
6774 case MVE_ASRL:
6775 case MVE_ASRLI:
6776 case MVE_UQSHLL:
6777 case MVE_UQRSHLL:
6778 case MVE_URSHRL:
6779 case MVE_SRSHRL:
6780 case MVE_SQSHLL:
6781 case MVE_SQRSHRL:
6782 {
6783 unsigned long gpr = arm_decode_field (given, 9, 11);
6784 gpr = ((gpr << 1) | 1);
6785 if (gpr == 0xd)
6786 {
6787 *unpredictable_code = UNPRED_R13;
6788 return TRUE;
6789 }
6790 else if (gpr == 0xf)
6791 {
6792 *unpredictable_code = UNPRED_R15;
6793 return TRUE;
6794 }
6795
6796 return FALSE;
6797 }
6798
6799 default:
6800 return FALSE;
6801 }
6802 }
6803
6804 static void
6805 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6806 {
6807 unsigned long op1 = arm_decode_field (given, 21, 22);
6808 unsigned long op2 = arm_decode_field (given, 5, 6);
6809 unsigned long h = arm_decode_field (given, 16, 16);
6810 unsigned long index_operand, esize, targetBeat, idx;
6811 void *stream = info->stream;
6812 fprintf_ftype func = info->fprintf_func;
6813
6814 if ((op1 & 0x2) == 0x2)
6815 {
6816 index_operand = op2;
6817 esize = 8;
6818 }
6819 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6820 {
6821 index_operand = op2 >> 1;
6822 esize = 16;
6823 }
6824 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6825 {
6826 index_operand = 0;
6827 esize = 32;
6828 }
6829 else
6830 {
6831 func (stream, "<undefined index>");
6832 return;
6833 }
6834
6835 targetBeat = (op1 & 0x1) | (h << 1);
6836 idx = index_operand + targetBeat * (32/esize);
6837
6838 func (stream, "%lu", idx);
6839 }
6840
6841 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6842 in length and integer of floating-point type. */
6843 static void
6844 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6845 unsigned int ibit_loc, const struct mopcode32 *insn)
6846 {
6847 int bits = 0;
6848 int cmode = (given >> 8) & 0xf;
6849 int op = (given >> 5) & 0x1;
6850 unsigned long value = 0, hival = 0;
6851 unsigned shift;
6852 int size = 0;
6853 int isfloat = 0;
6854 void *stream = info->stream;
6855 fprintf_ftype func = info->fprintf_func;
6856
6857 /* On Neon the 'i' bit is at bit 24, on mve it is
6858 at bit 28. */
6859 bits |= ((given >> ibit_loc) & 1) << 7;
6860 bits |= ((given >> 16) & 7) << 4;
6861 bits |= ((given >> 0) & 15) << 0;
6862
6863 if (cmode < 8)
6864 {
6865 shift = (cmode >> 1) & 3;
6866 value = (unsigned long) bits << (8 * shift);
6867 size = 32;
6868 }
6869 else if (cmode < 12)
6870 {
6871 shift = (cmode >> 1) & 1;
6872 value = (unsigned long) bits << (8 * shift);
6873 size = 16;
6874 }
6875 else if (cmode < 14)
6876 {
6877 shift = (cmode & 1) + 1;
6878 value = (unsigned long) bits << (8 * shift);
6879 value |= (1ul << (8 * shift)) - 1;
6880 size = 32;
6881 }
6882 else if (cmode == 14)
6883 {
6884 if (op)
6885 {
6886 /* Bit replication into bytes. */
6887 int ix;
6888 unsigned long mask;
6889
6890 value = 0;
6891 hival = 0;
6892 for (ix = 7; ix >= 0; ix--)
6893 {
6894 mask = ((bits >> ix) & 1) ? 0xff : 0;
6895 if (ix <= 3)
6896 value = (value << 8) | mask;
6897 else
6898 hival = (hival << 8) | mask;
6899 }
6900 size = 64;
6901 }
6902 else
6903 {
6904 /* Byte replication. */
6905 value = (unsigned long) bits;
6906 size = 8;
6907 }
6908 }
6909 else if (!op)
6910 {
6911 /* Floating point encoding. */
6912 int tmp;
6913
6914 value = (unsigned long) (bits & 0x7f) << 19;
6915 value |= (unsigned long) (bits & 0x80) << 24;
6916 tmp = bits & 0x40 ? 0x3c : 0x40;
6917 value |= (unsigned long) tmp << 24;
6918 size = 32;
6919 isfloat = 1;
6920 }
6921 else
6922 {
6923 func (stream, "<illegal constant %.8x:%x:%x>",
6924 bits, cmode, op);
6925 size = 32;
6926 return;
6927 }
6928
6929 // printU determines whether the immediate value should be printed as
6930 // unsigned.
6931 unsigned printU = 0;
6932 switch (insn->mve_op)
6933 {
6934 default:
6935 break;
6936 // We want this for instructions that don't have a 'signed' type
6937 case MVE_VBIC_IMM:
6938 case MVE_VORR_IMM:
6939 case MVE_VMVN_IMM:
6940 case MVE_VMOV_IMM_TO_VEC:
6941 printU = 1;
6942 break;
6943 }
6944 switch (size)
6945 {
6946 case 8:
6947 func (stream, "#%ld\t; 0x%.2lx", value, value);
6948 break;
6949
6950 case 16:
6951 func (stream,
6952 printU
6953 ? "#%lu\t; 0x%.4lx"
6954 : "#%ld\t; 0x%.4lx", value, value);
6955 break;
6956
6957 case 32:
6958 if (isfloat)
6959 {
6960 unsigned char valbytes[4];
6961 double fvalue;
6962
6963 /* Do this a byte at a time so we don't have to
6964 worry about the host's endianness. */
6965 valbytes[0] = value & 0xff;
6966 valbytes[1] = (value >> 8) & 0xff;
6967 valbytes[2] = (value >> 16) & 0xff;
6968 valbytes[3] = (value >> 24) & 0xff;
6969
6970 floatformat_to_double
6971 (& floatformat_ieee_single_little, valbytes,
6972 & fvalue);
6973
6974 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6975 value);
6976 }
6977 else
6978 func (stream,
6979 printU
6980 ? "#%lu\t; 0x%.8lx"
6981 : "#%ld\t; 0x%.8lx",
6982 (long) (((value & 0x80000000L) != 0)
6983 && !printU
6984 ? value | ~0xffffffffL : value),
6985 value);
6986 break;
6987
6988 case 64:
6989 func (stream, "#0x%.8lx%.8lx", hival, value);
6990 break;
6991
6992 default:
6993 abort ();
6994 }
6995
6996 }
6997
6998 static void
6999 print_mve_undefined (struct disassemble_info *info,
7000 enum mve_undefined undefined_code)
7001 {
7002 void *stream = info->stream;
7003 fprintf_ftype func = info->fprintf_func;
7004
7005 func (stream, "\t\tundefined instruction: ");
7006
7007 switch (undefined_code)
7008 {
7009 case UNDEF_SIZE:
7010 func (stream, "illegal size");
7011 break;
7012
7013 case UNDEF_SIZE_0:
7014 func (stream, "size equals zero");
7015 break;
7016
7017 case UNDEF_SIZE_2:
7018 func (stream, "size equals two");
7019 break;
7020
7021 case UNDEF_SIZE_3:
7022 func (stream, "size equals three");
7023 break;
7024
7025 case UNDEF_SIZE_LE_1:
7026 func (stream, "size <= 1");
7027 break;
7028
7029 case UNDEF_SIZE_NOT_0:
7030 func (stream, "size not equal to 0");
7031 break;
7032
7033 case UNDEF_SIZE_NOT_2:
7034 func (stream, "size not equal to 2");
7035 break;
7036
7037 case UNDEF_SIZE_NOT_3:
7038 func (stream, "size not equal to 3");
7039 break;
7040
7041 case UNDEF_NOT_UNS_SIZE_0:
7042 func (stream, "not unsigned and size = zero");
7043 break;
7044
7045 case UNDEF_NOT_UNS_SIZE_1:
7046 func (stream, "not unsigned and size = one");
7047 break;
7048
7049 case UNDEF_NOT_UNSIGNED:
7050 func (stream, "not unsigned");
7051 break;
7052
7053 case UNDEF_VCVT_IMM6:
7054 func (stream, "invalid imm6");
7055 break;
7056
7057 case UNDEF_VCVT_FSI_IMM6:
7058 func (stream, "fsi = 0 and invalid imm6");
7059 break;
7060
7061 case UNDEF_BAD_OP1_OP2:
7062 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7063 break;
7064
7065 case UNDEF_BAD_U_OP1_OP2:
7066 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7067 break;
7068
7069 case UNDEF_OP_0_BAD_CMODE:
7070 func (stream, "op field equal 0 and bad cmode");
7071 break;
7072
7073 case UNDEF_XCHG_UNS:
7074 func (stream, "exchange and unsigned together");
7075 break;
7076
7077 case UNDEF_NONE:
7078 break;
7079 }
7080
7081 }
7082
7083 static void
7084 print_mve_unpredictable (struct disassemble_info *info,
7085 enum mve_unpredictable unpredict_code)
7086 {
7087 void *stream = info->stream;
7088 fprintf_ftype func = info->fprintf_func;
7089
7090 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7091
7092 switch (unpredict_code)
7093 {
7094 case UNPRED_IT_BLOCK:
7095 func (stream, "mve instruction in it block");
7096 break;
7097
7098 case UNPRED_FCA_0_FCB_1:
7099 func (stream, "condition bits, fca = 0 and fcb = 1");
7100 break;
7101
7102 case UNPRED_R13:
7103 func (stream, "use of r13 (sp)");
7104 break;
7105
7106 case UNPRED_R15:
7107 func (stream, "use of r15 (pc)");
7108 break;
7109
7110 case UNPRED_Q_GT_4:
7111 func (stream, "start register block > r4");
7112 break;
7113
7114 case UNPRED_Q_GT_6:
7115 func (stream, "start register block > r6");
7116 break;
7117
7118 case UNPRED_R13_AND_WB:
7119 func (stream, "use of r13 and write back");
7120 break;
7121
7122 case UNPRED_Q_REGS_EQUAL:
7123 func (stream,
7124 "same vector register used for destination and other operand");
7125 break;
7126
7127 case UNPRED_OS:
7128 func (stream, "use of offset scaled");
7129 break;
7130
7131 case UNPRED_GP_REGS_EQUAL:
7132 func (stream, "same general-purpose register used for both operands");
7133 break;
7134
7135 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7136 func (stream, "use of identical q registers and size = 1");
7137 break;
7138
7139 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7140 func (stream, "use of identical q registers and size = 1");
7141 break;
7142
7143 case UNPRED_NONE:
7144 break;
7145 }
7146 }
7147
7148 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7149
7150 static void
7151 print_mve_register_blocks (struct disassemble_info *info,
7152 unsigned long given,
7153 enum mve_instructions matched_insn)
7154 {
7155 void *stream = info->stream;
7156 fprintf_ftype func = info->fprintf_func;
7157
7158 unsigned long q_reg_start = arm_decode_field_multiple (given,
7159 13, 15,
7160 22, 22);
7161 switch (matched_insn)
7162 {
7163 case MVE_VLD2:
7164 case MVE_VST2:
7165 if (q_reg_start <= 6)
7166 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7167 else
7168 func (stream, "<illegal reg q%ld>", q_reg_start);
7169 break;
7170
7171 case MVE_VLD4:
7172 case MVE_VST4:
7173 if (q_reg_start <= 4)
7174 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7175 q_reg_start + 1, q_reg_start + 2,
7176 q_reg_start + 3);
7177 else
7178 func (stream, "<illegal reg q%ld>", q_reg_start);
7179 break;
7180
7181 default:
7182 break;
7183 }
7184 }
7185
7186 static void
7187 print_mve_rounding_mode (struct disassemble_info *info,
7188 unsigned long given,
7189 enum mve_instructions matched_insn)
7190 {
7191 void *stream = info->stream;
7192 fprintf_ftype func = info->fprintf_func;
7193
7194 switch (matched_insn)
7195 {
7196 case MVE_VCVT_FROM_FP_TO_INT:
7197 {
7198 switch (arm_decode_field (given, 8, 9))
7199 {
7200 case 0:
7201 func (stream, "a");
7202 break;
7203
7204 case 1:
7205 func (stream, "n");
7206 break;
7207
7208 case 2:
7209 func (stream, "p");
7210 break;
7211
7212 case 3:
7213 func (stream, "m");
7214 break;
7215
7216 default:
7217 break;
7218 }
7219 }
7220 break;
7221
7222 case MVE_VRINT_FP:
7223 {
7224 switch (arm_decode_field (given, 7, 9))
7225 {
7226 case 0:
7227 func (stream, "n");
7228 break;
7229
7230 case 1:
7231 func (stream, "x");
7232 break;
7233
7234 case 2:
7235 func (stream, "a");
7236 break;
7237
7238 case 3:
7239 func (stream, "z");
7240 break;
7241
7242 case 5:
7243 func (stream, "m");
7244 break;
7245
7246 case 7:
7247 func (stream, "p");
7248
7249 case 4:
7250 case 6:
7251 default:
7252 break;
7253 }
7254 }
7255 break;
7256
7257 default:
7258 break;
7259 }
7260 }
7261
7262 static void
7263 print_mve_vcvt_size (struct disassemble_info *info,
7264 unsigned long given,
7265 enum mve_instructions matched_insn)
7266 {
7267 unsigned long mode = 0;
7268 void *stream = info->stream;
7269 fprintf_ftype func = info->fprintf_func;
7270
7271 switch (matched_insn)
7272 {
7273 case MVE_VCVT_FP_FIX_VEC:
7274 {
7275 mode = (((given & 0x200) >> 7)
7276 | ((given & 0x10000000) >> 27)
7277 | ((given & 0x100) >> 8));
7278
7279 switch (mode)
7280 {
7281 case 0:
7282 func (stream, "f16.s16");
7283 break;
7284
7285 case 1:
7286 func (stream, "s16.f16");
7287 break;
7288
7289 case 2:
7290 func (stream, "f16.u16");
7291 break;
7292
7293 case 3:
7294 func (stream, "u16.f16");
7295 break;
7296
7297 case 4:
7298 func (stream, "f32.s32");
7299 break;
7300
7301 case 5:
7302 func (stream, "s32.f32");
7303 break;
7304
7305 case 6:
7306 func (stream, "f32.u32");
7307 break;
7308
7309 case 7:
7310 func (stream, "u32.f32");
7311 break;
7312
7313 default:
7314 break;
7315 }
7316 break;
7317 }
7318 case MVE_VCVT_BETWEEN_FP_INT:
7319 {
7320 unsigned long size = arm_decode_field (given, 18, 19);
7321 unsigned long op = arm_decode_field (given, 7, 8);
7322
7323 if (size == 1)
7324 {
7325 switch (op)
7326 {
7327 case 0:
7328 func (stream, "f16.s16");
7329 break;
7330
7331 case 1:
7332 func (stream, "f16.u16");
7333 break;
7334
7335 case 2:
7336 func (stream, "s16.f16");
7337 break;
7338
7339 case 3:
7340 func (stream, "u16.f16");
7341 break;
7342
7343 default:
7344 break;
7345 }
7346 }
7347 else if (size == 2)
7348 {
7349 switch (op)
7350 {
7351 case 0:
7352 func (stream, "f32.s32");
7353 break;
7354
7355 case 1:
7356 func (stream, "f32.u32");
7357 break;
7358
7359 case 2:
7360 func (stream, "s32.f32");
7361 break;
7362
7363 case 3:
7364 func (stream, "u32.f32");
7365 break;
7366 }
7367 }
7368 }
7369 break;
7370
7371 case MVE_VCVT_FP_HALF_FP:
7372 {
7373 unsigned long op = arm_decode_field (given, 28, 28);
7374 if (op == 0)
7375 func (stream, "f16.f32");
7376 else if (op == 1)
7377 func (stream, "f32.f16");
7378 }
7379 break;
7380
7381 case MVE_VCVT_FROM_FP_TO_INT:
7382 {
7383 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7384
7385 switch (size)
7386 {
7387 case 2:
7388 func (stream, "s16.f16");
7389 break;
7390
7391 case 3:
7392 func (stream, "u16.f16");
7393 break;
7394
7395 case 4:
7396 func (stream, "s32.f32");
7397 break;
7398
7399 case 5:
7400 func (stream, "u32.f32");
7401 break;
7402
7403 default:
7404 break;
7405 }
7406 }
7407 break;
7408
7409 default:
7410 break;
7411 }
7412 }
7413
7414 static void
7415 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7416 unsigned long rot_width)
7417 {
7418 void *stream = info->stream;
7419 fprintf_ftype func = info->fprintf_func;
7420
7421 if (rot_width == 1)
7422 {
7423 switch (rot)
7424 {
7425 case 0:
7426 func (stream, "90");
7427 break;
7428 case 1:
7429 func (stream, "270");
7430 break;
7431 default:
7432 break;
7433 }
7434 }
7435 else if (rot_width == 2)
7436 {
7437 switch (rot)
7438 {
7439 case 0:
7440 func (stream, "0");
7441 break;
7442 case 1:
7443 func (stream, "90");
7444 break;
7445 case 2:
7446 func (stream, "180");
7447 break;
7448 case 3:
7449 func (stream, "270");
7450 break;
7451 default:
7452 break;
7453 }
7454 }
7455 }
7456
7457 static void
7458 print_instruction_predicate (struct disassemble_info *info)
7459 {
7460 void *stream = info->stream;
7461 fprintf_ftype func = info->fprintf_func;
7462
7463 if (vpt_block_state.next_pred_state == PRED_THEN)
7464 func (stream, "t");
7465 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7466 func (stream, "e");
7467 }
7468
7469 static void
7470 print_mve_size (struct disassemble_info *info,
7471 unsigned long size,
7472 enum mve_instructions matched_insn)
7473 {
7474 void *stream = info->stream;
7475 fprintf_ftype func = info->fprintf_func;
7476
7477 switch (matched_insn)
7478 {
7479 case MVE_VABAV:
7480 case MVE_VABD_VEC:
7481 case MVE_VABS_FP:
7482 case MVE_VABS_VEC:
7483 case MVE_VADD_VEC_T1:
7484 case MVE_VADD_VEC_T2:
7485 case MVE_VADDV:
7486 case MVE_VBRSR:
7487 case MVE_VCADD_VEC:
7488 case MVE_VCLS:
7489 case MVE_VCLZ:
7490 case MVE_VCMP_VEC_T1:
7491 case MVE_VCMP_VEC_T2:
7492 case MVE_VCMP_VEC_T3:
7493 case MVE_VCMP_VEC_T4:
7494 case MVE_VCMP_VEC_T5:
7495 case MVE_VCMP_VEC_T6:
7496 case MVE_VCTP:
7497 case MVE_VDDUP:
7498 case MVE_VDWDUP:
7499 case MVE_VHADD_T1:
7500 case MVE_VHADD_T2:
7501 case MVE_VHCADD:
7502 case MVE_VHSUB_T1:
7503 case MVE_VHSUB_T2:
7504 case MVE_VIDUP:
7505 case MVE_VIWDUP:
7506 case MVE_VLD2:
7507 case MVE_VLD4:
7508 case MVE_VLDRB_GATHER_T1:
7509 case MVE_VLDRH_GATHER_T2:
7510 case MVE_VLDRW_GATHER_T3:
7511 case MVE_VLDRD_GATHER_T4:
7512 case MVE_VLDRB_T1:
7513 case MVE_VLDRH_T2:
7514 case MVE_VMAX:
7515 case MVE_VMAXA:
7516 case MVE_VMAXV:
7517 case MVE_VMAXAV:
7518 case MVE_VMIN:
7519 case MVE_VMINA:
7520 case MVE_VMINV:
7521 case MVE_VMINAV:
7522 case MVE_VMLA:
7523 case MVE_VMLAS:
7524 case MVE_VMUL_VEC_T1:
7525 case MVE_VMUL_VEC_T2:
7526 case MVE_VMULH:
7527 case MVE_VRMULH:
7528 case MVE_VMULL_INT:
7529 case MVE_VNEG_FP:
7530 case MVE_VNEG_VEC:
7531 case MVE_VPT_VEC_T1:
7532 case MVE_VPT_VEC_T2:
7533 case MVE_VPT_VEC_T3:
7534 case MVE_VPT_VEC_T4:
7535 case MVE_VPT_VEC_T5:
7536 case MVE_VPT_VEC_T6:
7537 case MVE_VQABS:
7538 case MVE_VQADD_T1:
7539 case MVE_VQADD_T2:
7540 case MVE_VQDMLADH:
7541 case MVE_VQRDMLADH:
7542 case MVE_VQDMLAH:
7543 case MVE_VQRDMLAH:
7544 case MVE_VQDMLASH:
7545 case MVE_VQRDMLASH:
7546 case MVE_VQDMLSDH:
7547 case MVE_VQRDMLSDH:
7548 case MVE_VQDMULH_T1:
7549 case MVE_VQRDMULH_T2:
7550 case MVE_VQDMULH_T3:
7551 case MVE_VQRDMULH_T4:
7552 case MVE_VQNEG:
7553 case MVE_VQRSHL_T1:
7554 case MVE_VQRSHL_T2:
7555 case MVE_VQSHL_T1:
7556 case MVE_VQSHL_T4:
7557 case MVE_VQSUB_T1:
7558 case MVE_VQSUB_T2:
7559 case MVE_VREV32:
7560 case MVE_VREV64:
7561 case MVE_VRHADD:
7562 case MVE_VRINT_FP:
7563 case MVE_VRSHL_T1:
7564 case MVE_VRSHL_T2:
7565 case MVE_VSHL_T2:
7566 case MVE_VSHL_T3:
7567 case MVE_VSHLL_T2:
7568 case MVE_VST2:
7569 case MVE_VST4:
7570 case MVE_VSTRB_SCATTER_T1:
7571 case MVE_VSTRH_SCATTER_T2:
7572 case MVE_VSTRW_SCATTER_T3:
7573 case MVE_VSTRB_T1:
7574 case MVE_VSTRH_T2:
7575 case MVE_VSUB_VEC_T1:
7576 case MVE_VSUB_VEC_T2:
7577 if (size <= 3)
7578 func (stream, "%s", mve_vec_sizename[size]);
7579 else
7580 func (stream, "<undef size>");
7581 break;
7582
7583 case MVE_VABD_FP:
7584 case MVE_VADD_FP_T1:
7585 case MVE_VADD_FP_T2:
7586 case MVE_VSUB_FP_T1:
7587 case MVE_VSUB_FP_T2:
7588 case MVE_VCMP_FP_T1:
7589 case MVE_VCMP_FP_T2:
7590 case MVE_VFMA_FP_SCALAR:
7591 case MVE_VFMA_FP:
7592 case MVE_VFMS_FP:
7593 case MVE_VFMAS_FP_SCALAR:
7594 case MVE_VMAXNM_FP:
7595 case MVE_VMAXNMA_FP:
7596 case MVE_VMAXNMV_FP:
7597 case MVE_VMAXNMAV_FP:
7598 case MVE_VMINNM_FP:
7599 case MVE_VMINNMA_FP:
7600 case MVE_VMINNMV_FP:
7601 case MVE_VMINNMAV_FP:
7602 case MVE_VMUL_FP_T1:
7603 case MVE_VMUL_FP_T2:
7604 case MVE_VPT_FP_T1:
7605 case MVE_VPT_FP_T2:
7606 if (size == 0)
7607 func (stream, "32");
7608 else if (size == 1)
7609 func (stream, "16");
7610 break;
7611
7612 case MVE_VCADD_FP:
7613 case MVE_VCMLA_FP:
7614 case MVE_VCMUL_FP:
7615 case MVE_VMLADAV_T1:
7616 case MVE_VMLALDAV:
7617 case MVE_VMLSDAV_T1:
7618 case MVE_VMLSLDAV:
7619 case MVE_VMOVN:
7620 case MVE_VQDMULL_T1:
7621 case MVE_VQDMULL_T2:
7622 case MVE_VQMOVN:
7623 case MVE_VQMOVUN:
7624 if (size == 0)
7625 func (stream, "16");
7626 else if (size == 1)
7627 func (stream, "32");
7628 break;
7629
7630 case MVE_VMOVL:
7631 if (size == 1)
7632 func (stream, "8");
7633 else if (size == 2)
7634 func (stream, "16");
7635 break;
7636
7637 case MVE_VDUP:
7638 switch (size)
7639 {
7640 case 0:
7641 func (stream, "32");
7642 break;
7643 case 1:
7644 func (stream, "16");
7645 break;
7646 case 2:
7647 func (stream, "8");
7648 break;
7649 default:
7650 break;
7651 }
7652 break;
7653
7654 case MVE_VMOV_GP_TO_VEC_LANE:
7655 case MVE_VMOV_VEC_LANE_TO_GP:
7656 switch (size)
7657 {
7658 case 0: case 4:
7659 func (stream, "32");
7660 break;
7661
7662 case 1: case 3:
7663 case 5: case 7:
7664 func (stream, "16");
7665 break;
7666
7667 case 8: case 9: case 10: case 11:
7668 case 12: case 13: case 14: case 15:
7669 func (stream, "8");
7670 break;
7671
7672 default:
7673 break;
7674 }
7675 break;
7676
7677 case MVE_VMOV_IMM_TO_VEC:
7678 switch (size)
7679 {
7680 case 0: case 4: case 8:
7681 case 12: case 24: case 26:
7682 func (stream, "i32");
7683 break;
7684 case 16: case 20:
7685 func (stream, "i16");
7686 break;
7687 case 28:
7688 func (stream, "i8");
7689 break;
7690 case 29:
7691 func (stream, "i64");
7692 break;
7693 case 30:
7694 func (stream, "f32");
7695 break;
7696 default:
7697 break;
7698 }
7699 break;
7700
7701 case MVE_VMULL_POLY:
7702 if (size == 0)
7703 func (stream, "p8");
7704 else if (size == 1)
7705 func (stream, "p16");
7706 break;
7707
7708 case MVE_VMVN_IMM:
7709 switch (size)
7710 {
7711 case 0: case 2: case 4:
7712 case 6: case 12: case 13:
7713 func (stream, "32");
7714 break;
7715
7716 case 8: case 10:
7717 func (stream, "16");
7718 break;
7719
7720 default:
7721 break;
7722 }
7723 break;
7724
7725 case MVE_VBIC_IMM:
7726 case MVE_VORR_IMM:
7727 switch (size)
7728 {
7729 case 1: case 3:
7730 case 5: case 7:
7731 func (stream, "32");
7732 break;
7733
7734 case 9: case 11:
7735 func (stream, "16");
7736 break;
7737
7738 default:
7739 break;
7740 }
7741 break;
7742
7743 case MVE_VQSHRN:
7744 case MVE_VQSHRUN:
7745 case MVE_VQRSHRN:
7746 case MVE_VQRSHRUN:
7747 case MVE_VRSHRN:
7748 case MVE_VSHRN:
7749 {
7750 switch (size)
7751 {
7752 case 1:
7753 func (stream, "16");
7754 break;
7755
7756 case 2: case 3:
7757 func (stream, "32");
7758 break;
7759
7760 default:
7761 break;
7762 }
7763 }
7764 break;
7765
7766 case MVE_VQSHL_T2:
7767 case MVE_VQSHLU_T3:
7768 case MVE_VRSHR:
7769 case MVE_VSHL_T1:
7770 case MVE_VSHLL_T1:
7771 case MVE_VSHR:
7772 case MVE_VSLI:
7773 case MVE_VSRI:
7774 {
7775 switch (size)
7776 {
7777 case 1:
7778 func (stream, "8");
7779 break;
7780
7781 case 2: case 3:
7782 func (stream, "16");
7783 break;
7784
7785 case 4: case 5: case 6: case 7:
7786 func (stream, "32");
7787 break;
7788
7789 default:
7790 break;
7791 }
7792 }
7793 break;
7794
7795 default:
7796 break;
7797 }
7798 }
7799
7800 static void
7801 print_mve_shift_n (struct disassemble_info *info, long given,
7802 enum mve_instructions matched_insn)
7803 {
7804 void *stream = info->stream;
7805 fprintf_ftype func = info->fprintf_func;
7806
7807 int startAt0
7808 = matched_insn == MVE_VQSHL_T2
7809 || matched_insn == MVE_VQSHLU_T3
7810 || matched_insn == MVE_VSHL_T1
7811 || matched_insn == MVE_VSHLL_T1
7812 || matched_insn == MVE_VSLI;
7813
7814 unsigned imm6 = (given & 0x3f0000) >> 16;
7815
7816 if (matched_insn == MVE_VSHLL_T1)
7817 imm6 &= 0x1f;
7818
7819 unsigned shiftAmount = 0;
7820 if ((imm6 & 0x20) != 0)
7821 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7822 else if ((imm6 & 0x10) != 0)
7823 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7824 else if ((imm6 & 0x08) != 0)
7825 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7826 else
7827 print_mve_undefined (info, UNDEF_SIZE_0);
7828
7829 func (stream, "%u", shiftAmount);
7830 }
7831
7832 static void
7833 print_vec_condition (struct disassemble_info *info, long given,
7834 enum mve_instructions matched_insn)
7835 {
7836 void *stream = info->stream;
7837 fprintf_ftype func = info->fprintf_func;
7838 long vec_cond = 0;
7839
7840 switch (matched_insn)
7841 {
7842 case MVE_VPT_FP_T1:
7843 case MVE_VCMP_FP_T1:
7844 vec_cond = (((given & 0x1000) >> 10)
7845 | ((given & 1) << 1)
7846 | ((given & 0x0080) >> 7));
7847 func (stream, "%s",vec_condnames[vec_cond]);
7848 break;
7849
7850 case MVE_VPT_FP_T2:
7851 case MVE_VCMP_FP_T2:
7852 vec_cond = (((given & 0x1000) >> 10)
7853 | ((given & 0x0020) >> 4)
7854 | ((given & 0x0080) >> 7));
7855 func (stream, "%s",vec_condnames[vec_cond]);
7856 break;
7857
7858 case MVE_VPT_VEC_T1:
7859 case MVE_VCMP_VEC_T1:
7860 vec_cond = (given & 0x0080) >> 7;
7861 func (stream, "%s",vec_condnames[vec_cond]);
7862 break;
7863
7864 case MVE_VPT_VEC_T2:
7865 case MVE_VCMP_VEC_T2:
7866 vec_cond = 2 | ((given & 0x0080) >> 7);
7867 func (stream, "%s",vec_condnames[vec_cond]);
7868 break;
7869
7870 case MVE_VPT_VEC_T3:
7871 case MVE_VCMP_VEC_T3:
7872 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7873 func (stream, "%s",vec_condnames[vec_cond]);
7874 break;
7875
7876 case MVE_VPT_VEC_T4:
7877 case MVE_VCMP_VEC_T4:
7878 vec_cond = (given & 0x0080) >> 7;
7879 func (stream, "%s",vec_condnames[vec_cond]);
7880 break;
7881
7882 case MVE_VPT_VEC_T5:
7883 case MVE_VCMP_VEC_T5:
7884 vec_cond = 2 | ((given & 0x0080) >> 7);
7885 func (stream, "%s",vec_condnames[vec_cond]);
7886 break;
7887
7888 case MVE_VPT_VEC_T6:
7889 case MVE_VCMP_VEC_T6:
7890 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7891 func (stream, "%s",vec_condnames[vec_cond]);
7892 break;
7893
7894 case MVE_NONE:
7895 case MVE_VPST:
7896 default:
7897 break;
7898 }
7899 }
7900
7901 #define W_BIT 21
7902 #define I_BIT 22
7903 #define U_BIT 23
7904 #define P_BIT 24
7905
7906 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7907 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7908 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7909 #define PRE_BIT_SET (given & (1 << P_BIT))
7910
7911
7912 /* Print one coprocessor instruction on INFO->STREAM.
7913 Return TRUE if the instuction matched, FALSE if this is not a
7914 recognised coprocessor instruction. */
7915
7916 static bfd_boolean
7917 print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7918 bfd_vma pc,
7919 struct disassemble_info *info,
7920 long given,
7921 bfd_boolean thumb)
7922 {
7923 const struct sopcode32 *insn;
7924 void *stream = info->stream;
7925 fprintf_ftype func = info->fprintf_func;
7926 unsigned long mask;
7927 unsigned long value = 0;
7928 int cond;
7929 int cp_num;
7930 struct arm_private_data *private_data = info->private_data;
7931 arm_feature_set allowed_arches = ARM_ARCH_NONE;
7932 arm_feature_set arm_ext_v8_1m_main =
7933 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7934
7935 allowed_arches = private_data->features;
7936
7937 for (insn = opcodes; insn->assembler; insn++)
7938 {
7939 unsigned long u_reg = 16;
7940 bfd_boolean is_unpredictable = FALSE;
7941 signed long value_in_comment = 0;
7942 const char *c;
7943
7944 if (ARM_FEATURE_ZERO (insn->arch))
7945 switch (insn->value)
7946 {
7947 case SENTINEL_IWMMXT_START:
7948 if (info->mach != bfd_mach_arm_XScale
7949 && info->mach != bfd_mach_arm_iWMMXt
7950 && info->mach != bfd_mach_arm_iWMMXt2)
7951 do
7952 insn++;
7953 while ((! ARM_FEATURE_ZERO (insn->arch))
7954 && insn->value != SENTINEL_IWMMXT_END);
7955 continue;
7956
7957 case SENTINEL_IWMMXT_END:
7958 continue;
7959
7960 case SENTINEL_GENERIC_START:
7961 allowed_arches = private_data->features;
7962 continue;
7963
7964 default:
7965 abort ();
7966 }
7967
7968 mask = insn->mask;
7969 value = insn->value;
7970 cp_num = (given >> 8) & 0xf;
7971
7972 if (thumb)
7973 {
7974 /* The high 4 bits are 0xe for Arm conditional instructions, and
7975 0xe for arm unconditional instructions. The rest of the
7976 encoding is the same. */
7977 mask |= 0xf0000000;
7978 value |= 0xe0000000;
7979 if (ifthen_state)
7980 cond = IFTHEN_COND;
7981 else
7982 cond = COND_UNCOND;
7983 }
7984 else
7985 {
7986 /* Only match unconditional instuctions against unconditional
7987 patterns. */
7988 if ((given & 0xf0000000) == 0xf0000000)
7989 {
7990 mask |= 0xf0000000;
7991 cond = COND_UNCOND;
7992 }
7993 else
7994 {
7995 cond = (given >> 28) & 0xf;
7996 if (cond == 0xe)
7997 cond = COND_UNCOND;
7998 }
7999 }
8000
8001 if ((insn->isa == T32 && !thumb)
8002 || (insn->isa == ARM && thumb))
8003 continue;
8004
8005 if ((given & mask) != value)
8006 continue;
8007
8008 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
8009 continue;
8010
8011 if (insn->value == 0xfe000010 /* mcr2 */
8012 || insn->value == 0xfe100010 /* mrc2 */
8013 || insn->value == 0xfc100000 /* ldc2 */
8014 || insn->value == 0xfc000000) /* stc2 */
8015 {
8016 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8017 is_unpredictable = TRUE;
8018
8019 /* Armv8.1-M Mainline FP & MVE instructions. */
8020 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8021 && !ARM_CPU_IS_ANY (allowed_arches)
8022 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8023 continue;
8024
8025 }
8026 else if (insn->value == 0x0e000000 /* cdp */
8027 || insn->value == 0xfe000000 /* cdp2 */
8028 || insn->value == 0x0e000010 /* mcr */
8029 || insn->value == 0x0e100010 /* mrc */
8030 || insn->value == 0x0c100000 /* ldc */
8031 || insn->value == 0x0c000000) /* stc */
8032 {
8033 /* Floating-point instructions. */
8034 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8035 continue;
8036
8037 /* Armv8.1-M Mainline FP & MVE instructions. */
8038 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8039 && !ARM_CPU_IS_ANY (allowed_arches)
8040 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8041 continue;
8042 }
8043 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8044 || insn->value == 0xec000f80) /* vstr (system register) */
8045 && arm_decode_field (given, 24, 24) == 0
8046 && arm_decode_field (given, 21, 21) == 0)
8047 /* If the P and W bits are both 0 then these encodings match the MVE
8048 VLDR and VSTR instructions, these are in a different table, so we
8049 don't let it match here. */
8050 continue;
8051
8052 for (c = insn->assembler; *c; c++)
8053 {
8054 if (*c == '%')
8055 {
8056 const char mod = *++c;
8057 switch (mod)
8058 {
8059 case '%':
8060 func (stream, "%%");
8061 break;
8062
8063 case 'A':
8064 case 'K':
8065 {
8066 int rn = (given >> 16) & 0xf;
8067 bfd_vma offset = given & 0xff;
8068
8069 if (mod == 'K')
8070 offset = given & 0x7f;
8071
8072 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8073
8074 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8075 {
8076 /* Not unindexed. The offset is scaled. */
8077 if (cp_num == 9)
8078 /* vldr.16/vstr.16 will shift the address
8079 left by 1 bit only. */
8080 offset = offset * 2;
8081 else
8082 offset = offset * 4;
8083
8084 if (NEGATIVE_BIT_SET)
8085 offset = - offset;
8086 if (rn != 15)
8087 value_in_comment = offset;
8088 }
8089
8090 if (PRE_BIT_SET)
8091 {
8092 if (offset)
8093 func (stream, ", #%d]%s",
8094 (int) offset,
8095 WRITEBACK_BIT_SET ? "!" : "");
8096 else if (NEGATIVE_BIT_SET)
8097 func (stream, ", #-0]");
8098 else
8099 func (stream, "]");
8100 }
8101 else
8102 {
8103 func (stream, "]");
8104
8105 if (WRITEBACK_BIT_SET)
8106 {
8107 if (offset)
8108 func (stream, ", #%d", (int) offset);
8109 else if (NEGATIVE_BIT_SET)
8110 func (stream, ", #-0");
8111 }
8112 else
8113 {
8114 func (stream, ", {%s%d}",
8115 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8116 (int) offset);
8117 value_in_comment = offset;
8118 }
8119 }
8120 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8121 {
8122 func (stream, "\t; ");
8123 /* For unaligned PCs, apply off-by-alignment
8124 correction. */
8125 info->print_address_func (offset + pc
8126 + info->bytes_per_chunk * 2
8127 - (pc & 3),
8128 info);
8129 }
8130 }
8131 break;
8132
8133 case 'B':
8134 {
8135 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8136 int offset = (given >> 1) & 0x3f;
8137
8138 if (offset == 1)
8139 func (stream, "{d%d}", regno);
8140 else if (regno + offset > 32)
8141 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8142 else
8143 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8144 }
8145 break;
8146
8147 case 'C':
8148 {
8149 bfd_boolean single = ((given >> 8) & 1) == 0;
8150 char reg_prefix = single ? 's' : 'd';
8151 int Dreg = (given >> 22) & 0x1;
8152 int Vdreg = (given >> 12) & 0xf;
8153 int reg = single ? ((Vdreg << 1) | Dreg)
8154 : ((Dreg << 4) | Vdreg);
8155 int num = (given >> (single ? 0 : 1)) & 0x7f;
8156 int maxreg = single ? 31 : 15;
8157 int topreg = reg + num - 1;
8158
8159 if (!num)
8160 func (stream, "{VPR}");
8161 else if (num == 1)
8162 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8163 else if (topreg > maxreg)
8164 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8165 reg_prefix, reg, single ? topreg >> 1 : topreg);
8166 else
8167 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8168 reg_prefix, topreg);
8169 }
8170 break;
8171
8172 case 'u':
8173 if (cond != COND_UNCOND)
8174 is_unpredictable = TRUE;
8175
8176 /* Fall through. */
8177 case 'c':
8178 if (cond != COND_UNCOND && cp_num == 9)
8179 is_unpredictable = TRUE;
8180
8181 /* Fall through. */
8182 case 'b':
8183 func (stream, "%s", arm_conditional[cond]);
8184 break;
8185
8186 case 'I':
8187 /* Print a Cirrus/DSP shift immediate. */
8188 /* Immediates are 7bit signed ints with bits 0..3 in
8189 bits 0..3 of opcode and bits 4..6 in bits 5..7
8190 of opcode. */
8191 {
8192 int imm;
8193
8194 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8195
8196 /* Is ``imm'' a negative number? */
8197 if (imm & 0x40)
8198 imm -= 0x80;
8199
8200 func (stream, "%d", imm);
8201 }
8202
8203 break;
8204
8205 case 'J':
8206 {
8207 unsigned long regno
8208 = arm_decode_field_multiple (given, 13, 15, 22, 22);
8209
8210 switch (regno)
8211 {
8212 case 0x1:
8213 func (stream, "FPSCR");
8214 break;
8215 case 0x2:
8216 func (stream, "FPSCR_nzcvqc");
8217 break;
8218 case 0xc:
8219 func (stream, "VPR");
8220 break;
8221 case 0xd:
8222 func (stream, "P0");
8223 break;
8224 case 0xe:
8225 func (stream, "FPCXTNS");
8226 break;
8227 case 0xf:
8228 func (stream, "FPCXTS");
8229 break;
8230 default:
8231 func (stream, "<invalid reg %lu>", regno);
8232 break;
8233 }
8234 }
8235 break;
8236
8237 case 'F':
8238 switch (given & 0x00408000)
8239 {
8240 case 0:
8241 func (stream, "4");
8242 break;
8243 case 0x8000:
8244 func (stream, "1");
8245 break;
8246 case 0x00400000:
8247 func (stream, "2");
8248 break;
8249 default:
8250 func (stream, "3");
8251 }
8252 break;
8253
8254 case 'P':
8255 switch (given & 0x00080080)
8256 {
8257 case 0:
8258 func (stream, "s");
8259 break;
8260 case 0x80:
8261 func (stream, "d");
8262 break;
8263 case 0x00080000:
8264 func (stream, "e");
8265 break;
8266 default:
8267 func (stream, _("<illegal precision>"));
8268 break;
8269 }
8270 break;
8271
8272 case 'Q':
8273 switch (given & 0x00408000)
8274 {
8275 case 0:
8276 func (stream, "s");
8277 break;
8278 case 0x8000:
8279 func (stream, "d");
8280 break;
8281 case 0x00400000:
8282 func (stream, "e");
8283 break;
8284 default:
8285 func (stream, "p");
8286 break;
8287 }
8288 break;
8289
8290 case 'R':
8291 switch (given & 0x60)
8292 {
8293 case 0:
8294 break;
8295 case 0x20:
8296 func (stream, "p");
8297 break;
8298 case 0x40:
8299 func (stream, "m");
8300 break;
8301 default:
8302 func (stream, "z");
8303 break;
8304 }
8305 break;
8306
8307 case '0': case '1': case '2': case '3': case '4':
8308 case '5': case '6': case '7': case '8': case '9':
8309 {
8310 int width;
8311
8312 c = arm_decode_bitfield (c, given, &value, &width);
8313
8314 switch (*c)
8315 {
8316 case 'R':
8317 if (value == 15)
8318 is_unpredictable = TRUE;
8319 /* Fall through. */
8320 case 'r':
8321 if (c[1] == 'u')
8322 {
8323 /* Eat the 'u' character. */
8324 ++ c;
8325
8326 if (u_reg == value)
8327 is_unpredictable = TRUE;
8328 u_reg = value;
8329 }
8330 func (stream, "%s", arm_regnames[value]);
8331 break;
8332 case 'V':
8333 if (given & (1 << 6))
8334 goto Q;
8335 /* FALLTHROUGH */
8336 case 'D':
8337 func (stream, "d%ld", value);
8338 break;
8339 case 'Q':
8340 Q:
8341 if (value & 1)
8342 func (stream, "<illegal reg q%ld.5>", value >> 1);
8343 else
8344 func (stream, "q%ld", value >> 1);
8345 break;
8346 case 'd':
8347 func (stream, "%ld", value);
8348 value_in_comment = value;
8349 break;
8350 case 'E':
8351 {
8352 /* Converts immediate 8 bit back to float value. */
8353 unsigned floatVal = (value & 0x80) << 24
8354 | (value & 0x3F) << 19
8355 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8356
8357 /* Quarter float have a maximum value of 31.0.
8358 Get floating point value multiplied by 1e7.
8359 The maximum value stays in limit of a 32-bit int. */
8360 unsigned decVal =
8361 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8362 (16 + (value & 0xF));
8363
8364 if (!(decVal % 1000000))
8365 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8366 floatVal, value & 0x80 ? '-' : ' ',
8367 decVal / 10000000,
8368 decVal % 10000000 / 1000000);
8369 else if (!(decVal % 10000))
8370 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8371 floatVal, value & 0x80 ? '-' : ' ',
8372 decVal / 10000000,
8373 decVal % 10000000 / 10000);
8374 else
8375 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8376 floatVal, value & 0x80 ? '-' : ' ',
8377 decVal / 10000000, decVal % 10000000);
8378 break;
8379 }
8380 case 'k':
8381 {
8382 int from = (given & (1 << 7)) ? 32 : 16;
8383 func (stream, "%ld", from - value);
8384 }
8385 break;
8386
8387 case 'f':
8388 if (value > 7)
8389 func (stream, "#%s", arm_fp_const[value & 7]);
8390 else
8391 func (stream, "f%ld", value);
8392 break;
8393
8394 case 'w':
8395 if (width == 2)
8396 func (stream, "%s", iwmmxt_wwnames[value]);
8397 else
8398 func (stream, "%s", iwmmxt_wwssnames[value]);
8399 break;
8400
8401 case 'g':
8402 func (stream, "%s", iwmmxt_regnames[value]);
8403 break;
8404 case 'G':
8405 func (stream, "%s", iwmmxt_cregnames[value]);
8406 break;
8407
8408 case 'x':
8409 func (stream, "0x%lx", (value & 0xffffffffUL));
8410 break;
8411
8412 case 'c':
8413 switch (value)
8414 {
8415 case 0:
8416 func (stream, "eq");
8417 break;
8418
8419 case 1:
8420 func (stream, "vs");
8421 break;
8422
8423 case 2:
8424 func (stream, "ge");
8425 break;
8426
8427 case 3:
8428 func (stream, "gt");
8429 break;
8430
8431 default:
8432 func (stream, "??");
8433 break;
8434 }
8435 break;
8436
8437 case '`':
8438 c++;
8439 if (value == 0)
8440 func (stream, "%c", *c);
8441 break;
8442 case '\'':
8443 c++;
8444 if (value == ((1ul << width) - 1))
8445 func (stream, "%c", *c);
8446 break;
8447 case '?':
8448 func (stream, "%c", c[(1 << width) - (int) value]);
8449 c += 1 << width;
8450 break;
8451 default:
8452 abort ();
8453 }
8454 }
8455 break;
8456
8457 case 'y':
8458 case 'z':
8459 {
8460 int single = *c++ == 'y';
8461 int regno;
8462
8463 switch (*c)
8464 {
8465 case '4': /* Sm pair */
8466 case '0': /* Sm, Dm */
8467 regno = given & 0x0000000f;
8468 if (single)
8469 {
8470 regno <<= 1;
8471 regno += (given >> 5) & 1;
8472 }
8473 else
8474 regno += ((given >> 5) & 1) << 4;
8475 break;
8476
8477 case '1': /* Sd, Dd */
8478 regno = (given >> 12) & 0x0000000f;
8479 if (single)
8480 {
8481 regno <<= 1;
8482 regno += (given >> 22) & 1;
8483 }
8484 else
8485 regno += ((given >> 22) & 1) << 4;
8486 break;
8487
8488 case '2': /* Sn, Dn */
8489 regno = (given >> 16) & 0x0000000f;
8490 if (single)
8491 {
8492 regno <<= 1;
8493 regno += (given >> 7) & 1;
8494 }
8495 else
8496 regno += ((given >> 7) & 1) << 4;
8497 break;
8498
8499 case '3': /* List */
8500 func (stream, "{");
8501 regno = (given >> 12) & 0x0000000f;
8502 if (single)
8503 {
8504 regno <<= 1;
8505 regno += (given >> 22) & 1;
8506 }
8507 else
8508 regno += ((given >> 22) & 1) << 4;
8509 break;
8510
8511 default:
8512 abort ();
8513 }
8514
8515 func (stream, "%c%d", single ? 's' : 'd', regno);
8516
8517 if (*c == '3')
8518 {
8519 int count = given & 0xff;
8520
8521 if (single == 0)
8522 count >>= 1;
8523
8524 if (--count)
8525 {
8526 func (stream, "-%c%d",
8527 single ? 's' : 'd',
8528 regno + count);
8529 }
8530
8531 func (stream, "}");
8532 }
8533 else if (*c == '4')
8534 func (stream, ", %c%d", single ? 's' : 'd',
8535 regno + 1);
8536 }
8537 break;
8538
8539 case 'L':
8540 switch (given & 0x00400100)
8541 {
8542 case 0x00000000: func (stream, "b"); break;
8543 case 0x00400000: func (stream, "h"); break;
8544 case 0x00000100: func (stream, "w"); break;
8545 case 0x00400100: func (stream, "d"); break;
8546 default:
8547 break;
8548 }
8549 break;
8550
8551 case 'Z':
8552 {
8553 /* given (20, 23) | given (0, 3) */
8554 value = ((given >> 16) & 0xf0) | (given & 0xf);
8555 func (stream, "%d", (int) value);
8556 }
8557 break;
8558
8559 case 'l':
8560 /* This is like the 'A' operator, except that if
8561 the width field "M" is zero, then the offset is
8562 *not* multiplied by four. */
8563 {
8564 int offset = given & 0xff;
8565 int multiplier = (given & 0x00000100) ? 4 : 1;
8566
8567 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8568
8569 if (multiplier > 1)
8570 {
8571 value_in_comment = offset * multiplier;
8572 if (NEGATIVE_BIT_SET)
8573 value_in_comment = - value_in_comment;
8574 }
8575
8576 if (offset)
8577 {
8578 if (PRE_BIT_SET)
8579 func (stream, ", #%s%d]%s",
8580 NEGATIVE_BIT_SET ? "-" : "",
8581 offset * multiplier,
8582 WRITEBACK_BIT_SET ? "!" : "");
8583 else
8584 func (stream, "], #%s%d",
8585 NEGATIVE_BIT_SET ? "-" : "",
8586 offset * multiplier);
8587 }
8588 else
8589 func (stream, "]");
8590 }
8591 break;
8592
8593 case 'r':
8594 {
8595 int imm4 = (given >> 4) & 0xf;
8596 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8597 int ubit = ! NEGATIVE_BIT_SET;
8598 const char *rm = arm_regnames [given & 0xf];
8599 const char *rn = arm_regnames [(given >> 16) & 0xf];
8600
8601 switch (puw_bits)
8602 {
8603 case 1:
8604 case 3:
8605 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8606 if (imm4)
8607 func (stream, ", lsl #%d", imm4);
8608 break;
8609
8610 case 4:
8611 case 5:
8612 case 6:
8613 case 7:
8614 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8615 if (imm4 > 0)
8616 func (stream, ", lsl #%d", imm4);
8617 func (stream, "]");
8618 if (puw_bits == 5 || puw_bits == 7)
8619 func (stream, "!");
8620 break;
8621
8622 default:
8623 func (stream, "INVALID");
8624 }
8625 }
8626 break;
8627
8628 case 'i':
8629 {
8630 long imm5;
8631 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8632 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8633 }
8634 break;
8635
8636 default:
8637 abort ();
8638 }
8639 }
8640 else
8641 func (stream, "%c", *c);
8642 }
8643
8644 if (value_in_comment > 32 || value_in_comment < -16)
8645 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
8646
8647 if (is_unpredictable)
8648 func (stream, UNPREDICTABLE_INSTRUCTION);
8649
8650 return TRUE;
8651 }
8652 return FALSE;
8653 }
8654
8655 static bfd_boolean
8656 print_insn_coprocessor (bfd_vma pc,
8657 struct disassemble_info *info,
8658 long given,
8659 bfd_boolean thumb)
8660 {
8661 return print_insn_coprocessor_1 (coprocessor_opcodes,
8662 pc, info, given, thumb);
8663 }
8664
8665 static bfd_boolean
8666 print_insn_generic_coprocessor (bfd_vma pc,
8667 struct disassemble_info *info,
8668 long given,
8669 bfd_boolean thumb)
8670 {
8671 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8672 pc, info, given, thumb);
8673 }
8674
8675 /* Decodes and prints ARM addressing modes. Returns the offset
8676 used in the address, if any, if it is worthwhile printing the
8677 offset as a hexadecimal value in a comment at the end of the
8678 line of disassembly. */
8679
8680 static signed long
8681 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8682 {
8683 void *stream = info->stream;
8684 fprintf_ftype func = info->fprintf_func;
8685 bfd_vma offset = 0;
8686
8687 if (((given & 0x000f0000) == 0x000f0000)
8688 && ((given & 0x02000000) == 0))
8689 {
8690 offset = given & 0xfff;
8691
8692 func (stream, "[pc");
8693
8694 if (PRE_BIT_SET)
8695 {
8696 /* Pre-indexed. Elide offset of positive zero when
8697 non-writeback. */
8698 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8699 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8700
8701 if (NEGATIVE_BIT_SET)
8702 offset = -offset;
8703
8704 offset += pc + 8;
8705
8706 /* Cope with the possibility of write-back
8707 being used. Probably a very dangerous thing
8708 for the programmer to do, but who are we to
8709 argue ? */
8710 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8711 }
8712 else /* Post indexed. */
8713 {
8714 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8715
8716 /* Ie ignore the offset. */
8717 offset = pc + 8;
8718 }
8719
8720 func (stream, "\t; ");
8721 info->print_address_func (offset, info);
8722 offset = 0;
8723 }
8724 else
8725 {
8726 func (stream, "[%s",
8727 arm_regnames[(given >> 16) & 0xf]);
8728
8729 if (PRE_BIT_SET)
8730 {
8731 if ((given & 0x02000000) == 0)
8732 {
8733 /* Elide offset of positive zero when non-writeback. */
8734 offset = given & 0xfff;
8735 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8736 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8737 }
8738 else
8739 {
8740 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
8741 arm_decode_shift (given, func, stream, TRUE);
8742 }
8743
8744 func (stream, "]%s",
8745 WRITEBACK_BIT_SET ? "!" : "");
8746 }
8747 else
8748 {
8749 if ((given & 0x02000000) == 0)
8750 {
8751 /* Always show offset. */
8752 offset = given & 0xfff;
8753 func (stream, "], #%s%d",
8754 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8755 }
8756 else
8757 {
8758 func (stream, "], %s",
8759 NEGATIVE_BIT_SET ? "-" : "");
8760 arm_decode_shift (given, func, stream, TRUE);
8761 }
8762 }
8763 if (NEGATIVE_BIT_SET)
8764 offset = -offset;
8765 }
8766
8767 return (signed long) offset;
8768 }
8769
8770 /* Print one neon instruction on INFO->STREAM.
8771 Return TRUE if the instuction matched, FALSE if this is not a
8772 recognised neon instruction. */
8773
8774 static bfd_boolean
8775 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8776 {
8777 const struct opcode32 *insn;
8778 void *stream = info->stream;
8779 fprintf_ftype func = info->fprintf_func;
8780
8781 if (thumb)
8782 {
8783 if ((given & 0xef000000) == 0xef000000)
8784 {
8785 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8786 unsigned long bit28 = given & (1 << 28);
8787
8788 given &= 0x00ffffff;
8789 if (bit28)
8790 given |= 0xf3000000;
8791 else
8792 given |= 0xf2000000;
8793 }
8794 else if ((given & 0xff000000) == 0xf9000000)
8795 given ^= 0xf9000000 ^ 0xf4000000;
8796 /* BFloat16 neon instructions without special top byte handling. */
8797 else if ((given & 0xff000000) == 0xfe000000
8798 || (given & 0xff000000) == 0xfc000000)
8799 ;
8800 /* vdup is also a valid neon instruction. */
8801 else if ((given & 0xff910f5f) != 0xee800b10)
8802 return FALSE;
8803 }
8804
8805 for (insn = neon_opcodes; insn->assembler; insn++)
8806 {
8807 if ((given & insn->mask) == insn->value)
8808 {
8809 signed long value_in_comment = 0;
8810 bfd_boolean is_unpredictable = FALSE;
8811 const char *c;
8812
8813 for (c = insn->assembler; *c; c++)
8814 {
8815 if (*c == '%')
8816 {
8817 switch (*++c)
8818 {
8819 case '%':
8820 func (stream, "%%");
8821 break;
8822
8823 case 'u':
8824 if (thumb && ifthen_state)
8825 is_unpredictable = TRUE;
8826
8827 /* Fall through. */
8828 case 'c':
8829 if (thumb && ifthen_state)
8830 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8831 break;
8832
8833 case 'A':
8834 {
8835 static const unsigned char enc[16] =
8836 {
8837 0x4, 0x14, /* st4 0,1 */
8838 0x4, /* st1 2 */
8839 0x4, /* st2 3 */
8840 0x3, /* st3 4 */
8841 0x13, /* st3 5 */
8842 0x3, /* st1 6 */
8843 0x1, /* st1 7 */
8844 0x2, /* st2 8 */
8845 0x12, /* st2 9 */
8846 0x2, /* st1 10 */
8847 0, 0, 0, 0, 0
8848 };
8849 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8850 int rn = ((given >> 16) & 0xf);
8851 int rm = ((given >> 0) & 0xf);
8852 int align = ((given >> 4) & 0x3);
8853 int type = ((given >> 8) & 0xf);
8854 int n = enc[type] & 0xf;
8855 int stride = (enc[type] >> 4) + 1;
8856 int ix;
8857
8858 func (stream, "{");
8859 if (stride > 1)
8860 for (ix = 0; ix != n; ix++)
8861 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8862 else if (n == 1)
8863 func (stream, "d%d", rd);
8864 else
8865 func (stream, "d%d-d%d", rd, rd + n - 1);
8866 func (stream, "}, [%s", arm_regnames[rn]);
8867 if (align)
8868 func (stream, " :%d", 32 << align);
8869 func (stream, "]");
8870 if (rm == 0xd)
8871 func (stream, "!");
8872 else if (rm != 0xf)
8873 func (stream, ", %s", arm_regnames[rm]);
8874 }
8875 break;
8876
8877 case 'B':
8878 {
8879 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8880 int rn = ((given >> 16) & 0xf);
8881 int rm = ((given >> 0) & 0xf);
8882 int idx_align = ((given >> 4) & 0xf);
8883 int align = 0;
8884 int size = ((given >> 10) & 0x3);
8885 int idx = idx_align >> (size + 1);
8886 int length = ((given >> 8) & 3) + 1;
8887 int stride = 1;
8888 int i;
8889
8890 if (length > 1 && size > 0)
8891 stride = (idx_align & (1 << size)) ? 2 : 1;
8892
8893 switch (length)
8894 {
8895 case 1:
8896 {
8897 int amask = (1 << size) - 1;
8898 if ((idx_align & (1 << size)) != 0)
8899 return FALSE;
8900 if (size > 0)
8901 {
8902 if ((idx_align & amask) == amask)
8903 align = 8 << size;
8904 else if ((idx_align & amask) != 0)
8905 return FALSE;
8906 }
8907 }
8908 break;
8909
8910 case 2:
8911 if (size == 2 && (idx_align & 2) != 0)
8912 return FALSE;
8913 align = (idx_align & 1) ? 16 << size : 0;
8914 break;
8915
8916 case 3:
8917 if ((size == 2 && (idx_align & 3) != 0)
8918 || (idx_align & 1) != 0)
8919 return FALSE;
8920 break;
8921
8922 case 4:
8923 if (size == 2)
8924 {
8925 if ((idx_align & 3) == 3)
8926 return FALSE;
8927 align = (idx_align & 3) * 64;
8928 }
8929 else
8930 align = (idx_align & 1) ? 32 << size : 0;
8931 break;
8932
8933 default:
8934 abort ();
8935 }
8936
8937 func (stream, "{");
8938 for (i = 0; i < length; i++)
8939 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8940 rd + i * stride, idx);
8941 func (stream, "}, [%s", arm_regnames[rn]);
8942 if (align)
8943 func (stream, " :%d", align);
8944 func (stream, "]");
8945 if (rm == 0xd)
8946 func (stream, "!");
8947 else if (rm != 0xf)
8948 func (stream, ", %s", arm_regnames[rm]);
8949 }
8950 break;
8951
8952 case 'C':
8953 {
8954 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8955 int rn = ((given >> 16) & 0xf);
8956 int rm = ((given >> 0) & 0xf);
8957 int align = ((given >> 4) & 0x1);
8958 int size = ((given >> 6) & 0x3);
8959 int type = ((given >> 8) & 0x3);
8960 int n = type + 1;
8961 int stride = ((given >> 5) & 0x1);
8962 int ix;
8963
8964 if (stride && (n == 1))
8965 n++;
8966 else
8967 stride++;
8968
8969 func (stream, "{");
8970 if (stride > 1)
8971 for (ix = 0; ix != n; ix++)
8972 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8973 else if (n == 1)
8974 func (stream, "d%d[]", rd);
8975 else
8976 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8977 func (stream, "}, [%s", arm_regnames[rn]);
8978 if (align)
8979 {
8980 align = (8 * (type + 1)) << size;
8981 if (type == 3)
8982 align = (size > 1) ? align >> 1 : align;
8983 if (type == 2 || (type == 0 && !size))
8984 func (stream, " :<bad align %d>", align);
8985 else
8986 func (stream, " :%d", align);
8987 }
8988 func (stream, "]");
8989 if (rm == 0xd)
8990 func (stream, "!");
8991 else if (rm != 0xf)
8992 func (stream, ", %s", arm_regnames[rm]);
8993 }
8994 break;
8995
8996 case 'D':
8997 {
8998 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8999 int size = (given >> 20) & 3;
9000 int reg = raw_reg & ((4 << size) - 1);
9001 int ix = raw_reg >> size >> 2;
9002
9003 func (stream, "d%d[%d]", reg, ix);
9004 }
9005 break;
9006
9007 case 'E':
9008 /* Neon encoded constant for mov, mvn, vorr, vbic. */
9009 {
9010 int bits = 0;
9011 int cmode = (given >> 8) & 0xf;
9012 int op = (given >> 5) & 0x1;
9013 unsigned long value = 0, hival = 0;
9014 unsigned shift;
9015 int size = 0;
9016 int isfloat = 0;
9017
9018 bits |= ((given >> 24) & 1) << 7;
9019 bits |= ((given >> 16) & 7) << 4;
9020 bits |= ((given >> 0) & 15) << 0;
9021
9022 if (cmode < 8)
9023 {
9024 shift = (cmode >> 1) & 3;
9025 value = (unsigned long) bits << (8 * shift);
9026 size = 32;
9027 }
9028 else if (cmode < 12)
9029 {
9030 shift = (cmode >> 1) & 1;
9031 value = (unsigned long) bits << (8 * shift);
9032 size = 16;
9033 }
9034 else if (cmode < 14)
9035 {
9036 shift = (cmode & 1) + 1;
9037 value = (unsigned long) bits << (8 * shift);
9038 value |= (1ul << (8 * shift)) - 1;
9039 size = 32;
9040 }
9041 else if (cmode == 14)
9042 {
9043 if (op)
9044 {
9045 /* Bit replication into bytes. */
9046 int ix;
9047 unsigned long mask;
9048
9049 value = 0;
9050 hival = 0;
9051 for (ix = 7; ix >= 0; ix--)
9052 {
9053 mask = ((bits >> ix) & 1) ? 0xff : 0;
9054 if (ix <= 3)
9055 value = (value << 8) | mask;
9056 else
9057 hival = (hival << 8) | mask;
9058 }
9059 size = 64;
9060 }
9061 else
9062 {
9063 /* Byte replication. */
9064 value = (unsigned long) bits;
9065 size = 8;
9066 }
9067 }
9068 else if (!op)
9069 {
9070 /* Floating point encoding. */
9071 int tmp;
9072
9073 value = (unsigned long) (bits & 0x7f) << 19;
9074 value |= (unsigned long) (bits & 0x80) << 24;
9075 tmp = bits & 0x40 ? 0x3c : 0x40;
9076 value |= (unsigned long) tmp << 24;
9077 size = 32;
9078 isfloat = 1;
9079 }
9080 else
9081 {
9082 func (stream, "<illegal constant %.8x:%x:%x>",
9083 bits, cmode, op);
9084 size = 32;
9085 break;
9086 }
9087 switch (size)
9088 {
9089 case 8:
9090 func (stream, "#%ld\t; 0x%.2lx", value, value);
9091 break;
9092
9093 case 16:
9094 func (stream, "#%ld\t; 0x%.4lx", value, value);
9095 break;
9096
9097 case 32:
9098 if (isfloat)
9099 {
9100 unsigned char valbytes[4];
9101 double fvalue;
9102
9103 /* Do this a byte at a time so we don't have to
9104 worry about the host's endianness. */
9105 valbytes[0] = value & 0xff;
9106 valbytes[1] = (value >> 8) & 0xff;
9107 valbytes[2] = (value >> 16) & 0xff;
9108 valbytes[3] = (value >> 24) & 0xff;
9109
9110 floatformat_to_double
9111 (& floatformat_ieee_single_little, valbytes,
9112 & fvalue);
9113
9114 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9115 value);
9116 }
9117 else
9118 func (stream, "#%ld\t; 0x%.8lx",
9119 (long) (((value & 0x80000000L) != 0)
9120 ? value | ~0xffffffffL : value),
9121 value);
9122 break;
9123
9124 case 64:
9125 func (stream, "#0x%.8lx%.8lx", hival, value);
9126 break;
9127
9128 default:
9129 abort ();
9130 }
9131 }
9132 break;
9133
9134 case 'F':
9135 {
9136 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9137 int num = (given >> 8) & 0x3;
9138
9139 if (!num)
9140 func (stream, "{d%d}", regno);
9141 else if (num + regno >= 32)
9142 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9143 else
9144 func (stream, "{d%d-d%d}", regno, regno + num);
9145 }
9146 break;
9147
9148
9149 case '0': case '1': case '2': case '3': case '4':
9150 case '5': case '6': case '7': case '8': case '9':
9151 {
9152 int width;
9153 unsigned long value;
9154
9155 c = arm_decode_bitfield (c, given, &value, &width);
9156
9157 switch (*c)
9158 {
9159 case 'r':
9160 func (stream, "%s", arm_regnames[value]);
9161 break;
9162 case 'd':
9163 func (stream, "%ld", value);
9164 value_in_comment = value;
9165 break;
9166 case 'e':
9167 func (stream, "%ld", (1ul << width) - value);
9168 break;
9169
9170 case 'S':
9171 case 'T':
9172 case 'U':
9173 /* Various width encodings. */
9174 {
9175 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9176 int limit;
9177 unsigned low, high;
9178
9179 c++;
9180 if (*c >= '0' && *c <= '9')
9181 limit = *c - '0';
9182 else if (*c >= 'a' && *c <= 'f')
9183 limit = *c - 'a' + 10;
9184 else
9185 abort ();
9186 low = limit >> 2;
9187 high = limit & 3;
9188
9189 if (value < low || value > high)
9190 func (stream, "<illegal width %d>", base << value);
9191 else
9192 func (stream, "%d", base << value);
9193 }
9194 break;
9195 case 'R':
9196 if (given & (1 << 6))
9197 goto Q;
9198 /* FALLTHROUGH */
9199 case 'D':
9200 func (stream, "d%ld", value);
9201 break;
9202 case 'Q':
9203 Q:
9204 if (value & 1)
9205 func (stream, "<illegal reg q%ld.5>", value >> 1);
9206 else
9207 func (stream, "q%ld", value >> 1);
9208 break;
9209
9210 case '`':
9211 c++;
9212 if (value == 0)
9213 func (stream, "%c", *c);
9214 break;
9215 case '\'':
9216 c++;
9217 if (value == ((1ul << width) - 1))
9218 func (stream, "%c", *c);
9219 break;
9220 case '?':
9221 func (stream, "%c", c[(1 << width) - (int) value]);
9222 c += 1 << width;
9223 break;
9224 default:
9225 abort ();
9226 }
9227 }
9228 break;
9229
9230 default:
9231 abort ();
9232 }
9233 }
9234 else
9235 func (stream, "%c", *c);
9236 }
9237
9238 if (value_in_comment > 32 || value_in_comment < -16)
9239 func (stream, "\t; 0x%lx", value_in_comment);
9240
9241 if (is_unpredictable)
9242 func (stream, UNPREDICTABLE_INSTRUCTION);
9243
9244 return TRUE;
9245 }
9246 }
9247 return FALSE;
9248 }
9249
9250 /* Print one mve instruction on INFO->STREAM.
9251 Return TRUE if the instuction matched, FALSE if this is not a
9252 recognised mve instruction. */
9253
9254 static bfd_boolean
9255 print_insn_mve (struct disassemble_info *info, long given)
9256 {
9257 const struct mopcode32 *insn;
9258 void *stream = info->stream;
9259 fprintf_ftype func = info->fprintf_func;
9260
9261 for (insn = mve_opcodes; insn->assembler; insn++)
9262 {
9263 if (((given & insn->mask) == insn->value)
9264 && !is_mve_encoding_conflict (given, insn->mve_op))
9265 {
9266 signed long value_in_comment = 0;
9267 bfd_boolean is_unpredictable = FALSE;
9268 bfd_boolean is_undefined = FALSE;
9269 const char *c;
9270 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9271 enum mve_undefined undefined_cond = UNDEF_NONE;
9272
9273 /* Most vector mve instruction are illegal in a it block.
9274 There are a few exceptions; check for them. */
9275 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9276 {
9277 is_unpredictable = TRUE;
9278 unpredictable_cond = UNPRED_IT_BLOCK;
9279 }
9280 else if (is_mve_unpredictable (given, insn->mve_op,
9281 &unpredictable_cond))
9282 is_unpredictable = TRUE;
9283
9284 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9285 is_undefined = TRUE;
9286
9287 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9288 i.e "VMOV Qd, Qm". */
9289 if ((insn->mve_op == MVE_VORR_REG)
9290 && (arm_decode_field (given, 1, 3)
9291 == arm_decode_field (given, 17, 19)))
9292 continue;
9293
9294 for (c = insn->assembler; *c; c++)
9295 {
9296 if (*c == '%')
9297 {
9298 switch (*++c)
9299 {
9300 case '%':
9301 func (stream, "%%");
9302 break;
9303
9304 case 'a':
9305 /* Don't print anything for '+' as it is implied. */
9306 if (arm_decode_field (given, 23, 23) == 0)
9307 func (stream, "-");
9308 break;
9309
9310 case 'c':
9311 if (ifthen_state)
9312 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9313 break;
9314
9315 case 'd':
9316 print_mve_vld_str_addr (info, given, insn->mve_op);
9317 break;
9318
9319 case 'i':
9320 {
9321 long mve_mask = mve_extract_pred_mask (given);
9322 func (stream, "%s", mve_predicatenames[mve_mask]);
9323 }
9324 break;
9325
9326 case 'j':
9327 {
9328 unsigned int imm5 = 0;
9329 imm5 |= arm_decode_field (given, 6, 7);
9330 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9331 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9332 }
9333 break;
9334
9335 case 'k':
9336 func (stream, "#%u",
9337 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9338 break;
9339
9340 case 'n':
9341 print_vec_condition (info, given, insn->mve_op);
9342 break;
9343
9344 case 'o':
9345 if (arm_decode_field (given, 0, 0) == 1)
9346 {
9347 unsigned long size
9348 = arm_decode_field (given, 4, 4)
9349 | (arm_decode_field (given, 6, 6) << 1);
9350
9351 func (stream, ", uxtw #%lu", size);
9352 }
9353 break;
9354
9355 case 'm':
9356 print_mve_rounding_mode (info, given, insn->mve_op);
9357 break;
9358
9359 case 's':
9360 print_mve_vcvt_size (info, given, insn->mve_op);
9361 break;
9362
9363 case 'u':
9364 {
9365 unsigned long op1 = arm_decode_field (given, 21, 22);
9366
9367 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9368 {
9369 /* Check for signed. */
9370 if (arm_decode_field (given, 23, 23) == 0)
9371 {
9372 /* We don't print 's' for S32. */
9373 if ((arm_decode_field (given, 5, 6) == 0)
9374 && ((op1 == 0) || (op1 == 1)))
9375 ;
9376 else
9377 func (stream, "s");
9378 }
9379 else
9380 func (stream, "u");
9381 }
9382 else
9383 {
9384 if (arm_decode_field (given, 28, 28) == 0)
9385 func (stream, "s");
9386 else
9387 func (stream, "u");
9388 }
9389 }
9390 break;
9391
9392 case 'v':
9393 print_instruction_predicate (info);
9394 break;
9395
9396 case 'w':
9397 if (arm_decode_field (given, 21, 21) == 1)
9398 func (stream, "!");
9399 break;
9400
9401 case 'B':
9402 print_mve_register_blocks (info, given, insn->mve_op);
9403 break;
9404
9405 case 'E':
9406 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9407
9408 print_simd_imm8 (info, given, 28, insn);
9409 break;
9410
9411 case 'N':
9412 print_mve_vmov_index (info, given);
9413 break;
9414
9415 case 'T':
9416 if (arm_decode_field (given, 12, 12) == 0)
9417 func (stream, "b");
9418 else
9419 func (stream, "t");
9420 break;
9421
9422 case 'X':
9423 if (arm_decode_field (given, 12, 12) == 1)
9424 func (stream, "x");
9425 break;
9426
9427 case '0': case '1': case '2': case '3': case '4':
9428 case '5': case '6': case '7': case '8': case '9':
9429 {
9430 int width;
9431 unsigned long value;
9432
9433 c = arm_decode_bitfield (c, given, &value, &width);
9434
9435 switch (*c)
9436 {
9437 case 'Z':
9438 if (value == 13)
9439 is_unpredictable = TRUE;
9440 else if (value == 15)
9441 func (stream, "zr");
9442 else
9443 func (stream, "%s", arm_regnames[value]);
9444 break;
9445
9446 case 'c':
9447 func (stream, "%s", arm_conditional[value]);
9448 break;
9449
9450 case 'C':
9451 value ^= 1;
9452 func (stream, "%s", arm_conditional[value]);
9453 break;
9454
9455 case 'S':
9456 if (value == 13 || value == 15)
9457 is_unpredictable = TRUE;
9458 else
9459 func (stream, "%s", arm_regnames[value]);
9460 break;
9461
9462 case 's':
9463 print_mve_size (info,
9464 value,
9465 insn->mve_op);
9466 break;
9467 case 'I':
9468 if (value == 1)
9469 func (stream, "i");
9470 break;
9471 case 'A':
9472 if (value == 1)
9473 func (stream, "a");
9474 break;
9475 case 'h':
9476 {
9477 unsigned int odd_reg = (value << 1) | 1;
9478 func (stream, "%s", arm_regnames[odd_reg]);
9479 }
9480 break;
9481 case 'i':
9482 {
9483 unsigned long imm
9484 = arm_decode_field (given, 0, 6);
9485 unsigned long mod_imm = imm;
9486
9487 switch (insn->mve_op)
9488 {
9489 case MVE_VLDRW_GATHER_T5:
9490 case MVE_VSTRW_SCATTER_T5:
9491 mod_imm = mod_imm << 2;
9492 break;
9493 case MVE_VSTRD_SCATTER_T6:
9494 case MVE_VLDRD_GATHER_T6:
9495 mod_imm = mod_imm << 3;
9496 break;
9497
9498 default:
9499 break;
9500 }
9501
9502 func (stream, "%lu", mod_imm);
9503 }
9504 break;
9505 case 'k':
9506 func (stream, "%lu", 64 - value);
9507 break;
9508 case 'l':
9509 {
9510 unsigned int even_reg = value << 1;
9511 func (stream, "%s", arm_regnames[even_reg]);
9512 }
9513 break;
9514 case 'u':
9515 switch (value)
9516 {
9517 case 0:
9518 func (stream, "1");
9519 break;
9520 case 1:
9521 func (stream, "2");
9522 break;
9523 case 2:
9524 func (stream, "4");
9525 break;
9526 case 3:
9527 func (stream, "8");
9528 break;
9529 default:
9530 break;
9531 }
9532 break;
9533 case 'o':
9534 print_mve_rotate (info, value, width);
9535 break;
9536 case 'r':
9537 func (stream, "%s", arm_regnames[value]);
9538 break;
9539 case 'd':
9540 if (insn->mve_op == MVE_VQSHL_T2
9541 || insn->mve_op == MVE_VQSHLU_T3
9542 || insn->mve_op == MVE_VRSHR
9543 || insn->mve_op == MVE_VRSHRN
9544 || insn->mve_op == MVE_VSHL_T1
9545 || insn->mve_op == MVE_VSHLL_T1
9546 || insn->mve_op == MVE_VSHR
9547 || insn->mve_op == MVE_VSHRN
9548 || insn->mve_op == MVE_VSLI
9549 || insn->mve_op == MVE_VSRI)
9550 print_mve_shift_n (info, given, insn->mve_op);
9551 else if (insn->mve_op == MVE_VSHLL_T2)
9552 {
9553 switch (value)
9554 {
9555 case 0x00:
9556 func (stream, "8");
9557 break;
9558 case 0x01:
9559 func (stream, "16");
9560 break;
9561 case 0x10:
9562 print_mve_undefined (info, UNDEF_SIZE_0);
9563 break;
9564 default:
9565 assert (0);
9566 break;
9567 }
9568 }
9569 else
9570 {
9571 if (insn->mve_op == MVE_VSHLC && value == 0)
9572 value = 32;
9573 func (stream, "%ld", value);
9574 value_in_comment = value;
9575 }
9576 break;
9577 case 'F':
9578 func (stream, "s%ld", value);
9579 break;
9580 case 'Q':
9581 if (value & 0x8)
9582 func (stream, "<illegal reg q%ld.5>", value);
9583 else
9584 func (stream, "q%ld", value);
9585 break;
9586 case 'x':
9587 func (stream, "0x%08lx", value);
9588 break;
9589 default:
9590 abort ();
9591 }
9592 break;
9593 default:
9594 abort ();
9595 }
9596 }
9597 }
9598 else
9599 func (stream, "%c", *c);
9600 }
9601
9602 if (value_in_comment > 32 || value_in_comment < -16)
9603 func (stream, "\t; 0x%lx", value_in_comment);
9604
9605 if (is_unpredictable)
9606 print_mve_unpredictable (info, unpredictable_cond);
9607
9608 if (is_undefined)
9609 print_mve_undefined (info, undefined_cond);
9610
9611 if ((vpt_block_state.in_vpt_block == FALSE)
9612 && !ifthen_state
9613 && (is_vpt_instruction (given) == TRUE))
9614 mark_inside_vpt_block (given);
9615 else if (vpt_block_state.in_vpt_block == TRUE)
9616 update_vpt_block_state ();
9617
9618 return TRUE;
9619 }
9620 }
9621 return FALSE;
9622 }
9623
9624
9625 /* Return the name of a v7A special register. */
9626
9627 static const char *
9628 banked_regname (unsigned reg)
9629 {
9630 switch (reg)
9631 {
9632 case 15: return "CPSR";
9633 case 32: return "R8_usr";
9634 case 33: return "R9_usr";
9635 case 34: return "R10_usr";
9636 case 35: return "R11_usr";
9637 case 36: return "R12_usr";
9638 case 37: return "SP_usr";
9639 case 38: return "LR_usr";
9640 case 40: return "R8_fiq";
9641 case 41: return "R9_fiq";
9642 case 42: return "R10_fiq";
9643 case 43: return "R11_fiq";
9644 case 44: return "R12_fiq";
9645 case 45: return "SP_fiq";
9646 case 46: return "LR_fiq";
9647 case 48: return "LR_irq";
9648 case 49: return "SP_irq";
9649 case 50: return "LR_svc";
9650 case 51: return "SP_svc";
9651 case 52: return "LR_abt";
9652 case 53: return "SP_abt";
9653 case 54: return "LR_und";
9654 case 55: return "SP_und";
9655 case 60: return "LR_mon";
9656 case 61: return "SP_mon";
9657 case 62: return "ELR_hyp";
9658 case 63: return "SP_hyp";
9659 case 79: return "SPSR";
9660 case 110: return "SPSR_fiq";
9661 case 112: return "SPSR_irq";
9662 case 114: return "SPSR_svc";
9663 case 116: return "SPSR_abt";
9664 case 118: return "SPSR_und";
9665 case 124: return "SPSR_mon";
9666 case 126: return "SPSR_hyp";
9667 default: return NULL;
9668 }
9669 }
9670
9671 /* Return the name of the DMB/DSB option. */
9672 static const char *
9673 data_barrier_option (unsigned option)
9674 {
9675 switch (option & 0xf)
9676 {
9677 case 0xf: return "sy";
9678 case 0xe: return "st";
9679 case 0xd: return "ld";
9680 case 0xb: return "ish";
9681 case 0xa: return "ishst";
9682 case 0x9: return "ishld";
9683 case 0x7: return "un";
9684 case 0x6: return "unst";
9685 case 0x5: return "nshld";
9686 case 0x3: return "osh";
9687 case 0x2: return "oshst";
9688 case 0x1: return "oshld";
9689 default: return NULL;
9690 }
9691 }
9692
9693 /* Print one ARM instruction from PC on INFO->STREAM. */
9694
9695 static void
9696 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
9697 {
9698 const struct opcode32 *insn;
9699 void *stream = info->stream;
9700 fprintf_ftype func = info->fprintf_func;
9701 struct arm_private_data *private_data = info->private_data;
9702
9703 if (print_insn_coprocessor (pc, info, given, FALSE))
9704 return;
9705
9706 if (print_insn_neon (info, given, FALSE))
9707 return;
9708
9709 if (print_insn_generic_coprocessor (pc, info, given, FALSE))
9710 return;
9711
9712 for (insn = arm_opcodes; insn->assembler; insn++)
9713 {
9714 if ((given & insn->mask) != insn->value)
9715 continue;
9716
9717 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
9718 continue;
9719
9720 /* Special case: an instruction with all bits set in the condition field
9721 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9722 or by the catchall at the end of the table. */
9723 if ((given & 0xF0000000) != 0xF0000000
9724 || (insn->mask & 0xF0000000) == 0xF0000000
9725 || (insn->mask == 0 && insn->value == 0))
9726 {
9727 unsigned long u_reg = 16;
9728 unsigned long U_reg = 16;
9729 bfd_boolean is_unpredictable = FALSE;
9730 signed long value_in_comment = 0;
9731 const char *c;
9732
9733 for (c = insn->assembler; *c; c++)
9734 {
9735 if (*c == '%')
9736 {
9737 bfd_boolean allow_unpredictable = FALSE;
9738
9739 switch (*++c)
9740 {
9741 case '%':
9742 func (stream, "%%");
9743 break;
9744
9745 case 'a':
9746 value_in_comment = print_arm_address (pc, info, given);
9747 break;
9748
9749 case 'P':
9750 /* Set P address bit and use normal address
9751 printing routine. */
9752 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
9753 break;
9754
9755 case 'S':
9756 allow_unpredictable = TRUE;
9757 /* Fall through. */
9758 case 's':
9759 if ((given & 0x004f0000) == 0x004f0000)
9760 {
9761 /* PC relative with immediate offset. */
9762 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
9763
9764 if (PRE_BIT_SET)
9765 {
9766 /* Elide positive zero offset. */
9767 if (offset || NEGATIVE_BIT_SET)
9768 func (stream, "[pc, #%s%d]\t; ",
9769 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9770 else
9771 func (stream, "[pc]\t; ");
9772 if (NEGATIVE_BIT_SET)
9773 offset = -offset;
9774 info->print_address_func (offset + pc + 8, info);
9775 }
9776 else
9777 {
9778 /* Always show the offset. */
9779 func (stream, "[pc], #%s%d",
9780 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9781 if (! allow_unpredictable)
9782 is_unpredictable = TRUE;
9783 }
9784 }
9785 else
9786 {
9787 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9788
9789 func (stream, "[%s",
9790 arm_regnames[(given >> 16) & 0xf]);
9791
9792 if (PRE_BIT_SET)
9793 {
9794 if (IMMEDIATE_BIT_SET)
9795 {
9796 /* Elide offset for non-writeback
9797 positive zero. */
9798 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9799 || offset)
9800 func (stream, ", #%s%d",
9801 NEGATIVE_BIT_SET ? "-" : "", offset);
9802
9803 if (NEGATIVE_BIT_SET)
9804 offset = -offset;
9805
9806 value_in_comment = offset;
9807 }
9808 else
9809 {
9810 /* Register Offset or Register Pre-Indexed. */
9811 func (stream, ", %s%s",
9812 NEGATIVE_BIT_SET ? "-" : "",
9813 arm_regnames[given & 0xf]);
9814
9815 /* Writing back to the register that is the source/
9816 destination of the load/store is unpredictable. */
9817 if (! allow_unpredictable
9818 && WRITEBACK_BIT_SET
9819 && ((given & 0xf) == ((given >> 12) & 0xf)))
9820 is_unpredictable = TRUE;
9821 }
9822
9823 func (stream, "]%s",
9824 WRITEBACK_BIT_SET ? "!" : "");
9825 }
9826 else
9827 {
9828 if (IMMEDIATE_BIT_SET)
9829 {
9830 /* Immediate Post-indexed. */
9831 /* PR 10924: Offset must be printed, even if it is zero. */
9832 func (stream, "], #%s%d",
9833 NEGATIVE_BIT_SET ? "-" : "", offset);
9834 if (NEGATIVE_BIT_SET)
9835 offset = -offset;
9836 value_in_comment = offset;
9837 }
9838 else
9839 {
9840 /* Register Post-indexed. */
9841 func (stream, "], %s%s",
9842 NEGATIVE_BIT_SET ? "-" : "",
9843 arm_regnames[given & 0xf]);
9844
9845 /* Writing back to the register that is the source/
9846 destination of the load/store is unpredictable. */
9847 if (! allow_unpredictable
9848 && (given & 0xf) == ((given >> 12) & 0xf))
9849 is_unpredictable = TRUE;
9850 }
9851
9852 if (! allow_unpredictable)
9853 {
9854 /* Writeback is automatically implied by post- addressing.
9855 Setting the W bit is unnecessary and ARM specify it as
9856 being unpredictable. */
9857 if (WRITEBACK_BIT_SET
9858 /* Specifying the PC register as the post-indexed
9859 registers is also unpredictable. */
9860 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9861 is_unpredictable = TRUE;
9862 }
9863 }
9864 }
9865 break;
9866
9867 case 'b':
9868 {
9869 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
9870 info->print_address_func (disp * 4 + pc + 8, info);
9871 }
9872 break;
9873
9874 case 'c':
9875 if (((given >> 28) & 0xf) != 0xe)
9876 func (stream, "%s",
9877 arm_conditional [(given >> 28) & 0xf]);
9878 break;
9879
9880 case 'm':
9881 {
9882 int started = 0;
9883 int reg;
9884
9885 func (stream, "{");
9886 for (reg = 0; reg < 16; reg++)
9887 if ((given & (1 << reg)) != 0)
9888 {
9889 if (started)
9890 func (stream, ", ");
9891 started = 1;
9892 func (stream, "%s", arm_regnames[reg]);
9893 }
9894 func (stream, "}");
9895 if (! started)
9896 is_unpredictable = TRUE;
9897 }
9898 break;
9899
9900 case 'q':
9901 arm_decode_shift (given, func, stream, FALSE);
9902 break;
9903
9904 case 'o':
9905 if ((given & 0x02000000) != 0)
9906 {
9907 unsigned int rotate = (given & 0xf00) >> 7;
9908 unsigned int immed = (given & 0xff);
9909 unsigned int a, i;
9910
9911 a = (((immed << (32 - rotate))
9912 | (immed >> rotate)) & 0xffffffff);
9913 /* If there is another encoding with smaller rotate,
9914 the rotate should be specified directly. */
9915 for (i = 0; i < 32; i += 2)
9916 if ((a << i | a >> (32 - i)) <= 0xff)
9917 break;
9918
9919 if (i != rotate)
9920 func (stream, "#%d, %d", immed, rotate);
9921 else
9922 func (stream, "#%d", a);
9923 value_in_comment = a;
9924 }
9925 else
9926 arm_decode_shift (given, func, stream, TRUE);
9927 break;
9928
9929 case 'p':
9930 if ((given & 0x0000f000) == 0x0000f000)
9931 {
9932 arm_feature_set arm_ext_v6 =
9933 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9934
9935 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9936 mechanism for setting PSR flag bits. They are
9937 obsolete in V6 onwards. */
9938 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9939 arm_ext_v6))
9940 func (stream, "p");
9941 else
9942 is_unpredictable = TRUE;
9943 }
9944 break;
9945
9946 case 't':
9947 if ((given & 0x01200000) == 0x00200000)
9948 func (stream, "t");
9949 break;
9950
9951 case 'A':
9952 {
9953 int offset = given & 0xff;
9954
9955 value_in_comment = offset * 4;
9956 if (NEGATIVE_BIT_SET)
9957 value_in_comment = - value_in_comment;
9958
9959 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
9960
9961 if (PRE_BIT_SET)
9962 {
9963 if (offset)
9964 func (stream, ", #%d]%s",
9965 (int) value_in_comment,
9966 WRITEBACK_BIT_SET ? "!" : "");
9967 else
9968 func (stream, "]");
9969 }
9970 else
9971 {
9972 func (stream, "]");
9973
9974 if (WRITEBACK_BIT_SET)
9975 {
9976 if (offset)
9977 func (stream, ", #%d", (int) value_in_comment);
9978 }
9979 else
9980 {
9981 func (stream, ", {%d}", (int) offset);
9982 value_in_comment = offset;
9983 }
9984 }
9985 }
9986 break;
9987
9988 case 'B':
9989 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9990 {
9991 bfd_vma address;
9992 bfd_vma offset = 0;
9993
9994 if (! NEGATIVE_BIT_SET)
9995 /* Is signed, hi bits should be ones. */
9996 offset = (-1) ^ 0x00ffffff;
9997
9998 /* Offset is (SignExtend(offset field)<<2). */
9999 offset += given & 0x00ffffff;
10000 offset <<= 2;
10001 address = offset + pc + 8;
10002
10003 if (given & 0x01000000)
10004 /* H bit allows addressing to 2-byte boundaries. */
10005 address += 2;
10006
10007 info->print_address_func (address, info);
10008 }
10009 break;
10010
10011 case 'C':
10012 if ((given & 0x02000200) == 0x200)
10013 {
10014 const char * name;
10015 unsigned sysm = (given & 0x004f0000) >> 16;
10016
10017 sysm |= (given & 0x300) >> 4;
10018 name = banked_regname (sysm);
10019
10020 if (name != NULL)
10021 func (stream, "%s", name);
10022 else
10023 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10024 }
10025 else
10026 {
10027 func (stream, "%cPSR_",
10028 (given & 0x00400000) ? 'S' : 'C');
10029 if (given & 0x80000)
10030 func (stream, "f");
10031 if (given & 0x40000)
10032 func (stream, "s");
10033 if (given & 0x20000)
10034 func (stream, "x");
10035 if (given & 0x10000)
10036 func (stream, "c");
10037 }
10038 break;
10039
10040 case 'U':
10041 if ((given & 0xf0) == 0x60)
10042 {
10043 switch (given & 0xf)
10044 {
10045 case 0xf: func (stream, "sy"); break;
10046 default:
10047 func (stream, "#%d", (int) given & 0xf);
10048 break;
10049 }
10050 }
10051 else
10052 {
10053 const char * opt = data_barrier_option (given & 0xf);
10054 if (opt != NULL)
10055 func (stream, "%s", opt);
10056 else
10057 func (stream, "#%d", (int) given & 0xf);
10058 }
10059 break;
10060
10061 case '0': case '1': case '2': case '3': case '4':
10062 case '5': case '6': case '7': case '8': case '9':
10063 {
10064 int width;
10065 unsigned long value;
10066
10067 c = arm_decode_bitfield (c, given, &value, &width);
10068
10069 switch (*c)
10070 {
10071 case 'R':
10072 if (value == 15)
10073 is_unpredictable = TRUE;
10074 /* Fall through. */
10075 case 'r':
10076 case 'T':
10077 /* We want register + 1 when decoding T. */
10078 if (*c == 'T')
10079 ++value;
10080
10081 if (c[1] == 'u')
10082 {
10083 /* Eat the 'u' character. */
10084 ++ c;
10085
10086 if (u_reg == value)
10087 is_unpredictable = TRUE;
10088 u_reg = value;
10089 }
10090 if (c[1] == 'U')
10091 {
10092 /* Eat the 'U' character. */
10093 ++ c;
10094
10095 if (U_reg == value)
10096 is_unpredictable = TRUE;
10097 U_reg = value;
10098 }
10099 func (stream, "%s", arm_regnames[value]);
10100 break;
10101 case 'd':
10102 func (stream, "%ld", value);
10103 value_in_comment = value;
10104 break;
10105 case 'b':
10106 func (stream, "%ld", value * 8);
10107 value_in_comment = value * 8;
10108 break;
10109 case 'W':
10110 func (stream, "%ld", value + 1);
10111 value_in_comment = value + 1;
10112 break;
10113 case 'x':
10114 func (stream, "0x%08lx", value);
10115
10116 /* Some SWI instructions have special
10117 meanings. */
10118 if ((given & 0x0fffffff) == 0x0FF00000)
10119 func (stream, "\t; IMB");
10120 else if ((given & 0x0fffffff) == 0x0FF00001)
10121 func (stream, "\t; IMBRange");
10122 break;
10123 case 'X':
10124 func (stream, "%01lx", value & 0xf);
10125 value_in_comment = value;
10126 break;
10127 case '`':
10128 c++;
10129 if (value == 0)
10130 func (stream, "%c", *c);
10131 break;
10132 case '\'':
10133 c++;
10134 if (value == ((1ul << width) - 1))
10135 func (stream, "%c", *c);
10136 break;
10137 case '?':
10138 func (stream, "%c", c[(1 << width) - (int) value]);
10139 c += 1 << width;
10140 break;
10141 default:
10142 abort ();
10143 }
10144 }
10145 break;
10146
10147 case 'e':
10148 {
10149 int imm;
10150
10151 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10152 func (stream, "%d", imm);
10153 value_in_comment = imm;
10154 }
10155 break;
10156
10157 case 'E':
10158 /* LSB and WIDTH fields of BFI or BFC. The machine-
10159 language instruction encodes LSB and MSB. */
10160 {
10161 long msb = (given & 0x001f0000) >> 16;
10162 long lsb = (given & 0x00000f80) >> 7;
10163 long w = msb - lsb + 1;
10164
10165 if (w > 0)
10166 func (stream, "#%lu, #%lu", lsb, w);
10167 else
10168 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10169 }
10170 break;
10171
10172 case 'R':
10173 /* Get the PSR/banked register name. */
10174 {
10175 const char * name;
10176 unsigned sysm = (given & 0x004f0000) >> 16;
10177
10178 sysm |= (given & 0x300) >> 4;
10179 name = banked_regname (sysm);
10180
10181 if (name != NULL)
10182 func (stream, "%s", name);
10183 else
10184 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10185 }
10186 break;
10187
10188 case 'V':
10189 /* 16-bit unsigned immediate from a MOVT or MOVW
10190 instruction, encoded in bits 0:11 and 15:19. */
10191 {
10192 long hi = (given & 0x000f0000) >> 4;
10193 long lo = (given & 0x00000fff);
10194 long imm16 = hi | lo;
10195
10196 func (stream, "#%lu", imm16);
10197 value_in_comment = imm16;
10198 }
10199 break;
10200
10201 default:
10202 abort ();
10203 }
10204 }
10205 else
10206 func (stream, "%c", *c);
10207 }
10208
10209 if (value_in_comment > 32 || value_in_comment < -16)
10210 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
10211
10212 if (is_unpredictable)
10213 func (stream, UNPREDICTABLE_INSTRUCTION);
10214
10215 return;
10216 }
10217 }
10218 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10219 return;
10220 }
10221
10222 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10223
10224 static void
10225 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10226 {
10227 const struct opcode16 *insn;
10228 void *stream = info->stream;
10229 fprintf_ftype func = info->fprintf_func;
10230
10231 for (insn = thumb_opcodes; insn->assembler; insn++)
10232 if ((given & insn->mask) == insn->value)
10233 {
10234 signed long value_in_comment = 0;
10235 const char *c = insn->assembler;
10236
10237 for (; *c; c++)
10238 {
10239 int domaskpc = 0;
10240 int domasklr = 0;
10241
10242 if (*c != '%')
10243 {
10244 func (stream, "%c", *c);
10245 continue;
10246 }
10247
10248 switch (*++c)
10249 {
10250 case '%':
10251 func (stream, "%%");
10252 break;
10253
10254 case 'c':
10255 if (ifthen_state)
10256 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10257 break;
10258
10259 case 'C':
10260 if (ifthen_state)
10261 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10262 else
10263 func (stream, "s");
10264 break;
10265
10266 case 'I':
10267 {
10268 unsigned int tmp;
10269
10270 ifthen_next_state = given & 0xff;
10271 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10272 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10273 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10274 }
10275 break;
10276
10277 case 'x':
10278 if (ifthen_next_state)
10279 func (stream, "\t; unpredictable branch in IT block\n");
10280 break;
10281
10282 case 'X':
10283 if (ifthen_state)
10284 func (stream, "\t; unpredictable <IT:%s>",
10285 arm_conditional[IFTHEN_COND]);
10286 break;
10287
10288 case 'S':
10289 {
10290 long reg;
10291
10292 reg = (given >> 3) & 0x7;
10293 if (given & (1 << 6))
10294 reg += 8;
10295
10296 func (stream, "%s", arm_regnames[reg]);
10297 }
10298 break;
10299
10300 case 'D':
10301 {
10302 long reg;
10303
10304 reg = given & 0x7;
10305 if (given & (1 << 7))
10306 reg += 8;
10307
10308 func (stream, "%s", arm_regnames[reg]);
10309 }
10310 break;
10311
10312 case 'N':
10313 if (given & (1 << 8))
10314 domasklr = 1;
10315 /* Fall through. */
10316 case 'O':
10317 if (*c == 'O' && (given & (1 << 8)))
10318 domaskpc = 1;
10319 /* Fall through. */
10320 case 'M':
10321 {
10322 int started = 0;
10323 int reg;
10324
10325 func (stream, "{");
10326
10327 /* It would be nice if we could spot
10328 ranges, and generate the rS-rE format: */
10329 for (reg = 0; (reg < 8); reg++)
10330 if ((given & (1 << reg)) != 0)
10331 {
10332 if (started)
10333 func (stream, ", ");
10334 started = 1;
10335 func (stream, "%s", arm_regnames[reg]);
10336 }
10337
10338 if (domasklr)
10339 {
10340 if (started)
10341 func (stream, ", ");
10342 started = 1;
10343 func (stream, "%s", arm_regnames[14] /* "lr" */);
10344 }
10345
10346 if (domaskpc)
10347 {
10348 if (started)
10349 func (stream, ", ");
10350 func (stream, "%s", arm_regnames[15] /* "pc" */);
10351 }
10352
10353 func (stream, "}");
10354 }
10355 break;
10356
10357 case 'W':
10358 /* Print writeback indicator for a LDMIA. We are doing a
10359 writeback if the base register is not in the register
10360 mask. */
10361 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10362 func (stream, "!");
10363 break;
10364
10365 case 'b':
10366 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10367 {
10368 bfd_vma address = (pc + 4
10369 + ((given & 0x00f8) >> 2)
10370 + ((given & 0x0200) >> 3));
10371 info->print_address_func (address, info);
10372 }
10373 break;
10374
10375 case 's':
10376 /* Right shift immediate -- bits 6..10; 1-31 print
10377 as themselves, 0 prints as 32. */
10378 {
10379 long imm = (given & 0x07c0) >> 6;
10380 if (imm == 0)
10381 imm = 32;
10382 func (stream, "#%ld", imm);
10383 }
10384 break;
10385
10386 case '0': case '1': case '2': case '3': case '4':
10387 case '5': case '6': case '7': case '8': case '9':
10388 {
10389 int bitstart = *c++ - '0';
10390 int bitend = 0;
10391
10392 while (*c >= '0' && *c <= '9')
10393 bitstart = (bitstart * 10) + *c++ - '0';
10394
10395 switch (*c)
10396 {
10397 case '-':
10398 {
10399 bfd_vma reg;
10400
10401 c++;
10402 while (*c >= '0' && *c <= '9')
10403 bitend = (bitend * 10) + *c++ - '0';
10404 if (!bitend)
10405 abort ();
10406 reg = given >> bitstart;
10407 reg &= (2 << (bitend - bitstart)) - 1;
10408
10409 switch (*c)
10410 {
10411 case 'r':
10412 func (stream, "%s", arm_regnames[reg]);
10413 break;
10414
10415 case 'd':
10416 func (stream, "%ld", (long) reg);
10417 value_in_comment = reg;
10418 break;
10419
10420 case 'H':
10421 func (stream, "%ld", (long) (reg << 1));
10422 value_in_comment = reg << 1;
10423 break;
10424
10425 case 'W':
10426 func (stream, "%ld", (long) (reg << 2));
10427 value_in_comment = reg << 2;
10428 break;
10429
10430 case 'a':
10431 /* PC-relative address -- the bottom two
10432 bits of the address are dropped
10433 before the calculation. */
10434 info->print_address_func
10435 (((pc + 4) & ~3) + (reg << 2), info);
10436 value_in_comment = 0;
10437 break;
10438
10439 case 'x':
10440 func (stream, "0x%04lx", (long) reg);
10441 break;
10442
10443 case 'B':
10444 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
10445 info->print_address_func (reg * 2 + pc + 4, info);
10446 value_in_comment = 0;
10447 break;
10448
10449 case 'c':
10450 func (stream, "%s", arm_conditional [reg]);
10451 break;
10452
10453 default:
10454 abort ();
10455 }
10456 }
10457 break;
10458
10459 case '\'':
10460 c++;
10461 if ((given & (1 << bitstart)) != 0)
10462 func (stream, "%c", *c);
10463 break;
10464
10465 case '?':
10466 ++c;
10467 if ((given & (1 << bitstart)) != 0)
10468 func (stream, "%c", *c++);
10469 else
10470 func (stream, "%c", *++c);
10471 break;
10472
10473 default:
10474 abort ();
10475 }
10476 }
10477 break;
10478
10479 default:
10480 abort ();
10481 }
10482 }
10483
10484 if (value_in_comment > 32 || value_in_comment < -16)
10485 func (stream, "\t; 0x%lx", value_in_comment);
10486 return;
10487 }
10488
10489 /* No match. */
10490 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10491 return;
10492 }
10493
10494 /* Return the name of an V7M special register. */
10495
10496 static const char *
10497 psr_name (int regno)
10498 {
10499 switch (regno)
10500 {
10501 case 0x0: return "APSR";
10502 case 0x1: return "IAPSR";
10503 case 0x2: return "EAPSR";
10504 case 0x3: return "PSR";
10505 case 0x5: return "IPSR";
10506 case 0x6: return "EPSR";
10507 case 0x7: return "IEPSR";
10508 case 0x8: return "MSP";
10509 case 0x9: return "PSP";
10510 case 0xa: return "MSPLIM";
10511 case 0xb: return "PSPLIM";
10512 case 0x10: return "PRIMASK";
10513 case 0x11: return "BASEPRI";
10514 case 0x12: return "BASEPRI_MAX";
10515 case 0x13: return "FAULTMASK";
10516 case 0x14: return "CONTROL";
10517 case 0x88: return "MSP_NS";
10518 case 0x89: return "PSP_NS";
10519 case 0x8a: return "MSPLIM_NS";
10520 case 0x8b: return "PSPLIM_NS";
10521 case 0x90: return "PRIMASK_NS";
10522 case 0x91: return "BASEPRI_NS";
10523 case 0x93: return "FAULTMASK_NS";
10524 case 0x94: return "CONTROL_NS";
10525 case 0x98: return "SP_NS";
10526 default: return "<unknown>";
10527 }
10528 }
10529
10530 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10531
10532 static void
10533 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
10534 {
10535 const struct opcode32 *insn;
10536 void *stream = info->stream;
10537 fprintf_ftype func = info->fprintf_func;
10538 bfd_boolean is_mve = is_mve_architecture (info);
10539
10540 if (print_insn_coprocessor (pc, info, given, TRUE))
10541 return;
10542
10543 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10544 return;
10545
10546 if (is_mve && print_insn_mve (info, given))
10547 return;
10548
10549 if (print_insn_generic_coprocessor (pc, info, given, TRUE))
10550 return;
10551
10552 for (insn = thumb32_opcodes; insn->assembler; insn++)
10553 if ((given & insn->mask) == insn->value)
10554 {
10555 bfd_boolean is_clrm = FALSE;
10556 bfd_boolean is_unpredictable = FALSE;
10557 signed long value_in_comment = 0;
10558 const char *c = insn->assembler;
10559
10560 for (; *c; c++)
10561 {
10562 if (*c != '%')
10563 {
10564 func (stream, "%c", *c);
10565 continue;
10566 }
10567
10568 switch (*++c)
10569 {
10570 case '%':
10571 func (stream, "%%");
10572 break;
10573
10574 case 'c':
10575 if (ifthen_state)
10576 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10577 break;
10578
10579 case 'x':
10580 if (ifthen_next_state)
10581 func (stream, "\t; unpredictable branch in IT block\n");
10582 break;
10583
10584 case 'X':
10585 if (ifthen_state)
10586 func (stream, "\t; unpredictable <IT:%s>",
10587 arm_conditional[IFTHEN_COND]);
10588 break;
10589
10590 case 'I':
10591 {
10592 unsigned int imm12 = 0;
10593
10594 imm12 |= (given & 0x000000ffu);
10595 imm12 |= (given & 0x00007000u) >> 4;
10596 imm12 |= (given & 0x04000000u) >> 15;
10597 func (stream, "#%u", imm12);
10598 value_in_comment = imm12;
10599 }
10600 break;
10601
10602 case 'M':
10603 {
10604 unsigned int bits = 0, imm, imm8, mod;
10605
10606 bits |= (given & 0x000000ffu);
10607 bits |= (given & 0x00007000u) >> 4;
10608 bits |= (given & 0x04000000u) >> 15;
10609 imm8 = (bits & 0x0ff);
10610 mod = (bits & 0xf00) >> 8;
10611 switch (mod)
10612 {
10613 case 0: imm = imm8; break;
10614 case 1: imm = ((imm8 << 16) | imm8); break;
10615 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10616 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
10617 default:
10618 mod = (bits & 0xf80) >> 7;
10619 imm8 = (bits & 0x07f) | 0x80;
10620 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10621 }
10622 func (stream, "#%u", imm);
10623 value_in_comment = imm;
10624 }
10625 break;
10626
10627 case 'J':
10628 {
10629 unsigned int imm = 0;
10630
10631 imm |= (given & 0x000000ffu);
10632 imm |= (given & 0x00007000u) >> 4;
10633 imm |= (given & 0x04000000u) >> 15;
10634 imm |= (given & 0x000f0000u) >> 4;
10635 func (stream, "#%u", imm);
10636 value_in_comment = imm;
10637 }
10638 break;
10639
10640 case 'K':
10641 {
10642 unsigned int imm = 0;
10643
10644 imm |= (given & 0x000f0000u) >> 16;
10645 imm |= (given & 0x00000ff0u) >> 0;
10646 imm |= (given & 0x0000000fu) << 12;
10647 func (stream, "#%u", imm);
10648 value_in_comment = imm;
10649 }
10650 break;
10651
10652 case 'H':
10653 {
10654 unsigned int imm = 0;
10655
10656 imm |= (given & 0x000f0000u) >> 4;
10657 imm |= (given & 0x00000fffu) >> 0;
10658 func (stream, "#%u", imm);
10659 value_in_comment = imm;
10660 }
10661 break;
10662
10663 case 'V':
10664 {
10665 unsigned int imm = 0;
10666
10667 imm |= (given & 0x00000fffu);
10668 imm |= (given & 0x000f0000u) >> 4;
10669 func (stream, "#%u", imm);
10670 value_in_comment = imm;
10671 }
10672 break;
10673
10674 case 'S':
10675 {
10676 unsigned int reg = (given & 0x0000000fu);
10677 unsigned int stp = (given & 0x00000030u) >> 4;
10678 unsigned int imm = 0;
10679 imm |= (given & 0x000000c0u) >> 6;
10680 imm |= (given & 0x00007000u) >> 10;
10681
10682 func (stream, "%s", arm_regnames[reg]);
10683 switch (stp)
10684 {
10685 case 0:
10686 if (imm > 0)
10687 func (stream, ", lsl #%u", imm);
10688 break;
10689
10690 case 1:
10691 if (imm == 0)
10692 imm = 32;
10693 func (stream, ", lsr #%u", imm);
10694 break;
10695
10696 case 2:
10697 if (imm == 0)
10698 imm = 32;
10699 func (stream, ", asr #%u", imm);
10700 break;
10701
10702 case 3:
10703 if (imm == 0)
10704 func (stream, ", rrx");
10705 else
10706 func (stream, ", ror #%u", imm);
10707 }
10708 }
10709 break;
10710
10711 case 'a':
10712 {
10713 unsigned int Rn = (given & 0x000f0000) >> 16;
10714 unsigned int U = ! NEGATIVE_BIT_SET;
10715 unsigned int op = (given & 0x00000f00) >> 8;
10716 unsigned int i12 = (given & 0x00000fff);
10717 unsigned int i8 = (given & 0x000000ff);
10718 bfd_boolean writeback = FALSE, postind = FALSE;
10719 bfd_vma offset = 0;
10720
10721 func (stream, "[%s", arm_regnames[Rn]);
10722 if (U) /* 12-bit positive immediate offset. */
10723 {
10724 offset = i12;
10725 if (Rn != 15)
10726 value_in_comment = offset;
10727 }
10728 else if (Rn == 15) /* 12-bit negative immediate offset. */
10729 offset = - (int) i12;
10730 else if (op == 0x0) /* Shifted register offset. */
10731 {
10732 unsigned int Rm = (i8 & 0x0f);
10733 unsigned int sh = (i8 & 0x30) >> 4;
10734
10735 func (stream, ", %s", arm_regnames[Rm]);
10736 if (sh)
10737 func (stream, ", lsl #%u", sh);
10738 func (stream, "]");
10739 break;
10740 }
10741 else switch (op)
10742 {
10743 case 0xE: /* 8-bit positive immediate offset. */
10744 offset = i8;
10745 break;
10746
10747 case 0xC: /* 8-bit negative immediate offset. */
10748 offset = -i8;
10749 break;
10750
10751 case 0xF: /* 8-bit + preindex with wb. */
10752 offset = i8;
10753 writeback = TRUE;
10754 break;
10755
10756 case 0xD: /* 8-bit - preindex with wb. */
10757 offset = -i8;
10758 writeback = TRUE;
10759 break;
10760
10761 case 0xB: /* 8-bit + postindex. */
10762 offset = i8;
10763 postind = TRUE;
10764 break;
10765
10766 case 0x9: /* 8-bit - postindex. */
10767 offset = -i8;
10768 postind = TRUE;
10769 break;
10770
10771 default:
10772 func (stream, ", <undefined>]");
10773 goto skip;
10774 }
10775
10776 if (postind)
10777 func (stream, "], #%d", (int) offset);
10778 else
10779 {
10780 if (offset)
10781 func (stream, ", #%d", (int) offset);
10782 func (stream, writeback ? "]!" : "]");
10783 }
10784
10785 if (Rn == 15)
10786 {
10787 func (stream, "\t; ");
10788 info->print_address_func (((pc + 4) & ~3) + offset, info);
10789 }
10790 }
10791 skip:
10792 break;
10793
10794 case 'A':
10795 {
10796 unsigned int U = ! NEGATIVE_BIT_SET;
10797 unsigned int W = WRITEBACK_BIT_SET;
10798 unsigned int Rn = (given & 0x000f0000) >> 16;
10799 unsigned int off = (given & 0x000000ff);
10800
10801 func (stream, "[%s", arm_regnames[Rn]);
10802
10803 if (PRE_BIT_SET)
10804 {
10805 if (off || !U)
10806 {
10807 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
10808 value_in_comment = off * 4 * (U ? 1 : -1);
10809 }
10810 func (stream, "]");
10811 if (W)
10812 func (stream, "!");
10813 }
10814 else
10815 {
10816 func (stream, "], ");
10817 if (W)
10818 {
10819 func (stream, "#%c%u", U ? '+' : '-', off * 4);
10820 value_in_comment = off * 4 * (U ? 1 : -1);
10821 }
10822 else
10823 {
10824 func (stream, "{%u}", off);
10825 value_in_comment = off;
10826 }
10827 }
10828 }
10829 break;
10830
10831 case 'w':
10832 {
10833 unsigned int Sbit = (given & 0x01000000) >> 24;
10834 unsigned int type = (given & 0x00600000) >> 21;
10835
10836 switch (type)
10837 {
10838 case 0: func (stream, Sbit ? "sb" : "b"); break;
10839 case 1: func (stream, Sbit ? "sh" : "h"); break;
10840 case 2:
10841 if (Sbit)
10842 func (stream, "??");
10843 break;
10844 case 3:
10845 func (stream, "??");
10846 break;
10847 }
10848 }
10849 break;
10850
10851 case 'n':
10852 is_clrm = TRUE;
10853 /* Fall through. */
10854 case 'm':
10855 {
10856 int started = 0;
10857 int reg;
10858
10859 func (stream, "{");
10860 for (reg = 0; reg < 16; reg++)
10861 if ((given & (1 << reg)) != 0)
10862 {
10863 if (started)
10864 func (stream, ", ");
10865 started = 1;
10866 if (is_clrm && reg == 13)
10867 func (stream, "(invalid: %s)", arm_regnames[reg]);
10868 else if (is_clrm && reg == 15)
10869 func (stream, "%s", "APSR");
10870 else
10871 func (stream, "%s", arm_regnames[reg]);
10872 }
10873 func (stream, "}");
10874 }
10875 break;
10876
10877 case 'E':
10878 {
10879 unsigned int msb = (given & 0x0000001f);
10880 unsigned int lsb = 0;
10881
10882 lsb |= (given & 0x000000c0u) >> 6;
10883 lsb |= (given & 0x00007000u) >> 10;
10884 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10885 }
10886 break;
10887
10888 case 'F':
10889 {
10890 unsigned int width = (given & 0x0000001f) + 1;
10891 unsigned int lsb = 0;
10892
10893 lsb |= (given & 0x000000c0u) >> 6;
10894 lsb |= (given & 0x00007000u) >> 10;
10895 func (stream, "#%u, #%u", lsb, width);
10896 }
10897 break;
10898
10899 case 'G':
10900 {
10901 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10902 func (stream, "%x", boff);
10903 }
10904 break;
10905
10906 case 'W':
10907 {
10908 unsigned int immA = (given & 0x001f0000u) >> 16;
10909 unsigned int immB = (given & 0x000007feu) >> 1;
10910 unsigned int immC = (given & 0x00000800u) >> 11;
10911 bfd_vma offset = 0;
10912
10913 offset |= immA << 12;
10914 offset |= immB << 2;
10915 offset |= immC << 1;
10916 /* Sign extend. */
10917 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10918
10919 info->print_address_func (pc + 4 + offset, info);
10920 }
10921 break;
10922
10923 case 'Y':
10924 {
10925 unsigned int immA = (given & 0x007f0000u) >> 16;
10926 unsigned int immB = (given & 0x000007feu) >> 1;
10927 unsigned int immC = (given & 0x00000800u) >> 11;
10928 bfd_vma offset = 0;
10929
10930 offset |= immA << 12;
10931 offset |= immB << 2;
10932 offset |= immC << 1;
10933 /* Sign extend. */
10934 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10935
10936 info->print_address_func (pc + 4 + offset, info);
10937 }
10938 break;
10939
10940 case 'Z':
10941 {
10942 unsigned int immA = (given & 0x00010000u) >> 16;
10943 unsigned int immB = (given & 0x000007feu) >> 1;
10944 unsigned int immC = (given & 0x00000800u) >> 11;
10945 bfd_vma offset = 0;
10946
10947 offset |= immA << 12;
10948 offset |= immB << 2;
10949 offset |= immC << 1;
10950 /* Sign extend. */
10951 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10952
10953 info->print_address_func (pc + 4 + offset, info);
10954
10955 unsigned int T = (given & 0x00020000u) >> 17;
10956 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10957 unsigned int boffset = (T == 1) ? 4 : 2;
10958 func (stream, ", ");
10959 func (stream, "%x", endoffset + boffset);
10960 }
10961 break;
10962
10963 case 'Q':
10964 {
10965 unsigned int immh = (given & 0x000007feu) >> 1;
10966 unsigned int imml = (given & 0x00000800u) >> 11;
10967 bfd_vma imm32 = 0;
10968
10969 imm32 |= immh << 2;
10970 imm32 |= imml << 1;
10971
10972 info->print_address_func (pc + 4 + imm32, info);
10973 }
10974 break;
10975
10976 case 'P':
10977 {
10978 unsigned int immh = (given & 0x000007feu) >> 1;
10979 unsigned int imml = (given & 0x00000800u) >> 11;
10980 bfd_vma imm32 = 0;
10981
10982 imm32 |= immh << 2;
10983 imm32 |= imml << 1;
10984
10985 info->print_address_func (pc + 4 - imm32, info);
10986 }
10987 break;
10988
10989 case 'b':
10990 {
10991 unsigned int S = (given & 0x04000000u) >> 26;
10992 unsigned int J1 = (given & 0x00002000u) >> 13;
10993 unsigned int J2 = (given & 0x00000800u) >> 11;
10994 bfd_vma offset = 0;
10995
10996 offset |= !S << 20;
10997 offset |= J2 << 19;
10998 offset |= J1 << 18;
10999 offset |= (given & 0x003f0000) >> 4;
11000 offset |= (given & 0x000007ff) << 1;
11001 offset -= (1 << 20);
11002
11003 info->print_address_func (pc + 4 + offset, info);
11004 }
11005 break;
11006
11007 case 'B':
11008 {
11009 unsigned int S = (given & 0x04000000u) >> 26;
11010 unsigned int I1 = (given & 0x00002000u) >> 13;
11011 unsigned int I2 = (given & 0x00000800u) >> 11;
11012 bfd_vma offset = 0;
11013
11014 offset |= !S << 24;
11015 offset |= !(I1 ^ S) << 23;
11016 offset |= !(I2 ^ S) << 22;
11017 offset |= (given & 0x03ff0000u) >> 4;
11018 offset |= (given & 0x000007ffu) << 1;
11019 offset -= (1 << 24);
11020 offset += pc + 4;
11021
11022 /* BLX target addresses are always word aligned. */
11023 if ((given & 0x00001000u) == 0)
11024 offset &= ~2u;
11025
11026 info->print_address_func (offset, info);
11027 }
11028 break;
11029
11030 case 's':
11031 {
11032 unsigned int shift = 0;
11033
11034 shift |= (given & 0x000000c0u) >> 6;
11035 shift |= (given & 0x00007000u) >> 10;
11036 if (WRITEBACK_BIT_SET)
11037 func (stream, ", asr #%u", shift);
11038 else if (shift)
11039 func (stream, ", lsl #%u", shift);
11040 /* else print nothing - lsl #0 */
11041 }
11042 break;
11043
11044 case 'R':
11045 {
11046 unsigned int rot = (given & 0x00000030) >> 4;
11047
11048 if (rot)
11049 func (stream, ", ror #%u", rot * 8);
11050 }
11051 break;
11052
11053 case 'U':
11054 if ((given & 0xf0) == 0x60)
11055 {
11056 switch (given & 0xf)
11057 {
11058 case 0xf: func (stream, "sy"); break;
11059 default:
11060 func (stream, "#%d", (int) given & 0xf);
11061 break;
11062 }
11063 }
11064 else
11065 {
11066 const char * opt = data_barrier_option (given & 0xf);
11067 if (opt != NULL)
11068 func (stream, "%s", opt);
11069 else
11070 func (stream, "#%d", (int) given & 0xf);
11071 }
11072 break;
11073
11074 case 'C':
11075 if ((given & 0xff) == 0)
11076 {
11077 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11078 if (given & 0x800)
11079 func (stream, "f");
11080 if (given & 0x400)
11081 func (stream, "s");
11082 if (given & 0x200)
11083 func (stream, "x");
11084 if (given & 0x100)
11085 func (stream, "c");
11086 }
11087 else if ((given & 0x20) == 0x20)
11088 {
11089 char const* name;
11090 unsigned sysm = (given & 0xf00) >> 8;
11091
11092 sysm |= (given & 0x30);
11093 sysm |= (given & 0x00100000) >> 14;
11094 name = banked_regname (sysm);
11095
11096 if (name != NULL)
11097 func (stream, "%s", name);
11098 else
11099 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
11100 }
11101 else
11102 {
11103 func (stream, "%s", psr_name (given & 0xff));
11104 }
11105 break;
11106
11107 case 'D':
11108 if (((given & 0xff) == 0)
11109 || ((given & 0x20) == 0x20))
11110 {
11111 char const* name;
11112 unsigned sm = (given & 0xf0000) >> 16;
11113
11114 sm |= (given & 0x30);
11115 sm |= (given & 0x00100000) >> 14;
11116 name = banked_regname (sm);
11117
11118 if (name != NULL)
11119 func (stream, "%s", name);
11120 else
11121 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
11122 }
11123 else
11124 func (stream, "%s", psr_name (given & 0xff));
11125 break;
11126
11127 case '0': case '1': case '2': case '3': case '4':
11128 case '5': case '6': case '7': case '8': case '9':
11129 {
11130 int width;
11131 unsigned long val;
11132
11133 c = arm_decode_bitfield (c, given, &val, &width);
11134
11135 switch (*c)
11136 {
11137 case 's':
11138 if (val <= 3)
11139 func (stream, "%s", mve_vec_sizename[val]);
11140 else
11141 func (stream, "<undef size>");
11142 break;
11143
11144 case 'd':
11145 func (stream, "%lu", val);
11146 value_in_comment = val;
11147 break;
11148
11149 case 'D':
11150 func (stream, "%lu", val + 1);
11151 value_in_comment = val + 1;
11152 break;
11153
11154 case 'W':
11155 func (stream, "%lu", val * 4);
11156 value_in_comment = val * 4;
11157 break;
11158
11159 case 'S':
11160 if (val == 13)
11161 is_unpredictable = TRUE;
11162 /* Fall through. */
11163 case 'R':
11164 if (val == 15)
11165 is_unpredictable = TRUE;
11166 /* Fall through. */
11167 case 'r':
11168 func (stream, "%s", arm_regnames[val]);
11169 break;
11170
11171 case 'c':
11172 func (stream, "%s", arm_conditional[val]);
11173 break;
11174
11175 case '\'':
11176 c++;
11177 if (val == ((1ul << width) - 1))
11178 func (stream, "%c", *c);
11179 break;
11180
11181 case '`':
11182 c++;
11183 if (val == 0)
11184 func (stream, "%c", *c);
11185 break;
11186
11187 case '?':
11188 func (stream, "%c", c[(1 << width) - (int) val]);
11189 c += 1 << width;
11190 break;
11191
11192 case 'x':
11193 func (stream, "0x%lx", val & 0xffffffffUL);
11194 break;
11195
11196 default:
11197 abort ();
11198 }
11199 }
11200 break;
11201
11202 case 'L':
11203 /* PR binutils/12534
11204 If we have a PC relative offset in an LDRD or STRD
11205 instructions then display the decoded address. */
11206 if (((given >> 16) & 0xf) == 0xf)
11207 {
11208 bfd_vma offset = (given & 0xff) * 4;
11209
11210 if ((given & (1 << 23)) == 0)
11211 offset = - offset;
11212 func (stream, "\t; ");
11213 info->print_address_func ((pc & ~3) + 4 + offset, info);
11214 }
11215 break;
11216
11217 default:
11218 abort ();
11219 }
11220 }
11221
11222 if (value_in_comment > 32 || value_in_comment < -16)
11223 func (stream, "\t; 0x%lx", value_in_comment);
11224
11225 if (is_unpredictable)
11226 func (stream, UNPREDICTABLE_INSTRUCTION);
11227
11228 return;
11229 }
11230
11231 /* No match. */
11232 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11233 return;
11234 }
11235
11236 /* Print data bytes on INFO->STREAM. */
11237
11238 static void
11239 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11240 struct disassemble_info *info,
11241 long given)
11242 {
11243 switch (info->bytes_per_chunk)
11244 {
11245 case 1:
11246 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11247 break;
11248 case 2:
11249 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11250 break;
11251 case 4:
11252 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11253 break;
11254 default:
11255 abort ();
11256 }
11257 }
11258
11259 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11260 being displayed in symbol relative addresses.
11261
11262 Also disallow private symbol, with __tagsym$$ prefix,
11263 from ARM RVCT toolchain being displayed. */
11264
11265 bfd_boolean
11266 arm_symbol_is_valid (asymbol * sym,
11267 struct disassemble_info * info ATTRIBUTE_UNUSED)
11268 {
11269 const char * name;
11270
11271 if (sym == NULL)
11272 return FALSE;
11273
11274 name = bfd_asymbol_name (sym);
11275
11276 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
11277 }
11278
11279 /* Parse the string of disassembler options. */
11280
11281 static void
11282 parse_arm_disassembler_options (const char *options)
11283 {
11284 const char *opt;
11285
11286 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
11287 {
11288 if (CONST_STRNEQ (opt, "reg-names-"))
11289 {
11290 unsigned int i;
11291 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11292 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11293 {
11294 regname_selected = i;
11295 break;
11296 }
11297
11298 if (i >= NUM_ARM_OPTIONS)
11299 /* xgettext: c-format */
11300 opcodes_error_handler (_("unrecognised register name set: %s"),
11301 opt);
11302 }
11303 else if (CONST_STRNEQ (opt, "force-thumb"))
11304 force_thumb = 1;
11305 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11306 force_thumb = 0;
11307 else
11308 /* xgettext: c-format */
11309 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
11310 }
11311
11312 return;
11313 }
11314
11315 static bfd_boolean
11316 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11317 enum map_type *map_symbol);
11318
11319 /* Search back through the insn stream to determine if this instruction is
11320 conditionally executed. */
11321
11322 static void
11323 find_ifthen_state (bfd_vma pc,
11324 struct disassemble_info *info,
11325 bfd_boolean little)
11326 {
11327 unsigned char b[2];
11328 unsigned int insn;
11329 int status;
11330 /* COUNT is twice the number of instructions seen. It will be odd if we
11331 just crossed an instruction boundary. */
11332 int count;
11333 int it_count;
11334 unsigned int seen_it;
11335 bfd_vma addr;
11336
11337 ifthen_address = pc;
11338 ifthen_state = 0;
11339
11340 addr = pc;
11341 count = 1;
11342 it_count = 0;
11343 seen_it = 0;
11344 /* Scan backwards looking for IT instructions, keeping track of where
11345 instruction boundaries are. We don't know if something is actually an
11346 IT instruction until we find a definite instruction boundary. */
11347 for (;;)
11348 {
11349 if (addr == 0 || info->symbol_at_address_func (addr, info))
11350 {
11351 /* A symbol must be on an instruction boundary, and will not
11352 be within an IT block. */
11353 if (seen_it && (count & 1))
11354 break;
11355
11356 return;
11357 }
11358 addr -= 2;
11359 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
11360 if (status)
11361 return;
11362
11363 if (little)
11364 insn = (b[0]) | (b[1] << 8);
11365 else
11366 insn = (b[1]) | (b[0] << 8);
11367 if (seen_it)
11368 {
11369 if ((insn & 0xf800) < 0xe800)
11370 {
11371 /* Addr + 2 is an instruction boundary. See if this matches
11372 the expected boundary based on the position of the last
11373 IT candidate. */
11374 if (count & 1)
11375 break;
11376 seen_it = 0;
11377 }
11378 }
11379 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11380 {
11381 enum map_type type = MAP_ARM;
11382 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11383
11384 if (!found || (found && type == MAP_THUMB))
11385 {
11386 /* This could be an IT instruction. */
11387 seen_it = insn;
11388 it_count = count >> 1;
11389 }
11390 }
11391 if ((insn & 0xf800) >= 0xe800)
11392 count++;
11393 else
11394 count = (count + 2) | 1;
11395 /* IT blocks contain at most 4 instructions. */
11396 if (count >= 8 && !seen_it)
11397 return;
11398 }
11399 /* We found an IT instruction. */
11400 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11401 if ((ifthen_state & 0xf) == 0)
11402 ifthen_state = 0;
11403 }
11404
11405 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11406 mapping symbol. */
11407
11408 static int
11409 is_mapping_symbol (struct disassemble_info *info, int n,
11410 enum map_type *map_type)
11411 {
11412 const char *name;
11413
11414 name = bfd_asymbol_name (info->symtab[n]);
11415 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11416 && (name[2] == 0 || name[2] == '.'))
11417 {
11418 *map_type = ((name[1] == 'a') ? MAP_ARM
11419 : (name[1] == 't') ? MAP_THUMB
11420 : MAP_DATA);
11421 return TRUE;
11422 }
11423
11424 return FALSE;
11425 }
11426
11427 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11428 Returns nonzero if *MAP_TYPE was set. */
11429
11430 static int
11431 get_map_sym_type (struct disassemble_info *info,
11432 int n,
11433 enum map_type *map_type)
11434 {
11435 /* If the symbol is in a different section, ignore it. */
11436 if (info->section != NULL && info->section != info->symtab[n]->section)
11437 return FALSE;
11438
11439 return is_mapping_symbol (info, n, map_type);
11440 }
11441
11442 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11443 Returns nonzero if *MAP_TYPE was set. */
11444
11445 static int
11446 get_sym_code_type (struct disassemble_info *info,
11447 int n,
11448 enum map_type *map_type)
11449 {
11450 elf_symbol_type *es;
11451 unsigned int type;
11452
11453 /* If the symbol is in a different section, ignore it. */
11454 if (info->section != NULL && info->section != info->symtab[n]->section)
11455 return FALSE;
11456
11457 es = *(elf_symbol_type **)(info->symtab + n);
11458 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11459
11460 /* If the symbol has function type then use that. */
11461 if (type == STT_FUNC || type == STT_GNU_IFUNC)
11462 {
11463 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11464 == ST_BRANCH_TO_THUMB)
11465 *map_type = MAP_THUMB;
11466 else
11467 *map_type = MAP_ARM;
11468 return TRUE;
11469 }
11470
11471 return FALSE;
11472 }
11473
11474 /* Search the mapping symbol state for instruction at pc. This is only
11475 applicable for elf target.
11476
11477 There is an assumption Here, info->private_data contains the correct AND
11478 up-to-date information about current scan process. The information will be
11479 used to speed this search process.
11480
11481 Return TRUE if the mapping state can be determined, and map_symbol
11482 will be updated accordingly. Otherwise, return FALSE. */
11483
11484 static bfd_boolean
11485 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11486 enum map_type *map_symbol)
11487 {
11488 bfd_vma addr, section_vma = 0;
11489 int n, last_sym = -1;
11490 bfd_boolean found = FALSE;
11491 bfd_boolean can_use_search_opt_p = FALSE;
11492
11493 /* Default to DATA. A text section is required by the ABI to contain an
11494 INSN mapping symbol at the start. A data section has no such
11495 requirement, hence if no mapping symbol is found the section must
11496 contain only data. This however isn't very useful if the user has
11497 fully stripped the binaries. If this is the case use the section
11498 attributes to determine the default. If we have no section default to
11499 INSN as well, as we may be disassembling some raw bytes on a baremetal
11500 HEX file or similar. */
11501 enum map_type type = MAP_DATA;
11502 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11503 type = MAP_ARM;
11504 struct arm_private_data *private_data;
11505
11506 if (info->private_data == NULL
11507 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11508 return FALSE;
11509
11510 private_data = info->private_data;
11511
11512 /* First, look for mapping symbols. */
11513 if (info->symtab_size != 0)
11514 {
11515 if (pc <= private_data->last_mapping_addr)
11516 private_data->last_mapping_sym = -1;
11517
11518 /* Start scanning at the start of the function, or wherever
11519 we finished last time. */
11520 n = info->symtab_pos + 1;
11521
11522 /* If the last stop offset is different from the current one it means we
11523 are disassembling a different glob of bytes. As such the optimization
11524 would not be safe and we should start over. */
11525 can_use_search_opt_p
11526 = private_data->last_mapping_sym >= 0
11527 && info->stop_offset == private_data->last_stop_offset;
11528
11529 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11530 n = private_data->last_mapping_sym;
11531
11532 /* Look down while we haven't passed the location being disassembled.
11533 The reason for this is that there's no defined order between a symbol
11534 and an mapping symbol that may be at the same address. We may have to
11535 look at least one position ahead. */
11536 for (; n < info->symtab_size; n++)
11537 {
11538 addr = bfd_asymbol_value (info->symtab[n]);
11539 if (addr > pc)
11540 break;
11541 if (get_map_sym_type (info, n, &type))
11542 {
11543 last_sym = n;
11544 found = TRUE;
11545 }
11546 }
11547
11548 if (!found)
11549 {
11550 n = info->symtab_pos;
11551 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11552 n = private_data->last_mapping_sym;
11553
11554 /* No mapping symbol found at this address. Look backwards
11555 for a preceeding one, but don't go pass the section start
11556 otherwise a data section with no mapping symbol can pick up
11557 a text mapping symbol of a preceeding section. The documentation
11558 says section can be NULL, in which case we will seek up all the
11559 way to the top. */
11560 if (info->section)
11561 section_vma = info->section->vma;
11562
11563 for (; n >= 0; n--)
11564 {
11565 addr = bfd_asymbol_value (info->symtab[n]);
11566 if (addr < section_vma)
11567 break;
11568
11569 if (get_map_sym_type (info, n, &type))
11570 {
11571 last_sym = n;
11572 found = TRUE;
11573 break;
11574 }
11575 }
11576 }
11577 }
11578
11579 /* If no mapping symbol was found, try looking up without a mapping
11580 symbol. This is done by walking up from the current PC to the nearest
11581 symbol. We don't actually have to loop here since symtab_pos will
11582 contain the nearest symbol already. */
11583 if (!found)
11584 {
11585 n = info->symtab_pos;
11586 if (n >= 0 && get_sym_code_type (info, n, &type))
11587 {
11588 last_sym = n;
11589 found = TRUE;
11590 }
11591 }
11592
11593 private_data->last_mapping_sym = last_sym;
11594 private_data->last_type = type;
11595 private_data->last_stop_offset = info->stop_offset;
11596
11597 *map_symbol = type;
11598 return found;
11599 }
11600
11601 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11602 of the supplied arm_feature_set structure with bitmasks indicating
11603 the supported base architectures and coprocessor extensions.
11604
11605 FIXME: This could more efficiently implemented as a constant array,
11606 although it would also be less robust. */
11607
11608 static void
11609 select_arm_features (unsigned long mach,
11610 arm_feature_set * features)
11611 {
11612 arm_feature_set arch_fset;
11613 const arm_feature_set fpu_any = FPU_ANY;
11614
11615 #undef ARM_SET_FEATURES
11616 #define ARM_SET_FEATURES(FSET) \
11617 { \
11618 const arm_feature_set fset = FSET; \
11619 arch_fset = fset; \
11620 }
11621
11622 /* When several architecture versions share the same bfd_mach_arm_XXX value
11623 the most featureful is chosen. */
11624 switch (mach)
11625 {
11626 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11627 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11628 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11629 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11630 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11631 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11632 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11633 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11634 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11635 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
11636 case bfd_mach_arm_ep9312:
11637 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11638 ARM_CEXT_MAVERICK | FPU_MAVERICK));
11639 break;
11640 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11641 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11642 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11643 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11644 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11645 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11646 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11647 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11648 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11649 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11650 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11651 case bfd_mach_arm_8:
11652 {
11653 /* Add bits for extensions that Armv8.6-A recognizes. */
11654 arm_feature_set armv8_6_ext_fset
11655 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11656 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
11657 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
11658 break;
11659 }
11660 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11661 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11662 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
11663 case bfd_mach_arm_8_1M_MAIN:
11664 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11665 force_thumb = 1;
11666 break;
11667 /* If the machine type is unknown allow all architecture types and all
11668 extensions. */
11669 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
11670 default:
11671 abort ();
11672 }
11673 #undef ARM_SET_FEATURES
11674
11675 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11676 and thus on bfd_mach_arm_XXX value. Therefore for a given
11677 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11678 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
11679 }
11680
11681
11682 /* NOTE: There are no checks in these routines that
11683 the relevant number of data bytes exist. */
11684
11685 static int
11686 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
11687 {
11688 unsigned char b[4];
11689 long given;
11690 int status;
11691 int is_thumb = FALSE;
11692 int is_data = FALSE;
11693 int little_code;
11694 unsigned int size = 4;
11695 void (*printer) (bfd_vma, struct disassemble_info *, long);
11696 bfd_boolean found = FALSE;
11697 struct arm_private_data *private_data;
11698
11699 if (info->disassembler_options)
11700 {
11701 parse_arm_disassembler_options (info->disassembler_options);
11702
11703 /* To avoid repeated parsing of these options, we remove them here. */
11704 info->disassembler_options = NULL;
11705 }
11706
11707 /* PR 10288: Control which instructions will be disassembled. */
11708 if (info->private_data == NULL)
11709 {
11710 static struct arm_private_data private;
11711
11712 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11713 /* If the user did not use the -m command line switch then default to
11714 disassembling all types of ARM instruction.
11715
11716 The info->mach value has to be ignored as this will be based on
11717 the default archictecture for the target and/or hints in the notes
11718 section, but it will never be greater than the current largest arm
11719 machine value (iWMMXt2), which is only equivalent to the V5TE
11720 architecture. ARM architectures have advanced beyond the machine
11721 value encoding, and these newer architectures would be ignored if
11722 the machine value was used.
11723
11724 Ie the -m switch is used to restrict which instructions will be
11725 disassembled. If it is necessary to use the -m switch to tell
11726 objdump that an ARM binary is being disassembled, eg because the
11727 input is a raw binary file, but it is also desired to disassemble
11728 all ARM instructions then use "-marm". This will select the
11729 "unknown" arm architecture which is compatible with any ARM
11730 instruction. */
11731 info->mach = bfd_mach_arm_unknown;
11732
11733 /* Compute the architecture bitmask from the machine number.
11734 Note: This assumes that the machine number will not change
11735 during disassembly.... */
11736 select_arm_features (info->mach, & private.features);
11737
11738 private.last_mapping_sym = -1;
11739 private.last_mapping_addr = 0;
11740 private.last_stop_offset = 0;
11741
11742 info->private_data = & private;
11743 }
11744
11745 private_data = info->private_data;
11746
11747 /* Decide if our code is going to be little-endian, despite what the
11748 function argument might say. */
11749 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11750
11751 /* For ELF, consult the symbol table to determine what kind of code
11752 or data we have. */
11753 if (info->symtab_size != 0
11754 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11755 {
11756 bfd_vma addr;
11757 int n;
11758 int last_sym = -1;
11759 enum map_type type = MAP_ARM;
11760
11761 found = mapping_symbol_for_insn (pc, info, &type);
11762 last_sym = private_data->last_mapping_sym;
11763
11764 is_thumb = (private_data->last_type == MAP_THUMB);
11765 is_data = (private_data->last_type == MAP_DATA);
11766
11767 /* Look a little bit ahead to see if we should print out
11768 two or four bytes of data. If there's a symbol,
11769 mapping or otherwise, after two bytes then don't
11770 print more. */
11771 if (is_data)
11772 {
11773 size = 4 - (pc & 3);
11774 for (n = last_sym + 1; n < info->symtab_size; n++)
11775 {
11776 addr = bfd_asymbol_value (info->symtab[n]);
11777 if (addr > pc
11778 && (info->section == NULL
11779 || info->section == info->symtab[n]->section))
11780 {
11781 if (addr - pc < size)
11782 size = addr - pc;
11783 break;
11784 }
11785 }
11786 /* If the next symbol is after three bytes, we need to
11787 print only part of the data, so that we can use either
11788 .byte or .short. */
11789 if (size == 3)
11790 size = (pc & 1) ? 1 : 2;
11791 }
11792 }
11793
11794 if (info->symbols != NULL)
11795 {
11796 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11797 {
11798 coff_symbol_type * cs;
11799
11800 cs = coffsymbol (*info->symbols);
11801 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11802 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11803 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11804 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11805 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11806 }
11807 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11808 && !found)
11809 {
11810 /* If no mapping symbol has been found then fall back to the type
11811 of the function symbol. */
11812 elf_symbol_type * es;
11813 unsigned int type;
11814
11815 es = *(elf_symbol_type **)(info->symbols);
11816 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11817
11818 is_thumb =
11819 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11820 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
11821 }
11822 else if (bfd_asymbol_flavour (*info->symbols)
11823 == bfd_target_mach_o_flavour)
11824 {
11825 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11826
11827 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11828 }
11829 }
11830
11831 if (force_thumb)
11832 is_thumb = TRUE;
11833
11834 if (is_data)
11835 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11836 else
11837 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11838
11839 info->bytes_per_line = 4;
11840
11841 /* PR 10263: Disassemble data if requested to do so by the user. */
11842 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
11843 {
11844 int i;
11845
11846 /* Size was already set above. */
11847 info->bytes_per_chunk = size;
11848 printer = print_insn_data;
11849
11850 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
11851 given = 0;
11852 if (little)
11853 for (i = size - 1; i >= 0; i--)
11854 given = b[i] | (given << 8);
11855 else
11856 for (i = 0; i < (int) size; i++)
11857 given = b[i] | (given << 8);
11858 }
11859 else if (!is_thumb)
11860 {
11861 /* In ARM mode endianness is a straightforward issue: the instruction
11862 is four bytes long and is either ordered 0123 or 3210. */
11863 printer = print_insn_arm;
11864 info->bytes_per_chunk = 4;
11865 size = 4;
11866
11867 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
11868 if (little_code)
11869 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11870 else
11871 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
11872 }
11873 else
11874 {
11875 /* In Thumb mode we have the additional wrinkle of two
11876 instruction lengths. Fortunately, the bits that determine
11877 the length of the current instruction are always to be found
11878 in the first two bytes. */
11879 printer = print_insn_thumb16;
11880 info->bytes_per_chunk = 2;
11881 size = 2;
11882
11883 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
11884 if (little_code)
11885 given = (b[0]) | (b[1] << 8);
11886 else
11887 given = (b[1]) | (b[0] << 8);
11888
11889 if (!status)
11890 {
11891 /* These bit patterns signal a four-byte Thumb
11892 instruction. */
11893 if ((given & 0xF800) == 0xF800
11894 || (given & 0xF800) == 0xF000
11895 || (given & 0xF800) == 0xE800)
11896 {
11897 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
11898 if (little_code)
11899 given = (b[0]) | (b[1] << 8) | (given << 16);
11900 else
11901 given = (b[1]) | (b[0] << 8) | (given << 16);
11902
11903 printer = print_insn_thumb32;
11904 size = 4;
11905 }
11906 }
11907
11908 if (ifthen_address != pc)
11909 find_ifthen_state (pc, info, little_code);
11910
11911 if (ifthen_state)
11912 {
11913 if ((ifthen_state & 0xf) == 0x8)
11914 ifthen_next_state = 0;
11915 else
11916 ifthen_next_state = (ifthen_state & 0xe0)
11917 | ((ifthen_state & 0xf) << 1);
11918 }
11919 }
11920
11921 if (status)
11922 {
11923 info->memory_error_func (status, pc, info);
11924 return -1;
11925 }
11926 if (info->flags & INSN_HAS_RELOC)
11927 /* If the instruction has a reloc associated with it, then
11928 the offset field in the instruction will actually be the
11929 addend for the reloc. (We are using REL type relocs).
11930 In such cases, we can ignore the pc when computing
11931 addresses, since the addend is not currently pc-relative. */
11932 pc = 0;
11933
11934 printer (pc, info, given);
11935
11936 if (is_thumb)
11937 {
11938 ifthen_state = ifthen_next_state;
11939 ifthen_address += size;
11940 }
11941 return size;
11942 }
11943
11944 int
11945 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
11946 {
11947 /* Detect BE8-ness and record it in the disassembler info. */
11948 if (info->flavour == bfd_target_elf_flavour
11949 && info->section != NULL
11950 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11951 info->endian_code = BFD_ENDIAN_LITTLE;
11952
11953 return print_insn (pc, info, FALSE);
11954 }
11955
11956 int
11957 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
11958 {
11959 return print_insn (pc, info, TRUE);
11960 }
11961
11962 const disasm_options_and_args_t *
11963 disassembler_options_arm (void)
11964 {
11965 static disasm_options_and_args_t *opts_and_args;
11966
11967 if (opts_and_args == NULL)
11968 {
11969 disasm_options_t *opts;
11970 unsigned int i;
11971
11972 opts_and_args = XNEW (disasm_options_and_args_t);
11973 opts_and_args->args = NULL;
11974
11975 opts = &opts_and_args->options;
11976 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11977 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11978 opts->arg = NULL;
11979 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11980 {
11981 opts->name[i] = regnames[i].name;
11982 if (regnames[i].description != NULL)
11983 opts->description[i] = _(regnames[i].description);
11984 else
11985 opts->description[i] = NULL;
11986 }
11987 /* The array we return must be NULL terminated. */
11988 opts->name[i] = NULL;
11989 opts->description[i] = NULL;
11990 }
11991
11992 return opts_and_args;
11993 }
11994
11995 void
11996 print_arm_disassembler_options (FILE *stream)
11997 {
11998 unsigned int i, max_len = 0;
11999 fprintf (stream, _("\n\
12000 The following ARM specific disassembler options are supported for use with\n\
12001 the -M switch:\n"));
12002
12003 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12004 {
12005 unsigned int len = strlen (regnames[i].name);
12006 if (max_len < len)
12007 max_len = len;
12008 }
12009
12010 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12011 fprintf (stream, " %s%*c %s\n",
12012 regnames[i].name,
12013 (int)(max_len - strlen (regnames[i].name)), ' ',
12014 _(regnames[i].description));
12015 }
GDB Binutils - Deliverables
This page took 0.304517 seconds and 5 git commands to generate.