1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
130 enum mve_unpredictable
132 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
134 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
136 UNPRED_R13
, /* Unpredictable because r13 (sp) or
138 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
139 UNPRED_Q_GT_4
, /* Unpredictable because
140 vec reg start > 4 (vld4/st4). */
141 UNPRED_Q_GT_6
, /* Unpredictable because
142 vec reg start > 6 (vld2/st2). */
143 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
145 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
147 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
148 UNPRED_NONE
/* No unpredictable behavior. */
153 UNDEF_SIZE_3
, /* undefined because size == 3. */
154 UNDEF_SIZE_3
, /* undefined because size == 3. */
155 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
156 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
157 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
158 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
160 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
162 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
163 UNDEF_NONE
/* no undefined behavior. */
168 arm_feature_set arch
; /* Architecture defining this insn. */
169 unsigned long value
; /* If arch is 0 then value is a sentinel. */
170 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
171 const char * assembler
; /* How to disassemble this insn. */
178 arm_feature_set arch
; /* Architecture defining this insn. */
179 enum mve_instructions mve_op
; /* Specific mve instruction for faster
181 unsigned long value
; /* If arch is 0 then value is a sentinel. */
182 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
183 const char * assembler
; /* How to disassemble this insn. */
193 /* Shared (between Arm and Thumb mode) opcode. */
196 enum isa isa
; /* Execution mode instruction availability. */
197 arm_feature_set arch
; /* Architecture defining this insn. */
198 unsigned long value
; /* If arch is 0 then value is a sentinel. */
199 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
200 const char * assembler
; /* How to disassemble this insn. */
205 arm_feature_set arch
; /* Architecture defining this insn. */
206 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
207 const char *assembler
; /* How to disassemble this insn. */
210 /* print_insn_coprocessor recognizes the following format control codes:
214 %c print condition code (always bits 28-31 in ARM mode)
215 %q print shifter argument
216 %u print condition code (unconditional in ARM mode,
217 UNPREDICTABLE if not AL in Thumb)
218 %A print address for ldc/stc/ldf/stf instruction
219 %B print vstm/vldm register list
220 %C print vscclrm register list
221 %I print cirrus signed shift immediate: bits 0..3|4..6
222 %J print register for VLDR instruction
223 %K print address for VLDR instruction
224 %F print the COUNT field of a LFM/SFM instruction.
225 %P print floating point precision in arithmetic insn
226 %Q print floating point precision in ldf/stf insn
227 %R print floating point rounding mode
229 %<bitfield>c print as a condition code (for vsel)
230 %<bitfield>r print as an ARM register
231 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
232 %<bitfield>ru as %<>r but each u register must be unique.
233 %<bitfield>d print the bitfield in decimal
234 %<bitfield>k print immediate for VFPv3 conversion instruction
235 %<bitfield>x print the bitfield in hex
236 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
237 %<bitfield>f print a floating point constant if >7 else a
238 floating point register
239 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
240 %<bitfield>g print as an iWMMXt 64-bit register
241 %<bitfield>G print as an iWMMXt general purpose or control register
242 %<bitfield>D print as a NEON D register
243 %<bitfield>Q print as a NEON Q register
244 %<bitfield>V print as a NEON D or Q register
245 %<bitfield>E print a quarter-float immediate value
247 %y<code> print a single precision VFP reg.
248 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
249 %z<code> print a double precision VFP reg
250 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
252 %<bitfield>'c print specified char iff bitfield is all ones
253 %<bitfield>`c print specified char iff bitfield is all zeroes
254 %<bitfield>?ab... select from array of values in big endian order
256 %L print as an iWMMXt N/M width field.
257 %Z print the Immediate of a WSHUFH instruction.
258 %l like 'A' except use byte offsets for 'B' & 'H'
260 %i print 5-bit immediate in bits 8,3..0
262 %r print register offset address for wldt/wstr instruction. */
264 enum opcode_sentinel_enum
266 SENTINEL_IWMMXT_START
= 1,
268 SENTINEL_GENERIC_START
271 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
272 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
273 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
274 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
276 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
278 static const struct sopcode32 coprocessor_opcodes
[] =
280 /* XScale instructions. */
281 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
282 0x0e200010, 0x0fff0ff0,
283 "mia%c\tacc0, %0-3r, %12-15r"},
284 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
285 0x0e280010, 0x0fff0ff0,
286 "miaph%c\tacc0, %0-3r, %12-15r"},
287 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
288 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
289 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
290 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
291 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
292 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
294 /* Intel Wireless MMX technology instructions. */
295 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
296 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
297 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
298 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
299 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
300 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
301 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
302 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
303 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
304 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
305 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
306 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
307 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
308 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
309 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
310 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
311 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
312 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
313 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
314 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
315 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
316 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
317 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
318 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
319 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
320 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
321 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
322 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
323 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
324 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
325 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
326 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
327 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
328 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
329 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
330 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
331 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
332 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
333 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
334 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
335 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
336 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
337 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
338 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
339 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
340 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
341 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
342 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
343 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
344 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
345 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
346 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
347 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
348 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
349 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
350 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
351 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
352 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
353 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
354 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
355 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
356 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
357 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
358 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
359 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
360 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
361 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
362 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
363 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
364 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
365 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
366 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
367 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
368 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
369 0x0e800120, 0x0f800ff0,
370 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
371 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
372 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
373 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
374 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
375 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
376 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
377 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
378 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
379 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
380 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
381 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
382 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
383 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
384 0x0e8000a0, 0x0f800ff0,
385 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
386 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
387 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
388 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
389 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
390 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
391 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
392 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
393 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
394 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
395 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
396 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
397 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
398 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
399 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
400 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
401 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
402 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
403 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
404 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
405 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
406 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
407 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
408 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
409 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
410 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
411 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
412 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
413 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
414 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
415 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
416 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
417 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
418 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
419 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
420 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
421 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
422 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
423 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
424 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
425 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
426 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
427 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
428 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
429 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
430 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
431 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
432 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
433 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
434 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
435 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
436 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
437 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
438 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
439 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
440 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
441 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
442 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
443 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
444 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
445 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
446 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
447 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
448 {ANY
, ARM_FEATURE_CORE_LOW (0),
449 SENTINEL_IWMMXT_END
, 0, "" },
451 /* Floating point coprocessor (FPA) instructions. */
452 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
453 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
454 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
455 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
456 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
457 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
458 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
459 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
460 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
461 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
462 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
463 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
464 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
465 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
466 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
467 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
468 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
469 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
470 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
471 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
472 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
473 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
474 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
475 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
476 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
477 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
478 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
479 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
480 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
481 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
482 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
483 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
484 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
485 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
486 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
487 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
488 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
489 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
490 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
491 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
492 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
493 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
494 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
495 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
496 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
497 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
498 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
499 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
500 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
501 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
502 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
503 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
504 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
505 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
506 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
507 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
508 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
509 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
510 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
511 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
512 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
513 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
514 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
515 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
516 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
517 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
518 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
519 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
520 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
521 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
522 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
523 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
524 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
525 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
526 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
527 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
528 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
529 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
530 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
531 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
532 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
533 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
534 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
535 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
536 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
537 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
539 /* Armv8.1-M Mainline instructions. */
540 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
541 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
542 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
543 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
545 /* ARMv8-M Mainline Security Extensions instructions. */
546 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
547 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
548 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
549 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
551 /* Register load/store. */
552 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
553 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
554 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
555 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
556 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
557 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
558 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
559 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
560 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
561 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
562 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
563 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
564 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
565 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
566 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
567 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
568 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
569 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
570 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
571 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
572 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
573 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
574 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
575 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
576 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
577 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
578 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
579 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
580 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
581 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
582 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
583 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
584 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
585 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
586 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
587 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
589 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
590 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
591 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
592 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
593 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
594 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
595 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
596 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
598 /* Data transfer between ARM and NEON registers. */
599 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
600 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
601 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
602 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
603 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
604 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
605 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
606 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
607 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
608 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
609 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
610 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
611 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
612 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
613 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
614 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
615 /* Half-precision conversion instructions. */
616 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
617 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
618 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
619 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
620 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
621 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
622 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
623 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
625 /* Floating point coprocessor (VFP) instructions. */
626 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
627 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
628 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
629 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
630 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
631 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
632 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
633 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
634 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
635 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
636 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
637 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
638 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
639 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
640 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
641 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
642 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
643 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
644 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
645 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
646 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
647 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
648 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
649 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
650 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
651 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
652 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
653 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
654 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
655 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
656 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
657 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
658 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
659 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
660 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
661 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
662 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
663 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
664 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
665 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
666 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
667 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
668 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
669 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
670 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
671 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
672 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
673 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
674 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
675 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
676 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
677 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
678 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
679 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
680 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
681 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
682 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
683 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
684 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
685 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
686 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
687 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
688 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
689 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
690 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
691 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
692 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
693 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
694 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
695 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
696 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
697 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
698 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
699 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
700 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
701 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
702 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
703 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
704 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
705 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
706 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
707 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
708 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
709 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
710 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
711 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
712 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
713 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
714 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
715 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
716 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
717 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
718 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
719 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
720 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
721 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
722 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
723 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
724 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
725 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
726 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
727 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
728 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
729 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
730 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
731 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
732 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
733 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
734 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
735 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
736 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
737 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
738 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
739 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
740 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
741 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
742 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
743 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
744 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
745 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
746 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
747 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
748 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
749 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
750 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
751 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
752 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
753 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
754 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
755 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
756 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
757 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
758 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
759 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
760 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
761 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
762 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
763 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
765 /* Cirrus coprocessor instructions. */
766 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
767 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
768 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
769 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
770 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
771 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
772 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
773 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
774 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
775 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
776 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
777 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
778 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
779 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
780 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
781 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
782 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
783 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
784 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
785 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
786 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
787 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
788 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
789 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
790 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
791 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
792 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
793 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
794 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
795 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
796 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
797 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
798 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
799 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
800 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
801 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
802 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
803 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
804 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
805 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
806 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
807 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
808 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
809 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
810 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
811 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
812 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
813 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
814 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
815 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
816 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
817 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
818 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
819 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
820 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
821 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
822 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
823 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
824 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
825 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
826 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
827 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
828 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
829 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
830 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
831 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
832 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
833 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
834 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
835 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
836 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
837 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
838 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
839 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
840 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
841 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
842 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
843 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
844 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
845 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
846 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
847 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
848 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
849 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
850 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
851 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
852 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
853 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
854 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
855 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
856 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
857 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
858 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
859 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
860 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
861 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
862 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
863 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
864 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
865 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
866 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
867 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
868 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
869 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
870 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
871 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
872 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
873 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
874 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
875 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
876 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
877 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
878 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
879 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
880 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
881 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
882 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
883 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
884 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
885 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
886 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
887 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
888 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
889 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
890 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
891 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
892 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
893 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
894 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
895 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
896 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
897 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
898 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
899 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
900 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
901 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
902 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
903 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
904 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
905 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
906 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
907 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
908 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
909 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
910 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
911 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
912 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
913 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
914 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
915 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
916 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
917 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
918 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
919 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
920 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
921 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
922 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
923 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
924 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
925 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
926 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
927 0x0e000600, 0x0ff00f10,
928 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
929 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
930 0x0e100600, 0x0ff00f10,
931 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
932 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
933 0x0e200600, 0x0ff00f10,
934 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
935 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
936 0x0e300600, 0x0ff00f10,
937 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
939 /* VFP Fused multiply add instructions. */
940 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
941 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
942 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
943 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
944 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
945 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
946 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
947 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
948 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
949 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
950 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
951 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
952 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
953 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
954 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
955 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
958 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
959 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
960 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
961 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
962 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
963 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
964 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
965 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
966 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
967 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
968 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
969 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
970 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
971 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
972 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
973 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
974 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
975 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
976 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
977 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
978 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
979 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
980 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
981 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
983 /* Generic coprocessor instructions. */
984 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
985 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
986 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
987 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
988 0x0c500000, 0x0ff00000,
989 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
990 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
991 0x0e000000, 0x0f000010,
992 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
993 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
994 0x0e10f010, 0x0f10f010,
995 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
996 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
997 0x0e100010, 0x0f100010,
998 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
999 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1000 0x0e000010, 0x0f100010,
1001 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1002 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1003 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1004 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1005 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1007 /* V6 coprocessor instructions. */
1008 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1009 0xfc500000, 0xfff00000,
1010 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1011 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1012 0xfc400000, 0xfff00000,
1013 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1015 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1016 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1017 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1018 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1019 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1020 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1021 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1022 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1023 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1024 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1025 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1026 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1027 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1028 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1029 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1030 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1031 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1032 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1033 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1034 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1035 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1037 /* Dot Product instructions in the space of coprocessor 13. */
1038 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1039 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1040 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1041 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1043 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1044 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1045 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1046 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1047 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1048 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1049 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1050 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1051 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1052 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1053 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1054 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1055 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1056 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1057 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1058 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1059 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1061 /* V5 coprocessor instructions. */
1062 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1063 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1064 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1065 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1066 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1067 0xfe000000, 0xff000010,
1068 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1069 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1070 0xfe000010, 0xff100010,
1071 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1072 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1073 0xfe100010, 0xff100010,
1074 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1076 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1077 cp_num: bit <11:8> == 0b1001.
1078 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1079 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1080 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1081 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1082 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1083 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1084 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1085 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1086 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1087 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1088 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1089 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1090 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1091 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1092 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1093 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1094 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1095 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1096 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1097 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1098 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1099 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1100 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1101 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1102 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1103 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1104 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1105 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1106 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1107 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1108 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1109 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1110 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1111 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1112 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1113 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1114 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1115 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1116 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1117 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1118 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1119 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1120 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1121 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1122 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1123 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1124 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1125 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1126 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1127 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1128 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1129 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1130 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1131 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1132 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1133 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1134 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1135 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1136 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1137 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1138 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1139 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1140 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1141 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1142 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1143 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1144 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1145 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1146 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1147 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1148 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1150 /* ARMv8.3 javascript conversion instruction. */
1151 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1152 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1154 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1157 /* Neon opcode table: This does not encode the top byte -- that is
1158 checked by the print_insn_neon routine, as it depends on whether we are
1159 doing thumb32 or arm32 disassembly. */
1161 /* print_insn_neon recognizes the following format control codes:
1165 %c print condition code
1166 %u print condition code (unconditional in ARM mode,
1167 UNPREDICTABLE if not AL in Thumb)
1168 %A print v{st,ld}[1234] operands
1169 %B print v{st,ld}[1234] any one operands
1170 %C print v{st,ld}[1234] single->all operands
1172 %E print vmov, vmvn, vorr, vbic encoded constant
1173 %F print vtbl,vtbx register list
1175 %<bitfield>r print as an ARM register
1176 %<bitfield>d print the bitfield in decimal
1177 %<bitfield>e print the 2^N - bitfield in decimal
1178 %<bitfield>D print as a NEON D register
1179 %<bitfield>Q print as a NEON Q register
1180 %<bitfield>R print as a NEON D or Q register
1181 %<bitfield>Sn print byte scaled width limited by n
1182 %<bitfield>Tn print short scaled width limited by n
1183 %<bitfield>Un print long scaled width limited by n
1185 %<bitfield>'c print specified char iff bitfield is all ones
1186 %<bitfield>`c print specified char iff bitfield is all zeroes
1187 %<bitfield>?ab... select from array of values in big endian order. */
1189 static const struct opcode32 neon_opcodes
[] =
1192 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1193 0xf2b00840, 0xffb00850,
1194 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1196 0xf2b00000, 0xffb00810,
1197 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1199 /* Data transfer between ARM and NEON registers. */
1200 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1201 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1203 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1204 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1205 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1206 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1207 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1208 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1209 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1210 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1211 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1213 /* Move data element to all lanes. */
1214 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1215 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1216 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1217 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1218 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1219 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1223 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1224 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1225 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1227 /* Half-precision conversions. */
1228 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1229 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1230 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1231 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1233 /* NEON fused multiply add instructions. */
1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1235 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1237 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1239 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1241 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243 /* Two registers, miscellaneous. */
1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1245 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1247 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1249 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1250 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1251 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1252 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1253 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1254 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1255 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1256 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1257 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1258 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1259 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1260 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1261 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1262 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1263 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1264 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1265 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1267 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1269 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1271 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1272 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1273 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1275 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1276 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1277 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1279 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1281 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1283 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1284 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1285 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1287 0xf3b20300, 0xffb30fd0,
1288 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1290 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1292 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1294 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1296 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1298 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1300 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1302 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1304 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1306 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1308 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1310 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1312 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1314 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1316 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1318 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1320 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1321 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1322 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1324 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1326 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1328 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1330 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1332 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1333 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1334 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1336 0xf3bb0600, 0xffbf0e10,
1337 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1339 0xf3b70600, 0xffbf0e10,
1340 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1342 /* Three registers of the same length. */
1343 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1344 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1345 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1346 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1347 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1348 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1349 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1350 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1351 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1352 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1353 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1354 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1355 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1356 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1357 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1358 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1359 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1360 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1362 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1363 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1364 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1366 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1368 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1370 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1372 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1374 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1376 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1378 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1380 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1382 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1383 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1384 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1386 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1387 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1388 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1390 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1392 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1394 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1395 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1396 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1398 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1399 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1400 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1402 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1404 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1406 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1407 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1408 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1410 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1412 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1414 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1416 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1418 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1420 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1422 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1423 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1424 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1426 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1428 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1430 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1431 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1432 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1434 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1436 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1438 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1440 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1442 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1443 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1444 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1446 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1447 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1448 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1450 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1452 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1454 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1456 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1458 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1460 0xf2000b00, 0xff800f10,
1461 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1463 0xf2000b10, 0xff800f10,
1464 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1466 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1468 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1470 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1472 0xf3000b00, 0xff800f10,
1473 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1475 0xf2000000, 0xfe800f10,
1476 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1478 0xf2000010, 0xfe800f10,
1479 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1481 0xf2000100, 0xfe800f10,
1482 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1484 0xf2000200, 0xfe800f10,
1485 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1487 0xf2000210, 0xfe800f10,
1488 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1490 0xf2000300, 0xfe800f10,
1491 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1493 0xf2000310, 0xfe800f10,
1494 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1496 0xf2000400, 0xfe800f10,
1497 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1499 0xf2000410, 0xfe800f10,
1500 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1502 0xf2000500, 0xfe800f10,
1503 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1505 0xf2000510, 0xfe800f10,
1506 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1508 0xf2000600, 0xfe800f10,
1509 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1511 0xf2000610, 0xfe800f10,
1512 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1514 0xf2000700, 0xfe800f10,
1515 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1517 0xf2000710, 0xfe800f10,
1518 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1520 0xf2000910, 0xfe800f10,
1521 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1523 0xf2000a00, 0xfe800f10,
1524 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1526 0xf2000a10, 0xfe800f10,
1527 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1529 0xf3000b10, 0xff800f10,
1530 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1532 0xf3000c10, 0xff800f10,
1533 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 /* One register and an immediate value. */
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1537 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1539 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1541 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1543 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1545 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1547 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1549 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1551 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1553 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1555 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1557 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1559 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1561 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1563 /* Two registers and a shift amount. */
1564 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1565 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1567 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1569 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1571 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1573 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1575 0xf2880950, 0xfeb80fd0,
1576 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1578 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1580 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1584 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1586 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1590 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1592 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1596 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1598 0xf2900950, 0xfeb00fd0,
1599 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1601 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1603 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1605 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1607 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1609 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1611 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1615 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1617 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1623 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1625 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1629 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1631 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1633 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1635 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1637 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1639 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1641 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1643 0xf2a00950, 0xfea00fd0,
1644 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1646 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1648 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1650 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1652 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1654 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1656 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1658 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1660 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1662 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1664 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1666 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1668 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1670 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1672 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1674 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1676 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1678 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1680 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1682 0xf2a00e10, 0xfea00e90,
1683 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1685 0xf2a00c10, 0xfea00e90,
1686 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1688 /* Three registers of different lengths. */
1689 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1690 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1692 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1694 0xf2800400, 0xff800f50,
1695 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf2800600, 0xff800f50,
1698 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1700 0xf2800900, 0xff800f50,
1701 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1703 0xf2800b00, 0xff800f50,
1704 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1706 0xf2800d00, 0xff800f50,
1707 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf3800400, 0xff800f50,
1710 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1712 0xf3800600, 0xff800f50,
1713 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1715 0xf2800000, 0xfe800f50,
1716 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1718 0xf2800100, 0xfe800f50,
1719 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1721 0xf2800200, 0xfe800f50,
1722 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1724 0xf2800300, 0xfe800f50,
1725 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1727 0xf2800500, 0xfe800f50,
1728 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1730 0xf2800700, 0xfe800f50,
1731 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1733 0xf2800800, 0xfe800f50,
1734 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1736 0xf2800a00, 0xfe800f50,
1737 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1739 0xf2800c00, 0xfe800f50,
1740 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1742 /* Two registers and a scalar. */
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1744 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1746 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1747 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1748 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1750 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1751 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1752 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1754 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1755 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1756 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1758 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1759 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1760 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1762 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1763 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1764 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1766 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1768 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1770 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1771 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1772 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1774 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1775 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1776 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1778 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1780 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1781 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1782 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1784 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1786 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1787 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1788 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1790 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1792 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf2800240, 0xfe800f50,
1795 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1797 0xf2800640, 0xfe800f50,
1798 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1800 0xf2800a40, 0xfe800f50,
1801 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1803 0xf2800e40, 0xff800f50,
1804 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1806 0xf2800f40, 0xff800f50,
1807 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1809 0xf3800e40, 0xff800f50,
1810 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1812 0xf3800f40, 0xff800f50,
1813 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1816 /* Element and structure load/store. */
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1818 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1820 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1822 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1824 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1826 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1828 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1830 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1832 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1834 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1836 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1838 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1840 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1842 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1844 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1846 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1848 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1850 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1852 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1854 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1856 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1859 /* mve opcode table. */
1861 /* print_insn_mve recognizes the following format control codes:
1865 %a print '+' or '-' or imm offset in vldr[bhwd] and
1867 %c print condition code
1868 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1869 %u print 'U' (unsigned) or 'S' for various mve instructions
1870 %i print MVE predicate(s) for vpt and vpst
1871 %n print vector comparison code for predicated instruction
1872 %v print vector predicate for instruction in predicated
1874 %o print offset scaled for vldr[hwd] and vstr[hwd]
1875 %w print writeback mode for MVE v{st,ld}[24]
1876 %B print v{st,ld}[24] any one operands
1878 %<bitfield>r print as an ARM register
1879 %<bitfield>d print the bitfield in decimal
1880 %<bitfield>Q print as a MVE Q register
1881 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1883 %<bitfield>s print size for vector predicate & non VMOV instructions
1884 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1887 static const struct mopcode32 mve_opcodes
[] =
1891 {ARM_FEATURE_COPROC (FPU_MVE
),
1893 0xfe310f4d, 0xffbf1fff,
1897 /* Floating point VPT T1. */
1898 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1900 0xee310f00, 0xefb10f50,
1901 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1902 /* Floating point VPT T2. */
1903 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1905 0xee310f40, 0xefb10f50,
1906 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1908 /* Vector VPT T1. */
1909 {ARM_FEATURE_COPROC (FPU_MVE
),
1911 0xfe010f00, 0xff811f51,
1912 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1913 /* Vector VPT T2. */
1914 {ARM_FEATURE_COPROC (FPU_MVE
),
1916 0xfe010f01, 0xff811f51,
1917 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1918 /* Vector VPT T3. */
1919 {ARM_FEATURE_COPROC (FPU_MVE
),
1921 0xfe011f00, 0xff811f50,
1922 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1923 /* Vector VPT T4. */
1924 {ARM_FEATURE_COPROC (FPU_MVE
),
1926 0xfe010f40, 0xff811f70,
1927 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1928 /* Vector VPT T5. */
1929 {ARM_FEATURE_COPROC (FPU_MVE
),
1931 0xfe010f60, 0xff811f70,
1932 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
1933 /* Vector VPT T6. */
1934 {ARM_FEATURE_COPROC (FPU_MVE
),
1936 0xfe011f40, 0xff811f50,
1937 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
1939 /* Vector VCMP floating point T1. */
1940 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1942 0xee310f00, 0xeff1ef50,
1943 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
1945 /* Vector VCMP floating point T2. */
1946 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1948 0xee310f40, 0xeff1ef50,
1949 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
1951 /* Vector VCMP T1. */
1952 {ARM_FEATURE_COPROC (FPU_MVE
),
1954 0xfe010f00, 0xffc1ff51,
1955 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1956 /* Vector VCMP T2. */
1957 {ARM_FEATURE_COPROC (FPU_MVE
),
1959 0xfe010f01, 0xffc1ff51,
1960 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1961 /* Vector VCMP T3. */
1962 {ARM_FEATURE_COPROC (FPU_MVE
),
1964 0xfe011f00, 0xffc1ff50,
1965 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1966 /* Vector VCMP T4. */
1967 {ARM_FEATURE_COPROC (FPU_MVE
),
1969 0xfe010f40, 0xffc1ff70,
1970 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
1971 /* Vector VCMP T5. */
1972 {ARM_FEATURE_COPROC (FPU_MVE
),
1974 0xfe010f60, 0xffc1ff70,
1975 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
1976 /* Vector VCMP T6. */
1977 {ARM_FEATURE_COPROC (FPU_MVE
),
1979 0xfe011f40, 0xffc1ff50,
1980 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
1983 {ARM_FEATURE_COPROC (FPU_MVE
),
1985 0xeea00b10, 0xffb10f5f,
1986 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
1989 {ARM_FEATURE_COPROC (FPU_MVE
),
1991 0xff000150, 0xffd11f51,
1992 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
1994 /* Vector VFMA, vector * scalar. */
1995 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1997 0xee310e40, 0xefb11f70,
1998 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2000 /* Vector VFMA floating point. */
2001 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2003 0xef000c50, 0xffa11f51,
2004 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2006 /* Vector VFMS floating point. */
2007 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2009 0xef200c50, 0xffa11f51,
2010 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2012 /* Vector VFMAS, vector * scalar. */
2013 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2014 MVE_VFMAS_FP_SCALAR
,
2015 0xee311e40, 0xefb11f70,
2016 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2018 /* Vector VHADD T1. */
2019 {ARM_FEATURE_COPROC (FPU_MVE
),
2021 0xef000040, 0xef811f51,
2022 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2024 /* Vector VHADD T2. */
2025 {ARM_FEATURE_COPROC (FPU_MVE
),
2027 0xee000f40, 0xef811f70,
2028 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2030 /* Vector VHSUB T1. */
2031 {ARM_FEATURE_COPROC (FPU_MVE
),
2033 0xef000240, 0xef811f51,
2034 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2036 /* Vector VHSUB T2. */
2037 {ARM_FEATURE_COPROC (FPU_MVE
),
2039 0xee001f40, 0xef811f70,
2040 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2043 {ARM_FEATURE_COPROC (FPU_MVE
),
2045 0xeea00b10, 0xffb10f5f,
2046 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2048 /* Vector VRHADD. */
2049 {ARM_FEATURE_COPROC (FPU_MVE
),
2051 0xef000140, 0xef811f51,
2052 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2055 {ARM_FEATURE_COPROC (FPU_MVE
),
2057 0xfc901e00, 0xff901e5f,
2058 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2061 {ARM_FEATURE_COPROC (FPU_MVE
),
2063 0xfc901e01, 0xff901e1f,
2064 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2066 /* Vector VLDRB gather load. */
2067 {ARM_FEATURE_COPROC (FPU_MVE
),
2068 MVE_VLDRB_GATHER_T1
,
2069 0xec900e00, 0xefb01e50,
2070 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2072 /* Vector VLDRH gather load. */
2073 {ARM_FEATURE_COPROC (FPU_MVE
),
2074 MVE_VLDRH_GATHER_T2
,
2075 0xec900e10, 0xefb01e50,
2076 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2078 /* Vector VLDRW gather load. */
2079 {ARM_FEATURE_COPROC (FPU_MVE
),
2080 MVE_VLDRW_GATHER_T3
,
2081 0xfc900f40, 0xffb01fd0,
2082 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2084 /* Vector VLDRD gather load. */
2085 {ARM_FEATURE_COPROC (FPU_MVE
),
2086 MVE_VLDRD_GATHER_T4
,
2087 0xec900fd0, 0xefb01fd0,
2088 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2090 /* Vector VLDRW gather load. */
2091 {ARM_FEATURE_COPROC (FPU_MVE
),
2092 MVE_VLDRW_GATHER_T5
,
2093 0xfd101e00, 0xff111f00,
2094 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2096 /* Vector VLDRD gather load, variant T6. */
2097 {ARM_FEATURE_COPROC (FPU_MVE
),
2098 MVE_VLDRD_GATHER_T6
,
2099 0xfd101f00, 0xff111f00,
2100 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2103 {ARM_FEATURE_COPROC (FPU_MVE
),
2105 0xec100e00, 0xee581e00,
2106 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2109 {ARM_FEATURE_COPROC (FPU_MVE
),
2111 0xec180e00, 0xee581e00,
2112 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2114 /* Vector VLDRB unsigned, variant T5. */
2115 {ARM_FEATURE_COPROC (FPU_MVE
),
2117 0xec101e00, 0xfe101f80,
2118 "vldrb%v.u8\t%13-15,22Q, %d"},
2120 /* Vector VLDRH unsigned, variant T6. */
2121 {ARM_FEATURE_COPROC (FPU_MVE
),
2123 0xec101e80, 0xfe101f80,
2124 "vldrh%v.u16\t%13-15,22Q, %d"},
2126 /* Vector VLDRW unsigned, variant T7. */
2127 {ARM_FEATURE_COPROC (FPU_MVE
),
2129 0xec101f00, 0xfe101f80,
2130 "vldrw%v.u32\t%13-15,22Q, %d"},
2132 /* Vector VST2 no writeback. */
2133 {ARM_FEATURE_COPROC (FPU_MVE
),
2135 0xfc801e00, 0xffb01e5f,
2136 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2138 /* Vector VST2 writeback. */
2139 {ARM_FEATURE_COPROC (FPU_MVE
),
2141 0xfca01e00, 0xffb01e5f,
2142 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2144 /* Vector VST4 no writeback. */
2145 {ARM_FEATURE_COPROC (FPU_MVE
),
2147 0xfc801e01, 0xffb01e1f,
2148 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2150 /* Vector VST4 writeback. */
2151 {ARM_FEATURE_COPROC (FPU_MVE
),
2153 0xfca01e01, 0xffb01e1f,
2154 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2156 /* Vector VSTRB scatter store, T1 variant. */
2157 {ARM_FEATURE_COPROC (FPU_MVE
),
2158 MVE_VSTRB_SCATTER_T1
,
2159 0xec800e00, 0xffb01e50,
2160 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2162 /* Vector VSTRH scatter store, T2 variant. */
2163 {ARM_FEATURE_COPROC (FPU_MVE
),
2164 MVE_VSTRH_SCATTER_T2
,
2165 0xec800e10, 0xffb01e50,
2166 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2168 /* Vector VSTRW scatter store, T3 variant. */
2169 {ARM_FEATURE_COPROC (FPU_MVE
),
2170 MVE_VSTRW_SCATTER_T3
,
2171 0xec800e40, 0xffb01e50,
2172 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2174 /* Vector VSTRD scatter store, T4 variant. */
2175 {ARM_FEATURE_COPROC (FPU_MVE
),
2176 MVE_VSTRD_SCATTER_T4
,
2177 0xec800fd0, 0xffb01fd0,
2178 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2180 /* Vector VSTRW scatter store, T5 variant. */
2181 {ARM_FEATURE_COPROC (FPU_MVE
),
2182 MVE_VSTRW_SCATTER_T5
,
2183 0xfd001e00, 0xff111f00,
2184 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2186 /* Vector VSTRD scatter store, T6 variant. */
2187 {ARM_FEATURE_COPROC (FPU_MVE
),
2188 MVE_VSTRD_SCATTER_T6
,
2189 0xfd001f00, 0xff111f00,
2190 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2193 {ARM_FEATURE_COPROC (FPU_MVE
),
2195 0xec000e00, 0xfe581e00,
2196 "vstrb%v.%7-8s\t%13-15Q, %d"},
2199 {ARM_FEATURE_COPROC (FPU_MVE
),
2201 0xec080e00, 0xfe581e00,
2202 "vstrh%v.%7-8s\t%13-15Q, %d"},
2204 /* Vector VSTRB variant T5. */
2205 {ARM_FEATURE_COPROC (FPU_MVE
),
2207 0xec001e00, 0xfe101f80,
2208 "vstrb%v.8\t%13-15,22Q, %d"},
2210 /* Vector VSTRH variant T6. */
2211 {ARM_FEATURE_COPROC (FPU_MVE
),
2213 0xec001e80, 0xfe101f80,
2214 "vstrh%v.16\t%13-15,22Q, %d"},
2216 /* Vector VSTRW variant T7. */
2217 {ARM_FEATURE_COPROC (FPU_MVE
),
2219 0xec001f00, 0xfe101f80,
2220 "vstrw%v.32\t%13-15,22Q, %d"},
2222 {ARM_FEATURE_CORE_LOW (0),
2224 0x00000000, 0x00000000, 0}
2227 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2228 ordered: they must be searched linearly from the top to obtain a correct
2231 /* print_insn_arm recognizes the following format control codes:
2235 %a print address for ldr/str instruction
2236 %s print address for ldr/str halfword/signextend instruction
2237 %S like %s but allow UNPREDICTABLE addressing
2238 %b print branch destination
2239 %c print condition code (always bits 28-31)
2240 %m print register mask for ldm/stm instruction
2241 %o print operand2 (immediate or register + shift)
2242 %p print 'p' iff bits 12-15 are 15
2243 %t print 't' iff bit 21 set and bit 24 clear
2244 %B print arm BLX(1) destination
2245 %C print the PSR sub type.
2246 %U print barrier type.
2247 %P print address for pli instruction.
2249 %<bitfield>r print as an ARM register
2250 %<bitfield>T print as an ARM register + 1
2251 %<bitfield>R as %r but r15 is UNPREDICTABLE
2252 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2253 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2254 %<bitfield>d print the bitfield in decimal
2255 %<bitfield>W print the bitfield plus one in decimal
2256 %<bitfield>x print the bitfield in hex
2257 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2259 %<bitfield>'c print specified char iff bitfield is all ones
2260 %<bitfield>`c print specified char iff bitfield is all zeroes
2261 %<bitfield>?ab... select from array of values in big endian order
2263 %e print arm SMI operand (bits 0..7,8..19).
2264 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
2265 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2266 %R print the SPSR/CPSR or banked register of an MRS. */
2268 static const struct opcode32 arm_opcodes
[] =
2270 /* ARM instructions. */
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2272 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2274 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
2277 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2279 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2281 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
2283 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2285 0x00800090, 0x0fa000f0,
2286 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2288 0x00a00090, 0x0fa000f0,
2289 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2291 /* V8.2 RAS extension instructions. */
2292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
2293 0xe320f010, 0xffffffff, "esb"},
2295 /* V8 instructions. */
2296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2297 0x0320f005, 0x0fffffff, "sevl"},
2298 /* Defined in V8 but is in NOP space so available to all arch. */
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2300 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
2302 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2304 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2306 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2308 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2310 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2312 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2314 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2316 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2318 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2320 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2322 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
2323 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2324 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2326 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
2327 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2328 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2329 /* CRC32 instructions. */
2330 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2331 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2332 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2333 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2334 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2335 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2336 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2337 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2338 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2339 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2340 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2341 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
2343 /* Privileged Access Never extension instructions. */
2344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
2345 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2347 /* Virtualization Extension instructions. */
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
2351 /* Integer Divide Extension instructions. */
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2353 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2355 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
2357 /* MP Extension instructions. */
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
2360 /* Speculation Barriers. */
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
2365 /* V7 instructions. */
2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
2374 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
2376 /* ARM V6T2 instructions. */
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2378 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2380 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2382 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2384 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2387 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2389 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2392 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
2393 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2394 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2396 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2398 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
2400 /* ARM Security extension instructions. */
2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
2402 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2404 /* ARM V6K instructions. */
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2406 0xf57ff01f, 0xffffffff, "clrex"},
2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2408 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2410 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2412 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2414 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2416 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2418 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
2420 /* ARMv8.5-A instructions. */
2421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
2423 /* ARM V6K NOP hints. */
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2425 0x0320f001, 0x0fffffff, "yield%c"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2427 0x0320f002, 0x0fffffff, "wfe%c"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2429 0x0320f003, 0x0fffffff, "wfi%c"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2431 0x0320f004, 0x0fffffff, "sev%c"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2433 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
2435 /* ARM V6 instructions. */
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2437 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2439 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2441 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2443 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2445 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2447 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2449 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2451 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2453 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2455 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2457 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2459 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2461 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2463 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2465 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2467 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2469 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2471 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2473 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2475 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2477 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2479 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2481 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2483 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2485 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2487 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2489 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2491 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2493 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2495 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2497 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2499 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2501 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2503 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2505 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2507 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2509 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2511 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2513 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2515 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2517 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2519 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2521 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2523 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2525 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2527 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2529 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2531 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2533 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2535 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2537 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2539 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2541 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2543 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2545 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2547 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2549 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2551 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2553 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2555 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2557 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2559 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2561 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2563 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2565 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2567 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2569 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2571 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2573 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2575 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2577 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2579 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2581 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2583 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2585 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2587 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2589 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2591 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2593 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2595 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2597 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2599 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2601 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2603 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2605 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2607 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2609 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2611 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2613 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2615 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2617 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2619 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2621 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2623 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2625 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2627 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2629 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2631 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2633 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2635 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2637 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2639 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2641 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2643 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2645 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2647 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2649 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2651 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2653 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2655 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2657 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2659 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2661 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2663 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2665 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2667 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2669 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2671 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2673 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2675 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2677 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2679 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2681 /* V5J instruction. */
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
2683 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2685 /* V5 Instructions. */
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2687 0xe1200070, 0xfff000f0,
2688 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2690 0xfa000000, 0xfe000000, "blx\t%B"},
2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2692 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2694 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2696 /* V5E "El Segundo" Instructions. */
2697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2698 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2700 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2702 0xf450f000, 0xfc70f000, "pld\t%a"},
2703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2704 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2706 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2708 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2710 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2713 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2715 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2718 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2720 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2722 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2724 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2727 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2729 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2731 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2733 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2736 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2738 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2741 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2743 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2745 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2747 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2749 /* ARM Instructions. */
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2751 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2754 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2756 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2758 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2760 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2762 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2764 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2767 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2769 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2771 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2773 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2776 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2778 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2780 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2782 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2785 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2787 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2789 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2792 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2794 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2796 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2799 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2801 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2803 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2806 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2808 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2810 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2813 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2815 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2817 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2820 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2822 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2824 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2827 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2829 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2831 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2834 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2836 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2838 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
2841 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
2843 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
2845 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2848 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2850 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2852 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2855 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2857 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2859 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2862 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2864 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2866 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2869 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2871 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2873 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2876 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2878 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2880 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2883 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2885 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2887 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2889 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2891 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2893 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2895 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2898 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2900 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2902 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2905 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2907 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2909 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2912 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2914 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2917 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2920 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2922 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2925 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2927 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2929 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2931 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2933 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2935 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2937 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2939 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2941 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2943 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2945 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2947 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2949 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2951 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2953 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2955 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2957 0x092d0000, 0x0fff0000, "push%c\t%m"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2959 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2961 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2964 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2966 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2968 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2970 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2972 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2974 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2976 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2978 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2980 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2982 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2984 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2986 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2988 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2990 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2992 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2994 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2996 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2998 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3000 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3003 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3005 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3009 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3011 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3012 {ARM_FEATURE_CORE_LOW (0),
3013 0x00000000, 0x00000000, 0}
3016 /* print_insn_thumb16 recognizes the following format control codes:
3018 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3019 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3020 %<bitfield>I print bitfield as a signed decimal
3021 (top bit of range being the sign bit)
3022 %N print Thumb register mask (with LR)
3023 %O print Thumb register mask (with PC)
3024 %M print Thumb register mask
3025 %b print CZB's 6-bit unsigned branch destination
3026 %s print Thumb right-shift immediate (6..10; 0 == 32).
3027 %c print the condition code
3028 %C print the condition code, or "s" if not conditional
3029 %x print warning if conditional an not at end of IT block"
3030 %X print "\t; unpredictable <IT:code>" if conditional
3031 %I print IT instruction suffix and operands
3032 %W print Thumb Writeback indicator for LDMIA
3033 %<bitfield>r print bitfield as an ARM register
3034 %<bitfield>d print bitfield as a decimal
3035 %<bitfield>H print (bitfield * 2) as a decimal
3036 %<bitfield>W print (bitfield * 4) as a decimal
3037 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3038 %<bitfield>B print Thumb branch destination (signed displacement)
3039 %<bitfield>c print bitfield as a condition code
3040 %<bitnum>'c print specified char iff bit is one
3041 %<bitnum>?ab print a if bit is one else print b. */
3043 static const struct opcode16 thumb_opcodes
[] =
3045 /* Thumb instructions. */
3047 /* ARMv8-M Security Extensions instructions. */
3048 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
3049 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
3051 /* ARM V8 instructions. */
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
3054 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3056 /* ARM V6K no-argument instructions. */
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3064 /* ARM V6T2 instructions. */
3065 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3066 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3067 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3068 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3084 /* ARM V5 ISA extends Thumb. */
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3086 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3087 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3089 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3090 /* ARM V4T ISA (Thumb v1). */
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3092 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3123 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3125 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3127 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3129 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3132 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3134 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3136 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3139 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3141 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3145 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3154 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3157 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3160 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3162 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3164 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3166 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3169 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3171 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3174 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3176 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3179 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3181 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3194 /* The E800 .. FFFF range is unconditionally redirected to the
3195 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3196 are processed via that table. Thus, we can never encounter a
3197 bare "second half of BL/BLX(1)" instruction here. */
3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
3199 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3202 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3203 We adopt the convention that hw1 is the high 16 bits of .value and
3204 .mask, hw2 the low 16 bits.
3206 print_insn_thumb32 recognizes the following format control codes:
3210 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3211 %M print a modified 12-bit immediate (same location)
3212 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3213 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3214 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
3215 %S print a possibly-shifted Rm
3217 %L print address for a ldrd/strd instruction
3218 %a print the address of a plain load/store
3219 %w print the width and signedness of a core load/store
3220 %m print register mask for ldm/stm
3221 %n print register mask for clrm
3223 %E print the lsb and width fields of a bfc/bfi instruction
3224 %F print the lsb and width fields of a sbfx/ubfx instruction
3225 %G print a fallback offset for Branch Future instructions
3226 %W print an offset for BF instruction
3227 %Y print an offset for BFL instruction
3228 %Z print an offset for BFCSEL instruction
3229 %Q print an offset for Low Overhead Loop instructions
3230 %P print an offset for Low Overhead Loop end instructions
3231 %b print a conditional branch offset
3232 %B print an unconditional branch offset
3233 %s print the shift field of an SSAT instruction
3234 %R print the rotation field of an SXT instruction
3235 %U print barrier type.
3236 %P print address for pli instruction.
3237 %c print the condition code
3238 %x print warning if conditional an not at end of IT block"
3239 %X print "\t; unpredictable <IT:code>" if conditional
3241 %<bitfield>d print bitfield in decimal
3242 %<bitfield>D print bitfield plus one in decimal
3243 %<bitfield>W print bitfield*4 in decimal
3244 %<bitfield>r print bitfield as an ARM register
3245 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
3246 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
3247 %<bitfield>c print bitfield as a condition code
3249 %<bitfield>'c print specified char iff bitfield is all ones
3250 %<bitfield>`c print specified char iff bitfield is all zeroes
3251 %<bitfield>?ab... select from array of values in big endian order
3253 With one exception at the bottom (done because BL and BLX(1) need
3254 to come dead last), this table was machine-sorted first in
3255 decreasing order of number of bits set in the mask, then in
3256 increasing numeric order of mask, then in increasing numeric order
3257 of opcode. This order is not the clearest for a human reader, but
3258 is guaranteed never to catch a special-case bit pattern with a more
3259 general mask, which is important, because this instruction encoding
3260 makes heavy use of special-case bit patterns. */
3261 static const struct opcode32 thumb32_opcodes
[] =
3263 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3266 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3268 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3270 0xf02fc001, 0xfffff001, "le\t%P"},
3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3272 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3275 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3277 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3278 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3279 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3281 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3283 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3286 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3288 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
3290 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3291 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3293 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3294 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3295 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3297 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3299 /* ARM V8.2 RAS extension instructions. */
3300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3301 0xf3af8010, 0xffffffff, "esb"},
3303 /* V8 instructions. */
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3305 0xf3af8005, 0xffffffff, "sevl%c.w"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3307 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3309 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3311 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3313 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3315 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3317 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3319 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3321 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3323 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3325 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3327 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3329 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3331 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3333 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3335 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
3337 /* CRC32 instructions. */
3338 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3339 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
3340 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3341 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
3342 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3343 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
3344 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3345 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
3346 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3347 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
3348 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3349 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
3351 /* Speculation Barriers. */
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
3353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
3354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
3356 /* V7 instructions. */
3357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3365 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3367 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3369 /* Virtualization Extension instructions. */
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3371 /* We skip ERET as that is SUBS pc, lr, #0. */
3373 /* MP Extension instructions. */
3374 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
3376 /* Security extension instructions. */
3377 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3379 /* ARMv8.5-A instructions. */
3380 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
3382 /* Instructions defined in the basic V6T2 set. */
3383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
3385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
3388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3389 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3393 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3395 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3397 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3399 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3401 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3403 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3405 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3407 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3409 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3411 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3413 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3415 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3417 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3419 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3421 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3422 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3423 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3425 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3427 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3429 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3431 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3433 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3435 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3437 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3439 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3441 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3443 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3445 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3447 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3449 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3451 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3453 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3455 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3457 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3459 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3461 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3463 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3465 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3467 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3469 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3471 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3473 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3475 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3477 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3479 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3481 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3483 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3485 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3487 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3489 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3491 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3493 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3495 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3497 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3499 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3501 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3503 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3505 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3507 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3509 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3511 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3513 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3515 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3517 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3519 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3521 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3523 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3525 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3527 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3529 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3531 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3533 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3535 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3537 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3539 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3541 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3543 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3545 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3547 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3549 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3551 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3553 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3555 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3557 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3559 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3561 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3563 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3565 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3567 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3569 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3571 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3573 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3575 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3577 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3579 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3581 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3583 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3585 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3587 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3589 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3591 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3593 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3595 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3597 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3599 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3601 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3603 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3605 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3607 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3609 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3611 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3613 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3615 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3616 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3617 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3619 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3621 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3623 0xf810f000, 0xff70f000, "pld%c\t%a"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3625 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3627 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3629 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3631 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3633 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3635 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3637 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3639 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3641 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3643 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3645 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3647 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3649 0xfb100000, 0xfff000c0,
3650 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3652 0xfbc00080, 0xfff000c0,
3653 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3655 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3657 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3659 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3661 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3663 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3665 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3667 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3669 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3671 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3673 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3675 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3677 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3679 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3681 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3683 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3685 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3687 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3689 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3691 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3693 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3695 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3697 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3699 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3701 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3703 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3705 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3707 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3709 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3711 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3713 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3715 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3717 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3719 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3721 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3723 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3725 0xe9400000, 0xff500000,
3726 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3728 0xe9500000, 0xff500000,
3729 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3731 0xe8600000, 0xff700000,
3732 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3734 0xe8700000, 0xff700000,
3735 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3737 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3739 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3741 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3743 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3745 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3747 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3749 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3751 /* These have been 32-bit since the invention of Thumb. */
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3753 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3755 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3759 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3760 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3763 static const char *const arm_conditional
[] =
3764 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3765 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3767 static const char *const arm_fp_const
[] =
3768 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3770 static const char *const arm_shift
[] =
3771 {"lsl", "lsr", "asr", "ror"};
3776 const char *description
;
3777 const char *reg_names
[16];
3781 static const arm_regname regnames
[] =
3783 { "reg-names-raw", N_("Select raw register names"),
3784 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3785 { "reg-names-gcc", N_("Select register names used by GCC"),
3786 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3787 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3788 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3789 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
3790 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
3791 { "reg-names-apcs", N_("Select register names used in the APCS"),
3792 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3793 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3794 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3795 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3796 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
3799 static const char *const iwmmxt_wwnames
[] =
3800 {"b", "h", "w", "d"};
3802 static const char *const iwmmxt_wwssnames
[] =
3803 {"b", "bus", "bc", "bss",
3804 "h", "hus", "hc", "hss",
3805 "w", "wus", "wc", "wss",
3806 "d", "dus", "dc", "dss"
3809 static const char *const iwmmxt_regnames
[] =
3810 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3811 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3814 static const char *const iwmmxt_cregnames
[] =
3815 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3816 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3819 static const char *const vec_condnames
[] =
3820 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
3823 static const char *const mve_predicatenames
[] =
3824 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
3825 "eee", "ee", "eet", "e", "ett", "et", "ete"
3828 /* Names for 2-bit size field for mve vector isntructions. */
3829 static const char *const mve_vec_sizename
[] =
3830 { "8", "16", "32", "64"};
3832 /* Indicates whether we are processing a then predicate,
3833 else predicate or none at all. */
3841 /* Information used to process a vpt block and subsequent instructions. */
3844 /* Are we in a vpt block. */
3845 bfd_boolean in_vpt_block
;
3847 /* Next predicate state if in vpt block. */
3848 enum vpt_pred_state next_pred_state
;
3850 /* Mask from vpt/vpst instruction. */
3851 long predicate_mask
;
3853 /* Instruction number in vpt block. */
3854 long current_insn_num
;
3856 /* Number of instructions in vpt block.. */
3860 static struct vpt_block vpt_block_state
=
3869 /* Default to GCC register name set. */
3870 static unsigned int regname_selected
= 1;
3872 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
3873 #define arm_regnames regnames[regname_selected].reg_names
3875 static bfd_boolean force_thumb
= FALSE
;
3877 /* Current IT instruction state. This contains the same state as the IT
3878 bits in the CPSR. */
3879 static unsigned int ifthen_state
;
3880 /* IT state for the next instruction. */
3881 static unsigned int ifthen_next_state
;
3882 /* The address of the insn for which the IT state is valid. */
3883 static bfd_vma ifthen_address
;
3884 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3885 /* Indicates that the current Conditional state is unconditional or outside
3887 #define COND_UNCOND 16
3891 /* Extract the predicate mask for a VPT or VPST instruction.
3892 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
3895 mve_extract_pred_mask (long given
)
3897 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
3900 /* Return the number of instructions in a MVE predicate block. */
3902 num_instructions_vpt_block (long given
)
3904 long mask
= mve_extract_pred_mask (given
);
3911 if ((mask
& 7) == 4)
3914 if ((mask
& 3) == 2)
3917 if ((mask
& 1) == 1)
3924 mark_outside_vpt_block (void)
3926 vpt_block_state
.in_vpt_block
= FALSE
;
3927 vpt_block_state
.next_pred_state
= PRED_NONE
;
3928 vpt_block_state
.predicate_mask
= 0;
3929 vpt_block_state
.current_insn_num
= 0;
3930 vpt_block_state
.num_pred_insn
= 0;
3934 mark_inside_vpt_block (long given
)
3936 vpt_block_state
.in_vpt_block
= TRUE
;
3937 vpt_block_state
.next_pred_state
= PRED_THEN
;
3938 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
3939 vpt_block_state
.current_insn_num
= 0;
3940 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
3941 assert (vpt_block_state
.num_pred_insn
>= 1);
3944 static enum vpt_pred_state
3945 invert_next_predicate_state (enum vpt_pred_state astate
)
3947 if (astate
== PRED_THEN
)
3949 else if (astate
== PRED_ELSE
)
3955 static enum vpt_pred_state
3956 update_next_predicate_state (void)
3958 long pred_mask
= vpt_block_state
.predicate_mask
;
3959 long mask_for_insn
= 0;
3961 switch (vpt_block_state
.current_insn_num
)
3979 if (pred_mask
& mask_for_insn
)
3980 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
3982 return vpt_block_state
.next_pred_state
;
3986 update_vpt_block_state (void)
3988 vpt_block_state
.current_insn_num
++;
3989 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
3991 /* No more instructions to process in vpt block. */
3992 mark_outside_vpt_block ();
3996 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
3999 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4000 Returns pointer to following character of the format string and
4001 fills in *VALUEP and *WIDTHP with the extracted value and number of
4002 bits extracted. WIDTHP can be NULL. */
4005 arm_decode_bitfield (const char *ptr
,
4007 unsigned long *valuep
,
4010 unsigned long value
= 0;
4018 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4019 start
= start
* 10 + *ptr
- '0';
4021 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4022 end
= end
* 10 + *ptr
- '0';
4028 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
4031 while (*ptr
++ == ',');
4039 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
4040 bfd_boolean print_shift
)
4042 func (stream
, "%s", arm_regnames
[given
& 0xf]);
4044 if ((given
& 0xff0) != 0)
4046 if ((given
& 0x10) == 0)
4048 int amount
= (given
& 0xf80) >> 7;
4049 int shift
= (given
& 0x60) >> 5;
4055 func (stream
, ", rrx");
4063 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
4065 func (stream
, ", #%d", amount
);
4067 else if ((given
& 0x80) == 0x80)
4068 func (stream
, "\t; <illegal shifter operand>");
4069 else if (print_shift
)
4070 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
4071 arm_regnames
[(given
& 0xf00) >> 8]);
4073 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
4077 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4080 is_mve_okay_in_it (enum mve_instructions matched_insn
)
4086 is_mve_architecture (struct disassemble_info
*info
)
4088 struct arm_private_data
*private_data
= info
->private_data
;
4089 arm_feature_set allowed_arches
= private_data
->features
;
4091 arm_feature_set arm_ext_v8_1m_main
4092 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
4094 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
4095 && !ARM_CPU_IS_ANY (allowed_arches
))
4102 is_vpt_instruction (long given
)
4105 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4106 if ((given
& 0x0040e000) == 0)
4109 /* VPT floating point T1 variant. */
4110 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
4111 /* VPT floating point T2 variant. */
4112 || ((given
& 0xefb10f50) == 0xee310f40)
4113 /* VPT vector T1 variant. */
4114 || ((given
& 0xff811f51) == 0xfe010f00)
4115 /* VPT vector T2 variant. */
4116 || ((given
& 0xff811f51) == 0xfe010f01
4117 && ((given
& 0x300000) != 0x300000))
4118 /* VPT vector T3 variant. */
4119 || ((given
& 0xff811f50) == 0xfe011f00)
4120 /* VPT vector T4 variant. */
4121 || ((given
& 0xff811f70) == 0xfe010f40)
4122 /* VPT vector T5 variant. */
4123 || ((given
& 0xff811f70) == 0xfe010f60)
4124 /* VPT vector T6 variant. */
4125 || ((given
& 0xff811f50) == 0xfe011f40)
4126 /* VPST vector T variant. */
4127 || ((given
& 0xffbf1fff) == 0xfe310f4d))
4133 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4134 and ending bitfield = END. END must be greater than START. */
4136 static unsigned long
4137 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
4139 int bits
= end
- start
;
4144 return ((given
>> start
) & ((2ul << bits
) - 1));
4147 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4148 START:END and START2:END2. END/END2 must be greater than
4151 static unsigned long
4152 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
4153 unsigned int end
, unsigned int start2
,
4156 int bits
= end
- start
;
4157 int bits2
= end2
- start2
;
4158 unsigned long value
= 0;
4164 value
= arm_decode_field (given
, start
, end
);
4167 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
4171 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4172 This helps us decode instructions that change mnemonic depending on specific
4173 operand values/encodings. */
4176 is_mve_encoding_conflict (unsigned long given
,
4177 enum mve_instructions matched_insn
)
4179 switch (matched_insn
)
4182 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4188 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4190 if ((arm_decode_field (given
, 12, 12) == 0)
4191 && (arm_decode_field (given
, 0, 0) == 1))
4196 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4198 if (arm_decode_field (given
, 0, 3) == 0xd)
4202 case MVE_VPT_VEC_T1
:
4203 case MVE_VPT_VEC_T2
:
4204 case MVE_VPT_VEC_T3
:
4205 case MVE_VPT_VEC_T4
:
4206 case MVE_VPT_VEC_T5
:
4207 case MVE_VPT_VEC_T6
:
4208 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4210 if (arm_decode_field (given
, 20, 21) == 3)
4214 case MVE_VCMP_FP_T1
:
4215 if ((arm_decode_field (given
, 12, 12) == 0)
4216 && (arm_decode_field (given
, 0, 0) == 1))
4221 case MVE_VCMP_FP_T2
:
4222 if (arm_decode_field (given
, 0, 3) == 0xd)
4229 case MVE_VCMP_VEC_T1
:
4230 case MVE_VCMP_VEC_T2
:
4231 case MVE_VCMP_VEC_T3
:
4232 case MVE_VCMP_VEC_T4
:
4233 case MVE_VCMP_VEC_T5
:
4234 case MVE_VCMP_VEC_T6
:
4235 if (arm_decode_field (given
, 20, 21) == 3)
4244 if (arm_decode_field (given
, 7, 8) == 3)
4251 if ((arm_decode_field (given
, 24, 24) == 0)
4252 && (arm_decode_field (given
, 21, 21) == 0))
4256 else if ((arm_decode_field (given
, 7, 8) == 3))
4264 if ((arm_decode_field (given
, 24, 24) == 0)
4265 && (arm_decode_field (given
, 21, 21) == 0))
4279 print_mve_vld_str_addr (struct disassemble_info
*info
,
4280 unsigned long given
,
4281 enum mve_instructions matched_insn
)
4283 void *stream
= info
->stream
;
4284 fprintf_ftype func
= info
->fprintf_func
;
4286 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
4288 imm
= arm_decode_field (given
, 0, 6);
4291 switch (matched_insn
)
4295 gpr
= arm_decode_field (given
, 16, 18);
4300 gpr
= arm_decode_field (given
, 16, 18);
4306 gpr
= arm_decode_field (given
, 16, 19);
4312 gpr
= arm_decode_field (given
, 16, 19);
4318 gpr
= arm_decode_field (given
, 16, 19);
4325 p
= arm_decode_field (given
, 24, 24);
4326 w
= arm_decode_field (given
, 21, 21);
4328 add
= arm_decode_field (given
, 23, 23);
4332 /* Don't print anything for '+' as it is implied. */
4342 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
4343 /* Pre-indexed mode. */
4345 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
4347 else if ((p
== 0) && (w
== 1))
4348 /* Post-index mode. */
4349 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
4352 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4353 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4354 this encoding is undefined. */
4357 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
4358 enum mve_undefined
*undefined_code
)
4360 *undefined_code
= UNDEF_NONE
;
4362 switch (matched_insn
)
4365 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
4367 *undefined_code
= UNDEF_SIZE_3
;
4376 if (arm_decode_field (given
, 20, 21) == 3)
4378 *undefined_code
= UNDEF_SIZE_3
;
4385 if (arm_decode_field (given
, 7, 8) == 3)
4387 *undefined_code
= UNDEF_SIZE_3
;
4394 if (arm_decode_field (given
, 7, 8) <= 1)
4396 *undefined_code
= UNDEF_SIZE_LE_1
;
4403 if ((arm_decode_field (given
, 7, 8) == 0))
4405 *undefined_code
= UNDEF_SIZE_0
;
4412 if ((arm_decode_field (given
, 7, 8) <= 1))
4414 *undefined_code
= UNDEF_SIZE_LE_1
;
4420 case MVE_VLDRB_GATHER_T1
:
4421 if (arm_decode_field (given
, 7, 8) == 3)
4423 *undefined_code
= UNDEF_SIZE_3
;
4426 else if ((arm_decode_field (given
, 28, 28) == 0)
4427 && (arm_decode_field (given
, 7, 8) == 0))
4429 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
4435 case MVE_VLDRH_GATHER_T2
:
4436 if (arm_decode_field (given
, 7, 8) == 3)
4438 *undefined_code
= UNDEF_SIZE_3
;
4441 else if ((arm_decode_field (given
, 28, 28) == 0)
4442 && (arm_decode_field (given
, 7, 8) == 1))
4444 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
4447 else if (arm_decode_field (given
, 7, 8) == 0)
4449 *undefined_code
= UNDEF_SIZE_0
;
4455 case MVE_VLDRW_GATHER_T3
:
4456 if (arm_decode_field (given
, 7, 8) != 2)
4458 *undefined_code
= UNDEF_SIZE_NOT_2
;
4461 else if (arm_decode_field (given
, 28, 28) == 0)
4463 *undefined_code
= UNDEF_NOT_UNSIGNED
;
4469 case MVE_VLDRD_GATHER_T4
:
4470 if (arm_decode_field (given
, 7, 8) != 3)
4472 *undefined_code
= UNDEF_SIZE_NOT_3
;
4475 else if (arm_decode_field (given
, 28, 28) == 0)
4477 *undefined_code
= UNDEF_NOT_UNSIGNED
;
4483 case MVE_VSTRB_SCATTER_T1
:
4484 if (arm_decode_field (given
, 7, 8) == 3)
4486 *undefined_code
= UNDEF_SIZE_3
;
4492 case MVE_VSTRH_SCATTER_T2
:
4494 unsigned long size
= arm_decode_field (given
, 7, 8);
4497 *undefined_code
= UNDEF_SIZE_3
;
4502 *undefined_code
= UNDEF_SIZE_0
;
4509 case MVE_VSTRW_SCATTER_T3
:
4510 if (arm_decode_field (given
, 7, 8) != 2)
4512 *undefined_code
= UNDEF_SIZE_NOT_2
;
4518 case MVE_VSTRD_SCATTER_T4
:
4519 if (arm_decode_field (given
, 7, 8) != 3)
4521 *undefined_code
= UNDEF_SIZE_NOT_3
;
4532 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
4533 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
4534 why this encoding is unpredictable. */
4537 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
4538 enum mve_unpredictable
*unpredictable_code
)
4540 *unpredictable_code
= UNPRED_NONE
;
4542 switch (matched_insn
)
4544 case MVE_VCMP_FP_T2
:
4546 if ((arm_decode_field (given
, 12, 12) == 0)
4547 && (arm_decode_field (given
, 5, 5) == 1))
4549 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
4555 case MVE_VPT_VEC_T4
:
4556 case MVE_VPT_VEC_T5
:
4557 case MVE_VPT_VEC_T6
:
4558 case MVE_VCMP_VEC_T4
:
4559 case MVE_VCMP_VEC_T5
:
4560 case MVE_VCMP_VEC_T6
:
4561 if (arm_decode_field (given
, 0, 3) == 0xd)
4563 *unpredictable_code
= UNPRED_R13
;
4571 unsigned long gpr
= arm_decode_field (given
, 12, 15);
4574 *unpredictable_code
= UNPRED_R13
;
4577 else if (gpr
== 0xf)
4579 *unpredictable_code
= UNPRED_R15
;
4586 case MVE_VFMA_FP_SCALAR
:
4587 case MVE_VFMAS_FP_SCALAR
:
4591 unsigned long gpr
= arm_decode_field (given
, 0, 3);
4594 *unpredictable_code
= UNPRED_R13
;
4597 else if (gpr
== 0xf)
4599 *unpredictable_code
= UNPRED_R15
;
4609 unsigned long rn
= arm_decode_field (given
, 16, 19);
4611 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
4613 *unpredictable_code
= UNPRED_R13_AND_WB
;
4619 *unpredictable_code
= UNPRED_R15
;
4623 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
4625 *unpredictable_code
= UNPRED_Q_GT_6
;
4635 unsigned long rn
= arm_decode_field (given
, 16, 19);
4637 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
4639 *unpredictable_code
= UNPRED_R13_AND_WB
;
4645 *unpredictable_code
= UNPRED_R15
;
4649 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
4651 *unpredictable_code
= UNPRED_Q_GT_4
;
4665 unsigned long rn
= arm_decode_field (given
, 16, 19);
4667 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
4669 *unpredictable_code
= UNPRED_R13_AND_WB
;
4674 *unpredictable_code
= UNPRED_R15
;
4681 case MVE_VLDRB_GATHER_T1
:
4682 if (arm_decode_field (given
, 0, 0) == 1)
4684 *unpredictable_code
= UNPRED_OS
;
4689 /* To handle common code with T2-T4 variants. */
4690 case MVE_VLDRH_GATHER_T2
:
4691 case MVE_VLDRW_GATHER_T3
:
4692 case MVE_VLDRD_GATHER_T4
:
4694 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
4695 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
4699 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
4703 if (arm_decode_field (given
, 16, 19) == 0xf)
4705 *unpredictable_code
= UNPRED_R15
;
4712 case MVE_VLDRW_GATHER_T5
:
4713 case MVE_VLDRD_GATHER_T6
:
4715 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
4716 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
4720 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
4727 case MVE_VSTRB_SCATTER_T1
:
4728 if (arm_decode_field (given
, 16, 19) == 0xf)
4730 *unpredictable_code
= UNPRED_R15
;
4733 else if (arm_decode_field (given
, 0, 0) == 1)
4735 *unpredictable_code
= UNPRED_OS
;
4741 case MVE_VSTRH_SCATTER_T2
:
4742 case MVE_VSTRW_SCATTER_T3
:
4743 case MVE_VSTRD_SCATTER_T4
:
4744 if (arm_decode_field (given
, 16, 19) == 0xf)
4746 *unpredictable_code
= UNPRED_R15
;
4758 print_mve_undefined (struct disassemble_info
*info
,
4759 enum mve_undefined undefined_code
)
4761 void *stream
= info
->stream
;
4762 fprintf_ftype func
= info
->fprintf_func
;
4764 func (stream
, "\t\tundefined instruction: ");
4766 switch (undefined_code
)
4769 func (stream
, "size equals zero");
4773 func (stream
, "size equals three");
4776 case UNDEF_SIZE_LE_1
:
4777 func (stream
, "size <= 1");
4780 case UNDEF_SIZE_NOT_2
:
4781 func (stream
, "size not equal to 2");
4784 case UNDEF_SIZE_NOT_3
:
4785 func (stream
, "size not equal to 3");
4788 case UNDEF_NOT_UNS_SIZE_0
:
4789 func (stream
, "not unsigned and size = zero");
4792 case UNDEF_NOT_UNS_SIZE_1
:
4793 func (stream
, "not unsigned and size = one");
4796 case UNDEF_NOT_UNSIGNED
:
4797 func (stream
, "not unsigned");
4807 print_mve_unpredictable (struct disassemble_info
*info
,
4808 enum mve_unpredictable unpredict_code
)
4810 void *stream
= info
->stream
;
4811 fprintf_ftype func
= info
->fprintf_func
;
4813 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
4815 switch (unpredict_code
)
4817 case UNPRED_IT_BLOCK
:
4818 func (stream
, "mve instruction in it block");
4821 case UNPRED_FCA_0_FCB_1
:
4822 func (stream
, "condition bits, fca = 0 and fcb = 1");
4826 func (stream
, "use of r13 (sp)");
4830 func (stream
, "use of r15 (pc)");
4834 func (stream
, "start register block > r4");
4838 func (stream
, "start register block > r6");
4841 case UNPRED_R13_AND_WB
:
4842 func (stream
, "use of r13 and write back");
4845 case UNPRED_Q_REGS_EQUAL
:
4847 "same vector register used for destination and other operand");
4851 func (stream
, "use of offset scaled");
4859 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
4862 print_mve_register_blocks (struct disassemble_info
*info
,
4863 unsigned long given
,
4864 enum mve_instructions matched_insn
)
4866 void *stream
= info
->stream
;
4867 fprintf_ftype func
= info
->fprintf_func
;
4869 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
4872 switch (matched_insn
)
4876 if (q_reg_start
<= 6)
4877 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
4879 func (stream
, "<illegal reg q%ld>", q_reg_start
);
4884 if (q_reg_start
<= 4)
4885 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
4886 q_reg_start
+ 1, q_reg_start
+ 2,
4889 func (stream
, "<illegal reg q%ld>", q_reg_start
);
4898 print_instruction_predicate (struct disassemble_info
*info
)
4900 void *stream
= info
->stream
;
4901 fprintf_ftype func
= info
->fprintf_func
;
4903 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
4905 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
4910 print_mve_size (struct disassemble_info
*info
,
4912 enum mve_instructions matched_insn
)
4914 void *stream
= info
->stream
;
4915 fprintf_ftype func
= info
->fprintf_func
;
4917 switch (matched_insn
)
4919 case MVE_VCMP_VEC_T1
:
4920 case MVE_VCMP_VEC_T2
:
4921 case MVE_VCMP_VEC_T3
:
4922 case MVE_VCMP_VEC_T4
:
4923 case MVE_VCMP_VEC_T5
:
4924 case MVE_VCMP_VEC_T6
:
4931 case MVE_VLDRB_GATHER_T1
:
4932 case MVE_VLDRH_GATHER_T2
:
4933 case MVE_VLDRW_GATHER_T3
:
4934 case MVE_VLDRD_GATHER_T4
:
4937 case MVE_VPT_VEC_T1
:
4938 case MVE_VPT_VEC_T2
:
4939 case MVE_VPT_VEC_T3
:
4940 case MVE_VPT_VEC_T4
:
4941 case MVE_VPT_VEC_T5
:
4942 case MVE_VPT_VEC_T6
:
4946 case MVE_VSTRB_SCATTER_T1
:
4947 case MVE_VSTRH_SCATTER_T2
:
4948 case MVE_VSTRW_SCATTER_T3
:
4952 func (stream
, "%s", mve_vec_sizename
[size
]);
4954 func (stream
, "<undef size>");
4957 case MVE_VCMP_FP_T1
:
4958 case MVE_VCMP_FP_T2
:
4959 case MVE_VFMA_FP_SCALAR
:
4962 case MVE_VFMAS_FP_SCALAR
:
4966 func (stream
, "32");
4968 func (stream
, "16");
4975 func (stream
, "32");
4978 func (stream
, "16");
4994 print_vec_condition (struct disassemble_info
*info
, long given
,
4995 enum mve_instructions matched_insn
)
4997 void *stream
= info
->stream
;
4998 fprintf_ftype func
= info
->fprintf_func
;
5001 switch (matched_insn
)
5004 case MVE_VCMP_FP_T1
:
5005 vec_cond
= (((given
& 0x1000) >> 10)
5006 | ((given
& 1) << 1)
5007 | ((given
& 0x0080) >> 7));
5008 func (stream
, "%s",vec_condnames
[vec_cond
]);
5012 case MVE_VCMP_FP_T2
:
5013 vec_cond
= (((given
& 0x1000) >> 10)
5014 | ((given
& 0x0020) >> 4)
5015 | ((given
& 0x0080) >> 7));
5016 func (stream
, "%s",vec_condnames
[vec_cond
]);
5019 case MVE_VPT_VEC_T1
:
5020 case MVE_VCMP_VEC_T1
:
5021 vec_cond
= (given
& 0x0080) >> 7;
5022 func (stream
, "%s",vec_condnames
[vec_cond
]);
5025 case MVE_VPT_VEC_T2
:
5026 case MVE_VCMP_VEC_T2
:
5027 vec_cond
= 2 | ((given
& 0x0080) >> 7);
5028 func (stream
, "%s",vec_condnames
[vec_cond
]);
5031 case MVE_VPT_VEC_T3
:
5032 case MVE_VCMP_VEC_T3
:
5033 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
5034 func (stream
, "%s",vec_condnames
[vec_cond
]);
5037 case MVE_VPT_VEC_T4
:
5038 case MVE_VCMP_VEC_T4
:
5039 vec_cond
= (given
& 0x0080) >> 7;
5040 func (stream
, "%s",vec_condnames
[vec_cond
]);
5043 case MVE_VPT_VEC_T5
:
5044 case MVE_VCMP_VEC_T5
:
5045 vec_cond
= 2 | ((given
& 0x0080) >> 7);
5046 func (stream
, "%s",vec_condnames
[vec_cond
]);
5049 case MVE_VPT_VEC_T6
:
5050 case MVE_VCMP_VEC_T6
:
5051 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
5052 func (stream
, "%s",vec_condnames
[vec_cond
]);
5067 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
5068 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
5069 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
5070 #define PRE_BIT_SET (given & (1 << P_BIT))
5073 /* Print one coprocessor instruction on INFO->STREAM.
5074 Return TRUE if the instuction matched, FALSE if this is not a
5075 recognised coprocessor instruction. */
5078 print_insn_coprocessor (bfd_vma pc
,
5079 struct disassemble_info
*info
,
5083 const struct sopcode32
*insn
;
5084 void *stream
= info
->stream
;
5085 fprintf_ftype func
= info
->fprintf_func
;
5087 unsigned long value
= 0;
5090 struct arm_private_data
*private_data
= info
->private_data
;
5091 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
5092 arm_feature_set arm_ext_v8_1m_main
=
5093 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
5095 allowed_arches
= private_data
->features
;
5097 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
5099 unsigned long u_reg
= 16;
5100 bfd_boolean is_unpredictable
= FALSE
;
5101 signed long value_in_comment
= 0;
5104 if (ARM_FEATURE_ZERO (insn
->arch
))
5105 switch (insn
->value
)
5107 case SENTINEL_IWMMXT_START
:
5108 if (info
->mach
!= bfd_mach_arm_XScale
5109 && info
->mach
!= bfd_mach_arm_iWMMXt
5110 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
5113 while ((! ARM_FEATURE_ZERO (insn
->arch
))
5114 && insn
->value
!= SENTINEL_IWMMXT_END
);
5117 case SENTINEL_IWMMXT_END
:
5120 case SENTINEL_GENERIC_START
:
5121 allowed_arches
= private_data
->features
;
5129 value
= insn
->value
;
5130 cp_num
= (given
>> 8) & 0xf;
5134 /* The high 4 bits are 0xe for Arm conditional instructions, and
5135 0xe for arm unconditional instructions. The rest of the
5136 encoding is the same. */
5138 value
|= 0xe0000000;
5146 /* Only match unconditional instuctions against unconditional
5148 if ((given
& 0xf0000000) == 0xf0000000)
5155 cond
= (given
>> 28) & 0xf;
5161 if ((insn
->isa
== T32
&& !thumb
)
5162 || (insn
->isa
== ARM
&& thumb
))
5165 if ((given
& mask
) != value
)
5168 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
5171 if (insn
->value
== 0xfe000010 /* mcr2 */
5172 || insn
->value
== 0xfe100010 /* mrc2 */
5173 || insn
->value
== 0xfc100000 /* ldc2 */
5174 || insn
->value
== 0xfc000000) /* stc2 */
5176 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
5177 is_unpredictable
= TRUE
;
5179 /* Armv8.1-M Mainline FP & MVE instructions. */
5180 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
5181 && !ARM_CPU_IS_ANY (allowed_arches
)
5182 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
5186 else if (insn
->value
== 0x0e000000 /* cdp */
5187 || insn
->value
== 0xfe000000 /* cdp2 */
5188 || insn
->value
== 0x0e000010 /* mcr */
5189 || insn
->value
== 0x0e100010 /* mrc */
5190 || insn
->value
== 0x0c100000 /* ldc */
5191 || insn
->value
== 0x0c000000) /* stc */
5193 /* Floating-point instructions. */
5194 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
5197 /* Armv8.1-M Mainline FP & MVE instructions. */
5198 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
5199 && !ARM_CPU_IS_ANY (allowed_arches
)
5200 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
5203 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
5204 || insn
->value
== 0xec000f80) /* vstr (system register) */
5205 && arm_decode_field (given
, 24, 24) == 0
5206 && arm_decode_field (given
, 21, 21) == 0)
5207 /* If the P and W bits are both 0 then these encodings match the MVE
5208 VLDR and VSTR instructions, these are in a different table, so we
5209 don't let it match here. */
5213 for (c
= insn
->assembler
; *c
; c
++)
5217 const char mod
= *++c
;
5221 func (stream
, "%%");
5227 int rn
= (given
>> 16) & 0xf;
5228 bfd_vma offset
= given
& 0xff;
5231 offset
= given
& 0x7f;
5233 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
5235 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
5237 /* Not unindexed. The offset is scaled. */
5239 /* vldr.16/vstr.16 will shift the address
5240 left by 1 bit only. */
5241 offset
= offset
* 2;
5243 offset
= offset
* 4;
5245 if (NEGATIVE_BIT_SET
)
5248 value_in_comment
= offset
;
5254 func (stream
, ", #%d]%s",
5256 WRITEBACK_BIT_SET
? "!" : "");
5257 else if (NEGATIVE_BIT_SET
)
5258 func (stream
, ", #-0]");
5266 if (WRITEBACK_BIT_SET
)
5269 func (stream
, ", #%d", (int) offset
);
5270 else if (NEGATIVE_BIT_SET
)
5271 func (stream
, ", #-0");
5275 func (stream
, ", {%s%d}",
5276 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
5278 value_in_comment
= offset
;
5281 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
5283 func (stream
, "\t; ");
5284 /* For unaligned PCs, apply off-by-alignment
5286 info
->print_address_func (offset
+ pc
5287 + info
->bytes_per_chunk
* 2
5296 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
5297 int offset
= (given
>> 1) & 0x3f;
5300 func (stream
, "{d%d}", regno
);
5301 else if (regno
+ offset
> 32)
5302 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
5304 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
5310 bfd_boolean single
= ((given
>> 8) & 1) == 0;
5311 char reg_prefix
= single
? 's' : 'd';
5312 int Dreg
= (given
>> 22) & 0x1;
5313 int Vdreg
= (given
>> 12) & 0xf;
5314 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
5315 : ((Dreg
<< 4) | Vdreg
);
5316 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
5317 int maxreg
= single
? 31 : 15;
5318 int topreg
= reg
+ num
- 1;
5321 func (stream
, "{VPR}");
5323 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
5324 else if (topreg
> maxreg
)
5325 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
5326 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
5328 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
5329 reg_prefix
, topreg
);
5334 if (cond
!= COND_UNCOND
)
5335 is_unpredictable
= TRUE
;
5339 if (cond
!= COND_UNCOND
&& cp_num
== 9)
5340 is_unpredictable
= TRUE
;
5342 func (stream
, "%s", arm_conditional
[cond
]);
5346 /* Print a Cirrus/DSP shift immediate. */
5347 /* Immediates are 7bit signed ints with bits 0..3 in
5348 bits 0..3 of opcode and bits 4..6 in bits 5..7
5353 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
5355 /* Is ``imm'' a negative number? */
5359 func (stream
, "%d", imm
);
5367 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
5372 func (stream
, "FPSCR");
5375 func (stream
, "FPSCR_nzcvqc");
5378 func (stream
, "VPR");
5381 func (stream
, "P0");
5384 func (stream
, "FPCXTNS");
5387 func (stream
, "FPCXTS");
5390 func (stream
, "<invalid reg %lu>", regno
);
5397 switch (given
& 0x00408000)
5414 switch (given
& 0x00080080)
5426 func (stream
, _("<illegal precision>"));
5432 switch (given
& 0x00408000)
5450 switch (given
& 0x60)
5466 case '0': case '1': case '2': case '3': case '4':
5467 case '5': case '6': case '7': case '8': case '9':
5471 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
5477 is_unpredictable
= TRUE
;
5482 /* Eat the 'u' character. */
5486 is_unpredictable
= TRUE
;
5489 func (stream
, "%s", arm_regnames
[value
]);
5492 if (given
& (1 << 6))
5496 func (stream
, "d%ld", value
);
5501 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
5503 func (stream
, "q%ld", value
>> 1);
5506 func (stream
, "%ld", value
);
5507 value_in_comment
= value
;
5511 /* Converts immediate 8 bit back to float value. */
5512 unsigned floatVal
= (value
& 0x80) << 24
5513 | (value
& 0x3F) << 19
5514 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
5516 /* Quarter float have a maximum value of 31.0.
5517 Get floating point value multiplied by 1e7.
5518 The maximum value stays in limit of a 32-bit int. */
5520 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
5521 (16 + (value
& 0xF));
5523 if (!(decVal
% 1000000))
5524 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
5525 floatVal
, value
& 0x80 ? '-' : ' ',
5527 decVal
% 10000000 / 1000000);
5528 else if (!(decVal
% 10000))
5529 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
5530 floatVal
, value
& 0x80 ? '-' : ' ',
5532 decVal
% 10000000 / 10000);
5534 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
5535 floatVal
, value
& 0x80 ? '-' : ' ',
5536 decVal
/ 10000000, decVal
% 10000000);
5541 int from
= (given
& (1 << 7)) ? 32 : 16;
5542 func (stream
, "%ld", from
- value
);
5548 func (stream
, "#%s", arm_fp_const
[value
& 7]);
5550 func (stream
, "f%ld", value
);
5555 func (stream
, "%s", iwmmxt_wwnames
[value
]);
5557 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
5561 func (stream
, "%s", iwmmxt_regnames
[value
]);
5564 func (stream
, "%s", iwmmxt_cregnames
[value
]);
5568 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
5575 func (stream
, "eq");
5579 func (stream
, "vs");
5583 func (stream
, "ge");
5587 func (stream
, "gt");
5591 func (stream
, "??");
5599 func (stream
, "%c", *c
);
5603 if (value
== ((1ul << width
) - 1))
5604 func (stream
, "%c", *c
);
5607 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
5619 int single
= *c
++ == 'y';
5624 case '4': /* Sm pair */
5625 case '0': /* Sm, Dm */
5626 regno
= given
& 0x0000000f;
5630 regno
+= (given
>> 5) & 1;
5633 regno
+= ((given
>> 5) & 1) << 4;
5636 case '1': /* Sd, Dd */
5637 regno
= (given
>> 12) & 0x0000000f;
5641 regno
+= (given
>> 22) & 1;
5644 regno
+= ((given
>> 22) & 1) << 4;
5647 case '2': /* Sn, Dn */
5648 regno
= (given
>> 16) & 0x0000000f;
5652 regno
+= (given
>> 7) & 1;
5655 regno
+= ((given
>> 7) & 1) << 4;
5658 case '3': /* List */
5660 regno
= (given
>> 12) & 0x0000000f;
5664 regno
+= (given
>> 22) & 1;
5667 regno
+= ((given
>> 22) & 1) << 4;
5674 func (stream
, "%c%d", single
? 's' : 'd', regno
);
5678 int count
= given
& 0xff;
5685 func (stream
, "-%c%d",
5693 func (stream
, ", %c%d", single
? 's' : 'd',
5699 switch (given
& 0x00400100)
5701 case 0x00000000: func (stream
, "b"); break;
5702 case 0x00400000: func (stream
, "h"); break;
5703 case 0x00000100: func (stream
, "w"); break;
5704 case 0x00400100: func (stream
, "d"); break;
5712 /* given (20, 23) | given (0, 3) */
5713 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
5714 func (stream
, "%d", (int) value
);
5719 /* This is like the 'A' operator, except that if
5720 the width field "M" is zero, then the offset is
5721 *not* multiplied by four. */
5723 int offset
= given
& 0xff;
5724 int multiplier
= (given
& 0x00000100) ? 4 : 1;
5726 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
5730 value_in_comment
= offset
* multiplier
;
5731 if (NEGATIVE_BIT_SET
)
5732 value_in_comment
= - value_in_comment
;
5738 func (stream
, ", #%s%d]%s",
5739 NEGATIVE_BIT_SET
? "-" : "",
5740 offset
* multiplier
,
5741 WRITEBACK_BIT_SET
? "!" : "");
5743 func (stream
, "], #%s%d",
5744 NEGATIVE_BIT_SET
? "-" : "",
5745 offset
* multiplier
);
5754 int imm4
= (given
>> 4) & 0xf;
5755 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
5756 int ubit
= ! NEGATIVE_BIT_SET
;
5757 const char *rm
= arm_regnames
[given
& 0xf];
5758 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
5764 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
5766 func (stream
, ", lsl #%d", imm4
);
5773 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
5775 func (stream
, ", lsl #%d", imm4
);
5777 if (puw_bits
== 5 || puw_bits
== 7)
5782 func (stream
, "INVALID");
5790 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
5791 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
5800 func (stream
, "%c", *c
);
5803 if (value_in_comment
> 32 || value_in_comment
< -16)
5804 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
5806 if (is_unpredictable
)
5807 func (stream
, UNPREDICTABLE_INSTRUCTION
);
5814 /* Decodes and prints ARM addressing modes. Returns the offset
5815 used in the address, if any, if it is worthwhile printing the
5816 offset as a hexadecimal value in a comment at the end of the
5817 line of disassembly. */
5820 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
5822 void *stream
= info
->stream
;
5823 fprintf_ftype func
= info
->fprintf_func
;
5826 if (((given
& 0x000f0000) == 0x000f0000)
5827 && ((given
& 0x02000000) == 0))
5829 offset
= given
& 0xfff;
5831 func (stream
, "[pc");
5835 /* Pre-indexed. Elide offset of positive zero when
5837 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
5838 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
5840 if (NEGATIVE_BIT_SET
)
5845 /* Cope with the possibility of write-back
5846 being used. Probably a very dangerous thing
5847 for the programmer to do, but who are we to
5849 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
5851 else /* Post indexed. */
5853 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
5855 /* Ie ignore the offset. */
5859 func (stream
, "\t; ");
5860 info
->print_address_func (offset
, info
);
5865 func (stream
, "[%s",
5866 arm_regnames
[(given
>> 16) & 0xf]);
5870 if ((given
& 0x02000000) == 0)
5872 /* Elide offset of positive zero when non-writeback. */
5873 offset
= given
& 0xfff;
5874 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
5875 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
5879 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
5880 arm_decode_shift (given
, func
, stream
, TRUE
);
5883 func (stream
, "]%s",
5884 WRITEBACK_BIT_SET
? "!" : "");
5888 if ((given
& 0x02000000) == 0)
5890 /* Always show offset. */
5891 offset
= given
& 0xfff;
5892 func (stream
, "], #%s%d",
5893 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
5897 func (stream
, "], %s",
5898 NEGATIVE_BIT_SET
? "-" : "");
5899 arm_decode_shift (given
, func
, stream
, TRUE
);
5902 if (NEGATIVE_BIT_SET
)
5906 return (signed long) offset
;
5909 /* Print one neon instruction on INFO->STREAM.
5910 Return TRUE if the instuction matched, FALSE if this is not a
5911 recognised neon instruction. */
5914 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
5916 const struct opcode32
*insn
;
5917 void *stream
= info
->stream
;
5918 fprintf_ftype func
= info
->fprintf_func
;
5922 if ((given
& 0xef000000) == 0xef000000)
5924 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
5925 unsigned long bit28
= given
& (1 << 28);
5927 given
&= 0x00ffffff;
5929 given
|= 0xf3000000;
5931 given
|= 0xf2000000;
5933 else if ((given
& 0xff000000) == 0xf9000000)
5934 given
^= 0xf9000000 ^ 0xf4000000;
5935 /* vdup is also a valid neon instruction. */
5936 else if ((given
& 0xff910f5f) != 0xee800b10)
5940 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
5942 if ((given
& insn
->mask
) == insn
->value
)
5944 signed long value_in_comment
= 0;
5945 bfd_boolean is_unpredictable
= FALSE
;
5948 for (c
= insn
->assembler
; *c
; c
++)
5955 func (stream
, "%%");
5959 if (thumb
&& ifthen_state
)
5960 is_unpredictable
= TRUE
;
5964 if (thumb
&& ifthen_state
)
5965 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
5970 static const unsigned char enc
[16] =
5972 0x4, 0x14, /* st4 0,1 */
5984 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
5985 int rn
= ((given
>> 16) & 0xf);
5986 int rm
= ((given
>> 0) & 0xf);
5987 int align
= ((given
>> 4) & 0x3);
5988 int type
= ((given
>> 8) & 0xf);
5989 int n
= enc
[type
] & 0xf;
5990 int stride
= (enc
[type
] >> 4) + 1;
5995 for (ix
= 0; ix
!= n
; ix
++)
5996 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
5998 func (stream
, "d%d", rd
);
6000 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
6001 func (stream
, "}, [%s", arm_regnames
[rn
]);
6003 func (stream
, " :%d", 32 << align
);
6008 func (stream
, ", %s", arm_regnames
[rm
]);
6014 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
6015 int rn
= ((given
>> 16) & 0xf);
6016 int rm
= ((given
>> 0) & 0xf);
6017 int idx_align
= ((given
>> 4) & 0xf);
6019 int size
= ((given
>> 10) & 0x3);
6020 int idx
= idx_align
>> (size
+ 1);
6021 int length
= ((given
>> 8) & 3) + 1;
6025 if (length
> 1 && size
> 0)
6026 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
6032 int amask
= (1 << size
) - 1;
6033 if ((idx_align
& (1 << size
)) != 0)
6037 if ((idx_align
& amask
) == amask
)
6039 else if ((idx_align
& amask
) != 0)
6046 if (size
== 2 && (idx_align
& 2) != 0)
6048 align
= (idx_align
& 1) ? 16 << size
: 0;
6052 if ((size
== 2 && (idx_align
& 3) != 0)
6053 || (idx_align
& 1) != 0)
6060 if ((idx_align
& 3) == 3)
6062 align
= (idx_align
& 3) * 64;
6065 align
= (idx_align
& 1) ? 32 << size
: 0;
6073 for (i
= 0; i
< length
; i
++)
6074 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
6075 rd
+ i
* stride
, idx
);
6076 func (stream
, "}, [%s", arm_regnames
[rn
]);
6078 func (stream
, " :%d", align
);
6083 func (stream
, ", %s", arm_regnames
[rm
]);
6089 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
6090 int rn
= ((given
>> 16) & 0xf);
6091 int rm
= ((given
>> 0) & 0xf);
6092 int align
= ((given
>> 4) & 0x1);
6093 int size
= ((given
>> 6) & 0x3);
6094 int type
= ((given
>> 8) & 0x3);
6096 int stride
= ((given
>> 5) & 0x1);
6099 if (stride
&& (n
== 1))
6106 for (ix
= 0; ix
!= n
; ix
++)
6107 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
6109 func (stream
, "d%d[]", rd
);
6111 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
6112 func (stream
, "}, [%s", arm_regnames
[rn
]);
6115 align
= (8 * (type
+ 1)) << size
;
6117 align
= (size
> 1) ? align
>> 1 : align
;
6118 if (type
== 2 || (type
== 0 && !size
))
6119 func (stream
, " :<bad align %d>", align
);
6121 func (stream
, " :%d", align
);
6127 func (stream
, ", %s", arm_regnames
[rm
]);
6133 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
6134 int size
= (given
>> 20) & 3;
6135 int reg
= raw_reg
& ((4 << size
) - 1);
6136 int ix
= raw_reg
>> size
>> 2;
6138 func (stream
, "d%d[%d]", reg
, ix
);
6143 /* Neon encoded constant for mov, mvn, vorr, vbic. */
6146 int cmode
= (given
>> 8) & 0xf;
6147 int op
= (given
>> 5) & 0x1;
6148 unsigned long value
= 0, hival
= 0;
6153 bits
|= ((given
>> 24) & 1) << 7;
6154 bits
|= ((given
>> 16) & 7) << 4;
6155 bits
|= ((given
>> 0) & 15) << 0;
6159 shift
= (cmode
>> 1) & 3;
6160 value
= (unsigned long) bits
<< (8 * shift
);
6163 else if (cmode
< 12)
6165 shift
= (cmode
>> 1) & 1;
6166 value
= (unsigned long) bits
<< (8 * shift
);
6169 else if (cmode
< 14)
6171 shift
= (cmode
& 1) + 1;
6172 value
= (unsigned long) bits
<< (8 * shift
);
6173 value
|= (1ul << (8 * shift
)) - 1;
6176 else if (cmode
== 14)
6180 /* Bit replication into bytes. */
6186 for (ix
= 7; ix
>= 0; ix
--)
6188 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
6190 value
= (value
<< 8) | mask
;
6192 hival
= (hival
<< 8) | mask
;
6198 /* Byte replication. */
6199 value
= (unsigned long) bits
;
6205 /* Floating point encoding. */
6208 value
= (unsigned long) (bits
& 0x7f) << 19;
6209 value
|= (unsigned long) (bits
& 0x80) << 24;
6210 tmp
= bits
& 0x40 ? 0x3c : 0x40;
6211 value
|= (unsigned long) tmp
<< 24;
6217 func (stream
, "<illegal constant %.8x:%x:%x>",
6225 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
6229 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
6235 unsigned char valbytes
[4];
6238 /* Do this a byte at a time so we don't have to
6239 worry about the host's endianness. */
6240 valbytes
[0] = value
& 0xff;
6241 valbytes
[1] = (value
>> 8) & 0xff;
6242 valbytes
[2] = (value
>> 16) & 0xff;
6243 valbytes
[3] = (value
>> 24) & 0xff;
6245 floatformat_to_double
6246 (& floatformat_ieee_single_little
, valbytes
,
6249 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
6253 func (stream
, "#%ld\t; 0x%.8lx",
6254 (long) (((value
& 0x80000000L
) != 0)
6255 ? value
| ~0xffffffffL
: value
),
6260 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
6271 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
6272 int num
= (given
>> 8) & 0x3;
6275 func (stream
, "{d%d}", regno
);
6276 else if (num
+ regno
>= 32)
6277 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
6279 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
6284 case '0': case '1': case '2': case '3': case '4':
6285 case '5': case '6': case '7': case '8': case '9':
6288 unsigned long value
;
6290 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
6295 func (stream
, "%s", arm_regnames
[value
]);
6298 func (stream
, "%ld", value
);
6299 value_in_comment
= value
;
6302 func (stream
, "%ld", (1ul << width
) - value
);
6308 /* Various width encodings. */
6310 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
6315 if (*c
>= '0' && *c
<= '9')
6317 else if (*c
>= 'a' && *c
<= 'f')
6318 limit
= *c
- 'a' + 10;
6324 if (value
< low
|| value
> high
)
6325 func (stream
, "<illegal width %d>", base
<< value
);
6327 func (stream
, "%d", base
<< value
);
6331 if (given
& (1 << 6))
6335 func (stream
, "d%ld", value
);
6340 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
6342 func (stream
, "q%ld", value
>> 1);
6348 func (stream
, "%c", *c
);
6352 if (value
== ((1ul << width
) - 1))
6353 func (stream
, "%c", *c
);
6356 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
6370 func (stream
, "%c", *c
);
6373 if (value_in_comment
> 32 || value_in_comment
< -16)
6374 func (stream
, "\t; 0x%lx", value_in_comment
);
6376 if (is_unpredictable
)
6377 func (stream
, UNPREDICTABLE_INSTRUCTION
);
6385 /* Print one mve instruction on INFO->STREAM.
6386 Return TRUE if the instuction matched, FALSE if this is not a
6387 recognised mve instruction. */
6390 print_insn_mve (struct disassemble_info
*info
, long given
)
6392 const struct mopcode32
*insn
;
6393 void *stream
= info
->stream
;
6394 fprintf_ftype func
= info
->fprintf_func
;
6396 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
6398 if (((given
& insn
->mask
) == insn
->value
)
6399 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
6401 signed long value_in_comment
= 0;
6402 bfd_boolean is_unpredictable
= FALSE
;
6403 bfd_boolean is_undefined
= FALSE
;
6405 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
6406 enum mve_undefined undefined_cond
= UNDEF_NONE
;
6408 /* Most vector mve instruction are illegal in a it block.
6409 There are a few exceptions; check for them. */
6410 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
6412 is_unpredictable
= TRUE
;
6413 unpredictable_cond
= UNPRED_IT_BLOCK
;
6415 else if (is_mve_unpredictable (given
, insn
->mve_op
,
6416 &unpredictable_cond
))
6417 is_unpredictable
= TRUE
;
6419 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
6420 is_undefined
= TRUE
;
6422 for (c
= insn
->assembler
; *c
; c
++)
6429 func (stream
, "%%");
6433 /* Don't print anything for '+' as it is implied. */
6434 if (arm_decode_field (given
, 23, 23) == 0)
6440 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
6444 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
6449 long mve_mask
= mve_extract_pred_mask (given
);
6450 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
6455 print_vec_condition (info
, given
, insn
->mve_op
);
6459 if (arm_decode_field (given
, 0, 0) == 1)
6462 = arm_decode_field (given
, 4, 4)
6463 | (arm_decode_field (given
, 6, 6) << 1);
6465 func (stream
, ", uxtw #%lu", size
);
6471 if (arm_decode_field (given
, 28, 28) == 0)
6479 print_instruction_predicate (info
);
6483 if (arm_decode_field (given
, 21, 21) == 1)
6488 print_mve_register_blocks (info
, given
, insn
->mve_op
);
6491 case '0': case '1': case '2': case '3': case '4':
6492 case '5': case '6': case '7': case '8': case '9':
6495 unsigned long value
;
6497 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
6503 is_unpredictable
= TRUE
;
6504 else if (value
== 15)
6505 func (stream
, "zr");
6507 func (stream
, "%s", arm_regnames
[value
]);
6510 print_mve_size (info
,
6517 = arm_decode_field (given
, 0, 6);
6518 unsigned long mod_imm
= imm
;
6520 switch (insn
->mve_op
)
6522 case MVE_VLDRW_GATHER_T5
:
6523 case MVE_VSTRW_SCATTER_T5
:
6524 mod_imm
= mod_imm
<< 2;
6526 case MVE_VSTRD_SCATTER_T6
:
6527 case MVE_VLDRD_GATHER_T6
:
6528 mod_imm
= mod_imm
<< 3;
6535 func (stream
, "%lu", mod_imm
);
6539 func (stream
, "%s", arm_regnames
[value
]);
6542 func (stream
, "%ld", value
);
6543 value_in_comment
= value
;
6547 func (stream
, "<illegal reg q%ld.5>", value
);
6549 func (stream
, "q%ld", value
);
6561 func (stream
, "%c", *c
);
6564 if (value_in_comment
> 32 || value_in_comment
< -16)
6565 func (stream
, "\t; 0x%lx", value_in_comment
);
6567 if (is_unpredictable
)
6568 print_mve_unpredictable (info
, unpredictable_cond
);
6571 print_mve_undefined (info
, undefined_cond
);
6573 if ((vpt_block_state
.in_vpt_block
== FALSE
)
6575 && (is_vpt_instruction (given
) == TRUE
))
6576 mark_inside_vpt_block (given
);
6577 else if (vpt_block_state
.in_vpt_block
== TRUE
)
6578 update_vpt_block_state ();
6587 /* Return the name of a v7A special register. */
6590 banked_regname (unsigned reg
)
6594 case 15: return "CPSR";
6595 case 32: return "R8_usr";
6596 case 33: return "R9_usr";
6597 case 34: return "R10_usr";
6598 case 35: return "R11_usr";
6599 case 36: return "R12_usr";
6600 case 37: return "SP_usr";
6601 case 38: return "LR_usr";
6602 case 40: return "R8_fiq";
6603 case 41: return "R9_fiq";
6604 case 42: return "R10_fiq";
6605 case 43: return "R11_fiq";
6606 case 44: return "R12_fiq";
6607 case 45: return "SP_fiq";
6608 case 46: return "LR_fiq";
6609 case 48: return "LR_irq";
6610 case 49: return "SP_irq";
6611 case 50: return "LR_svc";
6612 case 51: return "SP_svc";
6613 case 52: return "LR_abt";
6614 case 53: return "SP_abt";
6615 case 54: return "LR_und";
6616 case 55: return "SP_und";
6617 case 60: return "LR_mon";
6618 case 61: return "SP_mon";
6619 case 62: return "ELR_hyp";
6620 case 63: return "SP_hyp";
6621 case 79: return "SPSR";
6622 case 110: return "SPSR_fiq";
6623 case 112: return "SPSR_irq";
6624 case 114: return "SPSR_svc";
6625 case 116: return "SPSR_abt";
6626 case 118: return "SPSR_und";
6627 case 124: return "SPSR_mon";
6628 case 126: return "SPSR_hyp";
6629 default: return NULL
;
6633 /* Return the name of the DMB/DSB option. */
6635 data_barrier_option (unsigned option
)
6637 switch (option
& 0xf)
6639 case 0xf: return "sy";
6640 case 0xe: return "st";
6641 case 0xd: return "ld";
6642 case 0xb: return "ish";
6643 case 0xa: return "ishst";
6644 case 0x9: return "ishld";
6645 case 0x7: return "un";
6646 case 0x6: return "unst";
6647 case 0x5: return "nshld";
6648 case 0x3: return "osh";
6649 case 0x2: return "oshst";
6650 case 0x1: return "oshld";
6651 default: return NULL
;
6655 /* Print one ARM instruction from PC on INFO->STREAM. */
6658 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
6660 const struct opcode32
*insn
;
6661 void *stream
= info
->stream
;
6662 fprintf_ftype func
= info
->fprintf_func
;
6663 struct arm_private_data
*private_data
= info
->private_data
;
6665 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
6668 if (print_insn_neon (info
, given
, FALSE
))
6671 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
6673 if ((given
& insn
->mask
) != insn
->value
)
6676 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
6679 /* Special case: an instruction with all bits set in the condition field
6680 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
6681 or by the catchall at the end of the table. */
6682 if ((given
& 0xF0000000) != 0xF0000000
6683 || (insn
->mask
& 0xF0000000) == 0xF0000000
6684 || (insn
->mask
== 0 && insn
->value
== 0))
6686 unsigned long u_reg
= 16;
6687 unsigned long U_reg
= 16;
6688 bfd_boolean is_unpredictable
= FALSE
;
6689 signed long value_in_comment
= 0;
6692 for (c
= insn
->assembler
; *c
; c
++)
6696 bfd_boolean allow_unpredictable
= FALSE
;
6701 func (stream
, "%%");
6705 value_in_comment
= print_arm_address (pc
, info
, given
);
6709 /* Set P address bit and use normal address
6710 printing routine. */
6711 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
6715 allow_unpredictable
= TRUE
;
6718 if ((given
& 0x004f0000) == 0x004f0000)
6720 /* PC relative with immediate offset. */
6721 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
6725 /* Elide positive zero offset. */
6726 if (offset
|| NEGATIVE_BIT_SET
)
6727 func (stream
, "[pc, #%s%d]\t; ",
6728 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
6730 func (stream
, "[pc]\t; ");
6731 if (NEGATIVE_BIT_SET
)
6733 info
->print_address_func (offset
+ pc
+ 8, info
);
6737 /* Always show the offset. */
6738 func (stream
, "[pc], #%s%d",
6739 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
6740 if (! allow_unpredictable
)
6741 is_unpredictable
= TRUE
;
6746 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
6748 func (stream
, "[%s",
6749 arm_regnames
[(given
>> 16) & 0xf]);
6753 if (IMMEDIATE_BIT_SET
)
6755 /* Elide offset for non-writeback
6757 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
6759 func (stream
, ", #%s%d",
6760 NEGATIVE_BIT_SET
? "-" : "", offset
);
6762 if (NEGATIVE_BIT_SET
)
6765 value_in_comment
= offset
;
6769 /* Register Offset or Register Pre-Indexed. */
6770 func (stream
, ", %s%s",
6771 NEGATIVE_BIT_SET
? "-" : "",
6772 arm_regnames
[given
& 0xf]);
6774 /* Writing back to the register that is the source/
6775 destination of the load/store is unpredictable. */
6776 if (! allow_unpredictable
6777 && WRITEBACK_BIT_SET
6778 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
6779 is_unpredictable
= TRUE
;
6782 func (stream
, "]%s",
6783 WRITEBACK_BIT_SET
? "!" : "");
6787 if (IMMEDIATE_BIT_SET
)
6789 /* Immediate Post-indexed. */
6790 /* PR 10924: Offset must be printed, even if it is zero. */
6791 func (stream
, "], #%s%d",
6792 NEGATIVE_BIT_SET
? "-" : "", offset
);
6793 if (NEGATIVE_BIT_SET
)
6795 value_in_comment
= offset
;
6799 /* Register Post-indexed. */
6800 func (stream
, "], %s%s",
6801 NEGATIVE_BIT_SET
? "-" : "",
6802 arm_regnames
[given
& 0xf]);
6804 /* Writing back to the register that is the source/
6805 destination of the load/store is unpredictable. */
6806 if (! allow_unpredictable
6807 && (given
& 0xf) == ((given
>> 12) & 0xf))
6808 is_unpredictable
= TRUE
;
6811 if (! allow_unpredictable
)
6813 /* Writeback is automatically implied by post- addressing.
6814 Setting the W bit is unnecessary and ARM specify it as
6815 being unpredictable. */
6816 if (WRITEBACK_BIT_SET
6817 /* Specifying the PC register as the post-indexed
6818 registers is also unpredictable. */
6819 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
6820 is_unpredictable
= TRUE
;
6828 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
6829 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
6834 if (((given
>> 28) & 0xf) != 0xe)
6836 arm_conditional
[(given
>> 28) & 0xf]);
6845 for (reg
= 0; reg
< 16; reg
++)
6846 if ((given
& (1 << reg
)) != 0)
6849 func (stream
, ", ");
6851 func (stream
, "%s", arm_regnames
[reg
]);
6855 is_unpredictable
= TRUE
;
6860 arm_decode_shift (given
, func
, stream
, FALSE
);
6864 if ((given
& 0x02000000) != 0)
6866 unsigned int rotate
= (given
& 0xf00) >> 7;
6867 unsigned int immed
= (given
& 0xff);
6870 a
= (((immed
<< (32 - rotate
))
6871 | (immed
>> rotate
)) & 0xffffffff);
6872 /* If there is another encoding with smaller rotate,
6873 the rotate should be specified directly. */
6874 for (i
= 0; i
< 32; i
+= 2)
6875 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
6879 func (stream
, "#%d, %d", immed
, rotate
);
6881 func (stream
, "#%d", a
);
6882 value_in_comment
= a
;
6885 arm_decode_shift (given
, func
, stream
, TRUE
);
6889 if ((given
& 0x0000f000) == 0x0000f000)
6891 arm_feature_set arm_ext_v6
=
6892 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
6894 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
6895 mechanism for setting PSR flag bits. They are
6896 obsolete in V6 onwards. */
6897 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
6901 is_unpredictable
= TRUE
;
6906 if ((given
& 0x01200000) == 0x00200000)
6912 int offset
= given
& 0xff;
6914 value_in_comment
= offset
* 4;
6915 if (NEGATIVE_BIT_SET
)
6916 value_in_comment
= - value_in_comment
;
6918 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
6923 func (stream
, ", #%d]%s",
6924 (int) value_in_comment
,
6925 WRITEBACK_BIT_SET
? "!" : "");
6933 if (WRITEBACK_BIT_SET
)
6936 func (stream
, ", #%d", (int) value_in_comment
);
6940 func (stream
, ", {%d}", (int) offset
);
6941 value_in_comment
= offset
;
6948 /* Print ARM V5 BLX(1) address: pc+25 bits. */
6953 if (! NEGATIVE_BIT_SET
)
6954 /* Is signed, hi bits should be ones. */
6955 offset
= (-1) ^ 0x00ffffff;
6957 /* Offset is (SignExtend(offset field)<<2). */
6958 offset
+= given
& 0x00ffffff;
6960 address
= offset
+ pc
+ 8;
6962 if (given
& 0x01000000)
6963 /* H bit allows addressing to 2-byte boundaries. */
6966 info
->print_address_func (address
, info
);
6971 if ((given
& 0x02000200) == 0x200)
6974 unsigned sysm
= (given
& 0x004f0000) >> 16;
6976 sysm
|= (given
& 0x300) >> 4;
6977 name
= banked_regname (sysm
);
6980 func (stream
, "%s", name
);
6982 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
6986 func (stream
, "%cPSR_",
6987 (given
& 0x00400000) ? 'S' : 'C');
6988 if (given
& 0x80000)
6990 if (given
& 0x40000)
6992 if (given
& 0x20000)
6994 if (given
& 0x10000)
7000 if ((given
& 0xf0) == 0x60)
7002 switch (given
& 0xf)
7004 case 0xf: func (stream
, "sy"); break;
7006 func (stream
, "#%d", (int) given
& 0xf);
7012 const char * opt
= data_barrier_option (given
& 0xf);
7014 func (stream
, "%s", opt
);
7016 func (stream
, "#%d", (int) given
& 0xf);
7020 case '0': case '1': case '2': case '3': case '4':
7021 case '5': case '6': case '7': case '8': case '9':
7024 unsigned long value
;
7026 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7032 is_unpredictable
= TRUE
;
7036 /* We want register + 1 when decoding T. */
7042 /* Eat the 'u' character. */
7046 is_unpredictable
= TRUE
;
7051 /* Eat the 'U' character. */
7055 is_unpredictable
= TRUE
;
7058 func (stream
, "%s", arm_regnames
[value
]);
7061 func (stream
, "%ld", value
);
7062 value_in_comment
= value
;
7065 func (stream
, "%ld", value
* 8);
7066 value_in_comment
= value
* 8;
7069 func (stream
, "%ld", value
+ 1);
7070 value_in_comment
= value
+ 1;
7073 func (stream
, "0x%08lx", value
);
7075 /* Some SWI instructions have special
7077 if ((given
& 0x0fffffff) == 0x0FF00000)
7078 func (stream
, "\t; IMB");
7079 else if ((given
& 0x0fffffff) == 0x0FF00001)
7080 func (stream
, "\t; IMBRange");
7083 func (stream
, "%01lx", value
& 0xf);
7084 value_in_comment
= value
;
7089 func (stream
, "%c", *c
);
7093 if (value
== ((1ul << width
) - 1))
7094 func (stream
, "%c", *c
);
7097 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7110 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
7111 func (stream
, "%d", imm
);
7112 value_in_comment
= imm
;
7117 /* LSB and WIDTH fields of BFI or BFC. The machine-
7118 language instruction encodes LSB and MSB. */
7120 long msb
= (given
& 0x001f0000) >> 16;
7121 long lsb
= (given
& 0x00000f80) >> 7;
7122 long w
= msb
- lsb
+ 1;
7125 func (stream
, "#%lu, #%lu", lsb
, w
);
7127 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
7132 /* Get the PSR/banked register name. */
7135 unsigned sysm
= (given
& 0x004f0000) >> 16;
7137 sysm
|= (given
& 0x300) >> 4;
7138 name
= banked_regname (sysm
);
7141 func (stream
, "%s", name
);
7143 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
7148 /* 16-bit unsigned immediate from a MOVT or MOVW
7149 instruction, encoded in bits 0:11 and 15:19. */
7151 long hi
= (given
& 0x000f0000) >> 4;
7152 long lo
= (given
& 0x00000fff);
7153 long imm16
= hi
| lo
;
7155 func (stream
, "#%lu", imm16
);
7156 value_in_comment
= imm16
;
7165 func (stream
, "%c", *c
);
7168 if (value_in_comment
> 32 || value_in_comment
< -16)
7169 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
7171 if (is_unpredictable
)
7172 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7177 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
7181 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
7184 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
7186 const struct opcode16
*insn
;
7187 void *stream
= info
->stream
;
7188 fprintf_ftype func
= info
->fprintf_func
;
7190 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
7191 if ((given
& insn
->mask
) == insn
->value
)
7193 signed long value_in_comment
= 0;
7194 const char *c
= insn
->assembler
;
7203 func (stream
, "%c", *c
);
7210 func (stream
, "%%");
7215 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7220 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7229 ifthen_next_state
= given
& 0xff;
7230 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
7231 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
7232 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
7237 if (ifthen_next_state
)
7238 func (stream
, "\t; unpredictable branch in IT block\n");
7243 func (stream
, "\t; unpredictable <IT:%s>",
7244 arm_conditional
[IFTHEN_COND
]);
7251 reg
= (given
>> 3) & 0x7;
7252 if (given
& (1 << 6))
7255 func (stream
, "%s", arm_regnames
[reg
]);
7264 if (given
& (1 << 7))
7267 func (stream
, "%s", arm_regnames
[reg
]);
7272 if (given
& (1 << 8))
7276 if (*c
== 'O' && (given
& (1 << 8)))
7286 /* It would be nice if we could spot
7287 ranges, and generate the rS-rE format: */
7288 for (reg
= 0; (reg
< 8); reg
++)
7289 if ((given
& (1 << reg
)) != 0)
7292 func (stream
, ", ");
7294 func (stream
, "%s", arm_regnames
[reg
]);
7300 func (stream
, ", ");
7302 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
7308 func (stream
, ", ");
7309 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
7317 /* Print writeback indicator for a LDMIA. We are doing a
7318 writeback if the base register is not in the register
7320 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
7325 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
7327 bfd_vma address
= (pc
+ 4
7328 + ((given
& 0x00f8) >> 2)
7329 + ((given
& 0x0200) >> 3));
7330 info
->print_address_func (address
, info
);
7335 /* Right shift immediate -- bits 6..10; 1-31 print
7336 as themselves, 0 prints as 32. */
7338 long imm
= (given
& 0x07c0) >> 6;
7341 func (stream
, "#%ld", imm
);
7345 case '0': case '1': case '2': case '3': case '4':
7346 case '5': case '6': case '7': case '8': case '9':
7348 int bitstart
= *c
++ - '0';
7351 while (*c
>= '0' && *c
<= '9')
7352 bitstart
= (bitstart
* 10) + *c
++ - '0';
7361 while (*c
>= '0' && *c
<= '9')
7362 bitend
= (bitend
* 10) + *c
++ - '0';
7365 reg
= given
>> bitstart
;
7366 reg
&= (2 << (bitend
- bitstart
)) - 1;
7371 func (stream
, "%s", arm_regnames
[reg
]);
7375 func (stream
, "%ld", (long) reg
);
7376 value_in_comment
= reg
;
7380 func (stream
, "%ld", (long) (reg
<< 1));
7381 value_in_comment
= reg
<< 1;
7385 func (stream
, "%ld", (long) (reg
<< 2));
7386 value_in_comment
= reg
<< 2;
7390 /* PC-relative address -- the bottom two
7391 bits of the address are dropped
7392 before the calculation. */
7393 info
->print_address_func
7394 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
7395 value_in_comment
= 0;
7399 func (stream
, "0x%04lx", (long) reg
);
7403 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
7404 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
7405 value_in_comment
= 0;
7409 func (stream
, "%s", arm_conditional
[reg
]);
7420 if ((given
& (1 << bitstart
)) != 0)
7421 func (stream
, "%c", *c
);
7426 if ((given
& (1 << bitstart
)) != 0)
7427 func (stream
, "%c", *c
++);
7429 func (stream
, "%c", *++c
);
7443 if (value_in_comment
> 32 || value_in_comment
< -16)
7444 func (stream
, "\t; 0x%lx", value_in_comment
);
7449 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
7453 /* Return the name of an V7M special register. */
7456 psr_name (int regno
)
7460 case 0x0: return "APSR";
7461 case 0x1: return "IAPSR";
7462 case 0x2: return "EAPSR";
7463 case 0x3: return "PSR";
7464 case 0x5: return "IPSR";
7465 case 0x6: return "EPSR";
7466 case 0x7: return "IEPSR";
7467 case 0x8: return "MSP";
7468 case 0x9: return "PSP";
7469 case 0xa: return "MSPLIM";
7470 case 0xb: return "PSPLIM";
7471 case 0x10: return "PRIMASK";
7472 case 0x11: return "BASEPRI";
7473 case 0x12: return "BASEPRI_MAX";
7474 case 0x13: return "FAULTMASK";
7475 case 0x14: return "CONTROL";
7476 case 0x88: return "MSP_NS";
7477 case 0x89: return "PSP_NS";
7478 case 0x8a: return "MSPLIM_NS";
7479 case 0x8b: return "PSPLIM_NS";
7480 case 0x90: return "PRIMASK_NS";
7481 case 0x91: return "BASEPRI_NS";
7482 case 0x93: return "FAULTMASK_NS";
7483 case 0x94: return "CONTROL_NS";
7484 case 0x98: return "SP_NS";
7485 default: return "<unknown>";
7489 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
7492 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
7494 const struct opcode32
*insn
;
7495 void *stream
= info
->stream
;
7496 fprintf_ftype func
= info
->fprintf_func
;
7497 bfd_boolean is_mve
= is_mve_architecture (info
);
7499 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
7502 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
7505 if (is_mve
&& print_insn_mve (info
, given
))
7508 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
7509 if ((given
& insn
->mask
) == insn
->value
)
7511 bfd_boolean is_clrm
= FALSE
;
7512 bfd_boolean is_unpredictable
= FALSE
;
7513 signed long value_in_comment
= 0;
7514 const char *c
= insn
->assembler
;
7520 func (stream
, "%c", *c
);
7527 func (stream
, "%%");
7532 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7536 if (ifthen_next_state
)
7537 func (stream
, "\t; unpredictable branch in IT block\n");
7542 func (stream
, "\t; unpredictable <IT:%s>",
7543 arm_conditional
[IFTHEN_COND
]);
7548 unsigned int imm12
= 0;
7550 imm12
|= (given
& 0x000000ffu
);
7551 imm12
|= (given
& 0x00007000u
) >> 4;
7552 imm12
|= (given
& 0x04000000u
) >> 15;
7553 func (stream
, "#%u", imm12
);
7554 value_in_comment
= imm12
;
7560 unsigned int bits
= 0, imm
, imm8
, mod
;
7562 bits
|= (given
& 0x000000ffu
);
7563 bits
|= (given
& 0x00007000u
) >> 4;
7564 bits
|= (given
& 0x04000000u
) >> 15;
7565 imm8
= (bits
& 0x0ff);
7566 mod
= (bits
& 0xf00) >> 8;
7569 case 0: imm
= imm8
; break;
7570 case 1: imm
= ((imm8
<< 16) | imm8
); break;
7571 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
7572 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
7574 mod
= (bits
& 0xf80) >> 7;
7575 imm8
= (bits
& 0x07f) | 0x80;
7576 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
7578 func (stream
, "#%u", imm
);
7579 value_in_comment
= imm
;
7585 unsigned int imm
= 0;
7587 imm
|= (given
& 0x000000ffu
);
7588 imm
|= (given
& 0x00007000u
) >> 4;
7589 imm
|= (given
& 0x04000000u
) >> 15;
7590 imm
|= (given
& 0x000f0000u
) >> 4;
7591 func (stream
, "#%u", imm
);
7592 value_in_comment
= imm
;
7598 unsigned int imm
= 0;
7600 imm
|= (given
& 0x000f0000u
) >> 16;
7601 imm
|= (given
& 0x00000ff0u
) >> 0;
7602 imm
|= (given
& 0x0000000fu
) << 12;
7603 func (stream
, "#%u", imm
);
7604 value_in_comment
= imm
;
7610 unsigned int imm
= 0;
7612 imm
|= (given
& 0x000f0000u
) >> 4;
7613 imm
|= (given
& 0x00000fffu
) >> 0;
7614 func (stream
, "#%u", imm
);
7615 value_in_comment
= imm
;
7621 unsigned int imm
= 0;
7623 imm
|= (given
& 0x00000fffu
);
7624 imm
|= (given
& 0x000f0000u
) >> 4;
7625 func (stream
, "#%u", imm
);
7626 value_in_comment
= imm
;
7632 unsigned int reg
= (given
& 0x0000000fu
);
7633 unsigned int stp
= (given
& 0x00000030u
) >> 4;
7634 unsigned int imm
= 0;
7635 imm
|= (given
& 0x000000c0u
) >> 6;
7636 imm
|= (given
& 0x00007000u
) >> 10;
7638 func (stream
, "%s", arm_regnames
[reg
]);
7643 func (stream
, ", lsl #%u", imm
);
7649 func (stream
, ", lsr #%u", imm
);
7655 func (stream
, ", asr #%u", imm
);
7660 func (stream
, ", rrx");
7662 func (stream
, ", ror #%u", imm
);
7669 unsigned int Rn
= (given
& 0x000f0000) >> 16;
7670 unsigned int U
= ! NEGATIVE_BIT_SET
;
7671 unsigned int op
= (given
& 0x00000f00) >> 8;
7672 unsigned int i12
= (given
& 0x00000fff);
7673 unsigned int i8
= (given
& 0x000000ff);
7674 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
7677 func (stream
, "[%s", arm_regnames
[Rn
]);
7678 if (U
) /* 12-bit positive immediate offset. */
7682 value_in_comment
= offset
;
7684 else if (Rn
== 15) /* 12-bit negative immediate offset. */
7685 offset
= - (int) i12
;
7686 else if (op
== 0x0) /* Shifted register offset. */
7688 unsigned int Rm
= (i8
& 0x0f);
7689 unsigned int sh
= (i8
& 0x30) >> 4;
7691 func (stream
, ", %s", arm_regnames
[Rm
]);
7693 func (stream
, ", lsl #%u", sh
);
7699 case 0xE: /* 8-bit positive immediate offset. */
7703 case 0xC: /* 8-bit negative immediate offset. */
7707 case 0xF: /* 8-bit + preindex with wb. */
7712 case 0xD: /* 8-bit - preindex with wb. */
7717 case 0xB: /* 8-bit + postindex. */
7722 case 0x9: /* 8-bit - postindex. */
7728 func (stream
, ", <undefined>]");
7733 func (stream
, "], #%d", (int) offset
);
7737 func (stream
, ", #%d", (int) offset
);
7738 func (stream
, writeback
? "]!" : "]");
7743 func (stream
, "\t; ");
7744 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
7752 unsigned int U
= ! NEGATIVE_BIT_SET
;
7753 unsigned int W
= WRITEBACK_BIT_SET
;
7754 unsigned int Rn
= (given
& 0x000f0000) >> 16;
7755 unsigned int off
= (given
& 0x000000ff);
7757 func (stream
, "[%s", arm_regnames
[Rn
]);
7763 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
7764 value_in_comment
= off
* 4 * (U
? 1 : -1);
7772 func (stream
, "], ");
7775 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
7776 value_in_comment
= off
* 4 * (U
? 1 : -1);
7780 func (stream
, "{%u}", off
);
7781 value_in_comment
= off
;
7789 unsigned int Sbit
= (given
& 0x01000000) >> 24;
7790 unsigned int type
= (given
& 0x00600000) >> 21;
7794 case 0: func (stream
, Sbit
? "sb" : "b"); break;
7795 case 1: func (stream
, Sbit
? "sh" : "h"); break;
7798 func (stream
, "??");
7801 func (stream
, "??");
7816 for (reg
= 0; reg
< 16; reg
++)
7817 if ((given
& (1 << reg
)) != 0)
7820 func (stream
, ", ");
7822 if (is_clrm
&& reg
== 13)
7823 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
7824 else if (is_clrm
&& reg
== 15)
7825 func (stream
, "%s", "APSR");
7827 func (stream
, "%s", arm_regnames
[reg
]);
7835 unsigned int msb
= (given
& 0x0000001f);
7836 unsigned int lsb
= 0;
7838 lsb
|= (given
& 0x000000c0u
) >> 6;
7839 lsb
|= (given
& 0x00007000u
) >> 10;
7840 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
7846 unsigned int width
= (given
& 0x0000001f) + 1;
7847 unsigned int lsb
= 0;
7849 lsb
|= (given
& 0x000000c0u
) >> 6;
7850 lsb
|= (given
& 0x00007000u
) >> 10;
7851 func (stream
, "#%u, #%u", lsb
, width
);
7857 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
7858 func (stream
, "%x", boff
);
7864 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
7865 unsigned int immB
= (given
& 0x000007feu
) >> 1;
7866 unsigned int immC
= (given
& 0x00000800u
) >> 11;
7869 offset
|= immA
<< 12;
7870 offset
|= immB
<< 2;
7871 offset
|= immC
<< 1;
7873 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
7875 info
->print_address_func (pc
+ 4 + offset
, info
);
7881 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
7882 unsigned int immB
= (given
& 0x000007feu
) >> 1;
7883 unsigned int immC
= (given
& 0x00000800u
) >> 11;
7886 offset
|= immA
<< 12;
7887 offset
|= immB
<< 2;
7888 offset
|= immC
<< 1;
7890 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
7892 info
->print_address_func (pc
+ 4 + offset
, info
);
7898 unsigned int immA
= (given
& 0x00010000u
) >> 16;
7899 unsigned int immB
= (given
& 0x000007feu
) >> 1;
7900 unsigned int immC
= (given
& 0x00000800u
) >> 11;
7903 offset
|= immA
<< 12;
7904 offset
|= immB
<< 2;
7905 offset
|= immC
<< 1;
7907 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
7909 info
->print_address_func (pc
+ 4 + offset
, info
);
7911 unsigned int T
= (given
& 0x00020000u
) >> 17;
7912 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
7913 unsigned int boffset
= (T
== 1) ? 4 : 2;
7914 func (stream
, ", ");
7915 func (stream
, "%x", endoffset
+ boffset
);
7921 unsigned int immh
= (given
& 0x000007feu
) >> 1;
7922 unsigned int imml
= (given
& 0x00000800u
) >> 11;
7928 info
->print_address_func (pc
+ 4 + imm32
, info
);
7934 unsigned int immh
= (given
& 0x000007feu
) >> 1;
7935 unsigned int imml
= (given
& 0x00000800u
) >> 11;
7941 info
->print_address_func (pc
+ 4 - imm32
, info
);
7947 unsigned int S
= (given
& 0x04000000u
) >> 26;
7948 unsigned int J1
= (given
& 0x00002000u
) >> 13;
7949 unsigned int J2
= (given
& 0x00000800u
) >> 11;
7955 offset
|= (given
& 0x003f0000) >> 4;
7956 offset
|= (given
& 0x000007ff) << 1;
7957 offset
-= (1 << 20);
7959 info
->print_address_func (pc
+ 4 + offset
, info
);
7965 unsigned int S
= (given
& 0x04000000u
) >> 26;
7966 unsigned int I1
= (given
& 0x00002000u
) >> 13;
7967 unsigned int I2
= (given
& 0x00000800u
) >> 11;
7971 offset
|= !(I1
^ S
) << 23;
7972 offset
|= !(I2
^ S
) << 22;
7973 offset
|= (given
& 0x03ff0000u
) >> 4;
7974 offset
|= (given
& 0x000007ffu
) << 1;
7975 offset
-= (1 << 24);
7978 /* BLX target addresses are always word aligned. */
7979 if ((given
& 0x00001000u
) == 0)
7982 info
->print_address_func (offset
, info
);
7988 unsigned int shift
= 0;
7990 shift
|= (given
& 0x000000c0u
) >> 6;
7991 shift
|= (given
& 0x00007000u
) >> 10;
7992 if (WRITEBACK_BIT_SET
)
7993 func (stream
, ", asr #%u", shift
);
7995 func (stream
, ", lsl #%u", shift
);
7996 /* else print nothing - lsl #0 */
8002 unsigned int rot
= (given
& 0x00000030) >> 4;
8005 func (stream
, ", ror #%u", rot
* 8);
8010 if ((given
& 0xf0) == 0x60)
8012 switch (given
& 0xf)
8014 case 0xf: func (stream
, "sy"); break;
8016 func (stream
, "#%d", (int) given
& 0xf);
8022 const char * opt
= data_barrier_option (given
& 0xf);
8024 func (stream
, "%s", opt
);
8026 func (stream
, "#%d", (int) given
& 0xf);
8031 if ((given
& 0xff) == 0)
8033 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
8043 else if ((given
& 0x20) == 0x20)
8046 unsigned sysm
= (given
& 0xf00) >> 8;
8048 sysm
|= (given
& 0x30);
8049 sysm
|= (given
& 0x00100000) >> 14;
8050 name
= banked_regname (sysm
);
8053 func (stream
, "%s", name
);
8055 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
8059 func (stream
, "%s", psr_name (given
& 0xff));
8064 if (((given
& 0xff) == 0)
8065 || ((given
& 0x20) == 0x20))
8068 unsigned sm
= (given
& 0xf0000) >> 16;
8070 sm
|= (given
& 0x30);
8071 sm
|= (given
& 0x00100000) >> 14;
8072 name
= banked_regname (sm
);
8075 func (stream
, "%s", name
);
8077 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
8080 func (stream
, "%s", psr_name (given
& 0xff));
8083 case '0': case '1': case '2': case '3': case '4':
8084 case '5': case '6': case '7': case '8': case '9':
8089 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
8094 func (stream
, "%lu", val
);
8095 value_in_comment
= val
;
8099 func (stream
, "%lu", val
+ 1);
8100 value_in_comment
= val
+ 1;
8104 func (stream
, "%lu", val
* 4);
8105 value_in_comment
= val
* 4;
8110 is_unpredictable
= TRUE
;
8114 is_unpredictable
= TRUE
;
8117 func (stream
, "%s", arm_regnames
[val
]);
8121 func (stream
, "%s", arm_conditional
[val
]);
8126 if (val
== ((1ul << width
) - 1))
8127 func (stream
, "%c", *c
);
8133 func (stream
, "%c", *c
);
8137 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
8142 func (stream
, "0x%lx", val
& 0xffffffffUL
);
8152 /* PR binutils/12534
8153 If we have a PC relative offset in an LDRD or STRD
8154 instructions then display the decoded address. */
8155 if (((given
>> 16) & 0xf) == 0xf)
8157 bfd_vma offset
= (given
& 0xff) * 4;
8159 if ((given
& (1 << 23)) == 0)
8161 func (stream
, "\t; ");
8162 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
8171 if (value_in_comment
> 32 || value_in_comment
< -16)
8172 func (stream
, "\t; 0x%lx", value_in_comment
);
8174 if (is_unpredictable
)
8175 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8181 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
8185 /* Print data bytes on INFO->STREAM. */
8188 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
8189 struct disassemble_info
*info
,
8192 switch (info
->bytes_per_chunk
)
8195 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
8198 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
8201 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
8208 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
8209 being displayed in symbol relative addresses.
8211 Also disallow private symbol, with __tagsym$$ prefix,
8212 from ARM RVCT toolchain being displayed. */
8215 arm_symbol_is_valid (asymbol
* sym
,
8216 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
8223 name
= bfd_asymbol_name (sym
);
8225 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
8228 /* Parse the string of disassembler options. */
8231 parse_arm_disassembler_options (const char *options
)
8235 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
8237 if (CONST_STRNEQ (opt
, "reg-names-"))
8240 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
8241 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
8243 regname_selected
= i
;
8247 if (i
>= NUM_ARM_OPTIONS
)
8248 /* xgettext: c-format */
8249 opcodes_error_handler (_("unrecognised register name set: %s"),
8252 else if (CONST_STRNEQ (opt
, "force-thumb"))
8254 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
8257 /* xgettext: c-format */
8258 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
8265 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
8266 enum map_type
*map_symbol
);
8268 /* Search back through the insn stream to determine if this instruction is
8269 conditionally executed. */
8272 find_ifthen_state (bfd_vma pc
,
8273 struct disassemble_info
*info
,
8279 /* COUNT is twice the number of instructions seen. It will be odd if we
8280 just crossed an instruction boundary. */
8283 unsigned int seen_it
;
8286 ifthen_address
= pc
;
8293 /* Scan backwards looking for IT instructions, keeping track of where
8294 instruction boundaries are. We don't know if something is actually an
8295 IT instruction until we find a definite instruction boundary. */
8298 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
8300 /* A symbol must be on an instruction boundary, and will not
8301 be within an IT block. */
8302 if (seen_it
&& (count
& 1))
8308 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
8313 insn
= (b
[0]) | (b
[1] << 8);
8315 insn
= (b
[1]) | (b
[0] << 8);
8318 if ((insn
& 0xf800) < 0xe800)
8320 /* Addr + 2 is an instruction boundary. See if this matches
8321 the expected boundary based on the position of the last
8328 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
8330 enum map_type type
= MAP_ARM
;
8331 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
8333 if (!found
|| (found
&& type
== MAP_THUMB
))
8335 /* This could be an IT instruction. */
8337 it_count
= count
>> 1;
8340 if ((insn
& 0xf800) >= 0xe800)
8343 count
= (count
+ 2) | 1;
8344 /* IT blocks contain at most 4 instructions. */
8345 if (count
>= 8 && !seen_it
)
8348 /* We found an IT instruction. */
8349 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
8350 if ((ifthen_state
& 0xf) == 0)
8354 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
8358 is_mapping_symbol (struct disassemble_info
*info
, int n
,
8359 enum map_type
*map_type
)
8363 name
= bfd_asymbol_name (info
->symtab
[n
]);
8364 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
8365 && (name
[2] == 0 || name
[2] == '.'))
8367 *map_type
= ((name
[1] == 'a') ? MAP_ARM
8368 : (name
[1] == 't') ? MAP_THUMB
8376 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
8377 Returns nonzero if *MAP_TYPE was set. */
8380 get_map_sym_type (struct disassemble_info
*info
,
8382 enum map_type
*map_type
)
8384 /* If the symbol is in a different section, ignore it. */
8385 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
8388 return is_mapping_symbol (info
, n
, map_type
);
8391 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
8392 Returns nonzero if *MAP_TYPE was set. */
8395 get_sym_code_type (struct disassemble_info
*info
,
8397 enum map_type
*map_type
)
8399 elf_symbol_type
*es
;
8402 /* If the symbol is in a different section, ignore it. */
8403 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
8406 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
8407 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
8409 /* If the symbol has function type then use that. */
8410 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
8412 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
8413 == ST_BRANCH_TO_THUMB
)
8414 *map_type
= MAP_THUMB
;
8416 *map_type
= MAP_ARM
;
8423 /* Search the mapping symbol state for instruction at pc. This is only
8424 applicable for elf target.
8426 There is an assumption Here, info->private_data contains the correct AND
8427 up-to-date information about current scan process. The information will be
8428 used to speed this search process.
8430 Return TRUE if the mapping state can be determined, and map_symbol
8431 will be updated accordingly. Otherwise, return FALSE. */
8434 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
8435 enum map_type
*map_symbol
)
8437 bfd_vma addr
, section_vma
= 0;
8438 int n
, last_sym
= -1;
8439 bfd_boolean found
= FALSE
;
8440 bfd_boolean can_use_search_opt_p
= FALSE
;
8442 /* Default to DATA. A text section is required by the ABI to contain an
8443 INSN mapping symbol at the start. A data section has no such
8444 requirement, hence if no mapping symbol is found the section must
8445 contain only data. This however isn't very useful if the user has
8446 fully stripped the binaries. If this is the case use the section
8447 attributes to determine the default. If we have no section default to
8448 INSN as well, as we may be disassembling some raw bytes on a baremetal
8449 HEX file or similar. */
8450 enum map_type type
= MAP_DATA
;
8451 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
8453 struct arm_private_data
*private_data
;
8455 if (info
->private_data
== NULL
8456 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
8459 private_data
= info
->private_data
;
8461 /* First, look for mapping symbols. */
8462 if (info
->symtab_size
!= 0)
8464 if (pc
<= private_data
->last_mapping_addr
)
8465 private_data
->last_mapping_sym
= -1;
8467 /* Start scanning at the start of the function, or wherever
8468 we finished last time. */
8469 n
= info
->symtab_pos
+ 1;
8471 /* If the last stop offset is different from the current one it means we
8472 are disassembling a different glob of bytes. As such the optimization
8473 would not be safe and we should start over. */
8474 can_use_search_opt_p
8475 = private_data
->last_mapping_sym
>= 0
8476 && info
->stop_offset
== private_data
->last_stop_offset
;
8478 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
8479 n
= private_data
->last_mapping_sym
;
8481 /* Look down while we haven't passed the location being disassembled.
8482 The reason for this is that there's no defined order between a symbol
8483 and an mapping symbol that may be at the same address. We may have to
8484 look at least one position ahead. */
8485 for (; n
< info
->symtab_size
; n
++)
8487 addr
= bfd_asymbol_value (info
->symtab
[n
]);
8490 if (get_map_sym_type (info
, n
, &type
))
8499 n
= info
->symtab_pos
;
8500 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
8501 n
= private_data
->last_mapping_sym
;
8503 /* No mapping symbol found at this address. Look backwards
8504 for a preceeding one, but don't go pass the section start
8505 otherwise a data section with no mapping symbol can pick up
8506 a text mapping symbol of a preceeding section. The documentation
8507 says section can be NULL, in which case we will seek up all the
8510 section_vma
= info
->section
->vma
;
8514 addr
= bfd_asymbol_value (info
->symtab
[n
]);
8515 if (addr
< section_vma
)
8518 if (get_map_sym_type (info
, n
, &type
))
8528 /* If no mapping symbol was found, try looking up without a mapping
8529 symbol. This is done by walking up from the current PC to the nearest
8530 symbol. We don't actually have to loop here since symtab_pos will
8531 contain the nearest symbol already. */
8534 n
= info
->symtab_pos
;
8535 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
8542 private_data
->last_mapping_sym
= last_sym
;
8543 private_data
->last_type
= type
;
8544 private_data
->last_stop_offset
= info
->stop_offset
;
8550 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
8551 of the supplied arm_feature_set structure with bitmasks indicating
8552 the supported base architectures and coprocessor extensions.
8554 FIXME: This could more efficiently implemented as a constant array,
8555 although it would also be less robust. */
8558 select_arm_features (unsigned long mach
,
8559 arm_feature_set
* features
)
8561 arm_feature_set arch_fset
;
8562 const arm_feature_set fpu_any
= FPU_ANY
;
8564 #undef ARM_SET_FEATURES
8565 #define ARM_SET_FEATURES(FSET) \
8567 const arm_feature_set fset = FSET; \
8571 /* When several architecture versions share the same bfd_mach_arm_XXX value
8572 the most featureful is chosen. */
8575 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
8576 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
8577 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
8578 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
8579 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
8580 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
8581 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
8582 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
8583 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
8584 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
8585 case bfd_mach_arm_ep9312
:
8586 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
8587 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
8589 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
8590 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
8591 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
8592 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
8593 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
8594 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
8595 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
8596 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
8597 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
8598 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
8599 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
8600 case bfd_mach_arm_8
:
8602 /* Add bits for extensions that Armv8.5-A recognizes. */
8603 arm_feature_set armv8_5_ext_fset
8604 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
8605 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
8606 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
8609 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
8610 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
8611 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
8612 case bfd_mach_arm_8_1M_MAIN
:
8613 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
8616 /* If the machine type is unknown allow all architecture types and all
8618 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
8622 #undef ARM_SET_FEATURES
8624 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
8625 and thus on bfd_mach_arm_XXX value. Therefore for a given
8626 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
8627 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
8631 /* NOTE: There are no checks in these routines that
8632 the relevant number of data bytes exist. */
8635 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
8640 int is_thumb
= FALSE
;
8641 int is_data
= FALSE
;
8643 unsigned int size
= 4;
8644 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
8645 bfd_boolean found
= FALSE
;
8646 struct arm_private_data
*private_data
;
8648 if (info
->disassembler_options
)
8650 parse_arm_disassembler_options (info
->disassembler_options
);
8652 /* To avoid repeated parsing of these options, we remove them here. */
8653 info
->disassembler_options
= NULL
;
8656 /* PR 10288: Control which instructions will be disassembled. */
8657 if (info
->private_data
== NULL
)
8659 static struct arm_private_data
private;
8661 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
8662 /* If the user did not use the -m command line switch then default to
8663 disassembling all types of ARM instruction.
8665 The info->mach value has to be ignored as this will be based on
8666 the default archictecture for the target and/or hints in the notes
8667 section, but it will never be greater than the current largest arm
8668 machine value (iWMMXt2), which is only equivalent to the V5TE
8669 architecture. ARM architectures have advanced beyond the machine
8670 value encoding, and these newer architectures would be ignored if
8671 the machine value was used.
8673 Ie the -m switch is used to restrict which instructions will be
8674 disassembled. If it is necessary to use the -m switch to tell
8675 objdump that an ARM binary is being disassembled, eg because the
8676 input is a raw binary file, but it is also desired to disassemble
8677 all ARM instructions then use "-marm". This will select the
8678 "unknown" arm architecture which is compatible with any ARM
8680 info
->mach
= bfd_mach_arm_unknown
;
8682 /* Compute the architecture bitmask from the machine number.
8683 Note: This assumes that the machine number will not change
8684 during disassembly.... */
8685 select_arm_features (info
->mach
, & private.features
);
8687 private.last_mapping_sym
= -1;
8688 private.last_mapping_addr
= 0;
8689 private.last_stop_offset
= 0;
8691 info
->private_data
= & private;
8694 private_data
= info
->private_data
;
8696 /* Decide if our code is going to be little-endian, despite what the
8697 function argument might say. */
8698 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
8700 /* For ELF, consult the symbol table to determine what kind of code
8702 if (info
->symtab_size
!= 0
8703 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
8708 enum map_type type
= MAP_ARM
;
8710 found
= mapping_symbol_for_insn (pc
, info
, &type
);
8711 last_sym
= private_data
->last_mapping_sym
;
8713 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
8714 is_data
= (private_data
->last_type
== MAP_DATA
);
8716 /* Look a little bit ahead to see if we should print out
8717 two or four bytes of data. If there's a symbol,
8718 mapping or otherwise, after two bytes then don't
8722 size
= 4 - (pc
& 3);
8723 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
8725 addr
= bfd_asymbol_value (info
->symtab
[n
]);
8727 && (info
->section
== NULL
8728 || info
->section
== info
->symtab
[n
]->section
))
8730 if (addr
- pc
< size
)
8735 /* If the next symbol is after three bytes, we need to
8736 print only part of the data, so that we can use either
8739 size
= (pc
& 1) ? 1 : 2;
8743 if (info
->symbols
!= NULL
)
8745 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
8747 coff_symbol_type
* cs
;
8749 cs
= coffsymbol (*info
->symbols
);
8750 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
8751 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
8752 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
8753 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
8754 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
8756 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
8759 /* If no mapping symbol has been found then fall back to the type
8760 of the function symbol. */
8761 elf_symbol_type
* es
;
8764 es
= *(elf_symbol_type
**)(info
->symbols
);
8765 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
8768 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
8769 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
8771 else if (bfd_asymbol_flavour (*info
->symbols
)
8772 == bfd_target_mach_o_flavour
)
8774 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
8776 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
8784 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
8786 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
8788 info
->bytes_per_line
= 4;
8790 /* PR 10263: Disassemble data if requested to do so by the user. */
8791 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
8795 /* Size was already set above. */
8796 info
->bytes_per_chunk
= size
;
8797 printer
= print_insn_data
;
8799 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
8802 for (i
= size
- 1; i
>= 0; i
--)
8803 given
= b
[i
] | (given
<< 8);
8805 for (i
= 0; i
< (int) size
; i
++)
8806 given
= b
[i
] | (given
<< 8);
8810 /* In ARM mode endianness is a straightforward issue: the instruction
8811 is four bytes long and is either ordered 0123 or 3210. */
8812 printer
= print_insn_arm
;
8813 info
->bytes_per_chunk
= 4;
8816 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
8818 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
8820 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
8824 /* In Thumb mode we have the additional wrinkle of two
8825 instruction lengths. Fortunately, the bits that determine
8826 the length of the current instruction are always to be found
8827 in the first two bytes. */
8828 printer
= print_insn_thumb16
;
8829 info
->bytes_per_chunk
= 2;
8832 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
8834 given
= (b
[0]) | (b
[1] << 8);
8836 given
= (b
[1]) | (b
[0] << 8);
8840 /* These bit patterns signal a four-byte Thumb
8842 if ((given
& 0xF800) == 0xF800
8843 || (given
& 0xF800) == 0xF000
8844 || (given
& 0xF800) == 0xE800)
8846 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
8848 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
8850 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
8852 printer
= print_insn_thumb32
;
8857 if (ifthen_address
!= pc
)
8858 find_ifthen_state (pc
, info
, little_code
);
8862 if ((ifthen_state
& 0xf) == 0x8)
8863 ifthen_next_state
= 0;
8865 ifthen_next_state
= (ifthen_state
& 0xe0)
8866 | ((ifthen_state
& 0xf) << 1);
8872 info
->memory_error_func (status
, pc
, info
);
8875 if (info
->flags
& INSN_HAS_RELOC
)
8876 /* If the instruction has a reloc associated with it, then
8877 the offset field in the instruction will actually be the
8878 addend for the reloc. (We are using REL type relocs).
8879 In such cases, we can ignore the pc when computing
8880 addresses, since the addend is not currently pc-relative. */
8883 printer (pc
, info
, given
);
8887 ifthen_state
= ifthen_next_state
;
8888 ifthen_address
+= size
;
8894 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
8896 /* Detect BE8-ness and record it in the disassembler info. */
8897 if (info
->flavour
== bfd_target_elf_flavour
8898 && info
->section
!= NULL
8899 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
8900 info
->endian_code
= BFD_ENDIAN_LITTLE
;
8902 return print_insn (pc
, info
, FALSE
);
8906 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
8908 return print_insn (pc
, info
, TRUE
);
8911 const disasm_options_and_args_t
*
8912 disassembler_options_arm (void)
8914 static disasm_options_and_args_t
*opts_and_args
;
8916 if (opts_and_args
== NULL
)
8918 disasm_options_t
*opts
;
8921 opts_and_args
= XNEW (disasm_options_and_args_t
);
8922 opts_and_args
->args
= NULL
;
8924 opts
= &opts_and_args
->options
;
8925 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
8926 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
8928 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
8930 opts
->name
[i
] = regnames
[i
].name
;
8931 if (regnames
[i
].description
!= NULL
)
8932 opts
->description
[i
] = _(regnames
[i
].description
);
8934 opts
->description
[i
] = NULL
;
8936 /* The array we return must be NULL terminated. */
8937 opts
->name
[i
] = NULL
;
8938 opts
->description
[i
] = NULL
;
8941 return opts_and_args
;
8945 print_arm_disassembler_options (FILE *stream
)
8947 unsigned int i
, max_len
= 0;
8948 fprintf (stream
, _("\n\
8949 The following ARM specific disassembler options are supported for use with\n\
8950 the -M switch:\n"));
8952 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
8954 unsigned int len
= strlen (regnames
[i
].name
);
8959 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
8960 fprintf (stream
, " %s%*c %s\n",
8962 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
8963 _(regnames
[i
].description
));